Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/agp_intel.c
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1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include "opt_bus.h" 30 #include "opt_pci.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/lock.h> 38 39 #include <pci/pcivar.h> 40 #include <pci/pcireg.h> 41 #include <pci/agppriv.h> 42 #include <pci/agpreg.h> 43 44 #include <vm/vm.h> 45 #include <vm/vm_object.h> 46 #include <vm/pmap.h> 47 48 #define MAX_APSIZE 0x3f /* 256 MB */ 49 50 struct agp_intel_softc { 51 struct agp_softc agp; 52 u_int32_t initial_aperture; /* aperture size at startup */ 53 struct agp_gatt *gatt; 54 u_int aperture_mask; 55 }; 56 57 static const char* 58 agp_intel_match(device_t dev) 59 { 60 if (pci_get_class(dev) != PCIC_BRIDGE 61 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 62 return NULL; 63 64 if (agp_find_caps(dev) == 0) 65 return NULL; 66 67 switch (pci_get_devid(dev)) { 68 /* Intel -- vendor 0x8086 */ 69 case 0x71808086: 70 return ("Intel 82443LX (440 LX) host to PCI bridge"); 71 72 case 0x71908086: 73 return ("Intel 82443BX (440 BX) host to PCI bridge"); 74 75 case 0x71a08086: 76 return ("Intel 82443GX host to PCI bridge"); 77 78 case 0x71a18086: 79 return ("Intel 82443GX host to AGP bridge"); 80 81 case 0x11308086: 82 return ("Intel 82815 (i815 GMCH) host to PCI bridge"); 83 84 case 0x25008086: 85 case 0x25018086: 86 return ("Intel 82820 host to AGP bridge"); 87 88 case 0x35758086: 89 return ("Intel 82830 host to AGP bridge"); 90 91 case 0x1a218086: 92 return ("Intel 82840 host to AGP bridge"); 93 94 case 0x1a308086: 95 return ("Intel 82845 host to AGP bridge"); 96 97 case 0x25308086: 98 return ("Intel 82850 host to AGP bridge"); 99 100 case 0x33408086: 101 return ("Intel 82855 host to AGP bridge"); 102 103 case 0x25318086: 104 return ("Intel 82860 host to AGP bridge"); 105 106 case 0x25708086: 107 return ("Intel 82865 host to AGP bridge"); 108 109 case 0x25788086: 110 return ("Intel 82875P host to AGP bridge"); 111 }; 112 113 if (pci_get_vendor(dev) == 0x8086) 114 return ("Intel Generic host to PCI bridge"); 115 116 return NULL; 117 } 118 119 static int 120 agp_intel_probe(device_t dev) 121 { 122 const char *desc; 123 124 desc = agp_intel_match(dev); 125 if (desc) { 126 device_verbose(dev); 127 device_set_desc(dev, desc); 128 return 0; 129 } 130 131 return ENXIO; 132 } 133 134 static int 135 agp_intel_attach(device_t dev) 136 { 137 struct agp_intel_softc *sc = device_get_softc(dev); 138 struct agp_gatt *gatt; 139 u_int32_t type = pci_get_devid(dev); 140 u_int32_t value; 141 int error; 142 143 error = agp_generic_attach(dev); 144 if (error) 145 return error; 146 147 /* Determine maximum supported aperture size. */ 148 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1); 149 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1); 150 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 151 MAX_APSIZE; 152 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1); 153 sc->initial_aperture = AGP_GET_APERTURE(dev); 154 155 for (;;) { 156 gatt = agp_alloc_gatt(dev); 157 if (gatt) 158 break; 159 160 /* 161 * Probably contigmalloc failure. Try reducing the 162 * aperture so that the gatt size reduces. 163 */ 164 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 165 agp_generic_detach(dev); 166 return ENOMEM; 167 } 168 } 169 sc->gatt = gatt; 170 171 /* Install the gatt. */ 172 pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4); 173 174 /* Enable the GLTB and setup the control register. */ 175 switch (type) { 176 case 0x71908086: /* 440LX/EX */ 177 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4); 178 break; 179 case 0x71808086: /* 440BX */ 180 /* 181 * XXX: Should be 0xa080? Bit 9 is undefined, and 182 * bit 13 being on and bit 15 being clear is illegal. 183 */ 184 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 185 break; 186 default: 187 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 188 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4); 189 } 190 191 /* Enable things, clear errors etc. */ 192 switch (type) { 193 case 0x1a218086: /* i840 */ 194 case 0x25308086: /* i850 */ 195 case 0x25318086: /* i860 */ 196 pci_write_config(dev, AGP_INTEL_MCHCFG, 197 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 198 | (1 << 9)), 2); 199 break; 200 201 case 0x25008086: /* i820 */ 202 case 0x25018086: /* i820 */ 203 pci_write_config(dev, AGP_INTEL_I820_RDCR, 204 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 205 | (1 << 1)), 1); 206 break; 207 208 case 0x1a308086: /* i845 */ 209 case 0x33408086: /* i855 */ 210 case 0x25708086: /* i865 */ 211 case 0x25788086: /* i875P */ 212 pci_write_config(dev, AGP_INTEL_I845_MCHCFG, 213 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 214 | (1 << 1)), 1); 215 break; 216 217 default: /* Intel Generic (maybe) */ 218 pci_write_config(dev, AGP_INTEL_NBXCFG, 219 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 220 & ~(1 << 10)) | (1 << 9), 4); 221 } 222 223 switch (type) { 224 case 0x1a218086: /* i840 */ 225 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2); 226 break; 227 228 case 0x25008086: /* i820 */ 229 case 0x25018086: /* i820 */ 230 case 0x1a308086: /* i845 */ 231 case 0x25308086: /* i850 */ 232 case 0x33408086: /* i855 */ 233 case 0x25318086: /* i860 */ 234 case 0x25708086: /* i865 */ 235 case 0x25788086: /* i875P */ 236 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2); 237 break; 238 239 default: /* Intel Generic (maybe) */ 240 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 241 } 242 243 return 0; 244 } 245 246 static int 247 agp_intel_detach(device_t dev) 248 { 249 struct agp_intel_softc *sc = device_get_softc(dev); 250 u_int32_t type = pci_get_devid(dev); 251 int error; 252 253 error = agp_generic_detach(dev); 254 if (error) 255 return error; 256 257 switch (type) { 258 case 0x1a218086: /* i840 */ 259 case 0x25308086: /* i850 */ 260 case 0x25318086: /* i860 */ 261 printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned) 262 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 263 & ~(1 << 9))); 264 pci_write_config(dev, AGP_INTEL_MCHCFG, 265 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 266 & ~(1 << 9)), 2); 267 268 case 0x25008086: /* i820 */ 269 case 0x25018086: /* i820 */ 270 printf("%s: set RDCR to %x\n", __FUNCTION__, (unsigned) 271 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 272 & ~(1 << 1))); 273 pci_write_config(dev, AGP_INTEL_I820_RDCR, 274 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 275 & ~(1 << 1)), 1); 276 277 case 0x1a308086: /* i845 */ 278 case 0x33408086: /* i855 */ 279 case 0x25708086: /* i865 */ 280 case 0x25788086: /* i875P */ 281 printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned) 282 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 283 & ~(1 << 1))); 284 pci_write_config(dev, AGP_INTEL_MCHCFG, 285 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 286 & ~(1 << 1)), 1); 287 288 default: /* Intel Generic (maybe) */ 289 printf("%s: set NBXCFG to %x\n", __FUNCTION__, 290 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 291 & ~(1 << 9))); 292 pci_write_config(dev, AGP_INTEL_NBXCFG, 293 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 294 & ~(1 << 9)), 4); 295 } 296 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 297 AGP_SET_APERTURE(dev, sc->initial_aperture); 298 agp_free_gatt(sc->gatt); 299 300 return 0; 301 } 302 303 static u_int32_t 304 agp_intel_get_aperture(device_t dev) 305 { 306 struct agp_intel_softc *sc = device_get_softc(dev); 307 u_int32_t apsize; 308 309 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask; 310 311 /* 312 * The size is determined by the number of low bits of 313 * register APBASE which are forced to zero. The low 22 bits 314 * are always forced to zero and each zero bit in the apsize 315 * field just read forces the corresponding bit in the 27:22 316 * to be zero. We calculate the aperture size accordingly. 317 */ 318 return (((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 319 } 320 321 static int 322 agp_intel_set_aperture(device_t dev, u_int32_t aperture) 323 { 324 struct agp_intel_softc *sc = device_get_softc(dev); 325 u_int32_t apsize; 326 327 /* 328 * Reverse the magic from get_aperture. 329 */ 330 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask; 331 332 /* 333 * Double check for sanity. 334 */ 335 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture) 336 return EINVAL; 337 338 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 339 340 return 0; 341 } 342 343 static int 344 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical) 345 { 346 struct agp_intel_softc *sc = device_get_softc(dev); 347 348 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 349 return EINVAL; 350 351 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 352 return 0; 353 } 354 355 static int 356 agp_intel_unbind_page(device_t dev, int offset) 357 { 358 struct agp_intel_softc *sc = device_get_softc(dev); 359 360 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 361 return EINVAL; 362 363 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 364 return 0; 365 } 366 367 static void 368 agp_intel_flush_tlb(device_t dev) 369 { 370 u_int32_t val; 371 372 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 373 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4); 374 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); 375 } 376 377 static device_method_t agp_intel_methods[] = { 378 /* Device interface */ 379 DEVMETHOD(device_probe, agp_intel_probe), 380 DEVMETHOD(device_attach, agp_intel_attach), 381 DEVMETHOD(device_detach, agp_intel_detach), 382 DEVMETHOD(device_shutdown, bus_generic_shutdown), 383 DEVMETHOD(device_suspend, bus_generic_suspend), 384 DEVMETHOD(device_resume, bus_generic_resume), 385 386 /* AGP interface */ 387 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 388 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 389 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 390 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 391 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 392 DEVMETHOD(agp_enable, agp_generic_enable), 393 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 394 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 395 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 396 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 397 398 { 0, 0 } 399 }; 400 401 static driver_t agp_intel_driver = { 402 "agp", 403 agp_intel_methods, 404 sizeof(struct agp_intel_softc), 405 }; 406 407 static devclass_t agp_devclass; 408 409 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0);
Cache object: 928d8633f1304be1badd5188afb3f720
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