Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/agp_intel.c
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1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: releng/5.0/sys/pci/agp_intel.c 106860 2002-11-13 17:40:15Z mux $ 27 */ 28 29 #include "opt_bus.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/lock.h> 37 #include <sys/lockmgr.h> 38 #include <sys/mutex.h> 39 #include <sys/proc.h> 40 41 #include <pci/pcivar.h> 42 #include <pci/pcireg.h> 43 #include <pci/agppriv.h> 44 #include <pci/agpreg.h> 45 46 #include <vm/vm.h> 47 #include <vm/vm_object.h> 48 #include <vm/pmap.h> 49 50 struct agp_intel_softc { 51 struct agp_softc agp; 52 u_int32_t initial_aperture; /* aperture size at startup */ 53 struct agp_gatt *gatt; 54 }; 55 56 static const char* 57 agp_intel_match(device_t dev) 58 { 59 if (pci_get_class(dev) != PCIC_BRIDGE 60 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 61 return NULL; 62 63 if (agp_find_caps(dev) == 0) 64 return NULL; 65 66 switch (pci_get_devid(dev)) { 67 /* Intel -- vendor 0x8086 */ 68 case 0x71808086: 69 return ("Intel 82443LX (440 LX) host to PCI bridge"); 70 71 case 0x71908086: 72 return ("Intel 82443BX (440 BX) host to PCI bridge"); 73 74 case 0x71a08086: 75 return ("Intel 82443GX host to PCI bridge"); 76 77 case 0x71a18086: 78 return ("Intel 82443GX host to AGP bridge"); 79 80 case 0x11308086: 81 return ("Intel 82815 (i815 GMCH) host to PCI bridge"); 82 83 case 0x25008086: 84 return ("Intel 82820 host to AGP bridge"); 85 86 case 0x35758086: 87 return ("Intel 82830 host to AGP bridge"); 88 89 case 0x1a218086: 90 return ("Intel 82840 host to AGP bridge"); 91 92 case 0x1a308086: 93 return ("Intel 82845 host to AGP bridge"); 94 95 case 0x25308086: 96 return ("Intel 82850 host to AGP bridge"); 97 98 case 0x25318086: 99 return ("Intel 82860 host to AGP bridge"); 100 }; 101 102 if (pci_get_vendor(dev) == 0x8086) 103 return ("Intel Generic host to PCI bridge"); 104 105 return NULL; 106 } 107 108 static int 109 agp_intel_probe(device_t dev) 110 { 111 const char *desc; 112 113 desc = agp_intel_match(dev); 114 if (desc) { 115 device_verbose(dev); 116 device_set_desc(dev, desc); 117 return 0; 118 } 119 120 return ENXIO; 121 } 122 123 static int 124 agp_intel_attach(device_t dev) 125 { 126 struct agp_intel_softc *sc = device_get_softc(dev); 127 struct agp_gatt *gatt; 128 u_int32_t type = pci_get_devid(dev); 129 int error; 130 131 error = agp_generic_attach(dev); 132 if (error) 133 return error; 134 135 sc->initial_aperture = AGP_GET_APERTURE(dev); 136 137 for (;;) { 138 gatt = agp_alloc_gatt(dev); 139 if (gatt) 140 break; 141 142 /* 143 * Probably contigmalloc failure. Try reducing the 144 * aperture so that the gatt size reduces. 145 */ 146 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 147 agp_generic_detach(dev); 148 return ENOMEM; 149 } 150 } 151 sc->gatt = gatt; 152 153 /* Install the gatt. */ 154 pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4); 155 156 /* Enable the GLTB and setup the control register. */ 157 switch (type) { 158 case 0x71908086: /* 440LX/EX */ 159 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4); 160 break; 161 case 0x71808086: /* 440BX */ 162 /* 163 * XXX: Should be 0xa080? Bit 9 is undefined, and 164 * bit 13 being on and bit 15 being clear is illegal. 165 */ 166 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 167 break; 168 default: 169 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0080, 4); 170 } 171 172 /* Enable things, clear errors etc. */ 173 switch (type) { 174 case 0x1a218086: /* i840 */ 175 case 0x25308086: /* i850 */ 176 case 0x25318086: /* i860 */ 177 pci_write_config(dev, AGP_INTEL_MCHCFG, 178 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 179 | (1 << 9)), 2); 180 break; 181 182 case 0x25008086: /* i820 */ 183 pci_write_config(dev, AGP_INTEL_I820_RDCR, 184 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 185 | (1 << 1)), 1); 186 break; 187 188 case 0x1a308086: /* i845 */ 189 pci_write_config(dev, AGP_INTEL_I845_MCHCFG, 190 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 191 | (1 << 1)), 1); 192 break; 193 194 default: /* Intel Generic (maybe) */ 195 pci_write_config(dev, AGP_INTEL_NBXCFG, 196 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 197 & ~(1 << 10)) | (1 << 9), 4); 198 } 199 200 switch (type) { 201 case 0x1a218086: /* i840 */ 202 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2); 203 break; 204 205 case 0x25008086: /* i820 */ 206 case 0x1a308086: /* i845 */ 207 case 0x25308086: /* i850 */ 208 case 0x25318086: /* i860 */ 209 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x001c, 2); 210 break; 211 212 default: /* Intel Generic (maybe) */ 213 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 214 } 215 216 return 0; 217 } 218 219 static int 220 agp_intel_detach(device_t dev) 221 { 222 struct agp_intel_softc *sc = device_get_softc(dev); 223 u_int32_t type = pci_get_devid(dev); 224 int error; 225 226 error = agp_generic_detach(dev); 227 if (error) 228 return error; 229 230 switch (type) { 231 case 0x1a218086: /* i840 */ 232 case 0x25308086: /* i850 */ 233 case 0x25318086: /* i860 */ 234 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 235 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 236 & ~(1 << 9))); 237 pci_write_config(dev, AGP_INTEL_MCHCFG, 238 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 239 & ~(1 << 9)), 2); 240 241 case 0x25008086: /* i820 */ 242 printf("%s: set RDCR to %x\n", __func__, (unsigned) 243 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 244 & ~(1 << 1))); 245 pci_write_config(dev, AGP_INTEL_I820_RDCR, 246 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 247 & ~(1 << 1)), 1); 248 249 case 0x1a308086: /* i845 */ 250 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 251 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 252 & ~(1 << 1))); 253 pci_write_config(dev, AGP_INTEL_MCHCFG, 254 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 255 & ~(1 << 1)), 1); 256 257 default: /* Intel Generic (maybe) */ 258 printf("%s: set NBXCFG to %x\n", __func__, 259 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 260 & ~(1 << 9))); 261 pci_write_config(dev, AGP_INTEL_NBXCFG, 262 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 263 & ~(1 << 9)), 4); 264 } 265 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 266 AGP_SET_APERTURE(dev, sc->initial_aperture); 267 agp_free_gatt(sc->gatt); 268 269 return 0; 270 } 271 272 static u_int32_t 273 agp_intel_get_aperture(device_t dev) 274 { 275 u_int32_t apsize; 276 277 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 0x1f; 278 279 /* 280 * The size is determined by the number of low bits of 281 * register APBASE which are forced to zero. The low 22 bits 282 * are always forced to zero and each zero bit in the apsize 283 * field just read forces the corresponding bit in the 27:22 284 * to be zero. We calculate the aperture size accordingly. 285 */ 286 return (((apsize ^ 0x1f) << 22) | ((1 << 22) - 1)) + 1; 287 } 288 289 static int 290 agp_intel_set_aperture(device_t dev, u_int32_t aperture) 291 { 292 u_int32_t apsize; 293 294 /* 295 * Reverse the magic from get_aperture. 296 */ 297 apsize = ((aperture - 1) >> 22) ^ 0x1f; 298 299 /* 300 * Double check for sanity. 301 */ 302 if ((((apsize ^ 0x1f) << 22) | ((1 << 22) - 1)) + 1 != aperture) 303 return EINVAL; 304 305 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 306 307 return 0; 308 } 309 310 static int 311 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical) 312 { 313 struct agp_intel_softc *sc = device_get_softc(dev); 314 315 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 316 return EINVAL; 317 318 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 319 return 0; 320 } 321 322 static int 323 agp_intel_unbind_page(device_t dev, int offset) 324 { 325 struct agp_intel_softc *sc = device_get_softc(dev); 326 327 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 328 return EINVAL; 329 330 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 331 return 0; 332 } 333 334 static void 335 agp_intel_flush_tlb(device_t dev) 336 { 337 u_int32_t val; 338 339 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 340 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 8), 4); 341 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); 342 } 343 344 static device_method_t agp_intel_methods[] = { 345 /* Device interface */ 346 DEVMETHOD(device_probe, agp_intel_probe), 347 DEVMETHOD(device_attach, agp_intel_attach), 348 DEVMETHOD(device_detach, agp_intel_detach), 349 DEVMETHOD(device_shutdown, bus_generic_shutdown), 350 DEVMETHOD(device_suspend, bus_generic_suspend), 351 DEVMETHOD(device_resume, bus_generic_resume), 352 353 /* AGP interface */ 354 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 355 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 356 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 357 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 358 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 359 DEVMETHOD(agp_enable, agp_generic_enable), 360 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 361 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 362 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 363 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 364 365 { 0, 0 } 366 }; 367 368 static driver_t agp_intel_driver = { 369 "agp", 370 agp_intel_methods, 371 sizeof(struct agp_intel_softc), 372 }; 373 374 static devclass_t agp_devclass; 375 376 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0);
Cache object: 5f9a2fffbd0328172168ef750cd3b9d4
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