Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/pci/agp_intel.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: releng/5.1/sys/pci/agp_intel.c 115355 2003-05-27 20:13:44Z jhb $ 27 */ 28 29 #include "opt_bus.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/lock.h> 37 #include <sys/lockmgr.h> 38 #include <sys/mutex.h> 39 #include <sys/proc.h> 40 41 #include <pci/pcivar.h> 42 #include <pci/pcireg.h> 43 #include <pci/agppriv.h> 44 #include <pci/agpreg.h> 45 46 #include <vm/vm.h> 47 #include <vm/vm_object.h> 48 #include <vm/pmap.h> 49 50 #define MAX_APSIZE 0x3f /* 256 MB */ 51 52 struct agp_intel_softc { 53 struct agp_softc agp; 54 u_int32_t initial_aperture; /* aperture size at startup */ 55 struct agp_gatt *gatt; 56 u_int aperture_mask; 57 }; 58 59 static const char* 60 agp_intel_match(device_t dev) 61 { 62 if (pci_get_class(dev) != PCIC_BRIDGE 63 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 64 return NULL; 65 66 if (agp_find_caps(dev) == 0) 67 return NULL; 68 69 switch (pci_get_devid(dev)) { 70 /* Intel -- vendor 0x8086 */ 71 case 0x71808086: 72 return ("Intel 82443LX (440 LX) host to PCI bridge"); 73 74 case 0x71908086: 75 return ("Intel 82443BX (440 BX) host to PCI bridge"); 76 77 case 0x71a08086: 78 return ("Intel 82443GX host to PCI bridge"); 79 80 case 0x71a18086: 81 return ("Intel 82443GX host to AGP bridge"); 82 83 case 0x11308086: 84 return ("Intel 82815 (i815 GMCH) host to PCI bridge"); 85 86 case 0x25008086: 87 case 0x25018086: 88 return ("Intel 82820 host to AGP bridge"); 89 90 case 0x35758086: 91 return ("Intel 82830 host to AGP bridge"); 92 93 case 0x1a218086: 94 return ("Intel 82840 host to AGP bridge"); 95 96 case 0x1a308086: 97 return ("Intel 82845 host to AGP bridge"); 98 99 case 0x25308086: 100 return ("Intel 82850 host to AGP bridge"); 101 102 case 0x25318086: 103 return ("Intel 82860 host to AGP bridge"); 104 105 case 0x25708086: 106 return ("Intel 82865 host to AGP bridge"); 107 }; 108 109 if (pci_get_vendor(dev) == 0x8086) 110 return ("Intel Generic host to PCI bridge"); 111 112 return NULL; 113 } 114 115 static int 116 agp_intel_probe(device_t dev) 117 { 118 const char *desc; 119 120 desc = agp_intel_match(dev); 121 if (desc) { 122 device_verbose(dev); 123 device_set_desc(dev, desc); 124 return 0; 125 } 126 127 return ENXIO; 128 } 129 130 static int 131 agp_intel_attach(device_t dev) 132 { 133 struct agp_intel_softc *sc = device_get_softc(dev); 134 struct agp_gatt *gatt; 135 u_int32_t type = pci_get_devid(dev); 136 u_int32_t value; 137 int error; 138 139 error = agp_generic_attach(dev); 140 if (error) 141 return error; 142 143 /* Determine maximum supported aperture size. */ 144 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1); 145 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1); 146 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 147 MAX_APSIZE; 148 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1); 149 sc->initial_aperture = AGP_GET_APERTURE(dev); 150 151 for (;;) { 152 gatt = agp_alloc_gatt(dev); 153 if (gatt) 154 break; 155 156 /* 157 * Probably contigmalloc failure. Try reducing the 158 * aperture so that the gatt size reduces. 159 */ 160 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 161 agp_generic_detach(dev); 162 return ENOMEM; 163 } 164 } 165 sc->gatt = gatt; 166 167 /* Install the gatt. */ 168 pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4); 169 170 /* Enable the GLTB and setup the control register. */ 171 switch (type) { 172 case 0x71908086: /* 440LX/EX */ 173 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4); 174 break; 175 case 0x71808086: /* 440BX */ 176 /* 177 * XXX: Should be 0xa080? Bit 9 is undefined, and 178 * bit 13 being on and bit 15 being clear is illegal. 179 */ 180 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 181 break; 182 default: 183 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 184 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4); 185 } 186 187 /* Enable things, clear errors etc. */ 188 switch (type) { 189 case 0x1a218086: /* i840 */ 190 case 0x25308086: /* i850 */ 191 case 0x25318086: /* i860 */ 192 pci_write_config(dev, AGP_INTEL_MCHCFG, 193 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 194 | (1 << 9)), 2); 195 break; 196 197 case 0x25008086: /* i820 */ 198 case 0x25018086: /* i820 */ 199 pci_write_config(dev, AGP_INTEL_I820_RDCR, 200 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 201 | (1 << 1)), 1); 202 break; 203 204 case 0x1a308086: /* i845 */ 205 case 0x25708086: /* i865 */ 206 pci_write_config(dev, AGP_INTEL_I845_MCHCFG, 207 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 208 | (1 << 1)), 1); 209 break; 210 211 default: /* Intel Generic (maybe) */ 212 pci_write_config(dev, AGP_INTEL_NBXCFG, 213 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 214 & ~(1 << 10)) | (1 << 9), 4); 215 } 216 217 switch (type) { 218 case 0x1a218086: /* i840 */ 219 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2); 220 break; 221 222 case 0x25008086: /* i820 */ 223 case 0x25018086: /* i820 */ 224 case 0x1a308086: /* i845 */ 225 case 0x25308086: /* i850 */ 226 case 0x25318086: /* i860 */ 227 case 0x25708086: /* i865 */ 228 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2); 229 break; 230 231 default: /* Intel Generic (maybe) */ 232 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 233 } 234 235 return 0; 236 } 237 238 static int 239 agp_intel_detach(device_t dev) 240 { 241 struct agp_intel_softc *sc = device_get_softc(dev); 242 u_int32_t type = pci_get_devid(dev); 243 int error; 244 245 error = agp_generic_detach(dev); 246 if (error) 247 return error; 248 249 switch (type) { 250 case 0x1a218086: /* i840 */ 251 case 0x25308086: /* i850 */ 252 case 0x25318086: /* i860 */ 253 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 254 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 255 & ~(1 << 9))); 256 pci_write_config(dev, AGP_INTEL_MCHCFG, 257 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 258 & ~(1 << 9)), 2); 259 260 case 0x25008086: /* i820 */ 261 case 0x25018086: /* i820 */ 262 printf("%s: set RDCR to %x\n", __func__, (unsigned) 263 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 264 & ~(1 << 1))); 265 pci_write_config(dev, AGP_INTEL_I820_RDCR, 266 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 267 & ~(1 << 1)), 1); 268 269 case 0x1a308086: /* i845 */ 270 case 0x25708086: /* i865 */ 271 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 272 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 273 & ~(1 << 1))); 274 pci_write_config(dev, AGP_INTEL_MCHCFG, 275 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 276 & ~(1 << 1)), 1); 277 278 default: /* Intel Generic (maybe) */ 279 printf("%s: set NBXCFG to %x\n", __func__, 280 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 281 & ~(1 << 9))); 282 pci_write_config(dev, AGP_INTEL_NBXCFG, 283 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 284 & ~(1 << 9)), 4); 285 } 286 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 287 AGP_SET_APERTURE(dev, sc->initial_aperture); 288 agp_free_gatt(sc->gatt); 289 290 return 0; 291 } 292 293 static u_int32_t 294 agp_intel_get_aperture(device_t dev) 295 { 296 struct agp_intel_softc *sc = device_get_softc(dev); 297 u_int32_t apsize; 298 299 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask; 300 301 /* 302 * The size is determined by the number of low bits of 303 * register APBASE which are forced to zero. The low 22 bits 304 * are always forced to zero and each zero bit in the apsize 305 * field just read forces the corresponding bit in the 27:22 306 * to be zero. We calculate the aperture size accordingly. 307 */ 308 return (((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 309 } 310 311 static int 312 agp_intel_set_aperture(device_t dev, u_int32_t aperture) 313 { 314 struct agp_intel_softc *sc = device_get_softc(dev); 315 u_int32_t apsize; 316 317 /* 318 * Reverse the magic from get_aperture. 319 */ 320 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask; 321 322 /* 323 * Double check for sanity. 324 */ 325 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture) 326 return EINVAL; 327 328 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 329 330 return 0; 331 } 332 333 static int 334 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical) 335 { 336 struct agp_intel_softc *sc = device_get_softc(dev); 337 338 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 339 return EINVAL; 340 341 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 342 return 0; 343 } 344 345 static int 346 agp_intel_unbind_page(device_t dev, int offset) 347 { 348 struct agp_intel_softc *sc = device_get_softc(dev); 349 350 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 351 return EINVAL; 352 353 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 354 return 0; 355 } 356 357 static void 358 agp_intel_flush_tlb(device_t dev) 359 { 360 u_int32_t val; 361 362 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 363 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 8), 4); 364 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); 365 } 366 367 static device_method_t agp_intel_methods[] = { 368 /* Device interface */ 369 DEVMETHOD(device_probe, agp_intel_probe), 370 DEVMETHOD(device_attach, agp_intel_attach), 371 DEVMETHOD(device_detach, agp_intel_detach), 372 DEVMETHOD(device_shutdown, bus_generic_shutdown), 373 DEVMETHOD(device_suspend, bus_generic_suspend), 374 DEVMETHOD(device_resume, bus_generic_resume), 375 376 /* AGP interface */ 377 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 378 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 379 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 380 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 381 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 382 DEVMETHOD(agp_enable, agp_generic_enable), 383 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 384 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 385 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 386 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 387 388 { 0, 0 } 389 }; 390 391 static driver_t agp_intel_driver = { 392 "agp", 393 agp_intel_methods, 394 sizeof(struct agp_intel_softc), 395 }; 396 397 static devclass_t agp_devclass; 398 399 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0); 400 MODULE_DEPEND(agp_intel, agp, 1, 1, 1); 401 MODULE_DEPEND(agp_intel, pci, 1, 1, 1);
Cache object: bd3e5a0526c76d47fcb69d3960a528a5
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]