Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/agp_intel.c
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1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD: releng/5.2/sys/pci/agp_intel.c 120144 2003-09-17 02:58:17Z anholt $"); 29 30 #include "opt_bus.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/lock.h> 38 #include <sys/lockmgr.h> 39 #include <sys/mutex.h> 40 #include <sys/proc.h> 41 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <pci/agppriv.h> 45 #include <pci/agpreg.h> 46 47 #include <vm/vm.h> 48 #include <vm/vm_object.h> 49 #include <vm/pmap.h> 50 51 #define MAX_APSIZE 0x3f /* 256 MB */ 52 53 struct agp_intel_softc { 54 struct agp_softc agp; 55 u_int32_t initial_aperture; /* aperture size at startup */ 56 struct agp_gatt *gatt; 57 u_int aperture_mask; 58 }; 59 60 static const char* 61 agp_intel_match(device_t dev) 62 { 63 if (pci_get_class(dev) != PCIC_BRIDGE 64 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 65 return NULL; 66 67 if (agp_find_caps(dev) == 0) 68 return NULL; 69 70 switch (pci_get_devid(dev)) { 71 /* Intel -- vendor 0x8086 */ 72 case 0x71808086: 73 return ("Intel 82443LX (440 LX) host to PCI bridge"); 74 75 case 0x71908086: 76 return ("Intel 82443BX (440 BX) host to PCI bridge"); 77 78 case 0x71a08086: 79 return ("Intel 82443GX host to PCI bridge"); 80 81 case 0x71a18086: 82 return ("Intel 82443GX host to AGP bridge"); 83 84 case 0x11308086: 85 return ("Intel 82815 (i815 GMCH) host to PCI bridge"); 86 87 case 0x25008086: 88 case 0x25018086: 89 return ("Intel 82820 host to AGP bridge"); 90 91 case 0x35758086: 92 return ("Intel 82830 host to AGP bridge"); 93 94 case 0x1a218086: 95 return ("Intel 82840 host to AGP bridge"); 96 97 case 0x1a308086: 98 return ("Intel 82845 host to AGP bridge"); 99 100 case 0x25308086: 101 return ("Intel 82850 host to AGP bridge"); 102 103 case 0x33408086: 104 return ("Intel 82855 host to AGP bridge"); 105 106 case 0x25318086: 107 return ("Intel 82860 host to AGP bridge"); 108 109 case 0x25708086: 110 return ("Intel 82865 host to AGP bridge"); 111 112 case 0x25788086: 113 return ("Intel 82875P host to AGP bridge"); 114 }; 115 116 if (pci_get_vendor(dev) == 0x8086) 117 return ("Intel Generic host to PCI bridge"); 118 119 return NULL; 120 } 121 122 static int 123 agp_intel_probe(device_t dev) 124 { 125 const char *desc; 126 127 desc = agp_intel_match(dev); 128 if (desc) { 129 device_verbose(dev); 130 device_set_desc(dev, desc); 131 return 0; 132 } 133 134 return ENXIO; 135 } 136 137 static int 138 agp_intel_attach(device_t dev) 139 { 140 struct agp_intel_softc *sc = device_get_softc(dev); 141 struct agp_gatt *gatt; 142 u_int32_t type = pci_get_devid(dev); 143 u_int32_t value; 144 int error; 145 146 error = agp_generic_attach(dev); 147 if (error) 148 return error; 149 150 /* Determine maximum supported aperture size. */ 151 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1); 152 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1); 153 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 154 MAX_APSIZE; 155 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1); 156 sc->initial_aperture = AGP_GET_APERTURE(dev); 157 158 for (;;) { 159 gatt = agp_alloc_gatt(dev); 160 if (gatt) 161 break; 162 163 /* 164 * Probably contigmalloc failure. Try reducing the 165 * aperture so that the gatt size reduces. 166 */ 167 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 168 agp_generic_detach(dev); 169 return ENOMEM; 170 } 171 } 172 sc->gatt = gatt; 173 174 /* Install the gatt. */ 175 pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4); 176 177 /* Enable the GLTB and setup the control register. */ 178 switch (type) { 179 case 0x71908086: /* 440LX/EX */ 180 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4); 181 break; 182 case 0x71808086: /* 440BX */ 183 /* 184 * XXX: Should be 0xa080? Bit 9 is undefined, and 185 * bit 13 being on and bit 15 being clear is illegal. 186 */ 187 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 188 break; 189 default: 190 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 191 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4); 192 } 193 194 /* Enable things, clear errors etc. */ 195 switch (type) { 196 case 0x1a218086: /* i840 */ 197 case 0x25308086: /* i850 */ 198 case 0x25318086: /* i860 */ 199 pci_write_config(dev, AGP_INTEL_MCHCFG, 200 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 201 | (1 << 9)), 2); 202 break; 203 204 case 0x25008086: /* i820 */ 205 case 0x25018086: /* i820 */ 206 pci_write_config(dev, AGP_INTEL_I820_RDCR, 207 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 208 | (1 << 1)), 1); 209 break; 210 211 case 0x1a308086: /* i845 */ 212 case 0x33408086: /* i855 */ 213 case 0x25708086: /* i865 */ 214 case 0x25788086: /* i875P */ 215 pci_write_config(dev, AGP_INTEL_I845_MCHCFG, 216 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 217 | (1 << 1)), 1); 218 break; 219 220 default: /* Intel Generic (maybe) */ 221 pci_write_config(dev, AGP_INTEL_NBXCFG, 222 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 223 & ~(1 << 10)) | (1 << 9), 4); 224 } 225 226 switch (type) { 227 case 0x1a218086: /* i840 */ 228 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2); 229 break; 230 231 case 0x25008086: /* i820 */ 232 case 0x25018086: /* i820 */ 233 case 0x1a308086: /* i845 */ 234 case 0x25308086: /* i850 */ 235 case 0x33408086: /* i855 */ 236 case 0x25318086: /* i860 */ 237 case 0x25708086: /* i865 */ 238 case 0x25788086: /* i875P */ 239 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2); 240 break; 241 242 default: /* Intel Generic (maybe) */ 243 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 244 } 245 246 return 0; 247 } 248 249 static int 250 agp_intel_detach(device_t dev) 251 { 252 struct agp_intel_softc *sc = device_get_softc(dev); 253 u_int32_t type = pci_get_devid(dev); 254 int error; 255 256 error = agp_generic_detach(dev); 257 if (error) 258 return error; 259 260 switch (type) { 261 case 0x1a218086: /* i840 */ 262 case 0x25308086: /* i850 */ 263 case 0x25318086: /* i860 */ 264 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 265 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 266 & ~(1 << 9))); 267 pci_write_config(dev, AGP_INTEL_MCHCFG, 268 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 269 & ~(1 << 9)), 2); 270 271 case 0x25008086: /* i820 */ 272 case 0x25018086: /* i820 */ 273 printf("%s: set RDCR to %x\n", __func__, (unsigned) 274 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 275 & ~(1 << 1))); 276 pci_write_config(dev, AGP_INTEL_I820_RDCR, 277 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 278 & ~(1 << 1)), 1); 279 280 case 0x1a308086: /* i845 */ 281 case 0x33408086: /* i855 */ 282 case 0x25708086: /* i865 */ 283 case 0x25788086: /* i875P */ 284 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 285 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 286 & ~(1 << 1))); 287 pci_write_config(dev, AGP_INTEL_MCHCFG, 288 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 289 & ~(1 << 1)), 1); 290 291 default: /* Intel Generic (maybe) */ 292 printf("%s: set NBXCFG to %x\n", __func__, 293 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 294 & ~(1 << 9))); 295 pci_write_config(dev, AGP_INTEL_NBXCFG, 296 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 297 & ~(1 << 9)), 4); 298 } 299 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 300 AGP_SET_APERTURE(dev, sc->initial_aperture); 301 agp_free_gatt(sc->gatt); 302 303 return 0; 304 } 305 306 static u_int32_t 307 agp_intel_get_aperture(device_t dev) 308 { 309 struct agp_intel_softc *sc = device_get_softc(dev); 310 u_int32_t apsize; 311 312 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask; 313 314 /* 315 * The size is determined by the number of low bits of 316 * register APBASE which are forced to zero. The low 22 bits 317 * are always forced to zero and each zero bit in the apsize 318 * field just read forces the corresponding bit in the 27:22 319 * to be zero. We calculate the aperture size accordingly. 320 */ 321 return (((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 322 } 323 324 static int 325 agp_intel_set_aperture(device_t dev, u_int32_t aperture) 326 { 327 struct agp_intel_softc *sc = device_get_softc(dev); 328 u_int32_t apsize; 329 330 /* 331 * Reverse the magic from get_aperture. 332 */ 333 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask; 334 335 /* 336 * Double check for sanity. 337 */ 338 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture) 339 return EINVAL; 340 341 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 342 343 return 0; 344 } 345 346 static int 347 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical) 348 { 349 struct agp_intel_softc *sc = device_get_softc(dev); 350 351 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 352 return EINVAL; 353 354 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 355 return 0; 356 } 357 358 static int 359 agp_intel_unbind_page(device_t dev, int offset) 360 { 361 struct agp_intel_softc *sc = device_get_softc(dev); 362 363 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 364 return EINVAL; 365 366 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 367 return 0; 368 } 369 370 static void 371 agp_intel_flush_tlb(device_t dev) 372 { 373 u_int32_t val; 374 375 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 376 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4); 377 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); 378 } 379 380 static device_method_t agp_intel_methods[] = { 381 /* Device interface */ 382 DEVMETHOD(device_probe, agp_intel_probe), 383 DEVMETHOD(device_attach, agp_intel_attach), 384 DEVMETHOD(device_detach, agp_intel_detach), 385 DEVMETHOD(device_shutdown, bus_generic_shutdown), 386 DEVMETHOD(device_suspend, bus_generic_suspend), 387 DEVMETHOD(device_resume, bus_generic_resume), 388 389 /* AGP interface */ 390 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 391 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 392 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 393 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 394 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 395 DEVMETHOD(agp_enable, agp_generic_enable), 396 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 397 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 398 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 399 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 400 401 { 0, 0 } 402 }; 403 404 static driver_t agp_intel_driver = { 405 "agp", 406 agp_intel_methods, 407 sizeof(struct agp_intel_softc), 408 }; 409 410 static devclass_t agp_devclass; 411 412 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0); 413 MODULE_DEPEND(agp_intel, agp, 1, 1, 1); 414 MODULE_DEPEND(agp_intel, pci, 1, 1, 1);
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