The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/pci/agp_intel.c

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    1 /*-
    2  * Copyright (c) 2000 Doug Rabson
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: releng/5.3/sys/pci/agp_intel.c 129878 2004-05-30 20:00:41Z phk $");
   29 
   30 #include "opt_bus.h"
   31 
   32 #include <sys/param.h>
   33 #include <sys/systm.h>
   34 #include <sys/malloc.h>
   35 #include <sys/kernel.h>
   36 #include <sys/module.h>
   37 #include <sys/bus.h>
   38 #include <sys/lock.h>
   39 #include <sys/mutex.h>
   40 #include <sys/proc.h>
   41 
   42 #include <dev/pci/pcivar.h>
   43 #include <dev/pci/pcireg.h>
   44 #include <pci/agppriv.h>
   45 #include <pci/agpreg.h>
   46 
   47 #include <vm/vm.h>
   48 #include <vm/vm_object.h>
   49 #include <vm/pmap.h>
   50 
   51 #define MAX_APSIZE      0x3f            /* 256 MB */
   52 
   53 struct agp_intel_softc {
   54         struct agp_softc agp;
   55         u_int32_t       initial_aperture; /* aperture size at startup */
   56         struct agp_gatt *gatt;
   57         u_int           aperture_mask;
   58 };
   59 
   60 static const char*
   61 agp_intel_match(device_t dev)
   62 {
   63         if (pci_get_class(dev) != PCIC_BRIDGE
   64             || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
   65                 return NULL;
   66 
   67         if (agp_find_caps(dev) == 0)
   68                 return NULL;
   69 
   70         switch (pci_get_devid(dev)) {
   71         /* Intel -- vendor 0x8086 */
   72         case 0x71808086:
   73                 return ("Intel 82443LX (440 LX) host to PCI bridge");
   74 
   75         case 0x71908086:
   76                 return ("Intel 82443BX (440 BX) host to PCI bridge");
   77 
   78         case 0x71a08086:
   79                 return ("Intel 82443GX host to PCI bridge");
   80 
   81         case 0x71a18086:
   82                 return ("Intel 82443GX host to AGP bridge");
   83 
   84         case 0x11308086:
   85                 return ("Intel 82815 (i815 GMCH) host to PCI bridge");
   86 
   87         case 0x25008086:
   88         case 0x25018086:
   89                 return ("Intel 82820 host to AGP bridge");
   90 
   91         case 0x35758086:
   92                 return ("Intel 82830 host to AGP bridge");
   93 
   94         case 0x1a218086:
   95                 return ("Intel 82840 host to AGP bridge");
   96 
   97         case 0x1a308086:
   98                 return ("Intel 82845 host to AGP bridge");
   99 
  100         case 0x25308086:
  101                 return ("Intel 82850 host to AGP bridge");
  102 
  103         case 0x33408086:
  104                 return ("Intel 82855 host to AGP bridge");
  105 
  106         case 0x25318086:
  107                 return ("Intel 82860 host to AGP bridge");
  108 
  109         case 0x25708086:
  110                 return ("Intel 82865 host to AGP bridge");
  111 
  112         case 0x25788086:
  113                 return ("Intel 82875P host to AGP bridge");
  114 
  115         case 0x25608086: /* i845G */
  116                 return ("Intel 82845G host to AGP bridge");
  117         };
  118 
  119         if (pci_get_vendor(dev) == 0x8086)
  120                 return ("Intel Generic host to PCI bridge");
  121 
  122         return NULL;
  123 }
  124 
  125 static int
  126 agp_intel_probe(device_t dev)
  127 {
  128         const char *desc;
  129 
  130         if (resource_disabled("agp", device_get_unit(dev)))
  131                 return (ENXIO);
  132         desc = agp_intel_match(dev);
  133         if (desc) {
  134                 device_verbose(dev);
  135                 device_set_desc(dev, desc);
  136                 return 0;
  137         }
  138 
  139         return ENXIO;
  140 }
  141 
  142 static int
  143 agp_intel_attach(device_t dev)
  144 {
  145         struct agp_intel_softc *sc = device_get_softc(dev);
  146         struct agp_gatt *gatt;
  147         u_int32_t type = pci_get_devid(dev);
  148         u_int32_t value;
  149         int error;
  150 
  151         error = agp_generic_attach(dev);
  152         if (error)
  153                 return error;
  154 
  155         /* Determine maximum supported aperture size. */
  156         value = pci_read_config(dev, AGP_INTEL_APSIZE, 1);
  157         pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1);
  158         sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) &
  159             MAX_APSIZE;
  160         pci_write_config(dev, AGP_INTEL_APSIZE, value, 1);
  161         sc->initial_aperture = AGP_GET_APERTURE(dev);
  162 
  163         for (;;) {
  164                 gatt = agp_alloc_gatt(dev);
  165                 if (gatt)
  166                         break;
  167 
  168                 /*
  169                  * Probably contigmalloc failure. Try reducing the
  170                  * aperture so that the gatt size reduces.
  171                  */
  172                 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
  173                         agp_generic_detach(dev);
  174                         return ENOMEM;
  175                 }
  176         }
  177         sc->gatt = gatt;
  178 
  179         /* Install the gatt. */
  180         pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
  181 
  182         /* Enable the GLTB and setup the control register. */
  183         switch (type) {
  184         case 0x71908086: /* 440LX/EX */
  185                 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4);
  186                 break;
  187         case 0x71808086: /* 440BX */
  188                 /*
  189                  * XXX: Should be 0xa080?  Bit 9 is undefined, and
  190                  * bit 13 being on and bit 15 being clear is illegal.
  191                  */
  192                 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
  193                 break;
  194         default:
  195                 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
  196                 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
  197         }
  198 
  199         /* Enable things, clear errors etc. */
  200         switch (type) {
  201         case 0x1a218086: /* i840 */
  202         case 0x25308086: /* i850 */
  203         case 0x25318086: /* i860 */
  204                 pci_write_config(dev, AGP_INTEL_MCHCFG,
  205                                  (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
  206                                   | (1 << 9)), 2);
  207                 break;
  208 
  209         case 0x25008086: /* i820 */
  210         case 0x25018086: /* i820 */
  211                 pci_write_config(dev, AGP_INTEL_I820_RDCR,
  212                                  (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
  213                                   | (1 << 1)), 1);
  214                 break;
  215 
  216         case 0x1a308086: /* i845 */
  217         case 0x33408086: /* i855 */
  218         case 0x25708086: /* i865 */
  219         case 0x25788086: /* i875P */
  220         case 0x25608086: /* i845G */
  221                 pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
  222                                  (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
  223                                   | (1 << 1)), 1);
  224                 break;
  225 
  226         default: /* Intel Generic (maybe) */
  227                 pci_write_config(dev, AGP_INTEL_NBXCFG,
  228                                  (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
  229                                   & ~(1 << 10)) | (1 << 9), 4);
  230         }
  231 
  232         switch (type) {
  233         case 0x1a218086: /* i840 */
  234                 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
  235                 break;
  236 
  237         case 0x25008086: /* i820 */
  238         case 0x25018086: /* i820 */
  239         case 0x1a308086: /* i845 */
  240         case 0x25308086: /* i850 */
  241         case 0x33408086: /* i855 */
  242         case 0x25318086: /* i860 */
  243         case 0x25708086: /* i865 */
  244         case 0x25788086: /* i875P */
  245         case 0x25608086: /* i845G */
  246                 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
  247                 break;
  248 
  249         default: /* Intel Generic (maybe) */
  250                 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
  251         }
  252 
  253         return 0;
  254 }
  255 
  256 static int
  257 agp_intel_detach(device_t dev)
  258 {
  259         struct agp_intel_softc *sc = device_get_softc(dev);
  260         u_int32_t type = pci_get_devid(dev);
  261         int error;
  262 
  263         error = agp_generic_detach(dev);
  264         if (error)
  265                 return error;
  266 
  267         switch (type) {
  268         case 0x1a218086: /* i840 */
  269         case 0x25308086: /* i850 */
  270         case 0x25318086: /* i860 */
  271                 printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
  272                                 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
  273                                 & ~(1 << 9)));
  274                 pci_write_config(dev, AGP_INTEL_MCHCFG,
  275                                 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
  276                                 & ~(1 << 9)), 2);
  277 
  278         case 0x25008086: /* i820 */
  279         case 0x25018086: /* i820 */
  280                 printf("%s: set RDCR to %x\n", __func__, (unsigned)
  281                                 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
  282                                 & ~(1 << 1)));
  283                 pci_write_config(dev, AGP_INTEL_I820_RDCR,
  284                                 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
  285                                 & ~(1 << 1)), 1);
  286 
  287         case 0x1a308086: /* i845 */
  288         case 0x25608086: /* i845G */
  289         case 0x33408086: /* i855 */
  290         case 0x25708086: /* i865 */
  291         case 0x25788086: /* i875P */
  292                 printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
  293                                 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
  294                                 & ~(1 << 1)));
  295                 pci_write_config(dev, AGP_INTEL_MCHCFG,
  296                                 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
  297                                 & ~(1 << 1)), 1);
  298 
  299         default: /* Intel Generic (maybe) */
  300                 printf("%s: set NBXCFG to %x\n", __func__,
  301                                  (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
  302                                   & ~(1 << 9)));
  303                 pci_write_config(dev, AGP_INTEL_NBXCFG,
  304                                  (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
  305                                   & ~(1 << 9)), 4);
  306         }
  307         pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
  308         AGP_SET_APERTURE(dev, sc->initial_aperture);
  309         agp_free_gatt(sc->gatt);
  310 
  311         return 0;
  312 }
  313 
  314 static u_int32_t
  315 agp_intel_get_aperture(device_t dev)
  316 {
  317         struct agp_intel_softc *sc = device_get_softc(dev);
  318         u_int32_t apsize;
  319 
  320         apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask;
  321 
  322         /*
  323          * The size is determined by the number of low bits of
  324          * register APBASE which are forced to zero. The low 22 bits
  325          * are always forced to zero and each zero bit in the apsize
  326          * field just read forces the corresponding bit in the 27:22
  327          * to be zero. We calculate the aperture size accordingly.
  328          */
  329         return (((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1;
  330 }
  331 
  332 static int
  333 agp_intel_set_aperture(device_t dev, u_int32_t aperture)
  334 {
  335         struct agp_intel_softc *sc = device_get_softc(dev);
  336         u_int32_t apsize;
  337 
  338         /*
  339          * Reverse the magic from get_aperture.
  340          */
  341         apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask;
  342 
  343         /*
  344          * Double check for sanity.
  345          */
  346         if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture)
  347                 return EINVAL;
  348 
  349         pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1);
  350 
  351         return 0;
  352 }
  353 
  354 static int
  355 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical)
  356 {
  357         struct agp_intel_softc *sc = device_get_softc(dev);
  358 
  359         if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
  360                 return EINVAL;
  361 
  362         sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17;
  363         return 0;
  364 }
  365 
  366 static int
  367 agp_intel_unbind_page(device_t dev, int offset)
  368 {
  369         struct agp_intel_softc *sc = device_get_softc(dev);
  370 
  371         if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
  372                 return EINVAL;
  373 
  374         sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
  375         return 0;
  376 }
  377 
  378 static void
  379 agp_intel_flush_tlb(device_t dev)
  380 {
  381         u_int32_t val;
  382 
  383         val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
  384         pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4);
  385         pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4);
  386 }
  387 
  388 static device_method_t agp_intel_methods[] = {
  389         /* Device interface */
  390         DEVMETHOD(device_probe,         agp_intel_probe),
  391         DEVMETHOD(device_attach,        agp_intel_attach),
  392         DEVMETHOD(device_detach,        agp_intel_detach),
  393         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  394         DEVMETHOD(device_suspend,       bus_generic_suspend),
  395         DEVMETHOD(device_resume,        bus_generic_resume),
  396 
  397         /* AGP interface */
  398         DEVMETHOD(agp_get_aperture,     agp_intel_get_aperture),
  399         DEVMETHOD(agp_set_aperture,     agp_intel_set_aperture),
  400         DEVMETHOD(agp_bind_page,        agp_intel_bind_page),
  401         DEVMETHOD(agp_unbind_page,      agp_intel_unbind_page),
  402         DEVMETHOD(agp_flush_tlb,        agp_intel_flush_tlb),
  403         DEVMETHOD(agp_enable,           agp_generic_enable),
  404         DEVMETHOD(agp_alloc_memory,     agp_generic_alloc_memory),
  405         DEVMETHOD(agp_free_memory,      agp_generic_free_memory),
  406         DEVMETHOD(agp_bind_memory,      agp_generic_bind_memory),
  407         DEVMETHOD(agp_unbind_memory,    agp_generic_unbind_memory),
  408 
  409         { 0, 0 }
  410 };
  411 
  412 static driver_t agp_intel_driver = {
  413         "agp",
  414         agp_intel_methods,
  415         sizeof(struct agp_intel_softc),
  416 };
  417 
  418 static devclass_t agp_devclass;
  419 
  420 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0);
  421 MODULE_DEPEND(agp_intel, agp, 1, 1, 1);
  422 MODULE_DEPEND(agp_intel, pci, 1, 1, 1);

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