FreeBSD/Linux Kernel Cross Reference
sys/pci/agp_intel.c
1 /*-
2 * Copyright (c) 2000 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: releng/6.1/sys/pci/agp_intel.c 153398 2005-12-14 00:46:23Z anholt $");
29
30 #include "opt_bus.h"
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/malloc.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/bus.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/proc.h>
41
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
44 #include <pci/agppriv.h>
45 #include <pci/agpreg.h>
46
47 #include <vm/vm.h>
48 #include <vm/vm_object.h>
49 #include <vm/pmap.h>
50
51 #define MAX_APSIZE 0x3f /* 256 MB */
52
53 struct agp_intel_softc {
54 struct agp_softc agp;
55 u_int32_t initial_aperture; /* aperture size at startup */
56 struct agp_gatt *gatt;
57 u_int aperture_mask;
58 };
59
60 static const char*
61 agp_intel_match(device_t dev)
62 {
63 if (pci_get_class(dev) != PCIC_BRIDGE
64 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
65 return NULL;
66
67 if (agp_find_caps(dev) == 0)
68 return NULL;
69
70 switch (pci_get_devid(dev)) {
71 /* Intel -- vendor 0x8086 */
72 case 0x71808086:
73 return ("Intel 82443LX (440 LX) host to PCI bridge");
74
75 case 0x71908086:
76 return ("Intel 82443BX (440 BX) host to PCI bridge");
77
78 case 0x71a08086:
79 return ("Intel 82443GX host to PCI bridge");
80
81 case 0x71a18086:
82 return ("Intel 82443GX host to AGP bridge");
83
84 case 0x11308086:
85 return ("Intel 82815 (i815 GMCH) host to PCI bridge");
86
87 case 0x25008086:
88 case 0x25018086:
89 return ("Intel 82820 host to AGP bridge");
90
91 case 0x35758086:
92 return ("Intel 82830 host to AGP bridge");
93
94 case 0x1a218086:
95 return ("Intel 82840 host to AGP bridge");
96
97 case 0x1a308086:
98 return ("Intel 82845 host to AGP bridge");
99
100 case 0x25308086:
101 return ("Intel 82850 host to AGP bridge");
102
103 case 0x33408086:
104 return ("Intel 82855 host to AGP bridge");
105
106 case 0x25318086:
107 return ("Intel 82860 host to AGP bridge");
108
109 case 0x25708086:
110 return ("Intel 82865 host to AGP bridge");
111
112 case 0x255d8086:
113 return ("Intel E7205 host to AGP bridge");
114
115 case 0x25788086:
116 return ("Intel 82875P host to AGP bridge");
117
118 case 0x25608086:
119 return ("Intel 82845G host to AGP bridge");
120
121 case 0x35808086:
122 return ("Intel 82855GM host to AGP bridge");
123 };
124
125 return NULL;
126 }
127
128 static int
129 agp_intel_probe(device_t dev)
130 {
131 const char *desc;
132
133 if (resource_disabled("agp", device_get_unit(dev)))
134 return (ENXIO);
135 desc = agp_intel_match(dev);
136 if (desc) {
137 device_verbose(dev);
138 device_set_desc(dev, desc);
139 return BUS_PROBE_DEFAULT;
140 }
141
142 return ENXIO;
143 }
144
145 static int
146 agp_intel_attach(device_t dev)
147 {
148 struct agp_intel_softc *sc = device_get_softc(dev);
149 struct agp_gatt *gatt;
150 u_int32_t type = pci_get_devid(dev);
151 u_int32_t value;
152 int error;
153
154 error = agp_generic_attach(dev);
155 if (error)
156 return error;
157
158 /* Determine maximum supported aperture size. */
159 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1);
160 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1);
161 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) &
162 MAX_APSIZE;
163 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1);
164 sc->initial_aperture = AGP_GET_APERTURE(dev);
165
166 for (;;) {
167 gatt = agp_alloc_gatt(dev);
168 if (gatt)
169 break;
170
171 /*
172 * Probably contigmalloc failure. Try reducing the
173 * aperture so that the gatt size reduces.
174 */
175 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
176 agp_generic_detach(dev);
177 return ENOMEM;
178 }
179 }
180 sc->gatt = gatt;
181
182 /* Install the gatt. */
183 pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
184
185 /* Enable the GLTB and setup the control register. */
186 switch (type) {
187 case 0x71908086: /* 440LX/EX */
188 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4);
189 break;
190 case 0x71808086: /* 440BX */
191 /*
192 * XXX: Should be 0xa080? Bit 9 is undefined, and
193 * bit 13 being on and bit 15 being clear is illegal.
194 */
195 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
196 break;
197 default:
198 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
199 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
200 }
201
202 /* Enable things, clear errors etc. */
203 switch (type) {
204 case 0x1a218086: /* i840 */
205 case 0x25308086: /* i850 */
206 case 0x25318086: /* i860 */
207 pci_write_config(dev, AGP_INTEL_MCHCFG,
208 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
209 | (1 << 9)), 2);
210 break;
211
212 case 0x25008086: /* i820 */
213 case 0x25018086: /* i820 */
214 pci_write_config(dev, AGP_INTEL_I820_RDCR,
215 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
216 | (1 << 1)), 1);
217 break;
218
219 case 0x1a308086: /* i845 */
220 case 0x33408086: /* i855 */
221 case 0x35808086: /* i855GM */
222 case 0x255d8086: /* E7205 */
223 case 0x25708086: /* i865 */
224 case 0x25788086: /* i875P */
225 case 0x25608086: /* i845G */
226 pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
227 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
228 | (1 << 1)), 1);
229 break;
230
231 default: /* Intel Generic (maybe) */
232 pci_write_config(dev, AGP_INTEL_NBXCFG,
233 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
234 & ~(1 << 10)) | (1 << 9), 4);
235 }
236
237 switch (type) {
238 case 0x1a218086: /* i840 */
239 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
240 break;
241
242 case 0x25008086: /* i820 */
243 case 0x25018086: /* i820 */
244 case 0x1a308086: /* i845 */
245 case 0x25308086: /* i850 */
246 case 0x33408086: /* i855 */
247 case 0x255d8086: /* E7205 */
248 case 0x25318086: /* i860 */
249 case 0x25708086: /* i865 */
250 case 0x25788086: /* i875P */
251 case 0x25608086: /* i845G */
252 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
253 break;
254
255 default: /* Intel Generic (maybe) */
256 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
257 }
258
259 return 0;
260 }
261
262 static int
263 agp_intel_detach(device_t dev)
264 {
265 struct agp_intel_softc *sc = device_get_softc(dev);
266 u_int32_t type = pci_get_devid(dev);
267 int error;
268
269 error = agp_generic_detach(dev);
270 if (error)
271 return error;
272
273 switch (type) {
274 case 0x1a218086: /* i840 */
275 case 0x25308086: /* i850 */
276 case 0x25318086: /* i860 */
277 printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
278 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
279 & ~(1 << 9)));
280 pci_write_config(dev, AGP_INTEL_MCHCFG,
281 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
282 & ~(1 << 9)), 2);
283
284 case 0x25008086: /* i820 */
285 case 0x25018086: /* i820 */
286 printf("%s: set RDCR to %x\n", __func__, (unsigned)
287 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
288 & ~(1 << 1)));
289 pci_write_config(dev, AGP_INTEL_I820_RDCR,
290 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
291 & ~(1 << 1)), 1);
292
293 case 0x1a308086: /* i845 */
294 case 0x25608086: /* i845G */
295 case 0x33408086: /* i855 */
296 case 0x35808086: /* i855GM */
297 case 0x255d8086: /* E7205 */
298 case 0x25708086: /* i865 */
299 case 0x25788086: /* i875P */
300 printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
301 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
302 & ~(1 << 1)));
303 pci_write_config(dev, AGP_INTEL_MCHCFG,
304 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
305 & ~(1 << 1)), 1);
306
307 default: /* Intel Generic (maybe) */
308 printf("%s: set NBXCFG to %x\n", __func__,
309 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
310 & ~(1 << 9)));
311 pci_write_config(dev, AGP_INTEL_NBXCFG,
312 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
313 & ~(1 << 9)), 4);
314 }
315 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
316 AGP_SET_APERTURE(dev, sc->initial_aperture);
317 agp_free_gatt(sc->gatt);
318
319 return 0;
320 }
321
322 static u_int32_t
323 agp_intel_get_aperture(device_t dev)
324 {
325 struct agp_intel_softc *sc = device_get_softc(dev);
326 u_int32_t apsize;
327
328 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask;
329
330 /*
331 * The size is determined by the number of low bits of
332 * register APBASE which are forced to zero. The low 22 bits
333 * are always forced to zero and each zero bit in the apsize
334 * field just read forces the corresponding bit in the 27:22
335 * to be zero. We calculate the aperture size accordingly.
336 */
337 return (((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1;
338 }
339
340 static int
341 agp_intel_set_aperture(device_t dev, u_int32_t aperture)
342 {
343 struct agp_intel_softc *sc = device_get_softc(dev);
344 u_int32_t apsize;
345
346 /*
347 * Reverse the magic from get_aperture.
348 */
349 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask;
350
351 /*
352 * Double check for sanity.
353 */
354 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture)
355 return EINVAL;
356
357 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1);
358
359 return 0;
360 }
361
362 static int
363 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical)
364 {
365 struct agp_intel_softc *sc = device_get_softc(dev);
366
367 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
368 return EINVAL;
369
370 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17;
371 return 0;
372 }
373
374 static int
375 agp_intel_unbind_page(device_t dev, int offset)
376 {
377 struct agp_intel_softc *sc = device_get_softc(dev);
378
379 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
380 return EINVAL;
381
382 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
383 return 0;
384 }
385
386 static void
387 agp_intel_flush_tlb(device_t dev)
388 {
389 u_int32_t val;
390
391 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
392 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4);
393 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4);
394 }
395
396 static device_method_t agp_intel_methods[] = {
397 /* Device interface */
398 DEVMETHOD(device_probe, agp_intel_probe),
399 DEVMETHOD(device_attach, agp_intel_attach),
400 DEVMETHOD(device_detach, agp_intel_detach),
401 DEVMETHOD(device_shutdown, bus_generic_shutdown),
402 DEVMETHOD(device_suspend, bus_generic_suspend),
403 DEVMETHOD(device_resume, bus_generic_resume),
404
405 /* AGP interface */
406 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture),
407 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture),
408 DEVMETHOD(agp_bind_page, agp_intel_bind_page),
409 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page),
410 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb),
411 DEVMETHOD(agp_enable, agp_generic_enable),
412 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
413 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
414 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
415 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
416
417 { 0, 0 }
418 };
419
420 static driver_t agp_intel_driver = {
421 "agp",
422 agp_intel_methods,
423 sizeof(struct agp_intel_softc),
424 };
425
426 static devclass_t agp_devclass;
427
428 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0);
429 MODULE_DEPEND(agp_intel, agp, 1, 1, 1);
430 MODULE_DEPEND(agp_intel, pci, 1, 1, 1);
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