Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/pci/agp_intel.c
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1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD: releng/6.4/sys/pci/agp_intel.c 173478 2007-11-08 20:50:13Z jhb $"); 29 30 #include "opt_bus.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/proc.h> 41 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <pci/agppriv.h> 45 #include <pci/agpreg.h> 46 47 #include <vm/vm.h> 48 #include <vm/vm_object.h> 49 #include <vm/pmap.h> 50 51 #define MAX_APSIZE 0x3f /* 256 MB */ 52 53 struct agp_intel_softc { 54 struct agp_softc agp; 55 u_int32_t initial_aperture; /* aperture size at startup */ 56 struct agp_gatt *gatt; 57 u_int aperture_mask; 58 }; 59 60 static const char* 61 agp_intel_match(device_t dev) 62 { 63 if (pci_get_class(dev) != PCIC_BRIDGE 64 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 65 return NULL; 66 67 if (agp_find_caps(dev) == 0) 68 return NULL; 69 70 switch (pci_get_devid(dev)) { 71 /* Intel -- vendor 0x8086 */ 72 case 0x71808086: 73 return ("Intel 82443LX (440 LX) host to PCI bridge"); 74 75 case 0x71908086: 76 return ("Intel 82443BX (440 BX) host to PCI bridge"); 77 78 case 0x71a08086: 79 return ("Intel 82443GX host to PCI bridge"); 80 81 case 0x71a18086: 82 return ("Intel 82443GX host to AGP bridge"); 83 84 case 0x11308086: 85 return ("Intel 82815 (i815 GMCH) host to PCI bridge"); 86 87 case 0x25008086: 88 case 0x25018086: 89 return ("Intel 82820 host to AGP bridge"); 90 91 case 0x35758086: 92 return ("Intel 82830 host to AGP bridge"); 93 94 case 0x1a218086: 95 return ("Intel 82840 host to AGP bridge"); 96 97 case 0x1a308086: 98 return ("Intel 82845 host to AGP bridge"); 99 100 case 0x25308086: 101 return ("Intel 82850 host to AGP bridge"); 102 103 case 0x33408086: 104 return ("Intel 82855 host to AGP bridge"); 105 106 case 0x25318086: 107 return ("Intel 82860 host to AGP bridge"); 108 109 case 0x25708086: 110 return ("Intel 82865 host to AGP bridge"); 111 112 case 0x255d8086: 113 return ("Intel E7205 host to AGP bridge"); 114 115 case 0x25508086: 116 return ("Intel E7505 host to AGP bridge"); 117 118 case 0x25788086: 119 return ("Intel 82875P host to AGP bridge"); 120 121 case 0x25608086: 122 return ("Intel 82845G host to AGP bridge"); 123 124 case 0x35808086: 125 return ("Intel 82855GM host to AGP bridge"); 126 }; 127 128 return NULL; 129 } 130 131 static int 132 agp_intel_probe(device_t dev) 133 { 134 const char *desc; 135 136 if (resource_disabled("agp", device_get_unit(dev))) 137 return (ENXIO); 138 desc = agp_intel_match(dev); 139 if (desc) { 140 device_verbose(dev); 141 device_set_desc(dev, desc); 142 return BUS_PROBE_DEFAULT; 143 } 144 145 return ENXIO; 146 } 147 148 static int 149 agp_intel_attach(device_t dev) 150 { 151 struct agp_intel_softc *sc = device_get_softc(dev); 152 struct agp_gatt *gatt; 153 u_int32_t type = pci_get_devid(dev); 154 u_int32_t value; 155 int error; 156 157 error = agp_generic_attach(dev); 158 if (error) 159 return error; 160 161 /* Determine maximum supported aperture size. */ 162 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1); 163 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1); 164 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 165 MAX_APSIZE; 166 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1); 167 sc->initial_aperture = AGP_GET_APERTURE(dev); 168 169 for (;;) { 170 gatt = agp_alloc_gatt(dev); 171 if (gatt) 172 break; 173 174 /* 175 * Probably contigmalloc failure. Try reducing the 176 * aperture so that the gatt size reduces. 177 */ 178 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 179 agp_generic_detach(dev); 180 return ENOMEM; 181 } 182 } 183 sc->gatt = gatt; 184 185 /* Install the gatt. */ 186 pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4); 187 188 /* Enable the GLTB and setup the control register. */ 189 switch (type) { 190 case 0x71908086: /* 440LX/EX */ 191 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4); 192 break; 193 case 0x71808086: /* 440BX */ 194 /* 195 * XXX: Should be 0xa080? Bit 9 is undefined, and 196 * bit 13 being on and bit 15 being clear is illegal. 197 */ 198 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 199 break; 200 default: 201 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 202 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4); 203 } 204 205 /* Enable things, clear errors etc. */ 206 switch (type) { 207 case 0x1a218086: /* i840 */ 208 case 0x25308086: /* i850 */ 209 case 0x25318086: /* i860 */ 210 pci_write_config(dev, AGP_INTEL_MCHCFG, 211 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 212 | (1 << 9)), 2); 213 break; 214 215 case 0x25008086: /* i820 */ 216 case 0x25018086: /* i820 */ 217 pci_write_config(dev, AGP_INTEL_I820_RDCR, 218 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 219 | (1 << 1)), 1); 220 break; 221 222 case 0x1a308086: /* i845 */ 223 case 0x33408086: /* i855 */ 224 case 0x35808086: /* i855GM */ 225 case 0x255d8086: /* E7205 */ 226 case 0x25508086: /* E7505 */ 227 case 0x25708086: /* i865 */ 228 case 0x25788086: /* i875P */ 229 case 0x25608086: /* i845G */ 230 pci_write_config(dev, AGP_INTEL_I845_MCHCFG, 231 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 232 | (1 << 1)), 1); 233 break; 234 235 default: /* Intel Generic (maybe) */ 236 pci_write_config(dev, AGP_INTEL_NBXCFG, 237 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 238 & ~(1 << 10)) | (1 << 9), 4); 239 } 240 241 switch (type) { 242 case 0x1a218086: /* i840 */ 243 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2); 244 break; 245 246 case 0x25008086: /* i820 */ 247 case 0x25018086: /* i820 */ 248 case 0x1a308086: /* i845 */ 249 case 0x25308086: /* i850 */ 250 case 0x33408086: /* i855 */ 251 case 0x255d8086: /* E7205 */ 252 case 0x25508086: /* E7505 */ 253 case 0x25318086: /* i860 */ 254 case 0x25708086: /* i865 */ 255 case 0x25788086: /* i875P */ 256 case 0x25608086: /* i845G */ 257 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2); 258 break; 259 260 default: /* Intel Generic (maybe) */ 261 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 262 } 263 264 return 0; 265 } 266 267 static int 268 agp_intel_detach(device_t dev) 269 { 270 struct agp_intel_softc *sc = device_get_softc(dev); 271 u_int32_t type = pci_get_devid(dev); 272 273 agp_free_cdev(dev); 274 275 switch (type) { 276 case 0x1a218086: /* i840 */ 277 case 0x25308086: /* i850 */ 278 case 0x25318086: /* i860 */ 279 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 280 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 281 & ~(1 << 9))); 282 pci_write_config(dev, AGP_INTEL_MCHCFG, 283 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 284 & ~(1 << 9)), 2); 285 286 case 0x25008086: /* i820 */ 287 case 0x25018086: /* i820 */ 288 printf("%s: set RDCR to %x\n", __func__, (unsigned) 289 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 290 & ~(1 << 1))); 291 pci_write_config(dev, AGP_INTEL_I820_RDCR, 292 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 293 & ~(1 << 1)), 1); 294 295 case 0x1a308086: /* i845 */ 296 case 0x25608086: /* i845G */ 297 case 0x33408086: /* i855 */ 298 case 0x35808086: /* i855GM */ 299 case 0x255d8086: /* E7205 */ 300 case 0x25508086: /* E7505 */ 301 case 0x25708086: /* i865 */ 302 case 0x25788086: /* i875P */ 303 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 304 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 305 & ~(1 << 1))); 306 pci_write_config(dev, AGP_INTEL_MCHCFG, 307 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 308 & ~(1 << 1)), 1); 309 310 default: /* Intel Generic (maybe) */ 311 printf("%s: set NBXCFG to %x\n", __func__, 312 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 313 & ~(1 << 9))); 314 pci_write_config(dev, AGP_INTEL_NBXCFG, 315 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 316 & ~(1 << 9)), 4); 317 } 318 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 319 AGP_SET_APERTURE(dev, sc->initial_aperture); 320 agp_free_gatt(sc->gatt); 321 agp_free_res(dev); 322 323 return 0; 324 } 325 326 static u_int32_t 327 agp_intel_get_aperture(device_t dev) 328 { 329 struct agp_intel_softc *sc = device_get_softc(dev); 330 u_int32_t apsize; 331 332 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask; 333 334 /* 335 * The size is determined by the number of low bits of 336 * register APBASE which are forced to zero. The low 22 bits 337 * are always forced to zero and each zero bit in the apsize 338 * field just read forces the corresponding bit in the 27:22 339 * to be zero. We calculate the aperture size accordingly. 340 */ 341 return (((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 342 } 343 344 static int 345 agp_intel_set_aperture(device_t dev, u_int32_t aperture) 346 { 347 struct agp_intel_softc *sc = device_get_softc(dev); 348 u_int32_t apsize; 349 350 /* 351 * Reverse the magic from get_aperture. 352 */ 353 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask; 354 355 /* 356 * Double check for sanity. 357 */ 358 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture) 359 return EINVAL; 360 361 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 362 363 return 0; 364 } 365 366 static int 367 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical) 368 { 369 struct agp_intel_softc *sc = device_get_softc(dev); 370 371 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 372 return EINVAL; 373 374 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 375 return 0; 376 } 377 378 static int 379 agp_intel_unbind_page(device_t dev, int offset) 380 { 381 struct agp_intel_softc *sc = device_get_softc(dev); 382 383 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 384 return EINVAL; 385 386 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 387 return 0; 388 } 389 390 static void 391 agp_intel_flush_tlb(device_t dev) 392 { 393 u_int32_t val; 394 395 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 396 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4); 397 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); 398 } 399 400 static device_method_t agp_intel_methods[] = { 401 /* Device interface */ 402 DEVMETHOD(device_probe, agp_intel_probe), 403 DEVMETHOD(device_attach, agp_intel_attach), 404 DEVMETHOD(device_detach, agp_intel_detach), 405 DEVMETHOD(device_shutdown, bus_generic_shutdown), 406 DEVMETHOD(device_suspend, bus_generic_suspend), 407 DEVMETHOD(device_resume, bus_generic_resume), 408 409 /* AGP interface */ 410 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 411 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 412 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 413 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 414 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 415 DEVMETHOD(agp_enable, agp_generic_enable), 416 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 417 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 418 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 419 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 420 421 { 0, 0 } 422 }; 423 424 static driver_t agp_intel_driver = { 425 "agp", 426 agp_intel_methods, 427 sizeof(struct agp_intel_softc), 428 }; 429 430 static devclass_t agp_devclass; 431 432 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0); 433 MODULE_DEPEND(agp_intel, agp, 1, 1, 1); 434 MODULE_DEPEND(agp_intel, pci, 1, 1, 1);
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