Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/agp_nvidia.c
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1 /*- 2 * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: releng/5.2/sys/pci/agp_nvidia.c 119371 2003-08-23 19:32:18Z mdodd $ 27 */ 28 29 /* 30 * Written using information gleaned from the 31 * NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch. 32 */ 33 34 #include "opt_bus.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/bus.h> 41 #include <sys/lock.h> 42 43 #if __FreeBSD_version < 500000 44 #include "opt_pci.h" 45 #endif 46 47 #if __FreeBSD_version > 500000 48 #include <sys/lockmgr.h> 49 #include <sys/mutex.h> 50 #include <sys/proc.h> 51 #endif 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <pci/agppriv.h> 56 #include <pci/agpreg.h> 57 58 #include <vm/vm.h> 59 #include <vm/vm_object.h> 60 #include <vm/pmap.h> 61 62 #include <machine/bus.h> 63 #include <machine/resource.h> 64 #include <sys/rman.h> 65 66 #define NVIDIA_VENDORID 0x10de 67 #define NVIDIA_DEVICEID_NFORCE 0x01a4 68 #define NVIDIA_DEVICEID_NFORCE2 0x01e0 69 70 struct agp_nvidia_softc { 71 struct agp_softc agp; 72 u_int32_t initial_aperture; /* aperture size at startup */ 73 struct agp_gatt * gatt; 74 75 device_t dev; /* AGP Controller */ 76 device_t mc1_dev; /* Memory Controller */ 77 device_t mc2_dev; /* Memory Controller */ 78 device_t bdev; /* Bridge */ 79 80 u_int32_t wbc_mask; 81 int num_dirs; 82 int num_active_entries; 83 off_t pg_offset; 84 }; 85 86 static const char * agp_nvidia_match (device_t dev); 87 static int agp_nvidia_probe (device_t); 88 static int agp_nvidia_attach (device_t); 89 static int agp_nvidia_detach (device_t); 90 static u_int32_t agp_nvidia_get_aperture (device_t); 91 static int agp_nvidia_set_aperture (device_t, u_int32_t); 92 static int agp_nvidia_bind_page (device_t, int, vm_offset_t); 93 static int agp_nvidia_unbind_page (device_t, int); 94 95 static int nvidia_init_iorr (u_int32_t, u_int32_t); 96 97 static const char * 98 agp_nvidia_match (device_t dev) 99 { 100 if (pci_get_class(dev) != PCIC_BRIDGE || 101 pci_get_subclass(dev) != PCIS_BRIDGE_HOST || 102 pci_get_vendor(dev) != NVIDIA_VENDORID) 103 return (NULL); 104 105 switch (pci_get_device(dev)) { 106 case NVIDIA_DEVICEID_NFORCE: 107 return ("NVIDIA nForce AGP Controller"); 108 case NVIDIA_DEVICEID_NFORCE2: 109 return ("NVIDIA nForce2 AGP Controller"); 110 } 111 return ("NVIDIA Generic AGP Controller"); 112 } 113 114 static int 115 agp_nvidia_probe (device_t dev) 116 { 117 const char *desc; 118 119 desc = agp_nvidia_match(dev); 120 if (desc) { 121 device_verbose(dev); 122 device_set_desc(dev, desc); 123 return (0); 124 } 125 return (ENXIO); 126 } 127 128 static int 129 agp_nvidia_attach (device_t dev) 130 { 131 struct agp_nvidia_softc *sc = device_get_softc(dev); 132 struct agp_gatt *gatt; 133 u_int32_t apbase; 134 u_int32_t aplimit; 135 u_int32_t temp; 136 int size; 137 int i; 138 int error; 139 140 switch (pci_get_device(dev)) { 141 case NVIDIA_DEVICEID_NFORCE: 142 sc->wbc_mask = 0x00010000; 143 break; 144 case NVIDIA_DEVICEID_NFORCE2: 145 sc->wbc_mask = 0x80000000; 146 break; 147 default: 148 sc->wbc_mask = 0; 149 break; 150 } 151 152 /* AGP Controller */ 153 sc->dev = dev; 154 155 /* Memory Controller 1 */ 156 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1); 157 if (sc->mc1_dev == NULL) { 158 device_printf(dev, 159 "Unable to find NVIDIA Memory Controller 1.\n"); 160 return (ENODEV); 161 } 162 163 /* Memory Controller 2 */ 164 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2); 165 if (sc->mc2_dev == NULL) { 166 device_printf(dev, 167 "Unable to find NVIDIA Memory Controller 2.\n"); 168 return (ENODEV); 169 } 170 171 /* AGP Host to PCI Bridge */ 172 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0); 173 if (sc->bdev == NULL) { 174 device_printf(dev, 175 "Unable to find NVIDIA AGP Host to PCI Bridge.\n"); 176 return (ENODEV); 177 } 178 179 error = agp_generic_attach(dev); 180 if (error) 181 return (error); 182 183 sc->initial_aperture = AGP_GET_APERTURE(dev); 184 185 for (;;) { 186 gatt = agp_alloc_gatt(dev); 187 if (gatt) 188 break; 189 /* 190 * Probably contigmalloc failure. Try reducing the 191 * aperture so that the gatt size reduces. 192 */ 193 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) 194 goto fail; 195 } 196 sc->gatt = gatt; 197 198 apbase = rman_get_start(sc->agp.as_aperture); 199 aplimit = apbase + AGP_GET_APERTURE(dev) - 1; 200 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4); 201 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4); 202 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4); 203 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4); 204 205 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev)); 206 if (error) { 207 device_printf(dev, "Failed to setup IORRs\n"); 208 goto fail; 209 } 210 211 /* directory size is 64k */ 212 size = AGP_GET_APERTURE(dev) / 1024 / 1024; 213 sc->num_dirs = size / 64; 214 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4); 215 sc->pg_offset = 0; 216 if (sc->num_dirs == 0) { 217 sc->num_dirs = 1; 218 sc->num_active_entries /= (64 / size); 219 sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) & 220 ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE; 221 } 222 223 /* (G)ATT Base Address */ 224 for (i = 0; i < 8; i++) { 225 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i), 226 (sc->gatt->ag_physical + 227 (i % sc->num_dirs) * 64 * 1024), 228 4); 229 } 230 231 /* GTLB Control */ 232 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4); 233 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4); 234 235 /* GART Control */ 236 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4); 237 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4); 238 239 return (0); 240 fail: 241 agp_generic_detach(dev); 242 return (ENOMEM); 243 } 244 245 static int 246 agp_nvidia_detach (device_t dev) 247 { 248 struct agp_nvidia_softc *sc = device_get_softc(dev); 249 int error; 250 u_int32_t temp; 251 252 error = agp_generic_detach(dev); 253 if (error) 254 return (error); 255 256 /* GART Control */ 257 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4); 258 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4); 259 260 /* GTLB Control */ 261 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4); 262 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4); 263 264 /* Put the aperture back the way it started. */ 265 AGP_SET_APERTURE(dev, sc->initial_aperture); 266 267 /* restore iorr for previous aperture size */ 268 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture), 269 sc->initial_aperture); 270 271 agp_free_gatt(sc->gatt); 272 273 return (0); 274 } 275 276 static u_int32_t 277 agp_nvidia_get_aperture(device_t dev) 278 { 279 u_int8_t key; 280 281 key = ffs(pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f); 282 return (1 << (24 + (key ? key : 5))); 283 } 284 285 static int 286 agp_nvidia_set_aperture(device_t dev, u_int32_t aperture) 287 { 288 u_int8_t val; 289 u_int8_t key; 290 291 switch (aperture) { 292 case (512 * 1024 * 1024): key = 0; break; 293 case (256 * 1024 * 1024): key = 8; break; 294 case (128 * 1024 * 1024): key = 12; break; 295 case (64 * 1024 * 1024): key = 14; break; 296 case (32 * 1024 * 1024): key = 15; break; 297 default: 298 device_printf(dev, "Invalid aperture size (%dMb)\n", 299 aperture / 1024 / 1024); 300 return (EINVAL); 301 } 302 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1); 303 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1); 304 305 return (0); 306 } 307 308 static int 309 agp_nvidia_bind_page(device_t dev, int offset, vm_offset_t physical) 310 { 311 struct agp_nvidia_softc *sc = device_get_softc(dev); 312 u_int32_t index; 313 314 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 315 return (EINVAL); 316 317 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT; 318 sc->gatt->ag_virtual[index] = physical; 319 320 return (0); 321 } 322 323 static int 324 agp_nvidia_unbind_page(device_t dev, int offset) 325 { 326 struct agp_nvidia_softc *sc = device_get_softc(dev); 327 u_int32_t index; 328 329 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 330 return (EINVAL); 331 332 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT; 333 sc->gatt->ag_virtual[index] = 0; 334 335 return (0); 336 } 337 338 static int 339 agp_nvidia_flush_tlb (device_t dev, int offset) 340 { 341 struct agp_nvidia_softc *sc; 342 u_int32_t wbc_reg, temp; 343 int i; 344 345 sc = (struct agp_nvidia_softc *)device_get_softc(dev); 346 347 if (sc->wbc_mask) { 348 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4); 349 wbc_reg |= sc->wbc_mask; 350 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4); 351 352 /* Wait no more than 3 seconds. */ 353 for (i = 0; i < 3000; i++) { 354 wbc_reg = pci_read_config(sc->mc1_dev, 355 AGP_NVIDIA_1_WBC, 4); 356 if ((sc->wbc_mask & wbc_reg) == 0) 357 break; 358 else 359 DELAY(1000); 360 } 361 if (i == 3000) 362 device_printf(dev, 363 "TLB flush took more than 3 seconds.\n"); 364 } 365 366 /* Flush TLB entries. */ 367 for(i = 0; i < 32 + 1; i++) 368 temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)]; 369 for(i = 0; i < 32 + 1; i++) 370 temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)]; 371 372 return (0); 373 } 374 375 #define SYSCFG 0xC0010010 376 #define IORR_BASE0 0xC0010016 377 #define IORR_MASK0 0xC0010017 378 #define AMD_K7_NUM_IORR 2 379 380 static int 381 nvidia_init_iorr(u_int32_t addr, u_int32_t size) 382 { 383 quad_t base, mask, sys; 384 u_int32_t iorr_addr, free_iorr_addr; 385 386 /* Find the iorr that is already used for the addr */ 387 /* If not found, determine the uppermost available iorr */ 388 free_iorr_addr = AMD_K7_NUM_IORR; 389 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) { 390 base = rdmsr(IORR_BASE0 + 2 * iorr_addr); 391 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr); 392 393 if ((base & 0xfffff000ULL) == (addr & 0xfffff000)) 394 break; 395 396 if ((mask & 0x00000800ULL) == 0) 397 free_iorr_addr = iorr_addr; 398 } 399 400 if (iorr_addr >= AMD_K7_NUM_IORR) { 401 iorr_addr = free_iorr_addr; 402 if (iorr_addr >= AMD_K7_NUM_IORR) 403 return (EINVAL); 404 } 405 406 base = (addr & ~0xfff) | 0x18; 407 mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800; 408 wrmsr(IORR_BASE0 + 2 * iorr_addr, base); 409 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask); 410 411 sys = rdmsr(SYSCFG); 412 sys |= 0x00100000ULL; 413 wrmsr(SYSCFG, sys); 414 415 return (0); 416 } 417 418 static device_method_t agp_nvidia_methods[] = { 419 /* Device interface */ 420 DEVMETHOD(device_probe, agp_nvidia_probe), 421 DEVMETHOD(device_attach, agp_nvidia_attach), 422 DEVMETHOD(device_detach, agp_nvidia_detach), 423 DEVMETHOD(device_shutdown, bus_generic_shutdown), 424 DEVMETHOD(device_suspend, bus_generic_suspend), 425 DEVMETHOD(device_resume, bus_generic_resume), 426 427 /* AGP interface */ 428 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture), 429 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture), 430 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page), 431 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page), 432 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb), 433 434 DEVMETHOD(agp_enable, agp_generic_enable), 435 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 436 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 437 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 438 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 439 440 { 0, 0 } 441 }; 442 443 static driver_t agp_nvidia_driver = { 444 "agp", 445 agp_nvidia_methods, 446 sizeof(struct agp_nvidia_softc), 447 }; 448 449 static devclass_t agp_devclass; 450 451 DRIVER_MODULE(agp_nvidia, pci, agp_nvidia_driver, agp_devclass, 0, 0); 452 MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1); 453 MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
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