Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/agp_nvidia.c
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1 /*- 2 * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD: releng/6.1/sys/pci/agp_nvidia.c 152433 2005-11-14 21:10:39Z anholt $"); 29 30 /* 31 * Written using information gleaned from the 32 * NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch. 33 */ 34 35 #include "opt_bus.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/bus.h> 43 #include <sys/lock.h> 44 45 #if __FreeBSD_version < 500000 46 #include "opt_pci.h" 47 #endif 48 49 #if __FreeBSD_version > 500000 50 #include <sys/mutex.h> 51 #include <sys/proc.h> 52 #endif 53 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcireg.h> 56 #include <pci/agppriv.h> 57 #include <pci/agpreg.h> 58 59 #include <vm/vm.h> 60 #include <vm/vm_object.h> 61 #include <vm/pmap.h> 62 63 #include <machine/bus.h> 64 #include <machine/resource.h> 65 #include <sys/rman.h> 66 67 #define NVIDIA_VENDORID 0x10de 68 #define NVIDIA_DEVICEID_NFORCE 0x01a4 69 #define NVIDIA_DEVICEID_NFORCE2 0x01e0 70 71 struct agp_nvidia_softc { 72 struct agp_softc agp; 73 u_int32_t initial_aperture; /* aperture size at startup */ 74 struct agp_gatt * gatt; 75 76 device_t dev; /* AGP Controller */ 77 device_t mc1_dev; /* Memory Controller */ 78 device_t mc2_dev; /* Memory Controller */ 79 device_t bdev; /* Bridge */ 80 81 u_int32_t wbc_mask; 82 int num_dirs; 83 int num_active_entries; 84 off_t pg_offset; 85 }; 86 87 static const char *agp_nvidia_match(device_t dev); 88 static int agp_nvidia_probe(device_t); 89 static int agp_nvidia_attach(device_t); 90 static int agp_nvidia_detach(device_t); 91 static u_int32_t agp_nvidia_get_aperture(device_t); 92 static int agp_nvidia_set_aperture(device_t, u_int32_t); 93 static int agp_nvidia_bind_page(device_t, int, vm_offset_t); 94 static int agp_nvidia_unbind_page(device_t, int); 95 96 static int nvidia_init_iorr(u_int32_t, u_int32_t); 97 98 static const char * 99 agp_nvidia_match (device_t dev) 100 { 101 if (pci_get_class(dev) != PCIC_BRIDGE || 102 pci_get_subclass(dev) != PCIS_BRIDGE_HOST || 103 pci_get_vendor(dev) != NVIDIA_VENDORID) 104 return (NULL); 105 106 switch (pci_get_device(dev)) { 107 case NVIDIA_DEVICEID_NFORCE: 108 return ("NVIDIA nForce AGP Controller"); 109 case NVIDIA_DEVICEID_NFORCE2: 110 return ("NVIDIA nForce2 AGP Controller"); 111 } 112 return (NULL); 113 } 114 115 static int 116 agp_nvidia_probe (device_t dev) 117 { 118 const char *desc; 119 120 if (resource_disabled("agp", device_get_unit(dev))) 121 return (ENXIO); 122 desc = agp_nvidia_match(dev); 123 if (desc) { 124 device_verbose(dev); 125 device_set_desc(dev, desc); 126 return (BUS_PROBE_DEFAULT); 127 } 128 return (ENXIO); 129 } 130 131 static int 132 agp_nvidia_attach (device_t dev) 133 { 134 struct agp_nvidia_softc *sc = device_get_softc(dev); 135 struct agp_gatt *gatt; 136 u_int32_t apbase; 137 u_int32_t aplimit; 138 u_int32_t temp; 139 int size; 140 int i; 141 int error; 142 143 switch (pci_get_device(dev)) { 144 case NVIDIA_DEVICEID_NFORCE: 145 sc->wbc_mask = 0x00010000; 146 break; 147 case NVIDIA_DEVICEID_NFORCE2: 148 sc->wbc_mask = 0x80000000; 149 break; 150 default: 151 device_printf(dev, "Bad chip id\n"); 152 return (ENODEV); 153 } 154 155 /* AGP Controller */ 156 sc->dev = dev; 157 158 /* Memory Controller 1 */ 159 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1); 160 if (sc->mc1_dev == NULL) { 161 device_printf(dev, 162 "Unable to find NVIDIA Memory Controller 1.\n"); 163 return (ENODEV); 164 } 165 166 /* Memory Controller 2 */ 167 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2); 168 if (sc->mc2_dev == NULL) { 169 device_printf(dev, 170 "Unable to find NVIDIA Memory Controller 2.\n"); 171 return (ENODEV); 172 } 173 174 /* AGP Host to PCI Bridge */ 175 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0); 176 if (sc->bdev == NULL) { 177 device_printf(dev, 178 "Unable to find NVIDIA AGP Host to PCI Bridge.\n"); 179 return (ENODEV); 180 } 181 182 error = agp_generic_attach(dev); 183 if (error) 184 return (error); 185 186 sc->initial_aperture = AGP_GET_APERTURE(dev); 187 188 for (;;) { 189 gatt = agp_alloc_gatt(dev); 190 if (gatt) 191 break; 192 /* 193 * Probably contigmalloc failure. Try reducing the 194 * aperture so that the gatt size reduces. 195 */ 196 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) 197 goto fail; 198 } 199 sc->gatt = gatt; 200 201 apbase = rman_get_start(sc->agp.as_aperture); 202 aplimit = apbase + AGP_GET_APERTURE(dev) - 1; 203 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4); 204 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4); 205 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4); 206 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4); 207 208 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev)); 209 if (error) { 210 device_printf(dev, "Failed to setup IORRs\n"); 211 goto fail; 212 } 213 214 /* directory size is 64k */ 215 size = AGP_GET_APERTURE(dev) / 1024 / 1024; 216 sc->num_dirs = size / 64; 217 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4); 218 sc->pg_offset = 0; 219 if (sc->num_dirs == 0) { 220 sc->num_dirs = 1; 221 sc->num_active_entries /= (64 / size); 222 sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) & 223 ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE; 224 } 225 226 /* (G)ATT Base Address */ 227 for (i = 0; i < 8; i++) { 228 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i), 229 (sc->gatt->ag_physical + 230 (i % sc->num_dirs) * 64 * 1024) | 1, 4); 231 } 232 233 /* GTLB Control */ 234 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4); 235 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4); 236 237 /* GART Control */ 238 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4); 239 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4); 240 241 return (0); 242 fail: 243 agp_generic_detach(dev); 244 return (ENOMEM); 245 } 246 247 static int 248 agp_nvidia_detach (device_t dev) 249 { 250 struct agp_nvidia_softc *sc = device_get_softc(dev); 251 int error; 252 u_int32_t temp; 253 254 error = agp_generic_detach(dev); 255 if (error) 256 return (error); 257 258 /* GART Control */ 259 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4); 260 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4); 261 262 /* GTLB Control */ 263 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4); 264 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4); 265 266 /* Put the aperture back the way it started. */ 267 AGP_SET_APERTURE(dev, sc->initial_aperture); 268 269 /* restore iorr for previous aperture size */ 270 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture), 271 sc->initial_aperture); 272 273 agp_free_gatt(sc->gatt); 274 275 return (0); 276 } 277 278 static u_int32_t 279 agp_nvidia_get_aperture(device_t dev) 280 { 281 switch (pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f) { 282 case 0: return (512 * 1024 * 1024); break; 283 case 8: return (256 * 1024 * 1024); break; 284 case 12: return (128 * 1024 * 1024); break; 285 case 14: return (64 * 1024 * 1024); break; 286 case 15: return (32 * 1024 * 1024); break; 287 default: 288 device_printf(dev, "Invalid aperture setting 0x%x", 289 pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1)); 290 return 0; 291 } 292 } 293 294 static int 295 agp_nvidia_set_aperture(device_t dev, u_int32_t aperture) 296 { 297 u_int8_t val; 298 u_int8_t key; 299 300 switch (aperture) { 301 case (512 * 1024 * 1024): key = 0; break; 302 case (256 * 1024 * 1024): key = 8; break; 303 case (128 * 1024 * 1024): key = 12; break; 304 case (64 * 1024 * 1024): key = 14; break; 305 case (32 * 1024 * 1024): key = 15; break; 306 default: 307 device_printf(dev, "Invalid aperture size (%dMb)\n", 308 aperture / 1024 / 1024); 309 return (EINVAL); 310 } 311 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1); 312 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1); 313 314 return (0); 315 } 316 317 static int 318 agp_nvidia_bind_page(device_t dev, int offset, vm_offset_t physical) 319 { 320 struct agp_nvidia_softc *sc = device_get_softc(dev); 321 u_int32_t index; 322 323 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 324 return (EINVAL); 325 326 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT; 327 sc->gatt->ag_virtual[index] = physical | 1; 328 329 return (0); 330 } 331 332 static int 333 agp_nvidia_unbind_page(device_t dev, int offset) 334 { 335 struct agp_nvidia_softc *sc = device_get_softc(dev); 336 u_int32_t index; 337 338 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 339 return (EINVAL); 340 341 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT; 342 sc->gatt->ag_virtual[index] = 0; 343 344 return (0); 345 } 346 347 static int 348 agp_nvidia_flush_tlb (device_t dev, int offset) 349 { 350 struct agp_nvidia_softc *sc; 351 u_int32_t wbc_reg, temp; 352 volatile u_int32_t *ag_virtual; 353 int i; 354 355 sc = (struct agp_nvidia_softc *)device_get_softc(dev); 356 357 if (sc->wbc_mask) { 358 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4); 359 wbc_reg |= sc->wbc_mask; 360 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4); 361 362 /* Wait no more than 3 seconds. */ 363 for (i = 0; i < 3000; i++) { 364 wbc_reg = pci_read_config(sc->mc1_dev, 365 AGP_NVIDIA_1_WBC, 4); 366 if ((sc->wbc_mask & wbc_reg) == 0) 367 break; 368 else 369 DELAY(1000); 370 } 371 if (i == 3000) 372 device_printf(dev, 373 "TLB flush took more than 3 seconds.\n"); 374 } 375 376 ag_virtual = (volatile u_int32_t *)sc->gatt->ag_virtual; 377 378 /* Flush TLB entries. */ 379 for(i = 0; i < 32 + 1; i++) 380 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)]; 381 for(i = 0; i < 32 + 1; i++) 382 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)]; 383 384 return (0); 385 } 386 387 #define SYSCFG 0xC0010010 388 #define IORR_BASE0 0xC0010016 389 #define IORR_MASK0 0xC0010017 390 #define AMD_K7_NUM_IORR 2 391 392 static int 393 nvidia_init_iorr(u_int32_t addr, u_int32_t size) 394 { 395 quad_t base, mask, sys; 396 u_int32_t iorr_addr, free_iorr_addr; 397 398 /* Find the iorr that is already used for the addr */ 399 /* If not found, determine the uppermost available iorr */ 400 free_iorr_addr = AMD_K7_NUM_IORR; 401 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) { 402 base = rdmsr(IORR_BASE0 + 2 * iorr_addr); 403 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr); 404 405 if ((base & 0xfffff000ULL) == (addr & 0xfffff000)) 406 break; 407 408 if ((mask & 0x00000800ULL) == 0) 409 free_iorr_addr = iorr_addr; 410 } 411 412 if (iorr_addr >= AMD_K7_NUM_IORR) { 413 iorr_addr = free_iorr_addr; 414 if (iorr_addr >= AMD_K7_NUM_IORR) 415 return (EINVAL); 416 } 417 418 base = (addr & ~0xfff) | 0x18; 419 mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800; 420 wrmsr(IORR_BASE0 + 2 * iorr_addr, base); 421 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask); 422 423 sys = rdmsr(SYSCFG); 424 sys |= 0x00100000ULL; 425 wrmsr(SYSCFG, sys); 426 427 return (0); 428 } 429 430 static device_method_t agp_nvidia_methods[] = { 431 /* Device interface */ 432 DEVMETHOD(device_probe, agp_nvidia_probe), 433 DEVMETHOD(device_attach, agp_nvidia_attach), 434 DEVMETHOD(device_detach, agp_nvidia_detach), 435 DEVMETHOD(device_shutdown, bus_generic_shutdown), 436 DEVMETHOD(device_suspend, bus_generic_suspend), 437 DEVMETHOD(device_resume, bus_generic_resume), 438 439 /* AGP interface */ 440 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture), 441 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture), 442 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page), 443 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page), 444 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb), 445 446 DEVMETHOD(agp_enable, agp_generic_enable), 447 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 448 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 449 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 450 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 451 452 { 0, 0 } 453 }; 454 455 static driver_t agp_nvidia_driver = { 456 "agp", 457 agp_nvidia_methods, 458 sizeof(struct agp_nvidia_softc), 459 }; 460 461 static devclass_t agp_devclass; 462 463 DRIVER_MODULE(agp_nvidia, pci, agp_nvidia_driver, agp_devclass, 0, 0); 464 MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1); 465 MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
Cache object: 031e29f07eb511666b1e08a7b1d23b23
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