FreeBSD/Linux Kernel Cross Reference
sys/pci/agp_nvidia.c
1 /*-
2 * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: releng/6.4/sys/pci/agp_nvidia.c 177313 2008-03-17 18:27:23Z jhb $");
29
30 /*
31 * Written using information gleaned from the
32 * NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch.
33 */
34
35 #include "opt_bus.h"
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/bus.h>
43 #include <sys/lock.h>
44
45 #if __FreeBSD_version < 500000
46 #include "opt_pci.h"
47 #endif
48
49 #if __FreeBSD_version > 500000
50 #include <sys/mutex.h>
51 #include <sys/proc.h>
52 #endif
53
54 #include <dev/pci/pcivar.h>
55 #include <dev/pci/pcireg.h>
56 #include <pci/agppriv.h>
57 #include <pci/agpreg.h>
58
59 #include <vm/vm.h>
60 #include <vm/vm_object.h>
61 #include <vm/pmap.h>
62
63 #include <machine/bus.h>
64 #include <machine/resource.h>
65 #include <sys/rman.h>
66
67 #define NVIDIA_VENDORID 0x10de
68 #define NVIDIA_DEVICEID_NFORCE 0x01a4
69 #define NVIDIA_DEVICEID_NFORCE2 0x01e0
70
71 struct agp_nvidia_softc {
72 struct agp_softc agp;
73 u_int32_t initial_aperture; /* aperture size at startup */
74 struct agp_gatt * gatt;
75
76 device_t dev; /* AGP Controller */
77 device_t mc1_dev; /* Memory Controller */
78 device_t mc2_dev; /* Memory Controller */
79 device_t bdev; /* Bridge */
80
81 u_int32_t wbc_mask;
82 int num_dirs;
83 int num_active_entries;
84 off_t pg_offset;
85 };
86
87 static const char *agp_nvidia_match(device_t dev);
88 static int agp_nvidia_probe(device_t);
89 static int agp_nvidia_attach(device_t);
90 static int agp_nvidia_detach(device_t);
91 static u_int32_t agp_nvidia_get_aperture(device_t);
92 static int agp_nvidia_set_aperture(device_t, u_int32_t);
93 static int agp_nvidia_bind_page(device_t, int, vm_offset_t);
94 static int agp_nvidia_unbind_page(device_t, int);
95
96 static int nvidia_init_iorr(u_int32_t, u_int32_t);
97
98 static const char *
99 agp_nvidia_match (device_t dev)
100 {
101 if (pci_get_class(dev) != PCIC_BRIDGE ||
102 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
103 pci_get_vendor(dev) != NVIDIA_VENDORID)
104 return (NULL);
105
106 switch (pci_get_device(dev)) {
107 case NVIDIA_DEVICEID_NFORCE:
108 return ("NVIDIA nForce AGP Controller");
109 case NVIDIA_DEVICEID_NFORCE2:
110 return ("NVIDIA nForce2 AGP Controller");
111 }
112 return (NULL);
113 }
114
115 static int
116 agp_nvidia_probe (device_t dev)
117 {
118 const char *desc;
119
120 if (resource_disabled("agp", device_get_unit(dev)))
121 return (ENXIO);
122 desc = agp_nvidia_match(dev);
123 if (desc) {
124 device_verbose(dev);
125 device_set_desc(dev, desc);
126 return (BUS_PROBE_DEFAULT);
127 }
128 return (ENXIO);
129 }
130
131 static int
132 agp_nvidia_attach (device_t dev)
133 {
134 struct agp_nvidia_softc *sc = device_get_softc(dev);
135 struct agp_gatt *gatt;
136 u_int32_t apbase;
137 u_int32_t aplimit;
138 u_int32_t temp;
139 int size;
140 int i;
141 int error;
142
143 switch (pci_get_device(dev)) {
144 case NVIDIA_DEVICEID_NFORCE:
145 sc->wbc_mask = 0x00010000;
146 break;
147 case NVIDIA_DEVICEID_NFORCE2:
148 sc->wbc_mask = 0x80000000;
149 break;
150 default:
151 device_printf(dev, "Bad chip id\n");
152 return (ENODEV);
153 }
154
155 /* AGP Controller */
156 sc->dev = dev;
157
158 /* Memory Controller 1 */
159 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
160 if (sc->mc1_dev == NULL) {
161 device_printf(dev,
162 "Unable to find NVIDIA Memory Controller 1.\n");
163 return (ENODEV);
164 }
165
166 /* Memory Controller 2 */
167 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
168 if (sc->mc2_dev == NULL) {
169 device_printf(dev,
170 "Unable to find NVIDIA Memory Controller 2.\n");
171 return (ENODEV);
172 }
173
174 /* AGP Host to PCI Bridge */
175 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
176 if (sc->bdev == NULL) {
177 device_printf(dev,
178 "Unable to find NVIDIA AGP Host to PCI Bridge.\n");
179 return (ENODEV);
180 }
181
182 error = agp_generic_attach(dev);
183 if (error)
184 return (error);
185
186 sc->initial_aperture = AGP_GET_APERTURE(dev);
187
188 for (;;) {
189 gatt = agp_alloc_gatt(dev);
190 if (gatt)
191 break;
192 /*
193 * Probably contigmalloc failure. Try reducing the
194 * aperture so that the gatt size reduces.
195 */
196 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
197 goto fail;
198 }
199 sc->gatt = gatt;
200
201 apbase = rman_get_start(sc->agp.as_aperture);
202 aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
203 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
204 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
205 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
206 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
207
208 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
209 if (error) {
210 device_printf(dev, "Failed to setup IORRs\n");
211 goto fail;
212 }
213
214 /* directory size is 64k */
215 size = AGP_GET_APERTURE(dev) / 1024 / 1024;
216 sc->num_dirs = size / 64;
217 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
218 sc->pg_offset = 0;
219 if (sc->num_dirs == 0) {
220 sc->num_dirs = 1;
221 sc->num_active_entries /= (64 / size);
222 sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
223 ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE;
224 }
225
226 /* (G)ATT Base Address */
227 for (i = 0; i < 8; i++) {
228 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
229 (sc->gatt->ag_physical +
230 (i % sc->num_dirs) * 64 * 1024) | 1, 4);
231 }
232
233 /* GTLB Control */
234 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
235 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
236
237 /* GART Control */
238 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
239 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
240
241 return (0);
242 fail:
243 agp_generic_detach(dev);
244 return (ENOMEM);
245 }
246
247 static int
248 agp_nvidia_detach (device_t dev)
249 {
250 struct agp_nvidia_softc *sc = device_get_softc(dev);
251 u_int32_t temp;
252
253 agp_free_cdev(dev);
254
255 /* GART Control */
256 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
257 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
258
259 /* GTLB Control */
260 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
261 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
262
263 /* Put the aperture back the way it started. */
264 AGP_SET_APERTURE(dev, sc->initial_aperture);
265
266 /* restore iorr for previous aperture size */
267 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
268 sc->initial_aperture);
269
270 agp_free_gatt(sc->gatt);
271 agp_free_res(dev);
272
273 return (0);
274 }
275
276 static u_int32_t
277 agp_nvidia_get_aperture(device_t dev)
278 {
279 switch (pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f) {
280 case 0: return (512 * 1024 * 1024); break;
281 case 8: return (256 * 1024 * 1024); break;
282 case 12: return (128 * 1024 * 1024); break;
283 case 14: return (64 * 1024 * 1024); break;
284 case 15: return (32 * 1024 * 1024); break;
285 default:
286 device_printf(dev, "Invalid aperture setting 0x%x",
287 pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1));
288 return 0;
289 }
290 }
291
292 static int
293 agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
294 {
295 u_int8_t val;
296 u_int8_t key;
297
298 switch (aperture) {
299 case (512 * 1024 * 1024): key = 0; break;
300 case (256 * 1024 * 1024): key = 8; break;
301 case (128 * 1024 * 1024): key = 12; break;
302 case (64 * 1024 * 1024): key = 14; break;
303 case (32 * 1024 * 1024): key = 15; break;
304 default:
305 device_printf(dev, "Invalid aperture size (%dMb)\n",
306 aperture / 1024 / 1024);
307 return (EINVAL);
308 }
309 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
310 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
311
312 return (0);
313 }
314
315 static int
316 agp_nvidia_bind_page(device_t dev, int offset, vm_offset_t physical)
317 {
318 struct agp_nvidia_softc *sc = device_get_softc(dev);
319 u_int32_t index;
320
321 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
322 return (EINVAL);
323
324 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
325 sc->gatt->ag_virtual[index] = physical | 1;
326
327 return (0);
328 }
329
330 static int
331 agp_nvidia_unbind_page(device_t dev, int offset)
332 {
333 struct agp_nvidia_softc *sc = device_get_softc(dev);
334 u_int32_t index;
335
336 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
337 return (EINVAL);
338
339 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
340 sc->gatt->ag_virtual[index] = 0;
341
342 return (0);
343 }
344
345 static int
346 agp_nvidia_flush_tlb (device_t dev, int offset)
347 {
348 struct agp_nvidia_softc *sc;
349 u_int32_t wbc_reg, temp;
350 volatile u_int32_t *ag_virtual;
351 int i, pages;
352
353 sc = (struct agp_nvidia_softc *)device_get_softc(dev);
354
355 if (sc->wbc_mask) {
356 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
357 wbc_reg |= sc->wbc_mask;
358 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
359
360 /* Wait no more than 3 seconds. */
361 for (i = 0; i < 3000; i++) {
362 wbc_reg = pci_read_config(sc->mc1_dev,
363 AGP_NVIDIA_1_WBC, 4);
364 if ((sc->wbc_mask & wbc_reg) == 0)
365 break;
366 else
367 DELAY(1000);
368 }
369 if (i == 3000)
370 device_printf(dev,
371 "TLB flush took more than 3 seconds.\n");
372 }
373
374 ag_virtual = (volatile u_int32_t *)sc->gatt->ag_virtual;
375
376 /* Flush TLB entries. */
377 pages = sc->gatt->ag_entries * sizeof(u_int32_t) / PAGE_SIZE;
378 for(i = 0; i < pages; i++)
379 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
380 for(i = 0; i < pages; i++)
381 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
382
383 return (0);
384 }
385
386 #define SYSCFG 0xC0010010
387 #define IORR_BASE0 0xC0010016
388 #define IORR_MASK0 0xC0010017
389 #define AMD_K7_NUM_IORR 2
390
391 static int
392 nvidia_init_iorr(u_int32_t addr, u_int32_t size)
393 {
394 quad_t base, mask, sys;
395 u_int32_t iorr_addr, free_iorr_addr;
396
397 /* Find the iorr that is already used for the addr */
398 /* If not found, determine the uppermost available iorr */
399 free_iorr_addr = AMD_K7_NUM_IORR;
400 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
401 base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
402 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
403
404 if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
405 break;
406
407 if ((mask & 0x00000800ULL) == 0)
408 free_iorr_addr = iorr_addr;
409 }
410
411 if (iorr_addr >= AMD_K7_NUM_IORR) {
412 iorr_addr = free_iorr_addr;
413 if (iorr_addr >= AMD_K7_NUM_IORR)
414 return (EINVAL);
415 }
416
417 base = (addr & ~0xfff) | 0x18;
418 mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800;
419 wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
420 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
421
422 sys = rdmsr(SYSCFG);
423 sys |= 0x00100000ULL;
424 wrmsr(SYSCFG, sys);
425
426 return (0);
427 }
428
429 static device_method_t agp_nvidia_methods[] = {
430 /* Device interface */
431 DEVMETHOD(device_probe, agp_nvidia_probe),
432 DEVMETHOD(device_attach, agp_nvidia_attach),
433 DEVMETHOD(device_detach, agp_nvidia_detach),
434 DEVMETHOD(device_shutdown, bus_generic_shutdown),
435 DEVMETHOD(device_suspend, bus_generic_suspend),
436 DEVMETHOD(device_resume, bus_generic_resume),
437
438 /* AGP interface */
439 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture),
440 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture),
441 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page),
442 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page),
443 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb),
444
445 DEVMETHOD(agp_enable, agp_generic_enable),
446 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
447 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
448 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
449 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
450
451 { 0, 0 }
452 };
453
454 static driver_t agp_nvidia_driver = {
455 "agp",
456 agp_nvidia_methods,
457 sizeof(struct agp_nvidia_softc),
458 };
459
460 static devclass_t agp_devclass;
461
462 DRIVER_MODULE(agp_nvidia, pci, agp_nvidia_driver, agp_devclass, 0, 0);
463 MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
464 MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
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