FreeBSD/Linux Kernel Cross Reference
sys/pci/dc21040reg.h
1 /* $NetBSD: dc21040reg.h,v 1.15 1998/05/22 18:50:59 matt Exp $ */
2 /* $FreeBSD$ */
3
4 /*-
5 * Copyright (c) 1994, 1995, 1996 Matt Thomas <matt@3am-software.com>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. The name of the author may not be used to endorse or promote products
14 * derived from this software withough specific prior written permission
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * Id: dc21040reg.h,v 1.24 1997/05/16 19:47:09 thomas Exp
28 */
29
30 #if !defined(_DC21040_H)
31 #define _DC21040_H
32
33 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN
34 #define TULIP_BITFIELD2(a, b) b, a
35 #define TULIP_BITFIELD3(a, b, c) c, b, a
36 #define TULIP_BITFIELD4(a, b, c, d) d, c, b, a
37 #else
38 #define TULIP_BITFIELD2(a, b) a, b
39 #define TULIP_BITFIELD3(a, b, c) a, b, c
40 #define TULIP_BITFIELD4(a, b, c, d) a, b, c, d
41 #endif
42
43 typedef struct {
44 u_int32_t d_status;
45 u_int32_t TULIP_BITFIELD3(d_length1 : 11,
46 d_length2 : 11,
47 d_flag : 10);
48 u_int32_t d_addr1;
49 u_int32_t d_addr2;
50 } tulip_desc_t;
51
52 #define TULIP_DSTS_OWNER 0x80000000 /* Owner (1 = 21040) */
53 #define TULIP_DSTS_ERRSUM 0x00008000 /* Error Summary */
54 /*
55 * Transmit Status
56 */
57 #define TULIP_DSTS_TxBABBLE 0x00004000 /* Transmitter Babbled */
58 #define TULIP_DSTS_TxCARRLOSS 0x00000800 /* Carrier Loss */
59 #define TULIP_DSTS_TxNOCARR 0x00000400 /* No Carrier */
60 #define TULIP_DSTS_TxLATECOLL 0x00000200 /* Late Collision */
61 #define TULIP_DSTS_TxEXCCOLL 0x00000100 /* Excessive Collisions */
62 #define TULIP_DSTS_TxNOHRTBT 0x00000080 /* No Heartbeat */
63 #define TULIP_DSTS_TxCOLLMASK 0x00000078 /* Collision Count (mask) */
64 #define TULIP_DSTS_V_TxCOLLCNT 0x00000003 /* Collision Count (bit) */
65 #define TULIP_DSTS_TxLINKFAIL 0x00000004 /* Link Failure */
66 #define TULIP_DSTS_TxUNDERFLOW 0x00000002 /* Underflow Error */
67 #define TULIP_DSTS_TxDEFERRED 0x00000001 /* Initially Deferred */
68 /*
69 * Receive Status
70 */
71 #define TULIP_DSTS_RxBADLENGTH 0x00004000 /* Length Error */
72 #define TULIP_DSTS_RxDATATYPE 0x00003000 /* Data Type */
73 #define TULIP_DSTS_RxRUNT 0x00000800 /* Runt Frame */
74 #define TULIP_DSTS_RxMULTICAST 0x00000400 /* Multicast Frame */
75 #define TULIP_DSTS_RxFIRSTDESC 0x00000200 /* First Descriptor */
76 #define TULIP_DSTS_RxLASTDESC 0x00000100 /* Last Descriptor */
77 #define TULIP_DSTS_RxTOOLONG 0x00000080 /* Frame Too Long */
78 #define TULIP_DSTS_RxCOLLSEEN 0x00000040 /* Collision Seen */
79 #define TULIP_DSTS_RxFRAMETYPE 0x00000020 /* Frame Type */
80 #define TULIP_DSTS_RxWATCHDOG 0x00000010 /* Receive Watchdog */
81 #define TULIP_DSTS_RxDRBBLBIT 0x00000004 /* Dribble Bit */
82 #define TULIP_DSTS_RxBADCRC 0x00000002 /* CRC Error */
83 #define TULIP_DSTS_RxOVERFLOW 0x00000001 /* Overflow */
84
85
86 #define TULIP_DFLAG_ENDRING 0x0008 /* End of Transmit Ring */
87 #define TULIP_DFLAG_CHAIN 0x0004 /* Chain using d_addr2 */
88
89 #define TULIP_DFLAG_TxWANTINTR 0x0200 /* Signal Interrupt on Completion */
90 #define TULIP_DFLAG_TxLASTSEG 0x0100 /* Last Segment */
91 #define TULIP_DFLAG_TxFIRSTSEG 0x0080 /* First Segment */
92 #define TULIP_DFLAG_TxINVRSFILT 0x0040 /* Inverse Filtering */
93 #define TULIP_DFLAG_TxSETUPPKT 0x0020 /* Setup Packet */
94 #define TULIP_DFLAG_TxHASCRC 0x0010 /* Don't Append the CRC */
95 #define TULIP_DFLAG_TxNOPADDING 0x0002 /* Don't AutoPad */
96 #define TULIP_DFLAG_TxHASHFILT 0x0001 /* Hash/Perfect Filtering */
97
98 /*
99 * The 21040 Registers (IO Space Addresses)
100 */
101 #define TULIP_REG_BUSMODE 0x00 /* CSR0 -- Bus Mode */
102 #define TULIP_REG_TXPOLL 0x08 /* CSR1 -- Transmit Poll Demand */
103 #define TULIP_REG_RXPOLL 0x10 /* CSR2 -- Receive Poll Demand */
104 #define TULIP_REG_RXLIST 0x18 /* CSR3 -- Receive List Base Addr */
105 #define TULIP_REG_TXLIST 0x20 /* CSR4 -- Transmit List Base Addr */
106 #define TULIP_REG_STATUS 0x28 /* CSR5 -- Status */
107 #define TULIP_REG_CMD 0x30 /* CSR6 -- Command */
108 #define TULIP_REG_INTR 0x38 /* CSR7 -- Interrupt Control */
109 #define TULIP_REG_MISSES 0x40 /* CSR8 -- Missed Frame Counter */
110 #define TULIP_REG_ADDRROM 0x48 /* CSR9 -- ENET ROM Register */
111 #define TULIP_REG_RSRVD 0x50 /* CSR10 -- Reserved */
112 #define TULIP_REG_FULL_DUPLEX 0x58 /* CSR11 -- Full Duplex */
113 #define TULIP_REG_SIA_STATUS 0x60 /* CSR12 -- SIA Status */
114 #define TULIP_REG_SIA_CONN 0x68 /* CSR13 -- SIA Connectivity */
115 #define TULIP_REG_SIA_TXRX 0x70 /* CSR14 -- SIA Tx Rx */
116 #define TULIP_REG_SIA_GEN 0x78 /* CSR15 -- SIA General */
117
118 /*
119 * CSR5 -- Status Register
120 * CSR7 -- Interrupt Control
121 */
122 #define TULIP_STS_ERRORMASK 0x03800000L /* ( R) Error Bits (Valid when SYSERROR is set) */
123 #define TULIP_STS_ERR_PARITY 0x00000000L /* 000 - Parity Error (Perform Reset) */
124 #define TULIP_STS_ERR_MASTER 0x00800000L /* 001 - Master Abort */
125 #define TULIP_STS_ERR_TARGET 0x01000000L /* 010 - Target Abort */
126 #define TULIP_STS_ERR_SHIFT 23
127 #define TULIP_STS_TXSTATEMASK 0x00700000L /* ( R) Transmission Process State */
128 #define TULIP_STS_TXS_RESET 0x00000000L /* 000 - Rset or transmit jabber expired */
129 #define TULIP_STS_TXS_FETCH 0x00100000L /* 001 - Fetching transmit descriptor */
130 #define TULIP_STS_TXS_WAITEND 0x00200000L /* 010 - Wait for end of transmission */
131 #define TULIP_STS_TXS_READING 0x00300000L /* 011 - Read buffer and enqueue data */
132 #define TULIP_STS_TXS_RSRVD 0x00400000L /* 100 - Reserved */
133 #define TULIP_STS_TXS_SETUP 0x00500000L /* 101 - Setup Packet */
134 #define TULIP_STS_TXS_SUSPEND 0x00600000L /* 110 - Transmit FIFO underflow or an
135 unavailable transmit descriptor */
136 #define TULIP_STS_TXS_CLOSE 0x00700000L /* 111 - Close transmit descriptor */
137 #define TULIP_STS_RXSTATEMASK 0x000E0000L /* ( R) Receive Process State*/
138 #define TULIP_STS_RXS_STOPPED 0x00000000L /* 000 - Stopped */
139 #define TULIP_STS_RXS_FETCH 0x00020000L /* 001 - Running -- Fetch receive descriptor */
140 #define TULIP_STS_RXS_ENDCHECK 0x00040000L /* 010 - Running -- Check for end of receive
141 packet before prefetch of next descriptor */
142 #define TULIP_STS_RXS_WAIT 0x00060000L /* 011 - Running -- Wait for receive packet */
143 #define TULIP_STS_RXS_SUSPEND 0x00080000L /* 100 - Suspended -- As a result of
144 unavailable receive buffers */
145 #define TULIP_STS_RXS_CLOSE 0x000A0000L /* 101 - Running -- Close receive descriptor */
146 #define TULIP_STS_RXS_FLUSH 0x000C0000L /* 110 - Running -- Flush the current frame
147 from the receive FIFO as a result of
148 an unavailable receive buffer */
149 #define TULIP_STS_RXS_DEQUEUE 0x000E0000L /* 111 - Running -- Dequeue the receive frame
150 from the receive FIFO into the receive
151 buffer. */
152 #define TULIP_STS_NORMALINTR 0x00010000L /* (RW) Normal Interrupt */
153 #define TULIP_STS_ABNRMLINTR 0x00008000L /* (RW) Abnormal Interrupt */
154 #define TULIP_STS_SYSERROR 0x00002000L /* (RW) System Error */
155 #define TULIP_STS_LINKFAIL 0x00001000L /* (RW) Link Failure (21040) */
156 #define TULIP_STS_FULDPLXSHRT 0x00000800L /* (RW) Full Duplex Short Fram Rcvd (21040) */
157 #define TULIP_STS_GPTIMEOUT 0x00000800L /* (RW) General Purpose Timeout (21140) */
158 #define TULIP_STS_AUI 0x00000400L /* (RW) AUI/TP Switch (21040) */
159 #define TULIP_STS_RXTIMEOUT 0x00000200L /* (RW) Receive Watchbog Timeout */
160 #define TULIP_STS_RXSTOPPED 0x00000100L /* (RW) Receive Process Stopped */
161 #define TULIP_STS_RXNOBUF 0x00000080L /* (RW) Receive Buffer Unavailable */
162 #define TULIP_STS_RXINTR 0x00000040L /* (RW) Receive Interrupt */
163 #define TULIP_STS_TXUNDERFLOW 0x00000020L /* (RW) Transmit Underflow */
164 #define TULIP_STS_LINKPASS 0x00000010L /* (RW) LinkPass (21041) */
165 #define TULIP_STS_TXBABBLE 0x00000008L /* (RW) Transmit Jabber Timeout */
166 #define TULIP_STS_TXNOBUF 0x00000004L /* (RW) Transmit Buffer Unavailable */
167 #define TULIP_STS_TXSTOPPED 0x00000002L /* (RW) Transmit Process Stopped */
168 #define TULIP_STS_TXINTR 0x00000001L /* (RW) Transmit Interrupt */
169
170 /*
171 * CSR6 -- Command (Operation Mode) Register
172 */
173 #define TULIP_CMD_MUSTBEONE 0x02000000L /* (RW) Must Be One (21140) */
174 #define TULIP_CMD_SCRAMBLER 0x01000000L /* (RW) Scrambler Mode (21140) */
175 #define TULIP_CMD_PCSFUNCTION 0x00800000L /* (RW) PCS Function (21140) */
176 #define TULIP_CMD_TXTHRSHLDCTL 0x00400000L /* (RW) Transmit Threshold Mode (21140) */
177 #define TULIP_CMD_STOREFWD 0x00200000L /* (RW) Store and Foward (21140) */
178 #define TULIP_CMD_NOHEARTBEAT 0x00080000L /* (RW) No Heartbeat (21140) */
179 #define TULIP_CMD_PORTSELECT 0x00040000L /* (RW) Post Select (100Mb) (21140) */
180 #define TULIP_CMD_ENHCAPTEFFCT 0x00040000L /* (RW) Enhanced Capture Effecty (21041) */
181 #define TULIP_CMD_CAPTREFFCT 0x00020000L /* (RW) Capture Effect (!802.3) */
182 #define TULIP_CMD_BACKPRESSURE 0x00010000L /* (RW) Back Pressure (!802.3) (21040) */
183 #define TULIP_CMD_THRESHOLDCTL 0x0000C000L /* (RW) Threshold Control */
184 #define TULIP_CMD_THRSHLD72 0x00000000L /* 00 - 72 Bytes */
185 #define TULIP_CMD_THRSHLD96 0x00004000L /* 01 - 96 Bytes */
186 #define TULIP_CMD_THRSHLD128 0x00008000L /* 10 - 128 bytes */
187 #define TULIP_CMD_THRSHLD160 0x0000C000L /* 11 - 160 Bytes */
188 #define TULIP_CMD_TXRUN 0x00002000L /* (RW) Start/Stop Transmitter */
189 #define TULIP_CMD_FORCECOLL 0x00001000L /* (RW) Force Collisions */
190 #define TULIP_CMD_OPERMODE 0x00000C00L /* (RW) Operating Mode */
191 #define TULIP_CMD_FULLDUPLEX 0x00000200L /* (RW) Full Duplex Mode */
192 #define TULIP_CMD_FLAKYOSCDIS 0x00000100L /* (RW) Flakey Oscillator Disable */
193 #define TULIP_CMD_ALLMULTI 0x00000080L /* (RW) Pass All Multicasts */
194 #define TULIP_CMD_PROMISCUOUS 0x00000040L /* (RW) Promiscuous Mode */
195 #define TULIP_CMD_BACKOFFCTR 0x00000020L /* (RW) Start/Stop Backoff Counter (!802.3) */
196 #define TULIP_CMD_INVFILTER 0x00000010L /* (R ) Inverse Filtering */
197 #define TULIP_CMD_PASSBADPKT 0x00000008L /* (RW) Pass Bad Frames */
198 #define TULIP_CMD_HASHONLYFLTR 0x00000004L /* (R ) Hash Only Filtering */
199 #define TULIP_CMD_RXRUN 0x00000002L /* (RW) Start/Stop Receive Filtering */
200 #define TULIP_CMD_HASHPRFCTFLTR 0x00000001L /* (R ) Hash/Perfect Receive Filtering */
201
202 #define TULIP_SIASTS_OTHERRXACTIVITY 0x00000200L
203 #define TULIP_SIASTS_RXACTIVITY 0x00000100L
204 #define TULIP_SIASTS_LINKFAIL 0x00000004L
205 #define TULIP_SIASTS_LINK100FAIL 0x00000002L
206 #define TULIP_SIACONN_RESET 0x00000000L
207
208 /*
209 * 21040 SIA definitions
210 */
211 #define TULIP_21040_PROBE_10BASET_TIMEOUT 2500
212 #define TULIP_21040_PROBE_AUIBNC_TIMEOUT 300
213 #define TULIP_21040_PROBE_EXTSIA_TIMEOUT 300
214
215 #define TULIP_21040_SIACONN_10BASET 0x0000EF01L
216 #define TULIP_21040_SIATXRX_10BASET 0x0000FFFFL
217 #define TULIP_21040_SIAGEN_10BASET 0x00000000L
218
219 #define TULIP_21040_SIACONN_10BASET_FD 0x0000EF01L
220 #define TULIP_21040_SIATXRX_10BASET_FD 0x0000FFFDL
221 #define TULIP_21040_SIAGEN_10BASET_FD 0x00000000L
222
223 #define TULIP_21040_SIACONN_AUIBNC 0x0000EF09L
224 #define TULIP_21040_SIATXRX_AUIBNC 0x00000705L
225 #define TULIP_21040_SIAGEN_AUIBNC 0x00000006L
226
227 #define TULIP_21040_SIACONN_EXTSIA 0x00003041L
228 #define TULIP_21040_SIATXRX_EXTSIA 0x00000000L
229 #define TULIP_21040_SIAGEN_EXTSIA 0x00000006L
230
231 /*
232 * 21041 SIA definitions
233 */
234
235 #define TULIP_21041_PROBE_10BASET_TIMEOUT 2500
236 #define TULIP_21041_PROBE_AUIBNC_TIMEOUT 300
237
238 #define TULIP_21041_SIACONN_10BASET 0x0000EF01L
239 #define TULIP_21041_SIATXRX_10BASET 0x0000FF3FL
240 #define TULIP_21041_SIAGEN_10BASET 0x00000000L
241
242 #define TULIP_21041P2_SIACONN_10BASET 0x0000EF01L
243 #define TULIP_21041P2_SIATXRX_10BASET 0x0000FFFFL
244 #define TULIP_21041P2_SIAGEN_10BASET 0x00000000L
245
246 #define TULIP_21041_SIACONN_10BASET_FD 0x0000EF01L
247 #define TULIP_21041_SIATXRX_10BASET_FD 0x0000FF3DL
248 #define TULIP_21041_SIAGEN_10BASET_FD 0x00000000L
249
250 #define TULIP_21041P2_SIACONN_10BASET_FD 0x0000EF01L
251 #define TULIP_21041P2_SIATXRX_10BASET_FD 0x0000FFFFL
252 #define TULIP_21041P2_SIAGEN_10BASET_FD 0x00000000L
253
254 #define TULIP_21041_SIACONN_AUI 0x0000EF09L
255 #define TULIP_21041_SIATXRX_AUI 0x0000F73DL
256 #define TULIP_21041_SIAGEN_AUI 0x0000000EL
257
258 #define TULIP_21041P2_SIACONN_AUI 0x0000EF09L
259 #define TULIP_21041P2_SIATXRX_AUI 0x0000F7FDL
260 #define TULIP_21041P2_SIAGEN_AUI 0x0000000EL
261
262 #define TULIP_21041_SIACONN_BNC 0x0000EF09L
263 #define TULIP_21041_SIATXRX_BNC 0x0000F73DL
264 #define TULIP_21041_SIAGEN_BNC 0x00000006L
265
266 #define TULIP_21041P2_SIACONN_BNC 0x0000EF09L
267 #define TULIP_21041P2_SIATXRX_BNC 0x0000F7FDL
268 #define TULIP_21041P2_SIAGEN_BNC 0x00000006L
269
270 /*
271 * 21142 SIA definitions
272 */
273
274 #define TULIP_21142_PROBE_10BASET_TIMEOUT 2500
275 #define TULIP_21142_PROBE_AUIBNC_TIMEOUT 300
276
277 #define TULIP_21142_SIACONN_10BASET 0x00000001L
278 #define TULIP_21142_SIATXRX_10BASET 0x00007F3FL
279 #define TULIP_21142_SIAGEN_10BASET 0x00000008L
280
281 #define TULIP_21142_SIACONN_10BASET_FD 0x00000001L
282 #define TULIP_21142_SIATXRX_10BASET_FD 0x00007F3DL
283 #define TULIP_21142_SIAGEN_10BASET_FD 0x00000008L
284
285 #define TULIP_21142_SIACONN_AUI 0x00000009L
286 #define TULIP_21142_SIATXRX_AUI 0x00000705L
287 #define TULIP_21142_SIAGEN_AUI 0x0000000EL
288
289 #define TULIP_21142_SIACONN_BNC 0x00000009L
290 #define TULIP_21142_SIATXRX_BNC 0x00000705L
291 #define TULIP_21142_SIAGEN_BNC 0x00000006L
292
293
294
295
296 #define TULIP_WATCHDOG_TXDISABLE 0x00000001L
297 #define TULIP_WATCHDOG_RXDISABLE 0x00000010L
298
299 #define TULIP_BUSMODE_SWRESET 0x00000001L
300 #define TULIP_BUSMODE_DESCSKIPLEN_MASK 0x0000007CL
301 #define TULIP_BUSMODE_BIGENDIAN 0x00000080L
302 #define TULIP_BUSMODE_BURSTLEN_MASK 0x00003F00L
303 #define TULIP_BUSMODE_BURSTLEN_DEFAULT 0x00000000L
304 #define TULIP_BUSMODE_BURSTLEN_1LW 0x00000100L
305 #define TULIP_BUSMODE_BURSTLEN_2LW 0x00000200L
306 #define TULIP_BUSMODE_BURSTLEN_4LW 0x00000400L
307 #define TULIP_BUSMODE_BURSTLEN_8LW 0x00000800L
308 #define TULIP_BUSMODE_BURSTLEN_16LW 0x00001000L
309 #define TULIP_BUSMODE_BURSTLEN_32LW 0x00002000L
310 #define TULIP_BUSMODE_CACHE_NOALIGN 0x00000000L
311 #define TULIP_BUSMODE_CACHE_ALIGN8 0x00004000L
312 #define TULIP_BUSMODE_CACHE_ALIGN16 0x00008000L
313 #define TULIP_BUSMODE_CACHE_ALIGN32 0x0000C000L
314 #define TULIP_BUSMODE_TXPOLL_NEVER 0x00000000L
315 #define TULIP_BUSMODE_TXPOLL_200000ns 0x00020000L
316 #define TULIP_BUSMODE_TXPOLL_800000ns 0x00040000L
317 #define TULIP_BUSMODE_TXPOLL_1600000ns 0x00060000L
318 #define TULIP_BUSMODE_TXPOLL_12800ns 0x00080000L /* 21041 only */
319 #define TULIP_BUSMODE_TXPOLL_25600ns 0x000A0000L /* 21041 only */
320 #define TULIP_BUSMODE_TXPOLL_51200ns 0x000C0000L /* 21041 only */
321 #define TULIP_BUSMODE_TXPOLL_102400ns 0x000E0000L /* 21041 only */
322 #define TULIP_BUSMODE_DESC_BIGENDIAN 0x00100000L /* 21041 only */
323 #define TULIP_BUSMODE_READMULTIPLE 0x00200000L /* */
324
325 #define TULIP_REG_CFDA 0x40
326 #define TULIP_CFDA_SLEEP 0x80000000L
327 #define TULIP_CFDA_SNOOZE 0x40000000L
328
329 #define TULIP_GP_PINSET 0x00000100L
330 /*
331 * These are the defintitions used for the DEC 21140
332 * evaluation board.
333 */
334 #define TULIP_GP_EB_PINS 0x0000001F /* General Purpose Pin directions */
335 #define TULIP_GP_EB_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */
336 #define TULIP_GP_EB_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */
337 #define TULIP_GP_EB_INIT 0x0000000B /* No loopback --- point-to-point */
338
339 /*
340 * These are the defintitions used for the SMC9332 (21140) board.
341 */
342 #define TULIP_GP_SMC_9332_PINS 0x0000003F /* General Purpose Pin directions */
343 #define TULIP_GP_SMC_9332_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */
344 #define TULIP_GP_SMC_9332_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */
345 #define TULIP_GP_SMC_9332_INIT 0x00000009 /* No loopback --- point-to-point */
346
347 #define TULIP_OUI_SMC_0 0x00
348 #define TULIP_OUI_SMC_1 0x00
349 #define TULIP_OUI_SMC_2 0xC0
350
351 /*
352 * There are the definitions used for the DEC DE500
353 * 10/100 family of boards
354 */
355 #define TULIP_GP_DE500_PINS 0x0000001FL
356 #define TULIP_GP_DE500_LINK_PASS 0x00000080L
357 #define TULIP_GP_DE500_SYM_LINK 0x00000040L
358 #define TULIP_GP_DE500_SIGNAL_DETECT 0x00000020L
359 #define TULIP_GP_DE500_PHY_RESET 0x00000010L
360 #define TULIP_GP_DE500_HALFDUPLEX 0x00000008L
361 #define TULIP_GP_DE500_PHY_LOOPBACK 0x00000004L
362 #define TULIP_GP_DE500_FORCE_LED 0x00000002L
363 #define TULIP_GP_DE500_FORCE_100 0x00000001L
364
365 /*
366 * These are the defintitions used for the Cogent EM100
367 * 21140 board.
368 */
369 #define TULIP_GP_EM100_PINS 0x0000003F /* General Purpose Pin directions */
370 #define TULIP_GP_EM100_INIT 0x00000009 /* No loopback --- point-to-point */
371 #define TULIP_OUI_COGENT_0 0x00
372 #define TULIP_OUI_COGENT_1 0x00
373 #define TULIP_OUI_COGENT_2 0x92
374 #define TULIP_COGENT_EM100TX_ID 0x12
375 #define TULIP_COGENT_EM100FX_ID 0x15
376
377
378 /*
379 * These are the defintitions used for the Znyx ZX342
380 * 10/100 board
381 */
382 #define TULIP_OUI_ZNYX_0 0x00
383 #define TULIP_OUI_ZNYX_1 0xC0
384 #define TULIP_OUI_ZNYX_2 0x95
385
386 #define TULIP_ZNYX_ID_ZX312 0x0602
387 #define TULIP_ZNYX_ID_ZX312T 0x0622
388 #define TULIP_ZNYX_ID_ZX314_INTA 0x0701
389 #define TULIP_ZNYX_ID_ZX314 0x0711
390 #define TULIP_ZNYX_ID_ZX315_INTA 0x0801
391 #define TULIP_ZNYX_ID_ZX315 0x0811
392 #define TULIP_ZNYX_ID_ZX342 0x0901
393 #define TULIP_ZNYX_ID_ZX342B 0x0921
394 #define TULIP_ZNYX_ID_ZX342_X3 0x0902
395 #define TULIP_ZNYX_ID_ZX342_X4 0x0903
396 #define TULIP_ZNYX_ID_ZX344 0x0A01
397 #define TULIP_ZNYX_ID_ZX351 0x0B01
398 #define TULIP_ZNYX_ID_ZX345 0x0C01
399 #define TULIP_ZNYX_ID_ZX311 0x0D01
400 #define TULIP_ZNYX_ID_ZX346 0x0E01
401
402 #define TULIP_GP_ZX34X_PINS 0x0000001F /* General Purpose Pin directions */
403 #define TULIP_GP_ZX344_PINS 0x0000000B /* General Purpose Pin directions */
404 #define TULIP_GP_ZX345_PINS 0x00000003 /* General Purpose Pin directions */
405 #define TULIP_GP_ZX346_PINS 0x00000043 /* General Purpose Pin directions */
406 #define TULIP_GP_ZX34X_LNKFAIL 0x00000080 /* 10Mb/s Link Failure */
407 #define TULIP_GP_ZX34X_SYMDET 0x00000040 /* 100Mb/s Symbol Detect */
408 #define TULIP_GP_ZX345_PHYACT 0x00000040 /* PHY Activity */
409 #define TULIP_GP_ZX34X_SIGDET 0x00000020 /* 100Mb/s Signal Detect */
410 #define TULIP_GP_ZX346_AUTONEG_ENABLED 0x00000020 /* 802.3u autoneg enabled */
411 #define TULIP_GP_ZX342_COLENA 0x00000008 /* 10t Ext LB */
412 #define TULIP_GP_ZX344_ROTINT 0x00000008 /* PPB IRQ rotation */
413 #define TULIP_GP_ZX345_SPEED10 0x00000008 /* 10Mb speed detect */
414 #define TULIP_GP_ZX346_SPEED100 0x00000008 /* 100Mb speed detect */
415 #define TULIP_GP_ZX34X_NCOLENA 0x00000004 /* 10t Int LB */
416 #define TULIP_GP_ZX34X_RXMATCH 0x00000004 /* RX Match */
417 #define TULIP_GP_ZX346_FULLDUPLEX 0x00000004 /* Full Duplex Sensed */
418 #define TULIP_GP_ZX34X_LB102 0x00000002 /* 100tx twister LB */
419 #define TULIP_GP_ZX34X_NLB101 0x00000001 /* PDT/PDR LB */
420 #define TULIP_GP_ZX34X_INIT 0x00000009
421
422 /*
423 * Compex's OUI. We need to twiddle a bit on their 21041 card.
424 */
425 #define TULIP_OUI_COMPEX_0 0x00
426 #define TULIP_OUI_COMPEX_1 0x80
427 #define TULIP_OUI_COMPEX_2 0x48
428 #define TULIP_21041_COMPEX_XREGDATA 1
429
430 /*
431 * Asante's OUI and stuff...
432 */
433 #define TULIP_OUI_ASANTE_0 0x00
434 #define TULIP_OUI_ASANTE_1 0x00
435 #define TULIP_OUI_ASANTE_2 0x94
436 #define TULIP_GP_ASANTE_PINS 0x000000bf /* GP pin config */
437 #define TULIP_GP_ASANTE_PHYRESET 0x00000008 /* Reset PHY */
438
439 /*
440 * ACCTON EN1207 specialties
441 */
442
443 #define TULIP_OUI_EN1207_0 0x00
444 #define TULIP_OUI_EN1207_1 0x00
445 #define TULIP_OUI_EN1207_2 0xE8
446
447 #define TULIP_CSR8_EN1207 0x08
448 #define TULIP_CSR9_EN1207 0x00
449 #define TULIP_CSR10_EN1207 0x03
450 #define TULIP_CSR11_EN1207 0x1F
451
452 #define TULIP_GP_EN1207_BNC_INIT 0x0000011B
453 #define TULIP_GP_EN1207_UTP_INIT 0x9E00000B
454 #define TULIP_GP_EN1207_100_INIT 0x6D00031B
455
456 /*
457 * SROM definitions for the 21140 and 21041.
458 */
459 #define SROMXREG 0x0400
460 #define SROMSEL 0x0800
461 #define SROMRD 0x4000
462 #define SROMWR 0x2000
463 #define SROMDIN 0x0008
464 #define SROMDOUT 0x0004
465 #define SROMDOUTON 0x0004
466 #define SROMDOUTOFF 0x0004
467 #define SROMCLKON 0x0002
468 #define SROMCLKOFF 0x0002
469 #define SROMCSON 0x0001
470 #define SROMCSOFF 0x0001
471 #define SROMCS 0x0001
472
473 #define SROMCMD_MODE 4
474 #define SROMCMD_WR 5
475 #define SROMCMD_RD 6
476
477 #define SROM_BITWIDTH 6
478
479 /*
480 * MII Definitions for the 21041 and 21140/21140A/21142
481 */
482 #define MII_PREAMBLE (~0)
483 #define MII_TEST 0xAAAAAAAA
484 #define MII_RDCMD 0xF6 /* 1111.0110 */
485 #define MII_WRCMD 0xF5 /* 1111.0101 */
486 #define MII_DIN 0x00080000
487 #define MII_RD 0x00040000
488 #define MII_WR 0x00000000
489 #define MII_DOUT 0x00020000
490 #define MII_CLK 0x00010000
491 #define MII_CLKON MII_CLK
492 #define MII_CLKOFF MII_CLK
493
494 #define PHYREG_CONTROL 0
495 #define PHYREG_STATUS 1
496 #define PHYREG_IDLOW 2
497 #define PHYREG_IDHIGH 3
498 #define PHYREG_AUTONEG_ADVERTISEMENT 4
499 #define PHYREG_AUTONEG_ABILITIES 5
500 #define PHYREG_AUTONEG_EXPANSION 6
501 #define PHYREG_AUTONEG_NEXTPAGE 7
502
503 #define PHYSTS_100BASET4 0x8000
504 #define PHYSTS_100BASETX_FD 0x4000
505 #define PHYSTS_100BASETX 0x2000
506 #define PHYSTS_10BASET_FD 0x1000
507 #define PHYSTS_10BASET 0x0800
508 #define PHYSTS_AUTONEG_DONE 0x0020
509 #define PHYSTS_REMOTE_FAULT 0x0010
510 #define PHYSTS_CAN_AUTONEG 0x0008
511 #define PHYSTS_LINK_UP 0x0004
512 #define PHYSTS_JABBER_DETECT 0x0002
513 #define PHYSTS_EXTENDED_REGS 0x0001
514
515 #define PHYCTL_RESET 0x8000
516 #define PHYCTL_SELECT_100MB 0x2000
517 #define PHYCTL_AUTONEG_ENABLE 0x1000
518 #define PHYCTL_ISOLATE 0x0400
519 #define PHYCTL_AUTONEG_RESTART 0x0200
520 #define PHYCTL_FULL_DUPLEX 0x0100
521
522 /*
523 * Definitions for the DE425.
524 */
525 #define DE425_CFID 0x08 /* Configuration Id */
526 #define DE425_CFCS 0x0C /* Configuration Command-Status */
527 #define DE425_CFRV 0x18 /* Configuration Revision */
528 #define DE425_CFLT 0x1C /* Configuration Latency Timer */
529 #define DE425_CBIO 0x28 /* Configuration Base IO Address */
530 #define DE425_CFDA 0x2C /* Configuration Driver Area */
531 #define DE425_ENETROM_OFFSET 0xC90 /* Offset in I/O space for ENETROM */
532 #define DE425_CFG0 0xC88 /* IRQ register */
533 #define DE425_EISAID 0x10a34250 /* EISA device id */
534 #define DE425_EISA_IOSIZE 0x100
535
536 #define DEC_VENDORID 0x1011
537 #define CHIPID_21040 0x0002
538 #define CHIPID_21140 0x0009
539 #define CHIPID_21041 0x0014
540 #define CHIPID_21142 0x0019
541 #define PCI_VENDORID(x) ((x) & 0xFFFF)
542 #define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF)
543
544 /*
545 * Generic SROM Format
546 *
547 *
548 */
549
550 typedef struct {
551 u_int8_t sh_idbuf[18];
552 u_int8_t sh_version;
553 u_int8_t sh_adapter_count;
554 u_int8_t sh_ieee802_address[6];
555 } tulip_srom_header_t;
556
557 typedef struct {
558 u_int8_t sai_device;
559 u_int8_t sai_leaf_offset_lowbyte;
560 u_int8_t sai_leaf_offset_highbyte;
561 } tulip_srom_adapter_info_t;
562
563 typedef enum {
564 TULIP_SROM_CONNTYPE_10BASET =0x0000,
565 TULIP_SROM_CONNTYPE_BNC =0x0001,
566 TULIP_SROM_CONNTYPE_AUI =0x0002,
567 TULIP_SROM_CONNTYPE_100BASETX =0x0003,
568 TULIP_SROM_CONNTYPE_100BASET4 =0x0006,
569 TULIP_SROM_CONNTYPE_100BASEFX =0x0007,
570 TULIP_SROM_CONNTYPE_MII_10BASET =0x0009,
571 TULIP_SROM_CONNTYPE_MII_100BASETX =0x000D,
572 TULIP_SROM_CONNTYPE_MII_100BASET4 =0x000F,
573 TULIP_SROM_CONNTYPE_MII_100BASEFX =0x0010,
574 TULIP_SROM_CONNTYPE_10BASET_NWAY =0x0100,
575 TULIP_SROM_CONNTYPE_10BASET_FD =0x0204,
576 TULIP_SROM_CONNTYPE_MII_10BASET_FD =0x020A,
577 TULIP_SROM_CONNTYPE_100BASETX_FD =0x020E,
578 TULIP_SROM_CONNTYPE_MII_100BASETX_FD =0x0211,
579 TULIP_SROM_CONNTYPE_10BASET_NOLINKPASS =0x0400,
580 TULIP_SROM_CONNTYPE_AUTOSENSE =0x0800,
581 TULIP_SROM_CONNTYPE_AUTOSENSE_POWERUP =0x8800,
582 TULIP_SROM_CONNTYPE_AUTOSENSE_NWAY =0x9000,
583 TULIP_SROM_CONNTYPE_NOT_USED =0xFFFF
584 } tulip_srom_connection_t;
585
586 typedef enum {
587 TULIP_SROM_MEDIA_10BASET =0x0000,
588 TULIP_SROM_MEDIA_BNC =0x0001,
589 TULIP_SROM_MEDIA_AUI =0x0002,
590 TULIP_SROM_MEDIA_100BASETX =0x0003,
591 TULIP_SROM_MEDIA_10BASET_FD =0x0004,
592 TULIP_SROM_MEDIA_100BASETX_FD =0x0005,
593 TULIP_SROM_MEDIA_100BASET4 =0x0006,
594 TULIP_SROM_MEDIA_100BASEFX =0x0007,
595 TULIP_SROM_MEDIA_100BASEFX_FD =0x0008
596 } tulip_srom_media_t;
597
598 #define TULIP_SROM_21041_EXTENDED 0x40
599
600 #define TULIP_SROM_2114X_NOINDICATOR 0x8000
601 #define TULIP_SROM_2114X_DEFAULT 0x4000
602 #define TULIP_SROM_2114X_POLARITY 0x0080
603 #define TULIP_SROM_2114X_CMDBITS(n) (((n) & 0x0071) << 18)
604 #define TULIP_SROM_2114X_BITPOS(b) (1 << (((b) & 0x0E) >> 1))
605
606
607
608 #endif /* !defined(_DC21040_H) */
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