FreeBSD/Linux Kernel Cross Reference
sys/pci/dpt_pci.h
1 /*
2 * Copyright (c) 1997 by Simon Shapiro
3 * All Rights Reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions, and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #ident "$FreeBSD: src/sys/pci/dpt_pci.h,v 1.1.2.3 1999/09/05 08:21:00 peter Exp $"
31
32 #define DPT_VENDOR_ID 0x00001044
33 #define DPT_DEVICE_ID 0x0000a400
34
35 /* The following are taken, shamelessly from Linux include/linux/pci.h */
36
37 /*
38 * Under PCI, each device has 256 bytes of configuration address space,
39 * of which the first 64 bytes are standardized as follows:
40 */
41 #define PCI_VENDOR_ID 0x00 /* 16 bits */
42 #define PCI_DEVICE_ID 0x02 /* 16 bits */
43 #define PCI_COMMAND 0x04 /* 16 bits */
44 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
45 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
46 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
47 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
48 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
49 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
50 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
51 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
52 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
53 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
54
55 #define PCI_STATUS 0x06 /* 16 bits */
56 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
57 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features */
58
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
60 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
61 #ifndef PCI_STATUS_DEVSEL_MASK
62 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
63 #define PCI_STATUS_DEVSEL_FAST 0x000
64 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
65 #define PCI_STATUS_DEVSEL_SLOW 0x400
66 #endif
67 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
68 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
69 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
70 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
71 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
72
73 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
74 * revision */
75 #define PCI_REVISION_ID 0x08 /* Revision ID */
76 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
77 #define PCI_CLASS_DEVICE 0x0a /* Device class */
78
79 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
80 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
81 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
82 #define PCI_BIST 0x0f /* 8 bits */
83 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
84 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
85 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
86
87 /*
88 * Base addresses specify locations in memory or I/O space.
89 * Decoded size can be determined by writing a value of
90 * 0xffffffff to the register, and reading it back. Only
91 * 1 bits are decoded.
92 */
93 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
94 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */
95 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */
96 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
97 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
98 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
99 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
100 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
101 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
102 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
103 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
104 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M */
105 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
106 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
107 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0f)
108 #define PCI_BASE_ADDRESS_IO_MASK (~0x03)
109 /* bit 1 is reserved if address_space = 1 */
110
111 #define PCI_CARDBUS_CIS 0x28
112 #define PCI_SUBSYSTEM_ID 0x2c
113 #define PCI_SUBSYSTEM_VENDOR_ID 0x2e
114 #define PCI_ROM_ADDRESS 0x30 /* 32 bits */
115 #define PCI_ROM_ADDRESS_ENABLE 0x01 /* Write 1 to enable ROM, bits 31..11
116 * are address, 10..2 are reserved */
117
118 /* 0x34-0x3b are reserved */
119 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
120 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
121 #define PCI_MIN_GNT 0x3e /* 8 bits */
122 #define PCI_MAX_LAT 0x3f /* 8 bits */
123
124 #define PCI_CLASS_NOT_DEFINED 0x0000
125 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
126
127 #define PCI_BASE_CLASS_STORAGE 0x01
128 #define PCI_CLASS_STORAGE_SCSI 0x0100
129 #define PCI_CLASS_STORAGE_IDE 0x0101
130 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
131 #define PCI_CLASS_STORAGE_IPI 0x0103
132 #define PCI_CLASS_STORAGE_RAID 0x0104
133 #define PCI_CLASS_STORAGE_OTHER 0x0180
134
135 #define PCI_BASE_CLASS_NETWORK 0x02
136 #define PCI_CLASS_NETWORK_ETHERNET 0x0200
137 #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
138 #define PCI_CLASS_NETWORK_FDDI 0x0202
139 #define PCI_CLASS_NETWORK_ATM 0x0203
140 #define PCI_CLASS_NETWORK_OTHER 0x0280
141
142 #define PCI_BASE_CLASS_DISPLAY 0x03
143 #define PCI_CLASS_DISPLAY_VGA 0x0300
144 #define PCI_CLASS_DISPLAY_XGA 0x0301
145 #define PCI_CLASS_DISPLAY_OTHER 0x0380
146
147 #define PCI_BASE_CLASS_MULTIMEDIA 0x04
148 #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
149 #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
150 #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
151
152 #define PCI_BASE_CLASS_MEMORY 0x05
153 #define PCI_CLASS_MEMORY_RAM 0x0500
154 #define PCI_CLASS_MEMORY_FLASH 0x0501
155 #define PCI_CLASS_MEMORY_OTHER 0x0580
156
157 #define PCI_BASE_CLASS_BRIDGE 0x06
158 #define PCI_CLASS_BRIDGE_HOST 0x0600
159 #define PCI_CLASS_BRIDGE_ISA 0x0601
160 #define PCI_CLASS_BRIDGE_EISA 0x0602
161 #define PCI_CLASS_BRIDGE_MC 0x0603
162 #define PCI_CLASS_BRIDGE_PCI 0x0604
163 #define PCI_CLASS_BRIDGE_PCMCIA 0x0605
164 #define PCI_CLASS_BRIDGE_NUBUS 0x0606
165 #define PCI_CLASS_BRIDGE_CARDBUS 0x0607
166 #define PCI_CLASS_BRIDGE_OTHER 0x0680
167
168
169 #define PCI_BASE_CLASS_COMMUNICATION 0x07
170 #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
171 #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
172 #define PCI_CLASS_COMMUNICATION_OTHER 0x0780
173
174 #define PCI_BASE_CLASS_SYSTEM 0x08
175 #define PCI_CLASS_SYSTEM_PIC 0x0800
176 #define PCI_CLASS_SYSTEM_DMA 0x0801
177 #define PCI_CLASS_SYSTEM_TIMER 0x0802
178 #define PCI_CLASS_SYSTEM_RTC 0x0803
179 #define PCI_CLASS_SYSTEM_OTHER 0x0880
180
181 #define PCI_BASE_CLASS_INPUT 0x09
182 #define PCI_CLASS_INPUT_KEYBOARD 0x0900
183 #define PCI_CLASS_INPUT_PEN 0x0901
184 #define PCI_CLASS_INPUT_MOUSE 0x0902
185 #define PCI_CLASS_INPUT_OTHER 0x0980
186
187 #define PCI_BASE_CLASS_DOCKING 0x0a
188 #define PCI_CLASS_DOCKING_GENERIC 0x0a00
189 #define PCI_CLASS_DOCKING_OTHER 0x0a01
190
191 #define PCI_BASE_CLASS_PROCESSOR 0x0b
192 #define PCI_CLASS_PROCESSOR_386 0x0b00
193 #define PCI_CLASS_PROCESSOR_486 0x0b01
194 #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
195 #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
196 #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
197 #define PCI_CLASS_PROCESSOR_CO 0x0b40
198
199 #define PCI_BASE_CLASS_SERIAL 0x0c
200 #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
201 #define PCI_CLASS_SERIAL_ACCESS 0x0c01
202 #define PCI_CLASS_SERIAL_SSA 0x0c02
203 #define PCI_CLASS_SERIAL_USB 0x0c03
204 #define PCI_CLASS_SERIAL_FIBER 0x0c04
205
206 #define PCI_CLASS_OTHERS 0xff
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