FreeBSD/Linux Kernel Cross Reference
sys/pci/dpt_pci.h

     /*
      *       Copyright (c) 1997 by Simon Shapiro
      *       All Rights Reserved
      *
      * Redistribution and use in source and binary forms, with or without
      * modification, are permitted provided that the following conditions
      * are met:
      * 1. Redistributions of source code must retain the above copyright
      *    notice, this list of conditions, and the following disclaimer,
     *    without modification, immediately at the beginning of the file.
     * 2. Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the distribution.
     * 3. The name of the author may not be used to endorse or promote products
     *    derived from this software without specific prior written permission.
     *
     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
     * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     * SUCH DAMAGE.
     */
    
    #ident "$FreeBSD: src/sys/pci/dpt_pci.h,v 1.1.2.3 1999/09/05 08:21:00 peter Exp $"
    
    #define DPT_VENDOR_ID             0x00001044
    #define DPT_DEVICE_ID             0x0000a400
    
    /* The following are taken, shamelessly from Linux include/linux/pci.h */
    
    /*
     * Under PCI, each device has 256 bytes of configuration address space,
     * of which the first 64 bytes are standardized as follows:
     */
    #define PCI_VENDOR_ID           0x00    /* 16 bits */
    #define PCI_DEVICE_ID           0x02    /* 16 bits */
    #define PCI_COMMAND             0x04    /* 16 bits */
    #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
    #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
    #define  PCI_COMMAND_MASTER     0x4     /* Enable bus mastering */
    #define  PCI_COMMAND_SPECIAL    0x8     /* Enable response to special cycles */
    #define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
    #define  PCI_COMMAND_VGA_PALETTE 0x20   /* Enable palette snooping */
    #define  PCI_COMMAND_PARITY     0x40    /* Enable parity checking */
    #define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
    #define  PCI_COMMAND_SERR       0x100   /* Enable SERR */
    #define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */
    
    #define PCI_STATUS              0x06    /* 16 bits */
    #define  PCI_STATUS_66MHZ       0x20    /* Support 66 Mhz PCI 2.1 bus */
    #define  PCI_STATUS_UDF         0x40    /* Support User Definable Features */
    
    #define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
    #define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
    #ifndef PCI_STATUS_DEVSEL_MASK
    #define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
    #define  PCI_STATUS_DEVSEL_FAST 0x000
    #define  PCI_STATUS_DEVSEL_MEDIUM 0x200
    #define  PCI_STATUS_DEVSEL_SLOW 0x400
    #endif
    #define  PCI_STATUS_SIG_TARGET_ABORT 0x800      /* Set on target abort */
    #define  PCI_STATUS_REC_TARGET_ABORT 0x1000     /* Master ack of " */
    #define  PCI_STATUS_REC_MASTER_ABORT 0x2000     /* Set on master abort */
    #define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000     /* Set when we drive SERR */
    #define  PCI_STATUS_DETECTED_PARITY 0x8000      /* Set on parity error */
    
    #define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8
                                             * revision */
    #define PCI_REVISION_ID         0x08    /* Revision ID */
    #define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
    #define PCI_CLASS_DEVICE        0x0a    /* Device class */
    
    #define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
    #define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
    #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
    #define PCI_BIST                0x0f    /* 8 bits */
    #define PCI_BIST_CODE_MASK      0x0f    /* Return result */
    #define PCI_BIST_START          0x40    /* 1 to start BIST, 2 secs or less */
    #define PCI_BIST_CAPABLE        0x80    /* 1 if BIST capable */
    
    /*
     * Base addresses specify locations in memory or I/O space.
     * Decoded size can be determined by writing a value of
     * 0xffffffff to the register, and reading it back.  Only
     * 1 bits are decoded.
     */
    #define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
    #define PCI_BASE_ADDRESS_1      0x14    /* 32 bits */
    #define PCI_BASE_ADDRESS_2      0x18    /* 32 bits */
    #define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
    #define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
    #define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
    #define  PCI_BASE_ADDRESS_SPACE 0x01    /* 0 = memory, 1 = I/O */
   #define  PCI_BASE_ADDRESS_SPACE_IO 0x01
   #define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
   #define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
   #define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
   #define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M */
   #define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
   #define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
   #define  PCI_BASE_ADDRESS_MEM_MASK      (~0x0f)
   #define  PCI_BASE_ADDRESS_IO_MASK       (~0x03)
   /* bit 1 is reserved if address_space = 1 */
   
   #define PCI_CARDBUS_CIS         0x28
   #define PCI_SUBSYSTEM_ID        0x2c
   #define PCI_SUBSYSTEM_VENDOR_ID 0x2e
   #define PCI_ROM_ADDRESS         0x30    /* 32 bits */
   #define  PCI_ROM_ADDRESS_ENABLE 0x01    /* Write 1 to enable ROM, bits 31..11
                                            * are address, 10..2 are reserved */
   
   /* 0x34-0x3b are reserved */
   #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
   #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
   #define PCI_MIN_GNT             0x3e    /* 8 bits */
   #define PCI_MAX_LAT             0x3f    /* 8 bits */
   
   #define PCI_CLASS_NOT_DEFINED           0x0000
   #define PCI_CLASS_NOT_DEFINED_VGA       0x0001
   
   #define PCI_BASE_CLASS_STORAGE          0x01
   #define PCI_CLASS_STORAGE_SCSI          0x0100
   #define PCI_CLASS_STORAGE_IDE           0x0101
   #define PCI_CLASS_STORAGE_FLOPPY        0x0102
   #define PCI_CLASS_STORAGE_IPI           0x0103
   #define PCI_CLASS_STORAGE_RAID          0x0104
   #define PCI_CLASS_STORAGE_OTHER         0x0180
   
   #define PCI_BASE_CLASS_NETWORK          0x02
   #define PCI_CLASS_NETWORK_ETHERNET      0x0200
   #define PCI_CLASS_NETWORK_TOKEN_RING    0x0201
   #define PCI_CLASS_NETWORK_FDDI          0x0202
   #define PCI_CLASS_NETWORK_ATM           0x0203
   #define PCI_CLASS_NETWORK_OTHER         0x0280
   
   #define PCI_BASE_CLASS_DISPLAY          0x03
   #define PCI_CLASS_DISPLAY_VGA           0x0300
   #define PCI_CLASS_DISPLAY_XGA           0x0301
   #define PCI_CLASS_DISPLAY_OTHER         0x0380
   
   #define PCI_BASE_CLASS_MULTIMEDIA       0x04
   #define PCI_CLASS_MULTIMEDIA_VIDEO      0x0400
   #define PCI_CLASS_MULTIMEDIA_AUDIO      0x0401
   #define PCI_CLASS_MULTIMEDIA_OTHER      0x0480
   
   #define PCI_BASE_CLASS_MEMORY           0x05
   #define  PCI_CLASS_MEMORY_RAM           0x0500
   #define  PCI_CLASS_MEMORY_FLASH         0x0501
   #define  PCI_CLASS_MEMORY_OTHER         0x0580
   
   #define PCI_BASE_CLASS_BRIDGE           0x06
   #define  PCI_CLASS_BRIDGE_HOST          0x0600
   #define  PCI_CLASS_BRIDGE_ISA           0x0601
   #define  PCI_CLASS_BRIDGE_EISA          0x0602
   #define  PCI_CLASS_BRIDGE_MC            0x0603
   #define  PCI_CLASS_BRIDGE_PCI           0x0604
   #define  PCI_CLASS_BRIDGE_PCMCIA        0x0605
   #define  PCI_CLASS_BRIDGE_NUBUS         0x0606
   #define  PCI_CLASS_BRIDGE_CARDBUS       0x0607
   #define  PCI_CLASS_BRIDGE_OTHER         0x0680
   
   
   #define PCI_BASE_CLASS_COMMUNICATION    0x07
   #define PCI_CLASS_COMMUNICATION_SERIAL  0x0700
   #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
   #define PCI_CLASS_COMMUNICATION_OTHER   0x0780
   
   #define PCI_BASE_CLASS_SYSTEM           0x08
   #define PCI_CLASS_SYSTEM_PIC            0x0800
   #define PCI_CLASS_SYSTEM_DMA            0x0801
   #define PCI_CLASS_SYSTEM_TIMER          0x0802
   #define PCI_CLASS_SYSTEM_RTC            0x0803
   #define PCI_CLASS_SYSTEM_OTHER          0x0880
   
   #define PCI_BASE_CLASS_INPUT            0x09
   #define PCI_CLASS_INPUT_KEYBOARD        0x0900
   #define PCI_CLASS_INPUT_PEN             0x0901
   #define PCI_CLASS_INPUT_MOUSE           0x0902
   #define PCI_CLASS_INPUT_OTHER           0x0980
   
   #define PCI_BASE_CLASS_DOCKING          0x0a
   #define PCI_CLASS_DOCKING_GENERIC       0x0a00
   #define PCI_CLASS_DOCKING_OTHER         0x0a01
   
   #define PCI_BASE_CLASS_PROCESSOR        0x0b
   #define PCI_CLASS_PROCESSOR_386         0x0b00
   #define PCI_CLASS_PROCESSOR_486         0x0b01
   #define PCI_CLASS_PROCESSOR_PENTIUM     0x0b02
   #define PCI_CLASS_PROCESSOR_ALPHA       0x0b10
   #define PCI_CLASS_PROCESSOR_POWERPC     0x0b20
   #define PCI_CLASS_PROCESSOR_CO          0x0b40
   
   #define PCI_BASE_CLASS_SERIAL           0x0c
   #define PCI_CLASS_SERIAL_FIREWIRE       0x0c00
   #define PCI_CLASS_SERIAL_ACCESS         0x0c01
   #define PCI_CLASS_SERIAL_SSA            0x0c02
   #define PCI_CLASS_SERIAL_USB            0x0c03
   #define PCI_CLASS_SERIAL_FIBER          0x0c04
   
   #define PCI_CLASS_OTHERS                0xff

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