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sys/pci/ide_pci.c
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1 /* 2 * Copyright 1996 Massachusetts Institute of Technology 3 * 4 * Permission to use, copy, modify, and distribute this software and 5 * its documentation for any purpose and without fee is hereby 6 * granted, provided that both the above copyright notice and this 7 * permission notice appear in all copies, that both the above 8 * copyright notice and this permission notice appear in all 9 * supporting documentation, and that the name of M.I.T. not be used 10 * in advertising or publicity pertaining to distribution of the 11 * software without specific, written prior permission. M.I.T. makes 12 * no representations about the suitability of this software for any 13 * purpose. It is provided "as is" without express or implied 14 * warranty. 15 * 16 * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS 17 * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE, 18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT 20 * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include "pci.h" 33 #if NPCI > 0 34 #include "opt_wd.h" 35 #include "wd.h" 36 37 #if NWDC > 0 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/buf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <vm/vm.h> 45 #include <vm/pmap.h> 46 47 #include <i386/isa/wdreg.h> 48 #ifdef PC98 49 #include <pc98/pc98/pc98.h> 50 #else 51 #include <i386/isa/isa.h> 52 #endif 53 #include <i386/isa/isa_device.h> 54 55 #include <pci/pcivar.h> 56 #include <pci/pcireg.h> 57 #include <pci/ide_pcireg.h> 58 59 #ifndef MIN 60 #define MIN(a,b) (((a)<(b))?(a):(b)) 61 #endif 62 63 #define PROMISE_ULTRA33 0x4d33105a 64 65 struct ide_pci_cookie; /* structs vendor_fns, ide_pci_cookie are recursive */ 66 67 struct vendor_fns { 68 int (*vendor_dmainit) /* initialize DMA controller and drive */ 69 (struct ide_pci_cookie *cookie, 70 struct wdparams *wp, 71 int (*wdcmd)(int, void *), 72 void *); 73 74 void (*vendor_status) /* prints off DMA timing info */ 75 (struct ide_pci_cookie *cookie); 76 }; 77 78 /* 79 * XXX the fact that this list keeps all kinds of info on PCI controllers 80 * is pretty grotty-- much of this should be replaced by a proper integration 81 * of PCI probes into the wd driver. 82 * XXX if we're going to support native-PCI controllers, we also need to 83 * keep the address of the IDE control block register, which is something wd.c 84 * needs to know, which is why this info is in the wrong place. 85 */ 86 87 struct ide_pci_cookie { 88 LIST_ENTRY(ide_pci_cookie) le; 89 int iobase_wd; 90 int ctlr; /* controller 0/1 on PCI IDE interface */ 91 int unit; 92 int iobase_bm; /* SFF-8038 control registers */ 93 int altiobase_wd; 94 pcici_t tag; 95 pcidi_t type; 96 struct ide_pci_prd *prd; 97 struct vendor_fns vs; 98 }; 99 100 struct ide_pci_softc { 101 LIST_HEAD(, ide_pci_cookie) cookies; 102 }; 103 104 static int 105 generic_dmainit(struct ide_pci_cookie *cookie, 106 struct wdparams *wp, 107 int (*wdcmd)(int, void *), 108 void *wdinfo); 109 110 static void 111 generic_status(struct ide_pci_cookie *cookie); 112 113 static void 114 via_571_status(struct ide_pci_cookie *cookie); 115 116 static int 117 via_571_dmainit(struct ide_pci_cookie *cookie, 118 struct wdparams *wp, 119 int (*wdcmd)(int, void *), 120 void *wdinfo); 121 122 static void 123 acer_status(struct ide_pci_cookie *cookie); 124 125 static int 126 acer_dmainit(struct ide_pci_cookie *cookie, 127 struct wdparams *wp, 128 int (*wdcmd)(int, void *), 129 void *wdinfo); 130 131 static void 132 intel_piix_dump_drive(char *ctlr, 133 int sitre, 134 int is_piix4, 135 int word40, 136 int word44, 137 int word48, 138 int word4a, 139 int drive); 140 141 static void 142 intel_piix_status(struct ide_pci_cookie *cookie); 143 static int 144 intel_piix_dmainit(struct ide_pci_cookie *cookie, 145 struct wdparams *wp, 146 int (*wdcmd)(int, void *), 147 void *wdinfo); 148 149 static struct ide_pci_cookie * 150 mkcookie(int iobase_wd, 151 int ctlr, 152 int unit, 153 int iobase_bm, 154 pcici_t tag, 155 pcidi_t type, 156 struct vendor_fns *vp, 157 int altiobase_wd); 158 159 160 161 static void ide_pci_attach(pcici_t tag, int unit); 162 static void *ide_pci_candma(int, int, int); 163 static int ide_pci_dmainit(void *, 164 struct wdparams *, 165 int (*)(int, void *), 166 void *); 167 168 static int ide_pci_dmaverify(void *, char *, u_long, int); 169 static int ide_pci_dmasetup(void *, char *, u_long, int); 170 static void ide_pci_dmastart(void *); 171 static int ide_pci_dmadone(void *); 172 static int ide_pci_status(void *); 173 static int ide_pci_iobase(void *xcp); 174 static int ide_pci_altiobase(void *xcp); 175 176 static struct ide_pci_softc softc; 177 178 static int ide_pci_softc_cookies_initted = 0; 179 180 extern struct isa_driver wdcdriver; 181 182 /* 183 * PRD_ALLOC_SIZE should be something that will not be allocated across a 64k 184 * boundary. 185 * PRD_MAX_SEGS is defined to be the maximum number of segments required for 186 * a transfer on an IDE drive, for an xfer that is linear in virtual memory. 187 * PRD_BUF_SIZE is the size of the buffer needed for a PRD table. 188 */ 189 #define PRD_ALLOC_SIZE PAGE_SIZE 190 #define PRD_MAX_SEGS ((256 * 512 / PAGE_SIZE) + 1) 191 #define PRD_BUF_SIZE PRD_MAX_SEGS * 8 192 193 static void *prdbuf = 0; 194 static void *prdbuf_next = 0; 195 196 /* 197 * Hardware specific IDE controller code. All vendor-specific code 198 * for handling IDE timing and other chipset peculiarities should be 199 * encapsulated here. 200 */ 201 202 /* helper funcs */ 203 204 /* 205 * nnn_mode() return the highest valid mode, or -1 if the mode class is 206 * not supported 207 */ 208 209 static __inline int 210 pio_mode(struct wdparams *wp) 211 { 212 if ((wp->wdp_atavalid & 2) == 2) { 213 if ((wp->wdp_eidepiomodes & 2) == 2) return 4; 214 if ((wp->wdp_eidepiomodes & 1) == 1) return 3; 215 } 216 return -1; 217 } 218 219 #if 0 220 static __inline int 221 dma_mode(struct wdparams *wp) 222 { 223 /* XXX not quite sure how to verify validity on this field */ 224 } 225 #endif 226 227 static __inline int 228 mwdma_mode(struct wdparams *wp) 229 { 230 /* 231 * XXX technically, using wdp_atavalid to test for validity of 232 * this field is not quite correct 233 */ 234 if ((wp->wdp_atavalid & 2) == 2) { 235 if ((wp->wdp_dmamword & 4) == 4) return 2; 236 if ((wp->wdp_dmamword & 2) == 2) return 1; 237 if ((wp->wdp_dmamword & 1) == 1) return 0; 238 } 239 return -1; 240 } 241 242 static __inline int 243 udma_mode(struct wdparams *wp) 244 { 245 if ((wp->wdp_atavalid & 4) == 4) { 246 if ((wp->wdp_udmamode & 4) == 4) return 2; 247 if ((wp->wdp_udmamode & 2) == 2) return 1; 248 if ((wp->wdp_udmamode & 1) == 1) return 0; 249 } 250 return -1; 251 } 252 253 254 /* Generic busmastering PCI-IDE */ 255 256 static int 257 generic_dmainit(struct ide_pci_cookie *cookie, 258 struct wdparams *wp, 259 int(*wdcmd)(int, void *), 260 void *wdinfo) 261 { 262 /* 263 * punt on the whole timing issue by looking for either a 264 * drive programmed for both PIO4 and mDMA2 (which use similar 265 * timing) or a drive in an UltraDMA mode (hopefully all 266 * controllers have separate timing for UDMA). one hopes that if 267 * the drive's DMA mode has been configured by the BIOS, the 268 * controller's has also. 269 * 270 * XXX there are examples where this approach is now known to be 271 * broken, at least on systems based on Intel chipsets. 272 */ 273 274 if ((pio_mode(wp) >= 4 && mwdma_mode(wp) >= 2) || 275 (udma_mode(wp) >= 2)) { 276 printf("ide_pci: generic_dmainit %04x:%d: warning, IDE controller timing not set\n", 277 cookie->iobase_wd, 278 cookie->unit); 279 /* If we're here, then this controller is most likely not set 280 for UDMA, even if the drive may be. Make the drive wise 281 up. */ 282 283 if(!wdcmd(WDDMA_MDMA2, wdinfo)) 284 printf("generic_dmainit: could not set multiword DMA mode!\n"); 285 return 1; 286 } 287 #ifdef IDE_PCI_DEBUG 288 printf("pio_mode: %d, mwdma_mode(wp): %d, udma_mode(wp): %d\n", 289 pio_mode(wp), mwdma_mode(wp), udma_mode(wp)); 290 #endif 291 return 0; 292 } 293 294 static void 295 generic_status(struct ide_pci_cookie *cookie) 296 { 297 printf("generic_status: no PCI IDE timing info available\n"); 298 } 299 300 static struct vendor_fns vs_generic = 301 { 302 generic_dmainit, 303 generic_status 304 }; 305 306 /* VIA Technologies "82C571" PCI-IDE controller core */ 307 308 static void 309 via_571_status(struct ide_pci_cookie *cookie) 310 { 311 int iobase_wd; 312 int ctlr, unit; 313 int iobase_bm; 314 pcici_t tag; 315 pcidi_t type; 316 u_long word40[5]; 317 int i, unitno; 318 319 iobase_wd = cookie->iobase_wd; 320 unit = cookie->unit; 321 ctlr = cookie->ctlr; 322 iobase_bm = cookie->iobase_bm; 323 tag = cookie->tag; 324 type = cookie->type; 325 326 unitno = ctlr * 2 + unit; 327 328 for (i=0; i<5; i++) { 329 word40[i] = pci_conf_read(tag, i * 4 + 0x40); 330 } 331 332 if (ctlr == 0) 333 printf("via_571_status: Primary IDE prefetch/postwrite %s/%s\n", 334 word40[0] & 0x8000 ? "enabled" : "disabled", 335 word40[0] & 0x4000 ? "enabled" : "disabled"); 336 else 337 printf("via_571_status: Secondary IDE prefetch/postwrite %s/%s\n", 338 word40[0] & 0x2000 ? "enabled" : "disabled", 339 word40[0] & 0x1000 ? "enabled" : "disabled"); 340 341 printf("via_571_status: busmaster status read retry %s\n", 342 (word40[1] & 0x08) ? "enabled" : "disabled"); 343 344 345 printf("via_571_status: %s drive %d data setup=%d active=%d recovery=%d\n", 346 unitno < 2 ? "primary" : "secondary", 347 unitno & 1, 348 ((u_int)(word40[3] >> ((3 - unitno) * 2)) & 3) + 1, 349 ((u_int)(word40[2] >> (((3 - unitno) * 8) + 4)) & 0x0f) + 1, 350 ((u_int)(word40[2] >> ((3 - unitno) * 8)) & 0x0f) + 1); 351 352 if (ctlr == 0) 353 printf("via_571_status: primary ctrl active=%d recovery=%d\n", 354 ((u_int)(word40[3] >> 28) & 0x0f) + 1, 355 ((u_int)(word40[2] >> 24) & 0x0f) + 1); 356 else 357 printf("via_571_status: secondary ctrl active=%d recovery=%d\n", 358 ((u_int)(word40[3] >> 20) & 0x0f) + 1, 359 ((u_int)(word40[2] >> 16) & 0x0f) + 1); 360 361 /* UltraDMA dump */ 362 { 363 int foo; 364 365 foo = word40[4] >> ((3 - unitno) * 8); 366 printf("via_571_status: %s drive %d udma method=%d enable=%d PIOmode=%d cycle=%d\n", 367 i < 2 ? "primary" : "secondary", 368 i & 1, 369 (foo >> 7) & 1, 370 (foo >> 6) & 1, 371 (foo >> 5) & 1, 372 (foo & 3) + 2); 373 } 374 } 375 376 /* 377 * XXX timing values set here are only good for 30/33MHz buses; should deal 378 * with slower ones too (BTW: you overclock-- you lose) 379 */ 380 381 static int 382 via_571_dmainit(struct ide_pci_cookie *cookie, 383 struct wdparams *wp, 384 int(*wdcmd)(int, void *), 385 void *wdinfo) 386 { 387 u_long pci_revision; 388 int unitno; 389 390 pci_revision = pci_conf_read(cookie->tag, PCI_CLASS_REG) & 391 PCI_REVISION_MASK; 392 393 unitno = cookie->ctlr * 2 + cookie->unit; 394 395 /* If it's a UDMA drive on a '590, set it up */ 396 /* 397 * XXX the revision number we check for is of dubious validity. 398 * it's extracted from the AMD 645 datasheet. 399 */ 400 if (pci_revision >= 1 && udma_mode(wp) >= 2) { 401 unsigned int word50, mask, new; 402 word50 = pci_conf_read(cookie->tag, 0x50); 403 404 /* UDMA enable by SET FEATURES, DMA cycles, cycle time 2T */ 405 mask = 0xe3000000 >> (unitno * 8); 406 new = 0x40000000 >> (unitno * 8); 407 408 word50 &= ~mask; 409 word50 |= new; 410 411 pci_conf_write(cookie->tag, 0x50, word50); 412 413 /* 414 * With the '590, drive configuration should come *after* the 415 * controller configuration, to make sure the controller sees 416 * the SET FEATURES command and does the right thing. 417 */ 418 /* Set UDMA mode 2 on drive */ 419 if (bootverbose) 420 printf("via_571_dmainit: setting ultra DMA mode 2\n"); 421 if (!wdcmd(WDDMA_UDMA2, wdinfo)) { 422 printf("via_571_dmainit: setting DMA mode failed\n"); 423 return 0; 424 } 425 426 if (bootverbose) 427 via_571_status(cookie); 428 return 1; 429 430 } 431 432 /* otherwise, try and program it for MW DMA mode 2 */ 433 else if (mwdma_mode(wp) >= 2 && pio_mode(wp) >= 4) { 434 u_long workword; 435 436 /* Set multiword DMA mode 2 on drive */ 437 if (bootverbose) 438 printf("via_571_dmainit: setting multiword DMA mode 2\n"); 439 if (!wdcmd(WDDMA_MDMA2, wdinfo)) { 440 printf("via_571_dmainit: setting DMA mode failed\n"); 441 return 0; 442 } 443 444 /* Configure the controller appropriately for MWDMA mode 2 */ 445 446 workword = pci_conf_read(cookie->tag, 0x40); 447 448 /* 449 * enable prefetch/postwrite-- XXX may cause problems 450 * with CD-ROMs? 451 */ 452 workword |= 0xc000 >> (cookie->ctlr * 2); 453 454 /* FIFO configurations-- equal split, threshold 1/2 */ 455 workword &= 0x90ffffff; 456 workword |= 0x2a000000; 457 458 pci_conf_write(cookie->tag, 0x40, workword); 459 460 workword = pci_conf_read(cookie->tag, 0x44); 461 462 /* enable status read retry */ 463 workword |= 8; 464 465 /* enable FIFO flush on interrupt and end of sector */ 466 workword &= 0xff0cffff; 467 workword |= 0x00f00000; 468 pci_conf_write(cookie->tag, 0x44, workword); 469 470 workword = pci_conf_read(cookie->tag, 0x48); 471 /* set Mode2 timing */ 472 workword &= ~(0xff000000 >> (unitno * 8)); 473 workword |= 0x31000000 >> (unitno * 8); 474 pci_conf_write(cookie->tag, 0x48, workword); 475 476 /* set sector size */ 477 pci_conf_write(cookie->tag, cookie->ctlr ? 0x68 : 0x60, 0x200); 478 479 if (bootverbose) 480 via_571_status(cookie); 481 482 return 1; 483 484 } 485 return 0; 486 } 487 488 489 static struct vendor_fns vs_via_571 = 490 { 491 via_571_dmainit, 492 via_571_status 493 }; 494 495 /* Cyrix Cx5530 Courtesy of Whistle Communications */ 496 497 /* 498 * Verify that controller can handle a dma request for cp. Should 499 * not affect any hardware or driver state. 500 * Special version for 5530 that allows only transfers on 16 byte boundaries.(!) 501 * (Yes the Cyrix 5530 can only UDMA to cache-line boundaries.(bleh!)) 502 * Luckily nearly all disk IO is to kernel bufers which are page alligned. 503 * They may fix this in some other version of the chip, but it's in the latest 504 * at this time (Jan 1999). 505 */ 506 static int 507 cyrix_5530_dmaverify(void *xcp, char *vaddr, u_long count, int dir) 508 { 509 int badfu; 510 511 /* 512 * check for nonaligned or odd-length Stuff 513 */ 514 badfu = ((unsigned int)vaddr & 0xf) || (count & 0xf); 515 #ifdef DIAGNOSTIC 516 if (badfu) { 517 printf("ide_pci: dmaverify odd vaddr or length, "); 518 printf("vaddr = %p length = %08lx\n", (void *)vaddr, count); 519 } 520 #endif 521 return (!badfu); 522 } 523 524 /* 525 * XXX Unit number handling may be broken in the Cx5530 modules. 526 * It has only been checked with a single drive. 527 * 12MByte/Sec transfer rates were seen with Quantum Fireball drives 528 * with negligable CPU usage. 529 */ 530 static void 531 cyrix_5530_status(struct ide_pci_cookie *cookie) 532 { 533 int iobase_wd; 534 int ctlr, unit; 535 int iobase_bm; 536 pcici_t tag; 537 pcidi_t type; 538 u_long PIO_config; 539 u_long DMA_config; 540 int unitno; 541 542 iobase_wd = cookie->iobase_wd; 543 unit = cookie->unit; 544 ctlr = cookie->ctlr; 545 iobase_bm = cookie->iobase_bm; 546 tag = cookie->tag; 547 type = cookie->type; 548 549 unitno = ctlr * 2 + unit; 550 551 PIO_config = inl(iobase_bm + (unit * 0x10) + 0x20); 552 DMA_config = inl(iobase_bm + (unit * 0x10) + 0x24); 553 554 555 printf("cyrix_5530_status: %s:%u IDE PIO cfg: 0x%08lx\n", 556 (ctlr ? "Secondary" : "Primary"), unit, PIO_config); 557 printf("cyrix_5530_status: %s:%u IDE DMA cfg: 0x%08lx\n", 558 (ctlr ? "Secondary" : "Primary"), unit, DMA_config); 559 } 560 561 /* 562 * XXX timing values set here are only good for 30/33MHz buses; should deal 563 * with slower ones too (BTW: you overclock-- you lose) 564 */ 565 566 static int 567 cyrix_5530_dmainit(struct ide_pci_cookie *cookie, 568 struct wdparams *wp, 569 int(*wdcmd)(int, void *), 570 void *wdinfo) 571 { 572 u_long pci_revision; 573 int unitno; 574 int iobase_bm; 575 int unit; 576 int drivemode; 577 int mode; 578 int regval; 579 580 /*cookie->unit = 0; */ /* XXX */ 581 unit = cookie->unit; 582 pci_revision = pci_conf_read(cookie->tag, PCI_CLASS_REG) & 583 PCI_REVISION_MASK; 584 585 unitno = cookie->ctlr * 2 + unit; 586 iobase_bm = cookie->iobase_bm; 587 588 printf("Setting using 0x%x\n", iobase_bm); 589 if ((cookie->ctlr == 0) && (unit == 0)) /* XXX */ 590 outb(iobase_bm + (unit * 0x10) + BMISTA_PORT, 0xe6); 591 /* If it's a UDMA drive on a '5530, set it up */ 592 /* 593 * depending on what the drive can do, 594 * set the correct modes, 595 */ 596 printf("wd%d: mw=0x%x, pio=0x%x, pcirev=0x%lx, udma=0x%x\n", 597 unitno, 598 mwdma_mode(wp), pio_mode(wp), 599 pci_revision, udma_mode(wp)); 600 if (/* pci_revision >= 1 && */ udma_mode(wp) >= 0) { 601 switch(udma_mode(wp)) { 602 case 0: 603 mode = 0; 604 drivemode = WDDMA_UDMA0; 605 regval = 0x00921250; 606 break; 607 default: /* newer modes not supported */ 608 case 2: 609 #if 0 610 /* 611 * XXX The 5530 can do mode 2 but if you do use it, it will block all 612 * access to the PCI bus (and thus the ISA bus, PICs, PIT, etc. etc.) until the 613 * transfer is complete. Mode 2 swamps the 5530 so much it can't really cope 614 * with any other operations. Therefore, use mode 1 for drives that can 615 * do mode 2 (or more). (FALL THROUGH) 616 */ 617 618 619 mode = 2; 620 drivemode = WDDMA_UDMA2; 621 regval = 0x00911030; 622 break; 623 #endif 624 case 1: 625 mode = 1; 626 drivemode = WDDMA_UDMA1; 627 regval = 0x00911140; 628 break; 629 } 630 /* 631 * With the Cx5530, drive configuration 632 * should come *after* the controller configuration, 633 * to make sure the controller sees 634 * the command and does the right thing. 635 */ 636 /* Set UDMA mode on drive */ 637 if (bootverbose) 638 printf("cyrix_5530_dmainit: set UDMA mode %d\n", mode); 639 outl(iobase_bm+0x24 + (unit * 16), regval); 640 if (!wdcmd(drivemode, wdinfo)) { 641 printf("cyrix_5530_dmainit: setting DMA mode failed\n"); 642 return 0; 643 } 644 645 if (bootverbose) 646 cyrix_5530_status(cookie); 647 return 1; 648 649 } 650 651 /* otherwise, try and program it for MW DMA mode 2 */ 652 else if (mwdma_mode(wp) >= 0 && pio_mode(wp) >= 4) { 653 654 switch(mwdma_mode(wp)) { 655 case 0: 656 mode = 0; 657 drivemode = WDDMA_MDMA0; 658 regval = 0x00017771; 659 break; 660 case 1: 661 mode = 1; 662 drivemode = WDDMA_MDMA1; 663 regval = 0x00012121; 664 break; 665 default: /* newer modes not supported */ 666 case 2: 667 mode = 2; 668 drivemode = WDDMA_MDMA2; 669 regval = 0x00002020; 670 671 break; 672 } 673 /* Set multiword DMA mode 2 on drive */ 674 if (bootverbose) 675 printf("cyrix_5530_dmainit: multiword DMA mode %d\n", 676 mode); 677 if (!wdcmd(drivemode, wdinfo)) { 678 printf("cyrix_5530_dmainit: setting DMA mode failed\n"); 679 return 0; 680 } 681 682 /* Configure the controller appropriately for MWDMA mode */ 683 684 outl(iobase_bm + 0x24 + (unit * 16), regval); 685 686 if (bootverbose) 687 cyrix_5530_status(cookie); 688 689 return 1; 690 691 } 692 /* 693 * Always set the PIO mode values. 694 */ 695 switch(pio_mode(wp)) { 696 case 0: 697 mode = 0; 698 drivemode = WDDMA_MDMA0; 699 regval = 0x0000E132; 700 break; 701 case 1: 702 mode = 1; 703 drivemode = WDDMA_MDMA1; 704 regval = 0x00001812; 705 break; 706 case 2: 707 mode = 2; 708 drivemode = WDDMA_MDMA1; 709 regval = 0x00024020; 710 break; 711 case 3: 712 mode = 3; 713 drivemode = WDDMA_MDMA1; 714 regval = 0x00032010; 715 break; 716 default: /* newer modes not supported */ 717 case 4: 718 mode = 4; 719 drivemode = WDDMA_MDMA2; 720 regval = 0x00040010; 721 722 break; 723 } 724 outl(iobase_bm + 0x20 + (unit * 16), regval); 725 printf("cyrix_5530_dmainit: setting PIO mode %d\n", mode); 726 return 0; 727 } 728 729 730 static struct vendor_fns vs_cyrix_5530 = 731 { 732 cyrix_5530_dmainit, 733 cyrix_5530_status 734 }; 735 736 737 static void 738 promise_status(struct ide_pci_cookie *cookie) 739 { 740 pcici_t tag; 741 int i; 742 u_int32_t port0_command, port0_altstatus; 743 u_int32_t port1_command, port1_altstatus; 744 u_int32_t dma_block; 745 746 u_int32_t lat_and_interrupt; 747 u_int32_t drivetiming; 748 int pa, pb, mb, mc; 749 750 tag = cookie->tag; 751 port0_command = pci_conf_read(tag, 0x10); 752 port0_altstatus = pci_conf_read(tag, 0x14); 753 port1_command = pci_conf_read(tag, 0x18); 754 port1_altstatus = pci_conf_read(tag, 0x1c); 755 756 dma_block = pci_conf_read(tag, 0x20); 757 lat_and_interrupt = pci_conf_read(tag, 0x3c); 758 759 printf("promise_status: port0: 0x%lx, port0_alt: 0x%lx, port1: 0x%lx, port1_alt: 0x%lx\n", 760 (u_long)port0_command, (u_long)port0_altstatus, (u_long)port1_command, 761 (u_long)port1_altstatus); 762 printf( 763 "promise_status: dma control blk address: 0x%lx, int: %d, irq: %d\n", 764 (u_long)dma_block, (u_int)(lat_and_interrupt >> 8) & 0xff, 765 (u_int)lat_and_interrupt & 0xff); 766 767 for(i=0;i<4;i+=2) { 768 drivetiming = pci_conf_read(tag, 0x60 + i * 4); 769 printf("drivebits%d-%d: %b\n", i, i+1, drivetiming, 770 "\020\05Prefetch\06Iordy\07Errdy\010Sync\025DmaW\026DmaR"); 771 pa = drivetiming & 0xf; 772 pb = (drivetiming >> 8) & 0x1f; 773 mb = (drivetiming >> 13) & 0x7; 774 mc = (drivetiming >> 16) & 0xf; 775 printf("drivetiming%d: pa: 0x%x, pb: 0x%x, mb: 0x%x, mc: 0x%x\n", 776 i, pa, pb, mb, mc); 777 778 drivetiming = pci_conf_read(tag, 0x60 + (i + 1) * 4); 779 pa = drivetiming & 0xf; 780 pb = (drivetiming >> 8) & 0x1f; 781 mb = (drivetiming >> 13) & 0x7; 782 mc = (drivetiming >> 16) & 0xf; 783 printf("drivetiming%d: pa: 0x%x, pb: 0x%x, mb: 0x%x, mc: 0x%x\n", 784 i + 1, pa, pb, mb, mc); 785 } 786 } 787 788 static struct vendor_fns vs_promise = 789 { 790 generic_dmainit, 791 promise_status 792 }; 793 794 /* Intel PIIX, PIIX3, and PIIX4 IDE controller subfunctions */ 795 static void 796 intel_piix_dump_drive(char *ctlr, 797 int sitre, 798 int is_piix4, 799 int word40, 800 int word44, 801 int word48, 802 int word4a, 803 int drive) 804 { 805 char *ms; 806 807 if (!sitre) 808 ms = "master/slave"; 809 else if (drive == 0) 810 ms = "master"; 811 else 812 ms = "slave"; 813 814 printf("intel_piix_status: %s %s sample = %d, %s recovery = %d\n", 815 ctlr, 816 ms, 817 5 - ((sitre && drive) ? 818 ((word44 >> 2) & 3) : 819 ((word40 >> 12) & 3)), 820 ms, 821 4 - ((sitre && drive) ? 822 ((word44 >> 0) & 3) : 823 ((word40 >> 8) & 3))); 824 825 word40 >>= (drive * 4); 826 printf("intel_piix_status: %s %s fastDMAonly %s, pre/post %s,\n\ 827 intel_piix_status: IORDY sampling %s,\n\ 828 intel_piix_status: fast PIO %s%s\n", 829 ctlr, 830 (drive == 0) ? "master" : "slave", 831 (word40 & 8) ? "enabled" : "disabled", 832 (word40 & 4) ? "enabled" : "disabled", 833 (word40 & 2) ? "enabled" : "disabled", 834 (word40 & 1) ? "enabled" : "disabled", 835 ((word40 & 9) == 9) ? " (overridden by fastDMAonly)" : "" ); 836 837 if (is_piix4) 838 printf("intel_piix_status: UltraDMA %s, CT/RP = %d/%d\n", 839 word48 ? "enabled": "disabled", 840 4 - (word4a & 3), 841 6 - (word4a & 3)); 842 } 843 844 static void 845 intel_piix_status(struct ide_pci_cookie *cookie) 846 { 847 int iobase_wd; 848 int unit; 849 int iobase_bm; 850 pcici_t tag; 851 pcidi_t type; 852 int ctlr; 853 u_long word40, word44, word48; 854 int sitre, is_piix4; 855 856 iobase_wd = cookie->iobase_wd; 857 unit = cookie->unit; 858 iobase_bm = cookie->iobase_bm; 859 tag = cookie->tag; 860 type = cookie->type; 861 ctlr = cookie->ctlr; 862 863 word40 = pci_conf_read(tag, 0x40); 864 word44 = pci_conf_read(tag, 0x44); 865 word48 = pci_conf_read(tag, 0x48); 866 867 /* 868 * XXX will not be right for the *next* generation of upward-compatible 869 * intel IDE controllers... 870 */ 871 is_piix4 = pci_conf_read(tag, PCI_CLASS_REG) == 0x71118086; 872 873 sitre = word40 & 0x4000; 874 875 switch (ctlr * 2 + unit) { 876 case 0: 877 intel_piix_dump_drive("primary", 878 sitre, 879 is_piix4, 880 word40 & 0xffff, 881 word44 & 0x0f, 882 word48, 883 word48 >> 16, 884 0); 885 break; 886 case 1: 887 intel_piix_dump_drive("primary", 888 sitre, 889 is_piix4, 890 word40 & 0xffff, 891 word44 & 0x0f, 892 word48 >> 1, 893 word48 >> 20, 894 1); 895 break; 896 case 2: 897 intel_piix_dump_drive("secondary", 898 sitre, 899 is_piix4, 900 (word40 >> 16) & 0xffff, 901 (word44 >> 4) & 0x0f, 902 word48 >> 2, 903 word48 >> 24, 904 0); 905 break; 906 case 3: 907 intel_piix_dump_drive("secondary", 908 sitre, 909 is_piix4, 910 (word40 >> 16) & 0xffff, 911 (word44 >> 4) & 0x0f, 912 word48 >> 3, 913 word48 >> 28, 914 1); 915 break; 916 default: 917 printf("intel_piix_status: bad drive or controller number\n"); 918 } 919 } 920 921 /* 922 * XXX timing values set hereare only good for 30/33MHz buses; should deal 923 * with slower ones too (BTW: you overclock-- you lose) 924 */ 925 926 static int 927 intel_piix_dmainit(struct ide_pci_cookie *cookie, 928 struct wdparams *wp, 929 int(*wdcmd)(int, void *), 930 void *wdinfo) 931 { 932 933 /* If it's a UDMA drive and a PIIX4, set it up */ 934 if (cookie->type == 0x71118086 && udma_mode(wp) >= 2) { 935 /* Set UDMA mode 2 on controller */ 936 int unitno, mask, new; 937 938 if (bootverbose) 939 printf("intel_piix_dmainit: setting ultra DMA mode 2\n"); 940 941 if (!wdcmd(WDDMA_UDMA2, wdinfo)) { 942 printf("intel_piix_dmainit: setting DMA mode failed\n"); 943 return 0; 944 } 945 946 unitno = cookie->ctlr * 2 + cookie->unit; 947 948 mask = (1 << unitno) + (3 << (16 + unitno * 4)); 949 new = (1 << unitno) + (2 << (16 + unitno * 4)); 950 951 pci_conf_write(cookie->tag, 0x48, 952 (pci_conf_read(cookie->tag, 0x48) & ~mask) | new); 953 954 if (bootverbose) 955 intel_piix_status(cookie); 956 return 1; 957 } 958 /* 959 * if it's an 82371FB, which can't do independent programming of 960 * drive timing, we punt; we're not going to fuss with trying to 961 * coordinate timing modes between drives. if this is you, get a 962 * new motherboard. or contribute patches :) 963 * 964 * we do now at least see if the modes set are OK to use. this should 965 * satisfy the majority of people, with mwdma mode2 drives. 966 */ 967 else if (cookie->type == 0x12308086) 968 { 969 u_long word40; 970 971 /* can drive do PIO 4 and MW DMA 2? */ 972 if (!(mwdma_mode(wp) >= 2 && pio_mode(wp) >= 4)) 973 return 0; 974 975 word40 = pci_conf_read(cookie->tag, 0x40); 976 word40 >>= cookie->ctlr * 16; 977 978 /* Check for timing config usable for DMA on controller */ 979 if (!((word40 & 0x3300) == 0x2300 && 980 ((word40 >> (cookie->unit * 4)) & 1) == 1)) 981 return 0; 982 983 /* Set multiword DMA mode 2 on drive */ 984 if (bootverbose) 985 printf("intel_piix_dmainit: setting multiword DMA mode 2\n"); 986 if (!wdcmd(WDDMA_MDMA2, wdinfo)) { 987 printf("intel_piix_dmainit: setting DMA mode failed\n"); 988 return 0; 989 } 990 return 1; 991 } 992 993 /* otherwise, treat it as a PIIX3 and program it for MW DMA mode 2 */ 994 else if (mwdma_mode(wp) >= 2 && pio_mode(wp) >= 4) { 995 u_long mask40, mask44, new40, new44; 996 997 /* 998 * If SITRE is not set, set it and copy the 999 * appropriate bits into the secondary registers. Do 1000 * both controllers at once. 1001 */ 1002 if (((pci_conf_read(cookie->tag, 0x40) >> (16 * cookie->ctlr)) 1003 & 0x4000) == 0) { 1004 unsigned int word40, word44; 1005 1006 word40 = pci_conf_read(cookie->tag, 0x40); 1007 1008 /* copy bits to secondary register */ 1009 word44 = pci_conf_read(cookie->tag, 0x44); 1010 /* 1011 * I've got a Biostar motherboard with Award 1012 * BIOS that sets SITRE and secondary timing 1013 * on one controller but not the other. 1014 * Bizarre. 1015 */ 1016 if ((word40 & 0x4000) == 0) { 1017 word44 &= ~0xf; 1018 word44 |= ((word40 & 0x3000) >> 10) | 1019 ((word40 & 0x0300) >> 8); 1020 } 1021 if ((word40 & 0x40000000) == 0) { 1022 word44 &= ~0xf0; 1023 word44 |= ((word40 & 0x30000000) >> 22) | 1024 ((word40 & 0x03000000) >> 20); 1025 } 1026 /* set SITRE */ 1027 word40 |= 0x40004000; 1028 1029 pci_conf_write(cookie->tag, 0x40, word40); 1030 pci_conf_write(cookie->tag, 0x44, word44); 1031 } 1032 1033 /* Set multiword DMA mode 2 on drive */ 1034 if (bootverbose) 1035 printf("intel_piix_dmainit: setting multiword DMA mode 2\n"); 1036 1037 if (!wdcmd(WDDMA_MDMA2, wdinfo)) { 1038 printf("intel_piix_dmainit: setting DMA mode failed\n"); 1039 return 0; 1040 } 1041 1042 /* 1043 * backward compatible hardware leaves us with such 1044 * twisted masses of software (aka twiddle the 1045 * extremely weird register layout on a PIIX3, setting 1046 * PIO mode 4 and MWDMA mode 2) 1047 */ 1048 if (cookie->unit == 0) { 1049 mask40 = 0x330f; 1050 new40 = 0x2307; 1051 mask44 = 0; 1052 new44 = 0; 1053 } else { 1054 mask40 = 0x00f0; 1055 new40 = 0x0070; 1056 mask44 = 0x000f; 1057 new44 = 0x000b; 1058 } 1059 1060 if (cookie->ctlr) { 1061 mask40 <<= 16; 1062 new40 <<= 16; 1063 mask44 <<= 4; 1064 new44 <<= 4; 1065 } 1066 1067 pci_conf_write(cookie->tag, 0x40, 1068 (pci_conf_read(cookie->tag, 0x40) & ~mask40) | new40); 1069 pci_conf_write(cookie->tag, 0x44, 1070 (pci_conf_read(cookie->tag, 0x44) & ~mask44) | new44); 1071 1072 if (bootverbose) 1073 intel_piix_status(cookie); 1074 return 1; 1075 } 1076 return 0; 1077 } 1078 1079 static struct vendor_fns vs_intel_piix = 1080 { 1081 intel_piix_dmainit, 1082 intel_piix_status 1083 }; 1084 1085 1086 static void 1087 acer_status(struct ide_pci_cookie *cookie) { 1088 /* XXX does not do anything right now */ 1089 } 1090 1091 static int 1092 acer_dmainit(struct ide_pci_cookie *cookie, 1093 struct wdparams *wp, 1094 int(*wdcmd)(int, void *), 1095 void *wdinfo) 1096 { 1097 /* Acer Aladdin DMA setup code. UDMA looks to be sinfully easy to set 1098 on this thing - just one register. */ 1099 1100 u_long word54 = pci_conf_read(cookie->tag, 0x54); 1101 1102 /* Set the default Acer FIFO settings (0x55 = 13-word depth and 1103 slave operation mode 1) */ 1104 1105 word54 |= 0x5555; 1106 1107 /* Is this drive UDMA? Set it up if so... */ 1108 if(udma_mode(wp) >= 2) { 1109 /* This is really easy to do. Just write 0xa (enable 1110 UDMA mode with 2T timing) into the word at the right 1111 places. */ 1112 word54 |= (0xA << (16 + (cookie->ctlr * 8) + (cookie->unit * 4))); 1113 1114 /* Now set the drive for UDMA2. */ 1115 if(!wdcmd(WDDMA_UDMA2, wdinfo)) { 1116 printf("acer_dmainit: could not set UDMA2 mode on wdc%d:%d!\n", cookie->ctlr, cookie->unit); 1117 return 0; 1118 } 1119 1120 /* Write the new config into the registers. I'm not 1121 sure if I'm doing this in the right order. */ 1122 1123 pci_conf_write(cookie->tag, 0x54, word54); 1124 1125 } else if(mwdma_mode(wp) >= 2 && pio_mode(wp) >=4) { 1126 1127 1128 /* Otherwise, we're already set for regular DMA. */ 1129 1130 if(!wdcmd(WDDMA_MDMA2, wdinfo)) { 1131 printf("acer_dmainit: could not set MWDMA2 mode on wdc%d:%d!\n", 1132 cookie->ctlr, cookie->unit); 1133 return 0; 1134 } 1135 return 1; 1136 } 1137 1138 return 0; 1139 } 1140 1141 static struct vendor_fns vs_acer = 1142 { 1143 acer_dmainit, 1144 acer_status 1145 }; 1146 1147 1148 1149 /* Generic SFF-8038i code-- all code below here, except for PCI probes, 1150 * more or less conforms to the SFF-8038i spec as extended for PCI. 1151 * There should be no code that goes beyond that feature set below. 1152 */ 1153 1154 /* XXX mkcookie is overloaded with too many parameters */ 1155 1156 static struct ide_pci_cookie * 1157 mkcookie(int iobase_wd, 1158 int ctlr, 1159 int unit, 1160 int iobase_bm, 1161 pcici_t tag, 1162 pcidi_t type, 1163 struct vendor_fns *vp, 1164 int altiobase_wd) 1165 { 1166 struct ide_pci_cookie *cp; 1167 1168 cp = malloc(sizeof *cp, M_DEVBUF, M_NOWAIT); 1169 if (!cp) return 0; 1170 1171 cp->iobase_wd = iobase_wd; 1172 cp->ctlr = ctlr; 1173 cp->unit = unit; 1174 cp->tag = tag; 1175 cp->type = type; 1176 cp->iobase_bm = iobase_bm; 1177 cp->altiobase_wd = altiobase_wd; 1178 bcopy(vp, &cp->vs, sizeof(struct vendor_fns)); 1179 1180 if (!prdbuf) { 1181 prdbuf = malloc(PRD_ALLOC_SIZE, M_DEVBUF, M_NOWAIT); 1182 if (!prdbuf) { 1183 FREE(cp, M_DEVBUF); 1184 return 0; 1185 } 1186 if (((int)prdbuf >> PAGE_SHIFT) ^ 1187 (((int)prdbuf + PRD_ALLOC_SIZE - 1) >> PAGE_SHIFT)) { 1188 printf("ide_pci: prdbuf straddles page boundary, no DMA\n"); 1189 FREE(cp, M_DEVBUF); 1190 FREE(prdbuf, M_DEVBUF); 1191 return 0; 1192 } 1193 1194 prdbuf_next = prdbuf; 1195 } 1196 if (((char *)prdbuf_next + PRD_BUF_SIZE) > 1197 ((char *)prdbuf + PRD_ALLOC_SIZE)) { 1198 printf("ide_pci: mkcookie %04x:%d: no more space for PRDs, no DMA\n", 1199 iobase_wd, unit); 1200 FREE(cp, M_DEVBUF); 1201 return 0; 1202 } 1203 1204 cp->prd = prdbuf_next; 1205 (char *)prdbuf_next += PRD_BUF_SIZE; 1206 1207 LIST_INSERT_HEAD(&softc.cookies, cp, le); 1208 return cp; 1209 } 1210 1211 static const char * 1212 ide_pci_probe(pcici_t tag, pcidi_t type) 1213 { 1214 u_long data; 1215 1216 data = pci_conf_read(tag, PCI_CLASS_REG); 1217 1218 if ((data & PCI_CLASS_MASK) == PCI_CLASS_MASS_STORAGE && 1219 ((data & PCI_SUBCLASS_MASK) == 0x00010000 || 1220 ((data & PCI_SUBCLASS_MASK) == 0x00040000))) { 1221 if (type == 0x71118086) 1222 return ("Intel PIIX4 Bus-master IDE controller"); 1223 if (type == 0x70108086) 1224 return ("Intel PIIX3 Bus-master IDE controller"); 1225 if (type == 0x12308086) 1226 return ("Intel PIIX Bus-master IDE controller"); 1227 if (type == PROMISE_ULTRA33) 1228 return ("Promise Ultra/33 IDE controller"); 1229 if (type == 0x05711106) 1230 return ("VIA 82C586x (Apollo) Bus-master IDE controller"); 1231 if (type == 0x01021078) 1232 return ("Cyrix 5530 Bus-master IDE controller"); 1233 if (type == 0x522910b9) 1234 return ("Acer Aladdin IV/V (M5229) Bus-master IDE controller"); 1235 if (data & 0x8000) 1236 return ("PCI IDE controller (busmaster capable)"); 1237 #ifndef CMD640 1238 /* 1239 * XXX the CMD640B hack should be better integrated, or 1240 * something. 1241 */ 1242 else 1243 return ("PCI IDE controller (not busmaster capable)"); 1244 #endif 1245 }; 1246 return ((char*)0); 1247 } 1248 1249 static void 1250 ide_pci_attach(pcici_t tag, int unit) 1251 { 1252 u_long class = 0, cmd; 1253 int bmista_1, bmista_2; 1254 int iobase_wd_1, iobase_wd_2, iobase_bm_1, iobase_bm_2; 1255 int altiobase_wd_1, altiobase_wd_2; 1256 struct vendor_fns *vp; 1257 pcidi_t type; 1258 struct ide_pci_cookie *cookie; 1259 int ctlridx; 1260 1261 ctlridx = unit * 2; 1262 1263 /* set up vendor-specific stuff */ 1264 type = pci_conf_read(tag, PCI_ID_REG); 1265 1266 if (type != PROMISE_ULTRA33) { 1267 /* is it busmaster capable? bail if not */ 1268 class = pci_conf_read(tag, PCI_CLASS_REG); 1269 if (!(class & 0x8000)) { 1270 return; 1271 } 1272 1273 /* is it enabled and is busmastering turned on? */ 1274 cmd = pci_conf_read(tag, PCI_COMMAND_STATUS_REG); 1275 if ((cmd & 5) != 5) { 1276 return; 1277 } 1278 } 1279 1280 switch (type) { 1281 case 0x71118086: 1282 case 0x70108086: 1283 case 0x12308086: 1284 /* Intel PIIX, PIIX3, PIIX4 */ 1285 vp = &vs_intel_piix; 1286 break; 1287 1288 case 0x5711106: 1289 /* VIA Apollo chipset family */ 1290 vp = &vs_via_571; 1291 break; 1292 1293 case PROMISE_ULTRA33: 1294 /* Promise controllers */ 1295 vp = &vs_promise; 1296 break; 1297 1298 case 0x01021078: /* cyrix 5530 */ 1299 printf("cyrix 5530\n"); 1300 vp = &vs_cyrix_5530; 1301 break; 1302 case 0x522910B9: /* Acer Aladdin IV/V (M5229) */ 1303 vp = &vs_acer; 1304 break; 1305 default: 1306 /* everybody else */ 1307 vp = &vs_generic; 1308 break; 1309 } 1310 1311 if (type != PROMISE_ULTRA33) { 1312 if ((class & 0x100) == 0) { 1313 iobase_wd_1 = IO_WD1; 1314 altiobase_wd_1 = iobase_wd_1 + wd_altsts; 1315 } else { 1316 iobase_wd_1 = pci_conf_read(tag, 0x10) & 0xfffc; 1317 altiobase_wd_1 = pci_conf_read(tag, 0x14) & 0xfffc; 1318 } 1319 1320 if ((class & 0x400) == 0) { 1321 iobase_wd_2 = IO_WD2; 1322 altiobase_wd_2 = iobase_wd_2 + wd_altsts; 1323 } else { 1324 iobase_wd_2 = pci_conf_read(tag, 0x18) & 0xfffc; 1325 altiobase_wd_2 = pci_conf_read(tag, 0x1c) & 0xfffc; 1326 } 1327 } else { 1328 iobase_wd_1 = pci_conf_read(tag, 0x10) & 0xfffc; 1329 altiobase_wd_1 = pci_conf_read(tag, 0x14) & 0xfffc; 1330 iobase_wd_2 = pci_conf_read(tag, 0x18) & 0xfffc; 1331 altiobase_wd_2 = pci_conf_read(tag, 0x1c) & 0xfffc; 1332 } 1333 1334 iobase_bm_1 = pci_conf_read(tag, 0x20) & 0xfffc; 1335 if (iobase_bm_1 == 0) { 1336 printf("ide_pci: BIOS has not configured busmaster" 1337 "I/O address,\n ide_pci: giving up\n"); 1338 return; 1339 } 1340 iobase_bm_2 = iobase_bm_1 + SFF8038_CTLR_1; 1341 1342 wddma[unit].wdd_candma = ide_pci_candma; 1343 wddma[unit].wdd_dmainit = ide_pci_dmainit; 1344 if (type == 0x01021078 /*CYRIX_5530*/) 1345 wddma[unit].wdd_dmaverify = cyrix_5530_dmaverify; 1346 else 1347 wddma[unit].wdd_dmaverify = ide_pci_dmaverify; 1348 wddma[unit].wdd_dmaprep = ide_pci_dmasetup; 1349 wddma[unit].wdd_dmastart = ide_pci_dmastart; 1350 wddma[unit].wdd_dmadone = ide_pci_dmadone; 1351 wddma[unit].wdd_dmastatus = ide_pci_status; 1352 wddma[unit].wdd_iobase = ide_pci_iobase; 1353 wddma[unit].wdd_altiobase = ide_pci_altiobase; 1354 1355 /* 1356 * This code below is mighty bogus. The config entries for the 1357 * isa_devtab_bio are plugged in before the standard ISA bios scan. 1358 * This is our "hack" way to simulate a dynamic assignment of I/O 1359 * addresses, from a PCI device to an ISA probe. Sorry :-). 1360 */ 1361 if (iobase_wd_1 != IO_WD1) { 1362 struct isa_device *dvp, *dvp1, *dvup; 1363 for( dvp = isa_devtab_bio; 1364 dvp->id_id != 0; 1365 dvp++) { 1366 if ((dvp->id_driver == &wdcdriver) && (dvp->id_iobase == 0)) { 1367 int biotabunit; 1368 biotabunit = dvp->id_unit * 2; 1369 dvp->id_iobase = iobase_wd_1; 1370 dvp1 = dvp + 1; 1371 dvp1->id_iobase = iobase_wd_2; 1372 printf("ide_pci%d: adding drives to controller %d:", 1373 unit, biotabunit); 1374 for(dvup = isa_biotab_wdc; 1375 dvup->id_id != 0; 1376 dvup++) { 1377 if (dvup->id_driver != &wdcdriver) 1378 continue; 1379 if (dvup->id_unit != biotabunit) 1380 continue; 1381 1382 dvup->id_iobase = dvp->id_iobase; 1383 printf(" %d", dvup->id_unit); 1384 dvup++; 1385 1386 pci_map_int(tag, wdintr, (void *) dvp->id_unit, &bio_imask); 1387 if (dvup->id_id == 0) 1388 break; 1389 1390 if (dvup->id_unit == biotabunit + 1) { 1391 dvup->id_iobase = dvp->id_iobase; 1392 printf(" %d", dvup->id_unit); 1393 dvup++; 1394 if (dvup->id_id == 0) { 1395 iobase_wd_2 = 0; 1396 break; 1397 } 1398 } 1399 1400 if (dvup->id_unit == biotabunit + 2) { 1401 pci_map_int(tag, wdintr, (void *) ((int) dvp->id_unit + 1), &bio_imask); 1402 dvup->id_iobase = dvp1->id_iobase; 1403 printf(" %d", dvup->id_unit); 1404 dvup++; 1405 if (dvup->id_id == 0) { 1406 break; 1407 } 1408 } 1409 1410 if (dvup->id_unit == biotabunit + 3) { 1411 pci_map_int(tag, wdintr, (void *) ((int) dvp->id_unit + 1), &bio_imask); 1412 dvup->id_iobase = dvp1->id_iobase; 1413 printf(" %d", dvup->id_unit); 1414 } 1415 1416 break; 1417 } 1418 printf("\n"); 1419 break; 1420 } 1421 } 1422 } 1423 1424 1425 bmista_1 = inb(iobase_bm_1 + BMISTA_PORT); 1426 bmista_2 = inb(iobase_bm_2 + BMISTA_PORT); 1427 1428 if (!ide_pci_softc_cookies_initted) { 1429 LIST_INIT(&softc.cookies); 1430 ide_pci_softc_cookies_initted = 1; 1431 } 1432 1433 if (iobase_wd_1 != 0) { 1434 cookie = mkcookie(iobase_wd_1, 1435 ctlridx, 1436 0, 1437 iobase_bm_1, 1438 tag, 1439 type, 1440 vp, 1441 altiobase_wd_1); 1442 if (bootverbose) 1443 vp->vendor_status(cookie); 1444 cookie = mkcookie(iobase_wd_1, 1445 ctlridx, 1446 1, 1447 iobase_bm_1, 1448 tag, 1449 type, 1450 vp, 1451 altiobase_wd_1); 1452 if (bootverbose) { 1453 vp->vendor_status(cookie); 1454 1455 bmista_1 = inb(iobase_bm_1 + BMISTA_PORT); 1456 bmista_2 = inb(iobase_bm_2 + BMISTA_PORT); 1457 printf("ide_pci: busmaster 0 status: %02x from port: %08x\n", 1458 bmista_1, iobase_bm_1+BMISTA_PORT); 1459 1460 if (bmista_1 & BMISTA_DMA0CAP) 1461 printf("ide_pci: ide0:0 has been configured for DMA by BIOS\n"); 1462 if (bmista_1 & BMISTA_DMA1CAP) 1463 printf("ide_pci: ide0:1 has been configured for DMA by BIOS\n"); 1464 } 1465 } 1466 1467 if (iobase_wd_2 != 0) { 1468 cookie = mkcookie(iobase_wd_2, 1469 ctlridx + 1, 1470 0, 1471 iobase_bm_2, 1472 tag, 1473 type, 1474 vp, 1475 altiobase_wd_2); 1476 if (bootverbose) 1477 vp->vendor_status(cookie); 1478 cookie = mkcookie(iobase_wd_2, 1479 ctlridx + 1, 1480 1, 1481 iobase_bm_2, 1482 tag, 1483 type, 1484 vp, 1485 altiobase_wd_2); 1486 if (bootverbose) { 1487 vp->vendor_status(cookie); 1488 1489 bmista_1 = inb(iobase_bm_1 + BMISTA_PORT); 1490 bmista_2 = inb(iobase_bm_2 + BMISTA_PORT); 1491 printf("ide_pci: busmaster 1 status: %02x from port: %08x\n", 1492 bmista_2, iobase_bm_2+BMISTA_PORT); 1493 1494 if (bmista_2 & BMISTA_DMA0CAP) 1495 printf("ide_pci: ide1:0 has been configured for DMA by BIOS\n"); 1496 if (bmista_2 & BMISTA_DMA1CAP) 1497 printf("ide_pci: ide1:1 has been configured for DMA by BIOS\n"); 1498 } 1499 } 1500 } 1501 1502 static u_long ide_pci_count; 1503 1504 static struct pci_device ide_pci_device = { 1505 "ide_pci", 1506 ide_pci_probe, 1507 ide_pci_attach, 1508 &ide_pci_count, 1509 0 1510 }; 1511 1512 DATA_SET(pcidevice_set, ide_pci_device); 1513 1514 /* 1515 * Return a cookie if we may be able to do DMA on the specified 1516 * (iobase_wd, ctlr, unit). 1517 */ 1518 static void * 1519 ide_pci_candma(int iobase_wd, int ctlr, int unit) 1520 { 1521 struct ide_pci_cookie *cp; 1522 1523 cp = softc.cookies.lh_first; 1524 while(cp) { 1525 if (cp->ctlr == ctlr && cp->unit == unit && 1526 ((iobase_wd == 0) || (cp->iobase_wd == iobase_wd))) 1527 break; 1528 cp = cp->le.le_next; 1529 } 1530 1531 return cp; 1532 } 1533 1534 /* 1535 * Initialize controller and drive for DMA operation, including timing modes. 1536 * Uses data passed from the wd driver and a callback function to initialize 1537 * timing modes on the drive. 1538 */ 1539 static int 1540 ide_pci_dmainit(void *cookie, 1541 struct wdparams *wp, 1542 int(*wdcmd)(int, void *), 1543 void *wdinfo) 1544 { 1545 struct ide_pci_cookie *cp = cookie; 1546 /* 1547 * If the controller status indicates that DMA is configured already, 1548 * we flounce happily away 1549 */ 1550 if (inb(cp->iobase_bm + BMISTA_PORT) & 1551 ((cp->unit == 0) ? BMISTA_DMA0CAP : BMISTA_DMA1CAP)) 1552 return 1; 1553 1554 /* We take a stab at it with device-dependent code */ 1555 return(cp->vs.vendor_dmainit(cp, wp, wdcmd, wdinfo)); 1556 } 1557 1558 /* 1559 * Verify that controller can handle a dma request for cp. Should 1560 * not affect any hardware or driver state. 1561 */ 1562 static int 1563 ide_pci_dmaverify(void *xcp, char *vaddr, u_long count, int dir) 1564 { 1565 int badfu; 1566 1567 /* 1568 * check for nonaligned or odd-length Stuff 1569 */ 1570 badfu = ((unsigned int)vaddr & 1) || (count & 1); 1571 #ifdef DIAGNOSTIC 1572 if (badfu) { 1573 printf("ide_pci: dmaverify odd vaddr or length, "); 1574 printf("vaddr = %p length = %08lx\n", (void *)vaddr, count); 1575 } 1576 #endif 1577 return (!badfu); 1578 } 1579 1580 /* 1581 * Set up DMA for cp. It is the responsibility of the caller 1582 * to ensure that the controller is idle before this routine 1583 * is called. 1584 */ 1585 static int 1586 ide_pci_dmasetup(void *xcp, char *vaddr, u_long vcount, int dir) 1587 { 1588 struct ide_pci_cookie *cp = xcp; 1589 struct ide_pci_prd *prd; 1590 int i; 1591 u_long firstpage; 1592 u_long prd_base, prd_count; 1593 u_long nbase, ncount, nend; 1594 int iobase_bm; 1595 u_long count; 1596 #ifdef DIAGNOSTIC 1597 u_long checkcount; 1598 #endif 1599 1600 prd = cp->prd; 1601 1602 count = vcount; 1603 1604 i = 0; 1605 1606 iobase_bm = cp->iobase_bm; 1607 1608 if (count == 0) { 1609 printf("ide_pci: dmasetup 0-length transfer, "); 1610 printf("vaddr = %p length = %08lx\n", (void *)vaddr, count); 1611 return 1; 1612 } 1613 1614 /* Generate first PRD entry, which may be non-aligned. */ 1615 1616 firstpage = PAGE_SIZE - ((uintptr_t)vaddr & PAGE_MASK); 1617 1618 prd_base = vtophys(vaddr); 1619 prd_count = MIN(count, firstpage); 1620 1621 vaddr += prd_count; 1622 count -= prd_count; 1623 1624 /* 1625 * Step through virtual pages. 1626 * Note that it is not worth trying to coalesce pages that are 1627 * next to each other physically, and some DMA engines (e.g. 1628 * Cyrix Cx5530) actually blow up if you do. 1629 */ 1630 while (count) { 1631 nbase = vtophys(vaddr); 1632 ncount = MIN(count, PAGE_SIZE); 1633 nend = nbase + ncount; 1634 1635 prd[i].prd_base = prd_base; 1636 prd[i].prd_count = (prd_count & 0xffff); 1637 i++; 1638 if (i >= PRD_MAX_SEGS) { 1639 printf("wd82371: too many segments in PRD table\n"); 1640 return 1; 1641 } 1642 prd_base = nbase; 1643 prd_count = ncount; 1644 vaddr += ncount; 1645 count -= ncount; 1646 } 1647 1648 /* Write last PRD entry. */ 1649 prd[i].prd_base = prd_base; 1650 prd[i].prd_count = (prd_count & 0xffff) | PRD_EOT_BIT; 1651 1652 #ifdef DIAGNOSTIC 1653 /* sanity check the transfer for length and page-alignment, at least */ 1654 checkcount = 0; 1655 for (i = 0;; i++) { 1656 unsigned int modcount; 1657 1658 modcount = prd[i].prd_count & 0xffffe; 1659 if (modcount == 0) modcount = 0x10000; 1660 checkcount += modcount; 1661 if (i != 0 && ((prd[i].prd_base & PAGE_MASK) != 0)) { 1662 printf("ide_pci: dmasetup() diagnostic fails-- unaligned page\n"); 1663 return 1; 1664 } 1665 if (prd[i].prd_count & PRD_EOT_BIT) 1666 break; 1667 } 1668 1669 if (checkcount != vcount) { 1670 printf("ide_pci: dmasetup() diagnostic fails-- bad length\n"); 1671 return 1; 1672 } 1673 #endif 1674 1675 /* Set up PRD base register */ 1676 outl(iobase_bm + BMIDTP_PORT, vtophys(prd)); 1677 1678 /* Set direction of transfer */ 1679 outb(iobase_bm + BMICOM_PORT, (dir == B_READ) ? BMICOM_READ_WRITE : 0); 1680 1681 /* Clear interrupt and error bits */ 1682 outb(iobase_bm + BMISTA_PORT, 1683 (inb(iobase_bm + BMISTA_PORT) 1684 | (BMISTA_INTERRUPT | BMISTA_DMA_ERROR))); 1685 1686 return 0; 1687 } 1688 1689 static void 1690 ide_pci_dmastart(void *xcp) 1691 { 1692 struct ide_pci_cookie *cp = xcp; 1693 int iobase_bm; 1694 1695 iobase_bm = cp->iobase_bm; 1696 1697 outb(iobase_bm + BMICOM_PORT, 1698 inb(iobase_bm + BMICOM_PORT) | BMICOM_STOP_START); 1699 1700 } 1701 1702 static int 1703 ide_pci_dmadone(void *xcp) 1704 { 1705 struct ide_pci_cookie *cp = xcp; 1706 int iobase_bm, status; 1707 1708 status = ide_pci_status(xcp); 1709 iobase_bm = cp->iobase_bm; 1710 1711 outb(iobase_bm + BMICOM_PORT, 1712 inb(iobase_bm + BMICOM_PORT) & ~BMICOM_STOP_START); 1713 1714 return status; 1715 } 1716 1717 static int 1718 ide_pci_status(void *xcp) 1719 { 1720 int iobase_bm, status, bmista; 1721 1722 status = 0; 1723 iobase_bm = ((struct ide_pci_cookie *)xcp)->iobase_bm; 1724 1725 bmista = inb(iobase_bm + BMISTA_PORT); 1726 1727 if (bmista & BMISTA_INTERRUPT) 1728 status |= WDDS_INTERRUPT; 1729 if (bmista & BMISTA_DMA_ERROR) 1730 status |= WDDS_ERROR; 1731 if (bmista & BMISTA_DMA_ACTIVE) 1732 status |= WDDS_ACTIVE; 1733 return status; 1734 } 1735 1736 static int 1737 ide_pci_altiobase(void *xcp) 1738 { 1739 struct ide_pci_cookie *cp = xcp; 1740 if (cp == 0) { 1741 return 0; 1742 } else { 1743 return cp->altiobase_wd; 1744 } 1745 } 1746 1747 static int 1748 ide_pci_iobase(void *xcp) 1749 { 1750 struct ide_pci_cookie *cp = xcp; 1751 if (cp == 0) { 1752 return 0; 1753 } else { 1754 return cp->iobase_wd; 1755 } 1756 } 1757 1758 #endif 1759 #endif /* NPCI > 0 */
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