Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_al.c
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * ADMtek AL981 Comet fast ethernet PCI NIC driver. Datasheets for 37 * the AL981 are available from http://www.admtek.com.tw. 38 * 39 * Written by Bill Paul <wpaul@ctr.columbia.edu> 40 * Electrical Engineering Department 41 * Columbia University, New York City 42 */ 43 44 /* 45 * The ADMtek AL981 Comet is still another DEC 21x4x clone. It's 46 * a reasonably close copy of the tulip, except for the receiver filter 47 * programming. Where the DEC chip has a special setup frame that 48 * needs to be downloaded into the transmit DMA engine, the ADMtek chip 49 * has physical address and multicast address registers. 50 */ 51 52 #include "bpfilter.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/sockio.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/ethernet.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <vm/vm.h> /* for vtophys */ 73 #include <vm/pmap.h> /* for vtophys */ 74 #include <machine/clock.h> /* for DELAY */ 75 #include <machine/bus_pio.h> 76 #include <machine/bus_memio.h> 77 #include <machine/bus.h> 78 79 #include <pci/pcireg.h> 80 #include <pci/pcivar.h> 81 82 /* Enable workaround for small transmitter bug. */ 83 #define AL_TX_STALL_WAR 84 85 #define AL_USEIOSPACE 86 87 /* #define AL_BACKGROUND_AUTONEG */ 88 89 #include <pci/if_alreg.h> 90 91 #ifndef lint 92 static const char rcsid[] = 93 "$FreeBSD$"; 94 #endif 95 96 /* 97 * Various supported device vendors/types and their names. 98 */ 99 static struct al_type al_devs[] = { 100 { AL_VENDORID, AL_DEVICEID_AL981, 101 "ADMtek AL981 10/100BaseTX" }, 102 { AL_VENDORID, AL_DEVICEID_AN985, 103 "ADMtek AN985 10/100BaseTX" }, 104 { 0, 0, NULL } 105 }; 106 107 /* 108 * Various supported PHY vendors/types and their names. Note that 109 * this driver will work with pretty much any MII-compliant PHY, 110 * so failure to positively identify the chip is not a fatal error. 111 */ 112 113 static struct al_type al_phys[] = { 114 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" }, 115 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" }, 116 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"}, 117 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 118 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" }, 119 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" }, 120 { 0, 0, "<MII-compliant physical interface>" } 121 }; 122 123 static unsigned long al_count = 0; 124 static const char *al_probe __P((pcici_t, pcidi_t)); 125 static void al_attach __P((pcici_t, int)); 126 127 static int al_newbuf __P((struct al_softc *, 128 struct al_chain_onefrag *)); 129 static int al_encap __P((struct al_softc *, struct al_chain *, 130 struct mbuf *)); 131 132 static void al_rxeof __P((struct al_softc *)); 133 static void al_rxeoc __P((struct al_softc *)); 134 static void al_txeof __P((struct al_softc *)); 135 static void al_txeoc __P((struct al_softc *)); 136 static void al_intr __P((void *)); 137 static void al_start __P((struct ifnet *)); 138 static int al_ioctl __P((struct ifnet *, u_long, caddr_t)); 139 static void al_init __P((void *)); 140 static void al_stop __P((struct al_softc *)); 141 static void al_watchdog __P((struct ifnet *)); 142 static void al_shutdown __P((int, void *)); 143 static int al_ifmedia_upd __P((struct ifnet *)); 144 static void al_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 145 146 static void al_delay __P((struct al_softc *)); 147 static void al_eeprom_idle __P((struct al_softc *)); 148 static void al_eeprom_putbyte __P((struct al_softc *, int)); 149 static void al_eeprom_getword __P((struct al_softc *, int, u_int16_t *)); 150 static void al_read_eeprom __P((struct al_softc *, caddr_t, int, 151 int, int)); 152 153 static void al_mii_writebit __P((struct al_softc *, int)); 154 static int al_mii_readbit __P((struct al_softc *)); 155 static void al_mii_sync __P((struct al_softc *)); 156 static void al_mii_send __P((struct al_softc *, u_int32_t, int)); 157 static int al_mii_readreg __P((struct al_softc *, struct al_mii_frame *)); 158 static int al_mii_writereg __P((struct al_softc *, struct al_mii_frame *)); 159 160 static u_int16_t al_phy_readreg __P((struct al_softc *, int)); 161 static void al_phy_writereg __P((struct al_softc *, int, int)); 162 163 static void al_autoneg_xmit __P((struct al_softc *)); 164 static void al_autoneg_mii __P((struct al_softc *, int, int)); 165 static void al_setmode_mii __P((struct al_softc *, int)); 166 static void al_getmode_mii __P((struct al_softc *)); 167 static u_int32_t al_calchash __P((caddr_t)); 168 static void al_setmulti __P((struct al_softc *)); 169 static void al_reset __P((struct al_softc *)); 170 static int al_list_rx_init __P((struct al_softc *)); 171 static int al_list_tx_init __P((struct al_softc *)); 172 173 #define AL_SETBIT(sc, reg, x) \ 174 CSR_WRITE_4(sc, reg, \ 175 CSR_READ_4(sc, reg) | x) 176 177 #define AL_CLRBIT(sc, reg, x) \ 178 CSR_WRITE_4(sc, reg, \ 179 CSR_READ_4(sc, reg) & ~x) 180 181 #define SIO_SET(x) \ 182 CSR_WRITE_4(sc, AL_SIO, \ 183 CSR_READ_4(sc, AL_SIO) | x) 184 185 #define SIO_CLR(x) \ 186 CSR_WRITE_4(sc, AL_SIO, \ 187 CSR_READ_4(sc, AL_SIO) & ~x) 188 189 static void al_delay(sc) 190 struct al_softc *sc; 191 { 192 int idx; 193 194 for (idx = (300 / 33) + 1; idx > 0; idx--) 195 CSR_READ_4(sc, AL_BUSCTL); 196 } 197 198 static void al_eeprom_idle(sc) 199 struct al_softc *sc; 200 { 201 register int i; 202 203 CSR_WRITE_4(sc, AL_SIO, AL_SIO_EESEL); 204 al_delay(sc); 205 AL_SETBIT(sc, AL_SIO, AL_SIO_ROMCTL_READ); 206 al_delay(sc); 207 AL_SETBIT(sc, AL_SIO, AL_SIO_EE_CS); 208 al_delay(sc); 209 AL_SETBIT(sc, AL_SIO, AL_SIO_EE_CLK); 210 al_delay(sc); 211 212 for (i = 0; i < 25; i++) { 213 AL_CLRBIT(sc, AL_SIO, AL_SIO_EE_CLK); 214 al_delay(sc); 215 AL_SETBIT(sc, AL_SIO, AL_SIO_EE_CLK); 216 al_delay(sc); 217 } 218 219 AL_CLRBIT(sc, AL_SIO, AL_SIO_EE_CLK); 220 al_delay(sc); 221 AL_CLRBIT(sc, AL_SIO, AL_SIO_EE_CS); 222 al_delay(sc); 223 CSR_WRITE_4(sc, AL_SIO, 0x00000000); 224 225 return; 226 } 227 228 /* 229 * Send a read command and address to the EEPROM, check for ACK. 230 */ 231 static void al_eeprom_putbyte(sc, addr) 232 struct al_softc *sc; 233 int addr; 234 { 235 register int d, i; 236 237 if (sc->al_info->al_did == AL_DEVICEID_AN985) 238 d = addr | (AL_EECMD_READ << 2); 239 else 240 d = addr | AL_EECMD_READ; 241 242 /* 243 * Feed in each bit and stobe the clock. 244 */ 245 for (i = 0x400; i; i >>= 1) { 246 if (d & i) { 247 SIO_SET(AL_SIO_EE_DATAIN); 248 } else { 249 SIO_CLR(AL_SIO_EE_DATAIN); 250 } 251 al_delay(sc); 252 SIO_SET(AL_SIO_EE_CLK); 253 al_delay(sc); 254 SIO_CLR(AL_SIO_EE_CLK); 255 al_delay(sc); 256 } 257 258 return; 259 } 260 261 /* 262 * Read a word of data stored in the EEPROM at address 'addr.' 263 */ 264 static void al_eeprom_getword(sc, addr, dest) 265 struct al_softc *sc; 266 int addr; 267 u_int16_t *dest; 268 { 269 register int i; 270 u_int16_t word = 0; 271 272 /* Force EEPROM to idle state. */ 273 al_eeprom_idle(sc); 274 275 /* Enter EEPROM access mode. */ 276 CSR_WRITE_4(sc, AL_SIO, AL_SIO_EESEL); 277 al_delay(sc); 278 AL_SETBIT(sc, AL_SIO, AL_SIO_ROMCTL_READ); 279 al_delay(sc); 280 AL_SETBIT(sc, AL_SIO, AL_SIO_EE_CS); 281 al_delay(sc); 282 AL_SETBIT(sc, AL_SIO, AL_SIO_EE_CLK); 283 al_delay(sc); 284 285 /* 286 * Send address of word we want to read. 287 */ 288 al_eeprom_putbyte(sc, addr); 289 290 /* 291 * Start reading bits from EEPROM. 292 */ 293 for (i = 0x8000; i; i >>= 1) { 294 SIO_SET(AL_SIO_EE_CLK); 295 al_delay(sc); 296 if (CSR_READ_4(sc, AL_SIO) & AL_SIO_EE_DATAOUT) 297 word |= i; 298 al_delay(sc); 299 SIO_CLR(AL_SIO_EE_CLK); 300 al_delay(sc); 301 } 302 303 /* Turn off EEPROM access mode. */ 304 al_eeprom_idle(sc); 305 306 *dest = word; 307 308 return; 309 } 310 311 /* 312 * Read a sequence of words from the EEPROM. 313 */ 314 static void al_read_eeprom(sc, dest, off, cnt, swap) 315 struct al_softc *sc; 316 caddr_t dest; 317 int off; 318 int cnt; 319 int swap; 320 { 321 int i; 322 u_int16_t word = 0, *ptr; 323 324 for (i = 0; i < cnt; i++) { 325 al_eeprom_getword(sc, off + i, &word); 326 ptr = (u_int16_t *)(dest + (i * 2)); 327 if (swap) 328 *ptr = ntohs(word); 329 else 330 *ptr = word; 331 } 332 333 return; 334 } 335 336 /* 337 * Write a bit to the MII bus. 338 */ 339 static void al_mii_writebit(sc, bit) 340 struct al_softc *sc; 341 int bit; 342 { 343 if (bit) 344 CSR_WRITE_4(sc, AL_SIO, AL_SIO_ROMCTL_WRITE|AL_SIO_MII_DATAOUT); 345 else 346 CSR_WRITE_4(sc, AL_SIO, AL_SIO_ROMCTL_WRITE); 347 348 AL_SETBIT(sc, AL_SIO, AL_SIO_MII_CLK); 349 AL_CLRBIT(sc, AL_SIO, AL_SIO_MII_CLK); 350 351 return; 352 } 353 354 /* 355 * Read a bit from the MII bus. 356 */ 357 static int al_mii_readbit(sc) 358 struct al_softc *sc; 359 { 360 CSR_WRITE_4(sc, AL_SIO, AL_SIO_ROMCTL_READ|AL_SIO_MII_DIR); 361 CSR_READ_4(sc, AL_SIO); 362 AL_SETBIT(sc, AL_SIO, AL_SIO_MII_CLK); 363 AL_CLRBIT(sc, AL_SIO, AL_SIO_MII_CLK); 364 if (CSR_READ_4(sc, AL_SIO) & AL_SIO_MII_DATAIN) 365 return(1); 366 367 return(0); 368 } 369 370 /* 371 * Sync the PHYs by setting data bit and strobing the clock 32 times. 372 */ 373 static void al_mii_sync(sc) 374 struct al_softc *sc; 375 { 376 register int i; 377 378 CSR_WRITE_4(sc, AL_SIO, AL_SIO_ROMCTL_WRITE); 379 380 for (i = 0; i < 32; i++) 381 al_mii_writebit(sc, 1); 382 383 return; 384 } 385 386 /* 387 * Clock a series of bits through the MII. 388 */ 389 static void al_mii_send(sc, bits, cnt) 390 struct al_softc *sc; 391 u_int32_t bits; 392 int cnt; 393 { 394 int i; 395 396 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 397 al_mii_writebit(sc, bits & i); 398 } 399 400 /* 401 * Read an PHY register through the MII. 402 */ 403 static int al_mii_readreg(sc, frame) 404 struct al_softc *sc; 405 struct al_mii_frame *frame; 406 407 { 408 int i, ack, s; 409 410 s = splimp(); 411 412 /* 413 * Set up frame for RX. 414 */ 415 frame->mii_stdelim = AL_MII_STARTDELIM; 416 frame->mii_opcode = AL_MII_READOP; 417 frame->mii_turnaround = 0; 418 frame->mii_data = 0; 419 420 /* 421 * Sync the PHYs. 422 */ 423 al_mii_sync(sc); 424 425 /* 426 * Send command/address info. 427 */ 428 al_mii_send(sc, frame->mii_stdelim, 2); 429 al_mii_send(sc, frame->mii_opcode, 2); 430 al_mii_send(sc, frame->mii_phyaddr, 5); 431 al_mii_send(sc, frame->mii_regaddr, 5); 432 433 #ifdef notdef 434 /* Idle bit */ 435 al_mii_writebit(sc, 1); 436 al_mii_writebit(sc, 0); 437 #endif 438 439 /* Check for ack */ 440 ack = al_mii_readbit(sc); 441 442 /* 443 * Now try reading data bits. If the ack failed, we still 444 * need to clock through 16 cycles to keep the PHY(s) in sync. 445 */ 446 if (ack) { 447 for(i = 0; i < 16; i++) { 448 al_mii_readbit(sc); 449 } 450 goto fail; 451 } 452 453 for (i = 0x8000; i; i >>= 1) { 454 if (!ack) { 455 if (al_mii_readbit(sc)) 456 frame->mii_data |= i; 457 } 458 } 459 460 fail: 461 462 al_mii_writebit(sc, 0); 463 al_mii_writebit(sc, 0); 464 465 splx(s); 466 467 if (ack) 468 return(1); 469 return(0); 470 } 471 472 /* 473 * Write to a PHY register through the MII. 474 */ 475 static int al_mii_writereg(sc, frame) 476 struct al_softc *sc; 477 struct al_mii_frame *frame; 478 479 { 480 int s; 481 482 s = splimp(); 483 /* 484 * Set up frame for TX. 485 */ 486 487 frame->mii_stdelim = AL_MII_STARTDELIM; 488 frame->mii_opcode = AL_MII_WRITEOP; 489 frame->mii_turnaround = AL_MII_TURNAROUND; 490 491 /* 492 * Sync the PHYs. 493 */ 494 al_mii_sync(sc); 495 496 al_mii_send(sc, frame->mii_stdelim, 2); 497 al_mii_send(sc, frame->mii_opcode, 2); 498 al_mii_send(sc, frame->mii_phyaddr, 5); 499 al_mii_send(sc, frame->mii_regaddr, 5); 500 al_mii_send(sc, frame->mii_turnaround, 2); 501 al_mii_send(sc, frame->mii_data, 16); 502 503 /* Idle bit. */ 504 al_mii_writebit(sc, 0); 505 al_mii_writebit(sc, 0); 506 507 splx(s); 508 509 return(0); 510 } 511 512 static u_int16_t al_phy_readreg(sc, reg) 513 struct al_softc *sc; 514 int reg; 515 { 516 u_int16_t rval = 0; 517 u_int16_t phy_reg = 0; 518 struct al_mii_frame frame; 519 520 if (sc->al_info->al_did == AL_DEVICEID_AN985) { 521 if (sc->al_phy_addr != 1) 522 return(0); 523 frame.mii_phyaddr = sc->al_phy_addr; 524 frame.mii_regaddr = reg; 525 al_mii_readreg(sc, &frame); 526 return(frame.mii_data); 527 } 528 529 switch(reg) { 530 case PHY_BMCR: 531 phy_reg = AL_BMCR; 532 break; 533 case PHY_BMSR: 534 phy_reg = AL_BMSR; 535 break; 536 case PHY_VENID: 537 phy_reg = AL_VENID; 538 break; 539 case PHY_DEVID: 540 phy_reg = AL_DEVID; 541 break; 542 case PHY_ANAR: 543 phy_reg = AL_ANAR; 544 break; 545 case PHY_LPAR: 546 phy_reg = AL_LPAR; 547 break; 548 case PHY_ANEXP: 549 phy_reg = AL_ANER; 550 break; 551 default: 552 printf("al%d: read: bad phy register %x\n", 553 sc->al_unit, reg); 554 break; 555 } 556 557 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 558 559 return(rval); 560 } 561 562 static void al_phy_writereg(sc, reg, data) 563 struct al_softc *sc; 564 int reg; 565 int data; 566 { 567 u_int16_t phy_reg = 0; 568 struct al_mii_frame frame; 569 570 if (sc->al_info->al_did == AL_DEVICEID_AN985) { 571 if (sc->al_phy_addr != 1) 572 return; 573 frame.mii_phyaddr = sc->al_phy_addr; 574 frame.mii_regaddr = reg; 575 frame.mii_data = data; 576 al_mii_writereg(sc, &frame); 577 return; 578 } 579 580 switch(reg) { 581 case PHY_BMCR: 582 phy_reg = AL_BMCR; 583 break; 584 case PHY_BMSR: 585 phy_reg = AL_BMSR; 586 break; 587 case PHY_VENID: 588 phy_reg = AL_VENID; 589 break; 590 case PHY_DEVID: 591 phy_reg = AL_DEVID; 592 break; 593 case PHY_ANAR: 594 phy_reg = AL_ANAR; 595 break; 596 case PHY_LPAR: 597 phy_reg = AL_LPAR; 598 break; 599 case PHY_ANEXP: 600 phy_reg = AL_ANER; 601 break; 602 default: 603 printf("al%d: phy_write: bad phy register %x\n", 604 sc->al_unit, reg); 605 break; 606 } 607 608 CSR_WRITE_4(sc, phy_reg, data); 609 610 return; 611 } 612 613 /* 614 * Calculate CRC of a multicast group address, return the lower 6 bits. 615 */ 616 static u_int32_t al_calchash(addr) 617 caddr_t addr; 618 { 619 u_int32_t crc, carry; 620 int i, j; 621 u_int8_t c; 622 623 /* Compute CRC for the address value. */ 624 crc = 0xFFFFFFFF; /* initial value */ 625 626 for (i = 0; i < 6; i++) { 627 c = *(addr + i); 628 for (j = 0; j < 8; j++) { 629 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 630 crc <<= 1; 631 c >>= 1; 632 if (carry) 633 crc = (crc ^ 0x04c11db6) | carry; 634 } 635 } 636 637 /* return the filter bit position */ 638 return((crc >> 26) & 0x0000003F); 639 } 640 641 static void al_setmulti(sc) 642 struct al_softc *sc; 643 { 644 struct ifnet *ifp; 645 int h = 0; 646 u_int32_t hashes[2] = { 0, 0 }; 647 struct ifmultiaddr *ifma; 648 u_int32_t rxfilt; 649 650 ifp = &sc->arpcom.ac_if; 651 652 rxfilt = CSR_READ_4(sc, AL_NETCFG); 653 654 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 655 rxfilt |= AL_NETCFG_RX_ALLMULTI; 656 CSR_WRITE_4(sc, AL_NETCFG, rxfilt); 657 return; 658 } else 659 rxfilt &= ~AL_NETCFG_RX_ALLMULTI; 660 661 /* first, zot all the existing hash bits */ 662 CSR_WRITE_4(sc, AL_MAR0, 0); 663 CSR_WRITE_4(sc, AL_MAR1, 0); 664 665 /* now program new ones */ 666 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 667 ifma = ifma->ifma_link.le_next) { 668 if (ifma->ifma_addr->sa_family != AF_LINK) 669 continue; 670 h = al_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 671 if (h < 32) 672 hashes[0] |= (1 << h); 673 else 674 hashes[1] |= (1 << (h - 32)); 675 } 676 677 CSR_WRITE_4(sc, AL_MAR0, hashes[0]); 678 CSR_WRITE_4(sc, AL_MAR1, hashes[1]); 679 CSR_WRITE_4(sc, AL_NETCFG, rxfilt); 680 681 return; 682 } 683 684 /* 685 * Initiate an autonegotiation session. 686 */ 687 static void al_autoneg_xmit(sc) 688 struct al_softc *sc; 689 { 690 u_int16_t phy_sts; 691 692 al_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 693 DELAY(500); 694 while(al_phy_readreg(sc, PHY_BMCR) 695 & PHY_BMCR_RESET); 696 697 phy_sts = al_phy_readreg(sc, PHY_BMCR); 698 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 699 al_phy_writereg(sc, PHY_BMCR, phy_sts); 700 701 return; 702 } 703 704 /* 705 * Invoke autonegotiation on a PHY. 706 */ 707 static void al_autoneg_mii(sc, flag, verbose) 708 struct al_softc *sc; 709 int flag; 710 int verbose; 711 { 712 u_int16_t phy_sts = 0, media, advert, ability; 713 struct ifnet *ifp; 714 struct ifmedia *ifm; 715 716 ifm = &sc->ifmedia; 717 ifp = &sc->arpcom.ac_if; 718 719 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 720 721 /* 722 * The 100baseT4 PHY on the 3c905-T4 has the 'autoneg supported' 723 * bit cleared in the status register, but has the 'autoneg enabled' 724 * bit set in the control register. This is a contradiction, and 725 * I'm not sure how to handle it. If you want to force an attempt 726 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR 727 * and see what happens. 728 */ 729 #ifndef FORCE_AUTONEG_TFOUR 730 /* 731 * First, see if autoneg is supported. If not, there's 732 * no point in continuing. 733 */ 734 phy_sts = al_phy_readreg(sc, PHY_BMSR); 735 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 736 if (verbose) 737 printf("al%d: autonegotiation not supported\n", 738 sc->al_unit); 739 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 740 return; 741 } 742 #endif 743 744 switch (flag) { 745 case AL_FLAG_FORCEDELAY: 746 /* 747 * XXX Never use this option anywhere but in the probe 748 * routine: making the kernel stop dead in its tracks 749 * for three whole seconds after we've gone multi-user 750 * is really bad manners. 751 */ 752 al_autoneg_xmit(sc); 753 DELAY(5000000); 754 break; 755 case AL_FLAG_SCHEDDELAY: 756 /* 757 * Wait for the transmitter to go idle before starting 758 * an autoneg session, otherwise al_start() may clobber 759 * our timeout, and we don't want to allow transmission 760 * during an autoneg session since that can screw it up. 761 */ 762 if (sc->al_cdata.al_tx_head != NULL) { 763 sc->al_want_auto = 1; 764 return; 765 } 766 al_autoneg_xmit(sc); 767 ifp->if_timer = 5; 768 sc->al_autoneg = 1; 769 sc->al_want_auto = 0; 770 return; 771 break; 772 case AL_FLAG_DELAYTIMEO: 773 ifp->if_timer = 0; 774 sc->al_autoneg = 0; 775 break; 776 default: 777 printf("al%d: invalid autoneg flag: %d\n", sc->al_unit, flag); 778 return; 779 } 780 781 if (al_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 782 if (verbose) 783 printf("al%d: autoneg complete, ", sc->al_unit); 784 phy_sts = al_phy_readreg(sc, PHY_BMSR); 785 } else { 786 if (verbose) 787 printf("al%d: autoneg not complete, ", sc->al_unit); 788 } 789 790 media = al_phy_readreg(sc, PHY_BMCR); 791 792 /* Link is good. Report modes and set duplex mode. */ 793 if (al_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 794 if (verbose) 795 printf("link status good "); 796 advert = al_phy_readreg(sc, PHY_ANAR); 797 ability = al_phy_readreg(sc, PHY_LPAR); 798 799 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 800 ifm->ifm_media = IFM_ETHER|IFM_100_T4; 801 media |= PHY_BMCR_SPEEDSEL; 802 media &= ~PHY_BMCR_DUPLEX; 803 printf("(100baseT4)\n"); 804 } else if (advert & PHY_ANAR_100BTXFULL && 805 ability & PHY_ANAR_100BTXFULL) { 806 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 807 media |= PHY_BMCR_SPEEDSEL; 808 media |= PHY_BMCR_DUPLEX; 809 printf("(full-duplex, 100Mbps)\n"); 810 } else if (advert & PHY_ANAR_100BTXHALF && 811 ability & PHY_ANAR_100BTXHALF) { 812 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 813 media |= PHY_BMCR_SPEEDSEL; 814 media &= ~PHY_BMCR_DUPLEX; 815 printf("(half-duplex, 100Mbps)\n"); 816 } else if (advert & PHY_ANAR_10BTFULL && 817 ability & PHY_ANAR_10BTFULL) { 818 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 819 media &= ~PHY_BMCR_SPEEDSEL; 820 media |= PHY_BMCR_DUPLEX; 821 printf("(full-duplex, 10Mbps)\n"); 822 } else if (advert & PHY_ANAR_10BTHALF && 823 ability & PHY_ANAR_10BTHALF) { 824 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 825 media &= ~PHY_BMCR_SPEEDSEL; 826 media &= ~PHY_BMCR_DUPLEX; 827 printf("(half-duplex, 10Mbps)\n"); 828 } 829 830 media &= ~PHY_BMCR_AUTONEGENBL; 831 832 /* Set ASIC's duplex mode to match the PHY. */ 833 al_phy_writereg(sc, PHY_BMCR, media); 834 } else { 835 if (verbose) 836 printf("no carrier\n"); 837 } 838 839 al_init(sc); 840 841 if (sc->al_tx_pend) { 842 sc->al_autoneg = 0; 843 sc->al_tx_pend = 0; 844 al_start(ifp); 845 } 846 847 return; 848 } 849 850 static void al_getmode_mii(sc) 851 struct al_softc *sc; 852 { 853 u_int16_t bmsr; 854 struct ifnet *ifp; 855 856 ifp = &sc->arpcom.ac_if; 857 858 bmsr = al_phy_readreg(sc, PHY_BMSR); 859 if (bootverbose) 860 printf("al%d: PHY status word: %x\n", sc->al_unit, bmsr); 861 862 /* fallback */ 863 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 864 865 if (bmsr & PHY_BMSR_10BTHALF) { 866 if (bootverbose) 867 printf("al%d: 10Mbps half-duplex mode supported\n", 868 sc->al_unit); 869 ifmedia_add(&sc->ifmedia, 870 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 871 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 872 } 873 874 if (bmsr & PHY_BMSR_10BTFULL) { 875 if (bootverbose) 876 printf("al%d: 10Mbps full-duplex mode supported\n", 877 sc->al_unit); 878 ifmedia_add(&sc->ifmedia, 879 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 880 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 881 } 882 883 if (bmsr & PHY_BMSR_100BTXHALF) { 884 if (bootverbose) 885 printf("al%d: 100Mbps half-duplex mode supported\n", 886 sc->al_unit); 887 ifp->if_baudrate = 100000000; 888 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 889 ifmedia_add(&sc->ifmedia, 890 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 891 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 892 } 893 894 if (bmsr & PHY_BMSR_100BTXFULL) { 895 if (bootverbose) 896 printf("al%d: 100Mbps full-duplex mode supported\n", 897 sc->al_unit); 898 ifp->if_baudrate = 100000000; 899 ifmedia_add(&sc->ifmedia, 900 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 901 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 902 } 903 904 /* Some also support 100BaseT4. */ 905 if (bmsr & PHY_BMSR_100BT4) { 906 if (bootverbose) 907 printf("al%d: 100baseT4 mode supported\n", sc->al_unit); 908 ifp->if_baudrate = 100000000; 909 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); 910 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4; 911 #ifdef FORCE_AUTONEG_TFOUR 912 if (bootverbose) 913 printf("al%d: forcing on autoneg support for BT4\n", 914 sc->al_unit); 915 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL): 916 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 917 #endif 918 } 919 920 if (bmsr & PHY_BMSR_CANAUTONEG) { 921 if (bootverbose) 922 printf("al%d: autoneg supported\n", sc->al_unit); 923 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 924 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 925 } 926 927 return; 928 } 929 930 /* 931 * Set speed and duplex mode. 932 */ 933 static void al_setmode_mii(sc, media) 934 struct al_softc *sc; 935 int media; 936 { 937 u_int16_t bmcr; 938 struct ifnet *ifp; 939 940 ifp = &sc->arpcom.ac_if; 941 942 /* 943 * If an autoneg session is in progress, stop it. 944 */ 945 if (sc->al_autoneg) { 946 printf("al%d: canceling autoneg session\n", sc->al_unit); 947 ifp->if_timer = sc->al_autoneg = sc->al_want_auto = 0; 948 bmcr = al_phy_readreg(sc, PHY_BMCR); 949 bmcr &= ~PHY_BMCR_AUTONEGENBL; 950 al_phy_writereg(sc, PHY_BMCR, bmcr); 951 } 952 953 printf("al%d: selecting MII, ", sc->al_unit); 954 955 bmcr = al_phy_readreg(sc, PHY_BMCR); 956 957 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL| 958 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK); 959 960 if (IFM_SUBTYPE(media) == IFM_100_T4) { 961 printf("100Mbps/T4, half-duplex\n"); 962 bmcr |= PHY_BMCR_SPEEDSEL; 963 bmcr &= ~PHY_BMCR_DUPLEX; 964 } 965 966 if (IFM_SUBTYPE(media) == IFM_100_TX) { 967 printf("100Mbps, "); 968 bmcr |= PHY_BMCR_SPEEDSEL; 969 } 970 971 if (IFM_SUBTYPE(media) == IFM_10_T) { 972 printf("10Mbps, "); 973 bmcr &= ~PHY_BMCR_SPEEDSEL; 974 } 975 976 if ((media & IFM_GMASK) == IFM_FDX) { 977 printf("full duplex\n"); 978 bmcr |= PHY_BMCR_DUPLEX; 979 } else { 980 printf("half duplex\n"); 981 bmcr &= ~PHY_BMCR_DUPLEX; 982 } 983 984 al_phy_writereg(sc, PHY_BMCR, bmcr); 985 986 return; 987 } 988 989 static void al_reset(sc) 990 struct al_softc *sc; 991 { 992 register int i; 993 994 AL_SETBIT(sc, AL_BUSCTL, AL_BUSCTL_RESET); 995 996 for (i = 0; i < AL_TIMEOUT; i++) { 997 DELAY(10); 998 if (!(CSR_READ_4(sc, AL_BUSCTL) & AL_BUSCTL_RESET)) 999 break; 1000 } 1001 #ifdef notdef 1002 if (i == AL_TIMEOUT) 1003 printf("al%d: reset never completed!\n", sc->al_unit); 1004 #endif 1005 CSR_WRITE_4(sc, AL_BUSCTL, AL_BUSCTL_ARBITRATION); 1006 1007 /* Wait a little while for the chip to get its brains in order. */ 1008 DELAY(1000); 1009 return; 1010 } 1011 1012 /* 1013 * Probe for an ADMtek chip. Check the PCI vendor and device 1014 * IDs against our list and return a device name if we find a match. 1015 */ 1016 static const char * 1017 al_probe(config_id, device_id) 1018 pcici_t config_id; 1019 pcidi_t device_id; 1020 { 1021 struct al_type *t; 1022 1023 t = al_devs; 1024 1025 while(t->al_name != NULL) { 1026 if ((device_id & 0xFFFF) == t->al_vid && 1027 ((device_id >> 16) & 0xFFFF) == t->al_did) { 1028 return(t->al_name); 1029 } 1030 t++; 1031 } 1032 1033 return(NULL); 1034 } 1035 1036 /* 1037 * Attach the interface. Allocate softc structures, do ifmedia 1038 * setup and ethernet/BPF attach. 1039 */ 1040 static void 1041 al_attach(config_id, unit) 1042 pcici_t config_id; 1043 int unit; 1044 { 1045 int s, i; 1046 #ifndef AL_USEIOSPACE 1047 vm_offset_t pbase, vbase; 1048 #endif 1049 u_char eaddr[ETHER_ADDR_LEN]; 1050 u_int32_t command; 1051 struct al_softc *sc; 1052 struct ifnet *ifp; 1053 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1054 unsigned int round; 1055 caddr_t roundptr; 1056 struct al_type *p; 1057 u_int16_t phy_vid, phy_did, phy_sts; 1058 u_int32_t device_id; 1059 1060 s = splimp(); 1061 1062 sc = malloc(sizeof(struct al_softc), M_DEVBUF, M_NOWAIT); 1063 if (sc == NULL) { 1064 printf("al%d: no memory for softc struct!\n", unit); 1065 goto fail; 1066 } 1067 bzero(sc, sizeof(struct al_softc)); 1068 1069 /* Save the device type; we need it later */ 1070 device_id = pci_conf_read(config_id, AL_PCI_VENDOR_ID); 1071 p = al_devs; 1072 1073 while(p->al_name != NULL) { 1074 if ((device_id & 0xFFFF) == p->al_vid && 1075 ((device_id >> 16) & 0xFFFF) == p->al_did) { 1076 break; 1077 } 1078 p++; 1079 } 1080 sc->al_info = p; 1081 1082 /* 1083 * Handle power management nonsense. 1084 */ 1085 1086 command = pci_conf_read(config_id, AL_PCI_CAPID) & 0x000000FF; 1087 if (command == 0x01) { 1088 1089 command = pci_conf_read(config_id, AL_PCI_PWRMGMTCTRL); 1090 if (command & AL_PSTATE_MASK) { 1091 u_int32_t iobase, membase, irq; 1092 1093 /* Save important PCI config data. */ 1094 iobase = pci_conf_read(config_id, AL_PCI_LOIO); 1095 membase = pci_conf_read(config_id, AL_PCI_LOMEM); 1096 irq = pci_conf_read(config_id, AL_PCI_INTLINE); 1097 1098 /* Reset the power state. */ 1099 printf("al%d: chip is in D%d power mode " 1100 "-- setting to D0\n", unit, command & AL_PSTATE_MASK); 1101 command &= 0xFFFFFFFC; 1102 pci_conf_write(config_id, AL_PCI_PWRMGMTCTRL, command); 1103 1104 /* Restore PCI config data. */ 1105 pci_conf_write(config_id, AL_PCI_LOIO, iobase); 1106 pci_conf_write(config_id, AL_PCI_LOMEM, membase); 1107 pci_conf_write(config_id, AL_PCI_INTLINE, irq); 1108 } 1109 } 1110 1111 /* 1112 * Map control/status registers. 1113 */ 1114 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1115 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1116 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); 1117 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1118 1119 #ifdef AL_USEIOSPACE 1120 if (!(command & PCIM_CMD_PORTEN)) { 1121 printf("al%d: failed to enable I/O ports!\n", unit); 1122 free(sc, M_DEVBUF); 1123 goto fail; 1124 } 1125 1126 if (!pci_map_port(config_id, AL_PCI_LOIO, 1127 (u_short *)&(sc->al_bhandle))) { 1128 printf ("al%d: couldn't map ports\n", unit); 1129 goto fail; 1130 } 1131 #ifdef __i386__ 1132 sc->al_btag = I386_BUS_SPACE_IO; 1133 #endif 1134 #ifdef __alpha__ 1135 sc->al_btag = ALPHA_BUS_SPACE_IO; 1136 #endif 1137 #else 1138 if (!(command & PCIM_CMD_MEMEN)) { 1139 printf("al%d: failed to enable memory mapping!\n", unit); 1140 goto fail; 1141 } 1142 1143 if (!pci_map_mem(config_id, AL_PCI_LOMEM, &vbase, &pbase)) { 1144 printf ("al%d: couldn't map memory\n", unit); 1145 goto fail; 1146 } 1147 #ifdef __i386__ 1148 sc->al_btag = I386_BUS_SPACE_MEM; 1149 #endif 1150 #ifdef __alpha__ 1151 sc->al_btag = ALPHA_BUS_SPACE_MEM; 1152 #endif 1153 sc->al_bhandle = vbase; 1154 #endif 1155 1156 /* Allocate interrupt */ 1157 if (!pci_map_int(config_id, al_intr, sc, &net_imask)) { 1158 printf("al%d: couldn't map interrupt\n", unit); 1159 goto fail; 1160 } 1161 1162 /* Save cache line size. */ 1163 sc->al_cachesize = pci_conf_read(config_id, AL_PCI_CACHELEN) & 0xFF; 1164 1165 /* Reset the adapter. */ 1166 al_reset(sc); 1167 1168 /* 1169 * Get station address from the EEPROM. 1170 */ 1171 al_read_eeprom(sc, (caddr_t)&eaddr, AL_EE_NODEADDR, 3, 0); 1172 1173 /* 1174 * An ADMtek chip was detected. Inform the world. 1175 */ 1176 printf("al%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1177 1178 sc->al_unit = unit; 1179 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1180 1181 sc->al_ldata_ptr = malloc(sizeof(struct al_list_data) + 8, 1182 M_DEVBUF, M_NOWAIT); 1183 if (sc->al_ldata_ptr == NULL) { 1184 free(sc, M_DEVBUF); 1185 printf("al%d: no memory for list buffers!\n", unit); 1186 goto fail; 1187 } 1188 1189 sc->al_ldata = (struct al_list_data *)sc->al_ldata_ptr; 1190 round = (unsigned long)sc->al_ldata_ptr & 0xF; 1191 roundptr = sc->al_ldata_ptr; 1192 for (i = 0; i < 8; i++) { 1193 if (round % 8) { 1194 round++; 1195 roundptr++; 1196 } else 1197 break; 1198 } 1199 sc->al_ldata = (struct al_list_data *)roundptr; 1200 bzero(sc->al_ldata, sizeof(struct al_list_data)); 1201 1202 ifp = &sc->arpcom.ac_if; 1203 ifp->if_softc = sc; 1204 ifp->if_unit = unit; 1205 ifp->if_name = "al"; 1206 ifp->if_mtu = ETHERMTU; 1207 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1208 ifp->if_ioctl = al_ioctl; 1209 ifp->if_output = ether_output; 1210 ifp->if_start = al_start; 1211 ifp->if_watchdog = al_watchdog; 1212 ifp->if_init = al_init; 1213 ifp->if_baudrate = 10000000; 1214 ifp->if_snd.ifq_maxlen = AL_TX_LIST_CNT - 1; 1215 1216 if (bootverbose) 1217 printf("al%d: probing for a PHY\n", sc->al_unit); 1218 for (i = AL_PHYADDR_MIN; i < AL_PHYADDR_MAL + 1; i++) { 1219 if (bootverbose) 1220 printf("al%d: checking address: %d\n", 1221 sc->al_unit, i); 1222 sc->al_phy_addr = i; 1223 al_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 1224 DELAY(500); 1225 while(al_phy_readreg(sc, PHY_BMCR) 1226 & PHY_BMCR_RESET); 1227 if ((phy_sts = al_phy_readreg(sc, PHY_BMSR))) 1228 break; 1229 } 1230 if (phy_sts) { 1231 phy_vid = al_phy_readreg(sc, PHY_VENID); 1232 phy_did = al_phy_readreg(sc, PHY_DEVID); 1233 if (bootverbose) 1234 printf("al%d: found PHY at address %d, ", 1235 sc->al_unit, sc->al_phy_addr); 1236 if (bootverbose) 1237 printf("vendor id: %x device id: %x\n", 1238 phy_vid, phy_did); 1239 p = al_phys; 1240 while(p->al_vid) { 1241 if (phy_vid == p->al_vid && 1242 (phy_did | 0x000F) == p->al_did) { 1243 sc->al_pinfo = p; 1244 break; 1245 } 1246 p++; 1247 } 1248 if (sc->al_pinfo == NULL) 1249 sc->al_pinfo = &al_phys[PHY_UNKNOWN]; 1250 if (bootverbose) 1251 printf("al%d: PHY type: %s\n", 1252 sc->al_unit, sc->al_pinfo->al_name); 1253 } else { 1254 #ifdef DIAGNOSTIC 1255 printf("al%d: MII without any phy!\n", sc->al_unit); 1256 #endif 1257 } 1258 1259 /* 1260 * Do ifmedia setup. 1261 */ 1262 ifmedia_init(&sc->ifmedia, 0, al_ifmedia_upd, al_ifmedia_sts); 1263 1264 if (sc->al_pinfo != NULL) { 1265 al_getmode_mii(sc); 1266 al_autoneg_mii(sc, AL_FLAG_FORCEDELAY, 1); 1267 } else { 1268 ifmedia_add(&sc->ifmedia, 1269 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1270 ifmedia_add(&sc->ifmedia, 1271 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1272 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1273 ifmedia_add(&sc->ifmedia, 1274 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 1275 ifmedia_add(&sc->ifmedia, 1276 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1277 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1278 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1279 } 1280 1281 media = sc->ifmedia.ifm_media; 1282 al_stop(sc); 1283 1284 ifmedia_set(&sc->ifmedia, media); 1285 1286 /* 1287 * Call MI attach routines. 1288 */ 1289 if_attach(ifp); 1290 ether_ifattach(ifp); 1291 1292 #if NBPFILTER > 0 1293 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1294 #endif 1295 at_shutdown(al_shutdown, sc, SHUTDOWN_POST_SYNC); 1296 1297 fail: 1298 splx(s); 1299 return; 1300 } 1301 1302 /* 1303 * Initialize the transmit descriptors. 1304 */ 1305 static int al_list_tx_init(sc) 1306 struct al_softc *sc; 1307 { 1308 struct al_chain_data *cd; 1309 struct al_list_data *ld; 1310 int i; 1311 1312 cd = &sc->al_cdata; 1313 ld = sc->al_ldata; 1314 for (i = 0; i < AL_TX_LIST_CNT; i++) { 1315 cd->al_tx_chain[i].al_ptr = &ld->al_tx_list[i]; 1316 if (i == (AL_TX_LIST_CNT - 1)) 1317 cd->al_tx_chain[i].al_nextdesc = 1318 &cd->al_tx_chain[0]; 1319 else 1320 cd->al_tx_chain[i].al_nextdesc = 1321 &cd->al_tx_chain[i + 1]; 1322 } 1323 1324 cd->al_tx_free = &cd->al_tx_chain[0]; 1325 cd->al_tx_tail = cd->al_tx_head = NULL; 1326 1327 return(0); 1328 } 1329 1330 1331 /* 1332 * Initialize the RX descriptors and allocate mbufs for them. Note that 1333 * we arrange the descriptors in a closed ring, so that the last descriptor 1334 * points back to the first. 1335 */ 1336 static int al_list_rx_init(sc) 1337 struct al_softc *sc; 1338 { 1339 struct al_chain_data *cd; 1340 struct al_list_data *ld; 1341 int i; 1342 1343 cd = &sc->al_cdata; 1344 ld = sc->al_ldata; 1345 1346 for (i = 0; i < AL_RX_LIST_CNT; i++) { 1347 cd->al_rx_chain[i].al_ptr = 1348 (volatile struct al_desc *)&ld->al_rx_list[i]; 1349 if (al_newbuf(sc, &cd->al_rx_chain[i]) == ENOBUFS) 1350 return(ENOBUFS); 1351 if (i == (AL_RX_LIST_CNT - 1)) { 1352 cd->al_rx_chain[i].al_nextdesc = 1353 &cd->al_rx_chain[0]; 1354 ld->al_rx_list[i].al_next = 1355 vtophys(&ld->al_rx_list[0]); 1356 } else { 1357 cd->al_rx_chain[i].al_nextdesc = 1358 &cd->al_rx_chain[i + 1]; 1359 ld->al_rx_list[i].al_next = 1360 vtophys(&ld->al_rx_list[i + 1]); 1361 } 1362 } 1363 1364 cd->al_rx_head = &cd->al_rx_chain[0]; 1365 1366 return(0); 1367 } 1368 1369 /* 1370 * Initialize an RX descriptor and attach an MBUF cluster. 1371 * Note: the length fields are only 11 bits wide, which means the 1372 * largest size we can specify is 2047. This is important because 1373 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1374 * overflow the field and make a mess. 1375 */ 1376 static int al_newbuf(sc, c) 1377 struct al_softc *sc; 1378 struct al_chain_onefrag *c; 1379 { 1380 struct mbuf *m_new = NULL; 1381 1382 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1383 if (m_new == NULL) { 1384 printf("al%d: no memory for rx list -- packet dropped!\n", 1385 sc->al_unit); 1386 return(ENOBUFS); 1387 } 1388 1389 MCLGET(m_new, M_DONTWAIT); 1390 if (!(m_new->m_flags & M_EXT)) { 1391 printf("al%d: no memory for rx list -- packet dropped!\n", 1392 sc->al_unit); 1393 m_freem(m_new); 1394 return(ENOBUFS); 1395 } 1396 1397 c->al_mbuf = m_new; 1398 c->al_ptr->al_status = AL_RXSTAT; 1399 c->al_ptr->al_data = vtophys(mtod(m_new, caddr_t)); 1400 c->al_ptr->al_ctl = MCLBYTES - 1; 1401 1402 return(0); 1403 } 1404 1405 /* 1406 * A frame has been uploaded: pass the resulting mbuf chain up to 1407 * the higher level protocols. 1408 */ 1409 static void al_rxeof(sc) 1410 struct al_softc *sc; 1411 { 1412 struct ether_header *eh; 1413 struct mbuf *m; 1414 struct ifnet *ifp; 1415 struct al_chain_onefrag *cur_rx; 1416 int total_len = 0; 1417 u_int32_t rxstat; 1418 1419 ifp = &sc->arpcom.ac_if; 1420 1421 while(!((rxstat = sc->al_cdata.al_rx_head->al_ptr->al_status) & 1422 AL_RXSTAT_OWN)) { 1423 #ifdef __alpha__ 1424 struct mbuf *m0 = NULL; 1425 #endif 1426 cur_rx = sc->al_cdata.al_rx_head; 1427 sc->al_cdata.al_rx_head = cur_rx->al_nextdesc; 1428 1429 /* 1430 * If an error occurs, update stats, clear the 1431 * status word and leave the mbuf cluster in place: 1432 * it should simply get re-used next time this descriptor 1433 * comes up in the ring. 1434 */ 1435 if (rxstat & AL_RXSTAT_RXERR) { 1436 ifp->if_ierrors++; 1437 if (rxstat & AL_RXSTAT_COLLSEEN) 1438 ifp->if_collisions++; 1439 cur_rx->al_ptr->al_status = AL_RXSTAT; 1440 cur_rx->al_ptr->al_ctl = (MCLBYTES - 1); 1441 continue; 1442 } 1443 1444 /* No errors; receive the packet. */ 1445 m = cur_rx->al_mbuf; 1446 total_len = AL_RXBYTES(cur_rx->al_ptr->al_status); 1447 1448 total_len -= ETHER_CRC_LEN; 1449 1450 #ifdef __alpha__ 1451 /* 1452 * Try to conjure up a new mbuf cluster. If that 1453 * fails, it means we have an out of memory condition and 1454 * should leave the buffer in place and continue. This will 1455 * result in a lost packet, but there's little else we 1456 * can do in this situation. 1457 */ 1458 if (al_newbuf(sc, cur_rx) == ENOBUFS) { 1459 ifp->if_ierrors++; 1460 cur_rx->al_ptr->al_status = AL_RXSTAT; 1461 cur_rx->al_ptr->al_ctl = (MCLBYTES - 1); 1462 continue; 1463 } 1464 1465 /* 1466 * Sadly, the ADMtek chip doesn't decode the last few 1467 * bits of the RX DMA buffer address, so we have to 1468 * cheat in order to obtain proper payload alignment 1469 * on the alpha. 1470 */ 1471 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1472 if (m0 == NULL) { 1473 ifp->if_ierrors++; 1474 cur_rx->al_ptr->al_status = AL_RXSTAT; 1475 cur_rx->al_ptr->al_ctl = (MCLBYTES - 1); 1476 continue; 1477 } 1478 1479 m0->m_data += 2; 1480 if (total_len <= (MHLEN - 2)) { 1481 bcopy(mtod(m, caddr_t), mtod(m0, caddr_t), total_len); m_freem(m); 1482 m = m0; 1483 m->m_pkthdr.len = m->m_len = total_len; 1484 } else { 1485 bcopy(mtod(m, caddr_t), mtod(m0, caddr_t), (MHLEN - 2)); 1486 m->m_len = total_len - (MHLEN - 2); 1487 m->m_data += (MHLEN - 2); 1488 m0->m_next = m; 1489 m0->m_len = (MHLEN - 2); 1490 m = m0; 1491 m->m_pkthdr.len = total_len; 1492 } 1493 m->m_pkthdr.rcvif = ifp; 1494 #else 1495 if (total_len < MINCLSIZE) { 1496 m = m_devget(mtod(cur_rx->al_mbuf, char *), 1497 total_len, 0, ifp, NULL); 1498 cur_rx->al_ptr->al_status = AL_RXSTAT; 1499 cur_rx->al_ptr->al_ctl = (MCLBYTES - 1); 1500 if (m == NULL) { 1501 ifp->if_ierrors++; 1502 continue; 1503 } 1504 } else { 1505 m = cur_rx->al_mbuf; 1506 /* 1507 * Try to conjure up a new mbuf cluster. If that 1508 * fails, it means we have an out of memory condition and 1509 * should leave the buffer in place and continue. This will 1510 * result in a lost packet, but there's little else we 1511 * can do in this situation. 1512 */ 1513 if (al_newbuf(sc, cur_rx) == ENOBUFS) { 1514 ifp->if_ierrors++; 1515 cur_rx->al_ptr->al_status = AL_RXSTAT; 1516 cur_rx->al_ptr->al_ctl = (MCLBYTES - 1); 1517 continue; 1518 } 1519 m->m_pkthdr.rcvif = ifp; 1520 m->m_pkthdr.len = m->m_len = total_len; 1521 } 1522 #endif 1523 1524 ifp->if_ipackets++; 1525 eh = mtod(m, struct ether_header *); 1526 #if NBPFILTER > 0 1527 /* 1528 * Handle BPF listeners. Let the BPF user see the packet, but 1529 * don't pass it up to the ether_input() layer unless it's 1530 * a broadcast packet, multicast packet, matches our ethernet 1531 * address or the interface is in promiscuous mode. 1532 */ 1533 if (ifp->if_bpf) { 1534 bpf_mtap(ifp, m); 1535 if (ifp->if_flags & IFF_PROMISC && 1536 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1537 ETHER_ADDR_LEN) && 1538 (eh->ether_dhost[0] & 1) == 0)) { 1539 m_freem(m); 1540 continue; 1541 } 1542 } 1543 #endif 1544 /* Remove header from mbuf and pass it on. */ 1545 m_adj(m, sizeof(struct ether_header)); 1546 ether_input(ifp, eh, m); 1547 } 1548 1549 return; 1550 } 1551 1552 void al_rxeoc(sc) 1553 struct al_softc *sc; 1554 { 1555 1556 al_rxeof(sc); 1557 AL_CLRBIT(sc, AL_NETCFG, AL_NETCFG_RX_ON); 1558 CSR_WRITE_4(sc, AL_RXADDR, vtophys(sc->al_cdata.al_rx_head->al_ptr)); 1559 AL_SETBIT(sc, AL_NETCFG, AL_NETCFG_RX_ON); 1560 CSR_WRITE_4(sc, AL_RXSTART, 0xFFFFFFFF); 1561 1562 return; 1563 } 1564 1565 /* 1566 * A frame was downloaded to the chip. It's safe for us to clean up 1567 * the list buffers. 1568 */ 1569 1570 static void al_txeof(sc) 1571 struct al_softc *sc; 1572 { 1573 struct al_chain *cur_tx; 1574 struct ifnet *ifp; 1575 1576 ifp = &sc->arpcom.ac_if; 1577 1578 /* Clear the timeout timer. */ 1579 ifp->if_timer = 0; 1580 1581 if (sc->al_cdata.al_tx_head == NULL) 1582 return; 1583 1584 /* 1585 * Go through our tx list and free mbufs for those 1586 * frames that have been transmitted. 1587 */ 1588 while(sc->al_cdata.al_tx_head->al_mbuf != NULL) { 1589 u_int32_t txstat; 1590 1591 cur_tx = sc->al_cdata.al_tx_head; 1592 txstat = AL_TXSTATUS(cur_tx); 1593 1594 if (txstat & AL_TXSTAT_OWN) 1595 break; 1596 1597 if (txstat & AL_TXSTAT_ERRSUM) { 1598 ifp->if_oerrors++; 1599 if (txstat & AL_TXSTAT_EXCESSCOLL) 1600 ifp->if_collisions++; 1601 if (txstat & AL_TXSTAT_LATECOLL) 1602 ifp->if_collisions++; 1603 } 1604 1605 ifp->if_collisions += (txstat & AL_TXSTAT_COLLCNT) >> 3; 1606 1607 ifp->if_opackets++; 1608 m_freem(cur_tx->al_mbuf); 1609 cur_tx->al_mbuf = NULL; 1610 1611 if (sc->al_cdata.al_tx_head == sc->al_cdata.al_tx_tail) { 1612 sc->al_cdata.al_tx_head = NULL; 1613 sc->al_cdata.al_tx_tail = NULL; 1614 ifp->if_flags &= ~IFF_OACTIVE; 1615 break; 1616 } 1617 1618 sc->al_cdata.al_tx_head = cur_tx->al_nextdesc; 1619 } 1620 1621 return; 1622 } 1623 1624 /* 1625 * TX 'end of channel' interrupt handler. 1626 */ 1627 static void al_txeoc(sc) 1628 struct al_softc *sc; 1629 { 1630 struct ifnet *ifp; 1631 1632 ifp = &sc->arpcom.ac_if; 1633 1634 ifp->if_timer = 0; 1635 1636 if (sc->al_cdata.al_tx_head == NULL) { 1637 ifp->if_flags &= ~IFF_OACTIVE; 1638 sc->al_cdata.al_tx_tail = NULL; 1639 if (sc->al_want_auto) 1640 al_autoneg_mii(sc, AL_FLAG_DELAYTIMEO, 1); 1641 } 1642 1643 return; 1644 } 1645 1646 static void al_intr(arg) 1647 void *arg; 1648 { 1649 struct al_softc *sc; 1650 struct ifnet *ifp; 1651 u_int32_t status; 1652 1653 sc = arg; 1654 ifp = &sc->arpcom.ac_if; 1655 1656 /* Supress unwanted interrupts */ 1657 if (!(ifp->if_flags & IFF_UP)) { 1658 al_stop(sc); 1659 return; 1660 } 1661 1662 /* Disable interrupts. */ 1663 CSR_WRITE_4(sc, AL_IMR, 0x00000000); 1664 1665 for (;;) { 1666 status = CSR_READ_4(sc, AL_ISR); 1667 if (status) 1668 CSR_WRITE_4(sc, AL_ISR, status); 1669 1670 if ((status & AL_INTRS) == 0) 1671 break; 1672 1673 if (status & AL_ISR_TX_OK) 1674 al_txeof(sc); 1675 1676 if (status & AL_ISR_TX_NOBUF) 1677 al_txeoc(sc); 1678 1679 if (status & AL_ISR_TX_IDLE) { 1680 al_txeof(sc); 1681 if (sc->al_cdata.al_tx_head != NULL) { 1682 AL_SETBIT(sc, AL_NETCFG, AL_NETCFG_TX_ON); 1683 CSR_WRITE_4(sc, AL_TXSTART, 0xFFFFFFFF); 1684 } 1685 } 1686 1687 if (status & AL_ISR_TX_UNDERRUN) { 1688 u_int32_t cfg; 1689 cfg = CSR_READ_4(sc, AL_NETCFG); 1690 if ((cfg & AL_NETCFG_TX_THRESH) == AL_TXTHRESH_160BYTES) 1691 AL_SETBIT(sc, AL_NETCFG, AL_NETCFG_STORENFWD); 1692 else 1693 CSR_WRITE_4(sc, AL_NETCFG, cfg + 0x4000); 1694 } 1695 1696 if (status & AL_ISR_RX_OK) 1697 al_rxeof(sc); 1698 1699 if ((status & AL_ISR_RX_WATDOGTIMEO) 1700 || (status & AL_ISR_RX_NOBUF)) 1701 al_rxeoc(sc); 1702 1703 if (status & AL_ISR_BUS_ERR) { 1704 al_reset(sc); 1705 al_init(sc); 1706 } 1707 } 1708 1709 /* Re-enable interrupts. */ 1710 CSR_WRITE_4(sc, AL_IMR, AL_INTRS); 1711 1712 if (ifp->if_snd.ifq_head != NULL) { 1713 al_start(ifp); 1714 } 1715 1716 return; 1717 } 1718 1719 /* 1720 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1721 * pointers to the fragment pointers. 1722 */ 1723 static int al_encap(sc, c, m_head) 1724 struct al_softc *sc; 1725 struct al_chain *c; 1726 struct mbuf *m_head; 1727 { 1728 int frag = 0; 1729 volatile struct al_desc *f = NULL; 1730 int total_len; 1731 struct mbuf *m; 1732 1733 /* 1734 * Start packing the mbufs in this chain into 1735 * the fragment pointers. Stop when we run out 1736 * of fragments or hit the end of the mbuf chain. 1737 */ 1738 m = m_head; 1739 total_len = 0; 1740 1741 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1742 if (m->m_len != 0) { 1743 if (frag == AL_MAXFRAGS) 1744 break; 1745 total_len += m->m_len; 1746 f = &c->al_ptr->al_frag[frag]; 1747 f->al_ctl = AL_TXCTL_TLINK | m->m_len; 1748 if (frag == 0) { 1749 f->al_status = 0; 1750 f->al_ctl |= AL_TXCTL_FIRSTFRAG; 1751 } else 1752 f->al_status = AL_TXSTAT_OWN; 1753 f->al_next = vtophys(&c->al_ptr->al_frag[frag + 1]); 1754 f->al_data = vtophys(mtod(m, vm_offset_t)); 1755 frag++; 1756 } 1757 } 1758 1759 /* 1760 * Handle special case: we ran out of fragments, 1761 * but we have more mbufs left in the chain. Copy the 1762 * data into an mbuf cluster. Note that we don't 1763 * bother clearing the values in the other fragment 1764 * pointers/counters; it wouldn't gain us anything, 1765 * and would waste cycles. 1766 */ 1767 if (m != NULL) { 1768 struct mbuf *m_new = NULL; 1769 1770 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1771 if (m_new == NULL) { 1772 printf("al%d: no memory for tx list", sc->al_unit); 1773 return(1); 1774 } 1775 if (m_head->m_pkthdr.len > MHLEN) { 1776 MCLGET(m_new, M_DONTWAIT); 1777 if (!(m_new->m_flags & M_EXT)) { 1778 m_freem(m_new); 1779 printf("al%d: no memory for tx list", 1780 sc->al_unit); 1781 return(1); 1782 } 1783 } 1784 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1785 mtod(m_new, caddr_t)); 1786 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1787 m_freem(m_head); 1788 m_head = m_new; 1789 f = &c->al_ptr->al_frag[0]; 1790 f->al_status = 0; 1791 f->al_data = vtophys(mtod(m_new, caddr_t)); 1792 f->al_ctl = total_len = m_new->m_len; 1793 f->al_ctl |= AL_TXCTL_TLINK|AL_TXCTL_FIRSTFRAG; 1794 frag = 1; 1795 } 1796 1797 c->al_mbuf = m_head; 1798 c->al_lastdesc = frag - 1; 1799 AL_TXCTL(c) |= AL_TXCTL_LASTFRAG|AL_TXCTL_FINT; 1800 AL_TXNEXT(c) = vtophys(&c->al_nextdesc->al_ptr->al_frag[0]); 1801 return(0); 1802 } 1803 1804 /* 1805 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1806 * to the mbuf data regions directly in the transmit lists. We also save a 1807 * copy of the pointers since the transmit list fragment pointers are 1808 * physical addresses. 1809 */ 1810 1811 static void al_start(ifp) 1812 struct ifnet *ifp; 1813 { 1814 struct al_softc *sc; 1815 struct mbuf *m_head = NULL; 1816 struct al_chain *cur_tx = NULL, *start_tx; 1817 1818 sc = ifp->if_softc; 1819 1820 if (ifp->if_flags & IFF_OACTIVE) 1821 return; 1822 1823 if (sc->al_autoneg) { 1824 sc->al_tx_pend = 1; 1825 return; 1826 } 1827 1828 /* 1829 * Check for an available queue slot. If there are none, 1830 * punt. 1831 */ 1832 if (sc->al_cdata.al_tx_free->al_mbuf != NULL) { 1833 ifp->if_flags |= IFF_OACTIVE; 1834 return; 1835 } 1836 1837 start_tx = sc->al_cdata.al_tx_free; 1838 1839 while(sc->al_cdata.al_tx_free->al_mbuf == NULL) { 1840 IF_DEQUEUE(&ifp->if_snd, m_head); 1841 if (m_head == NULL) 1842 break; 1843 1844 /* Pick a descriptor off the free list. */ 1845 cur_tx = sc->al_cdata.al_tx_free; 1846 sc->al_cdata.al_tx_free = cur_tx->al_nextdesc; 1847 1848 /* Pack the data into the descriptor. */ 1849 al_encap(sc, cur_tx, m_head); 1850 1851 #if NBPFILTER > 0 1852 /* 1853 * If there's a BPF listener, bounce a copy of this frame 1854 * to him. 1855 */ 1856 if (ifp->if_bpf) 1857 bpf_mtap(ifp, cur_tx->al_mbuf); 1858 #endif 1859 AL_TXOWN(cur_tx) = AL_TXSTAT_OWN; 1860 CSR_WRITE_4(sc, AL_TXSTART, 0xFFFFFFFF); 1861 #ifdef AL_TX_STALL_WAR 1862 /* 1863 * Work around some strange behavior in the Comet. For 1864 * some reason, the transmitter will sometimes wedge if 1865 * we queue up a descriptor chain that wraps from the end 1866 * of the transmit list back to the beginning. If we reach 1867 * the end of the list and still have more packets to queue, 1868 * don't queue them now: end the transmit session here and 1869 * then wait until it finishes before sending the other 1870 * packets. 1871 */ 1872 if (cur_tx == &sc->al_cdata.al_tx_chain[AL_TX_LIST_CNT - 1]) { 1873 ifp->if_flags |= IFF_OACTIVE; 1874 break; 1875 } 1876 #endif 1877 } 1878 1879 sc->al_cdata.al_tx_tail = cur_tx; 1880 if (sc->al_cdata.al_tx_head == NULL) 1881 sc->al_cdata.al_tx_head = start_tx; 1882 1883 /* 1884 * Set a timeout in case the chip goes out to lunch. 1885 */ 1886 ifp->if_timer = 5; 1887 1888 return; 1889 } 1890 1891 static void al_init(xsc) 1892 void *xsc; 1893 { 1894 struct al_softc *sc = xsc; 1895 struct ifnet *ifp = &sc->arpcom.ac_if; 1896 u_int16_t phy_bmcr = 0; 1897 int s; 1898 1899 if (sc->al_autoneg) 1900 return; 1901 1902 s = splimp(); 1903 1904 if (sc->al_pinfo != NULL) 1905 phy_bmcr = al_phy_readreg(sc, PHY_BMCR); 1906 1907 /* 1908 * Cancel pending I/O and free all RX/TX buffers. 1909 */ 1910 al_stop(sc); 1911 al_reset(sc); 1912 1913 /* 1914 * Set cache alignment and burst length. 1915 */ 1916 CSR_WRITE_4(sc, AL_BUSCTL, AL_BUSCTL_ARBITRATION); 1917 AL_SETBIT(sc, AL_BUSCTL, AL_BURSTLEN_16LONG); 1918 switch(sc->al_cachesize) { 1919 case 32: 1920 AL_SETBIT(sc, AL_BUSCTL, AL_CACHEALIGN_32LONG); 1921 break; 1922 case 16: 1923 AL_SETBIT(sc, AL_BUSCTL, AL_CACHEALIGN_16LONG); 1924 break; 1925 case 8: 1926 AL_SETBIT(sc, AL_BUSCTL, AL_CACHEALIGN_8LONG); 1927 break; 1928 case 0: 1929 default: 1930 AL_SETBIT(sc, AL_BUSCTL, AL_CACHEALIGN_NONE); 1931 break; 1932 } 1933 1934 AL_CLRBIT(sc, AL_NETCFG, AL_NETCFG_HEARTBEAT); 1935 AL_CLRBIT(sc, AL_NETCFG, AL_NETCFG_STORENFWD); 1936 1937 AL_CLRBIT(sc, AL_NETCFG, AL_NETCFG_TX_THRESH); 1938 1939 if (IFM_SUBTYPE(sc->ifmedia.ifm_media) == IFM_10_T) 1940 AL_SETBIT(sc, AL_NETCFG, AL_TXTHRESH_160BYTES); 1941 else 1942 AL_SETBIT(sc, AL_NETCFG, AL_TXTHRESH_72BYTES); 1943 1944 /* Init our MAC address */ 1945 CSR_WRITE_4(sc, AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1946 CSR_WRITE_4(sc, AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1947 1948 /* Init circular RX list. */ 1949 if (al_list_rx_init(sc) == ENOBUFS) { 1950 printf("al%d: initialization failed: no " 1951 "memory for rx buffers\n", sc->al_unit); 1952 al_stop(sc); 1953 (void)splx(s); 1954 return; 1955 } 1956 1957 /* 1958 * Init tx descriptors. 1959 */ 1960 al_list_tx_init(sc); 1961 1962 /* If we want promiscuous mode, set the allframes bit. */ 1963 if (ifp->if_flags & IFF_PROMISC) { 1964 AL_SETBIT(sc, AL_NETCFG, AL_NETCFG_RX_PROMISC); 1965 } else { 1966 AL_CLRBIT(sc, AL_NETCFG, AL_NETCFG_RX_PROMISC); 1967 } 1968 1969 /* 1970 * Load the multicast filter. 1971 */ 1972 al_setmulti(sc); 1973 1974 /* 1975 * Load the address of the RX list. 1976 */ 1977 CSR_WRITE_4(sc, AL_RXADDR, vtophys(sc->al_cdata.al_rx_head->al_ptr)); 1978 CSR_WRITE_4(sc, AL_TXADDR, vtophys(&sc->al_ldata->al_tx_list[0])); 1979 1980 /* 1981 * Enable interrupts. 1982 */ 1983 CSR_WRITE_4(sc, AL_IMR, AL_INTRS); 1984 CSR_WRITE_4(sc, AL_ISR, 0xFFFFFFFF); 1985 1986 /* Enable receiver and transmitter. */ 1987 AL_SETBIT(sc, AL_NETCFG, AL_NETCFG_TX_ON|AL_NETCFG_RX_ON); 1988 CSR_WRITE_4(sc, AL_RXSTART, 0xFFFFFFFF); 1989 1990 /* Restore state of BMCR */ 1991 if (sc->al_pinfo != NULL) 1992 al_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1993 1994 ifp->if_flags |= IFF_RUNNING; 1995 ifp->if_flags &= ~IFF_OACTIVE; 1996 1997 (void)splx(s); 1998 1999 return; 2000 } 2001 2002 /* 2003 * Set media options. 2004 */ 2005 static int al_ifmedia_upd(ifp) 2006 struct ifnet *ifp; 2007 { 2008 struct al_softc *sc; 2009 struct ifmedia *ifm; 2010 2011 sc = ifp->if_softc; 2012 ifm = &sc->ifmedia; 2013 2014 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2015 return(EINVAL); 2016 2017 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 2018 al_autoneg_mii(sc, AL_FLAG_SCHEDDELAY, 1); 2019 else { 2020 al_setmode_mii(sc, ifm->ifm_media); 2021 } 2022 2023 return(0); 2024 } 2025 2026 /* 2027 * Report current media status. 2028 */ 2029 static void al_ifmedia_sts(ifp, ifmr) 2030 struct ifnet *ifp; 2031 struct ifmediareq *ifmr; 2032 { 2033 struct al_softc *sc; 2034 u_int16_t advert = 0, ability = 0; 2035 2036 sc = ifp->if_softc; 2037 2038 ifmr->ifm_active = IFM_ETHER; 2039 2040 if (!(al_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 2041 if (al_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 2042 ifmr->ifm_active = IFM_ETHER|IFM_100_TX; 2043 else 2044 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2045 if (al_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 2046 ifmr->ifm_active |= IFM_FDX; 2047 else 2048 ifmr->ifm_active |= IFM_HDX; 2049 return; 2050 } 2051 2052 ability = al_phy_readreg(sc, PHY_LPAR); 2053 advert = al_phy_readreg(sc, PHY_ANAR); 2054 if (advert & PHY_ANAR_100BT4 && 2055 ability & PHY_ANAR_100BT4) { 2056 ifmr->ifm_active = IFM_ETHER|IFM_100_T4; 2057 } else if (advert & PHY_ANAR_100BTXFULL && 2058 ability & PHY_ANAR_100BTXFULL) { 2059 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX; 2060 } else if (advert & PHY_ANAR_100BTXHALF && 2061 ability & PHY_ANAR_100BTXHALF) { 2062 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX; 2063 } else if (advert & PHY_ANAR_10BTFULL && 2064 ability & PHY_ANAR_10BTFULL) { 2065 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX; 2066 } else if (advert & PHY_ANAR_10BTHALF && 2067 ability & PHY_ANAR_10BTHALF) { 2068 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX; 2069 } 2070 2071 return; 2072 } 2073 2074 static int al_ioctl(ifp, command, data) 2075 struct ifnet *ifp; 2076 u_long command; 2077 caddr_t data; 2078 { 2079 struct al_softc *sc = ifp->if_softc; 2080 struct ifreq *ifr = (struct ifreq *) data; 2081 int s, error = 0; 2082 2083 s = splimp(); 2084 2085 switch(command) { 2086 case SIOCSIFADDR: 2087 case SIOCGIFADDR: 2088 case SIOCSIFMTU: 2089 error = ether_ioctl(ifp, command, data); 2090 break; 2091 case SIOCSIFFLAGS: 2092 if (ifp->if_flags & IFF_UP) { 2093 al_init(sc); 2094 } else { 2095 if (ifp->if_flags & IFF_RUNNING) 2096 al_stop(sc); 2097 } 2098 error = 0; 2099 break; 2100 case SIOCADDMULTI: 2101 case SIOCDELMULTI: 2102 al_setmulti(sc); 2103 error = 0; 2104 break; 2105 case SIOCGIFMEDIA: 2106 case SIOCSIFMEDIA: 2107 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2108 break; 2109 default: 2110 error = EINVAL; 2111 break; 2112 } 2113 2114 (void)splx(s); 2115 2116 return(error); 2117 } 2118 2119 static void al_watchdog(ifp) 2120 struct ifnet *ifp; 2121 { 2122 struct al_softc *sc; 2123 2124 sc = ifp->if_softc; 2125 2126 if (sc->al_autoneg) { 2127 al_autoneg_mii(sc, AL_FLAG_DELAYTIMEO, 1); 2128 return; 2129 } 2130 2131 ifp->if_oerrors++; 2132 printf("al%d: watchdog timeout\n", sc->al_unit); 2133 2134 if (sc->al_pinfo != NULL) { 2135 if (!(al_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 2136 printf("al%d: no carrier - transceiver " 2137 "cable problem?\n", sc->al_unit); 2138 } 2139 2140 al_stop(sc); 2141 al_reset(sc); 2142 al_init(sc); 2143 2144 if (ifp->if_snd.ifq_head != NULL) 2145 al_start(ifp); 2146 2147 return; 2148 } 2149 2150 /* 2151 * Stop the adapter and free any mbufs allocated to the 2152 * RX and TX lists. 2153 */ 2154 static void al_stop(sc) 2155 struct al_softc *sc; 2156 { 2157 register int i; 2158 struct ifnet *ifp; 2159 2160 ifp = &sc->arpcom.ac_if; 2161 ifp->if_timer = 0; 2162 2163 AL_CLRBIT(sc, AL_NETCFG, (AL_NETCFG_RX_ON|AL_NETCFG_TX_ON)); 2164 CSR_WRITE_4(sc, AL_IMR, 0x00000000); 2165 CSR_WRITE_4(sc, AL_TXADDR, 0x00000000); 2166 CSR_WRITE_4(sc, AL_RXADDR, 0x00000000); 2167 2168 /* 2169 * Free data in the RX lists. 2170 */ 2171 for (i = 0; i < AL_RX_LIST_CNT; i++) { 2172 if (sc->al_cdata.al_rx_chain[i].al_mbuf != NULL) { 2173 m_freem(sc->al_cdata.al_rx_chain[i].al_mbuf); 2174 sc->al_cdata.al_rx_chain[i].al_mbuf = NULL; 2175 } 2176 } 2177 bzero((char *)&sc->al_ldata->al_rx_list, 2178 sizeof(sc->al_ldata->al_rx_list)); 2179 2180 /* 2181 * Free the TX list buffers. 2182 */ 2183 for (i = 0; i < AL_TX_LIST_CNT; i++) { 2184 if (sc->al_cdata.al_tx_chain[i].al_mbuf != NULL) { 2185 m_freem(sc->al_cdata.al_tx_chain[i].al_mbuf); 2186 sc->al_cdata.al_tx_chain[i].al_mbuf = NULL; 2187 } 2188 } 2189 2190 bzero((char *)&sc->al_ldata->al_tx_list, 2191 sizeof(sc->al_ldata->al_tx_list)); 2192 2193 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2194 2195 return; 2196 } 2197 2198 /* 2199 * Stop all chip I/O so that the kernel's probe routines don't 2200 * get confused by errant DMAs when rebooting. 2201 */ 2202 static void al_shutdown(howto, arg) 2203 int howto; 2204 void *arg; 2205 { 2206 struct al_softc *sc = (struct al_softc *)arg; 2207 2208 al_stop(sc); 2209 2210 return; 2211 } 2212 2213 static struct pci_device al_device = { 2214 "al", 2215 al_probe, 2216 al_attach, 2217 &al_count, 2218 NULL 2219 }; 2220 DATA_SET(pcidevice_set, al_device);
Cache object: cfd547144285d171c41ddaaf5aa63e79
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