FreeBSD/Linux Kernel Cross Reference
sys/pci/if_axreg.h
1 /*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD$
33 */
34
35 /*
36 * ASIX register definitions.
37 */
38
39 #define AX_BUSCTL 0x00 /* bus control */
40 #define AX_TXSTART 0x08 /* tx start demand */
41 #define AX_RXSTART 0x10 /* rx start demand */
42 #define AX_RXADDR 0x18 /* rx descriptor list start addr */
43 #define AX_TXADDR 0x20 /* tx descriptor list start addr */
44 #define AX_ISR 0x28 /* interrupt status register */
45 #define AX_NETCFG 0x30 /* network config register */
46 #define AX_IMR 0x38 /* interrupt mask */
47 #define AX_FRAMESDISCARDED 0x40 /* # of discarded frames */
48 #define AX_SIO 0x48 /* MII and ROM/EEPROM access */
49 #define AX_RESERVED 0x50
50 #define AX_GENTIMER 0x58 /* general timer */
51 #define AX_GENPORT 0x60 /* general purpose port */
52 #define AX_FILTIDX 0x68 /* RX filter index */
53 #define AX_FILTDATA 0x70 /* RX filter data */
54
55 /*
56 * Bus control bits.
57 */
58 #define AX_BUSCTL_RESET 0x00000001
59 #define AX_BUSCTL_ARBITRATION 0x00000002
60 #define AX_BUSCTL_BIGENDIAN 0x00000080
61 #define AX_BUSCTL_BURSTLEN 0x00003F00
62 #define AX_BUSCTL_BUF_BIGENDIAN 0x00100000
63 #define AX_BISCTL_READMULTI 0x00200000
64
65 #define AX_BURSTLEN_UNLIMIT 0x00000000
66 #define AX_BURSTLEN_1LONG 0x00000100
67 #define AX_BURSTLEN_2LONG 0x00000200
68 #define AX_BURSTLEN_4LONG 0x00000400
69 #define AX_BURSTLEN_8LONG 0x00000800
70 #define AX_BURSTLEN_16LONG 0x00001000
71 #define AX_BURSTLEN_32LONG 0x00002000
72
73 #define AX_BUSCTL_CONFIG (AX_BUSCTL_ARBITRATION|AX_BURSTLEN_8LONG|AX_BURSTLEN_8LONG)
74
75 /*
76 * Interrupt status bits.
77 */
78 #define AX_ISR_TX_OK 0x00000001
79 #define AX_ISR_TX_IDLE 0x00000002
80 #define AX_ISR_TX_NOBUF 0x00000004
81 #define AX_ISR_TX_JABBERTIMEO 0x00000008
82 #define AX_ISR_TX_UNDERRUN 0x00000020
83 #define AX_ISR_RX_OK 0x00000040
84 #define AX_ISR_RX_NOBUF 0x00000080
85 #define AX_ISR_RX_IDLE 0x00000100
86 #define AX_ISR_RX_WATDOGTIMEO 0x00000200
87 #define AX_ISR_TX_EARLY 0x00000400
88 #define AX_ISR_TIMER_EXPIRED 0x00000800
89 #define AX_ISR_BUS_ERR 0x00002000
90 #define AX_ISR_ABNORMAL 0x00008000
91 #define AX_ISR_NORMAL 0x00010000
92 #define AX_ISR_RX_STATE 0x000E0000
93 #define AX_ISR_TX_STATE 0x00700000
94 #define AX_ISR_BUSERRTYPE 0x03800000
95
96 #define AX_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
97 #define AX_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
98 #define AX_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
99 #define AX_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
100 #define AX_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
101 #define AX_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
102 #define AX_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
103 #define AX_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
104
105 #define AX_TXSTATE_RESET 0x00000000 /* 000 - reset */
106 #define AX_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
107 #define AX_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
108 #define AX_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
109 #define AX_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
110 #define AX_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
111 #define AX_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
112 #define AX_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
113
114 /*
115 * Network config bits.
116 */
117 #define AX_NETCFG_LINKSTAT_PCS 0x00000001
118 #define AX_NETCFG_RX_ON 0x00000002
119 #define AX_NETCFG_RX_BADFRAMES 0x00000008
120 #define AX_NETCFG_RX_PROMISC 0x00000040
121 #define AX_NETCFG_RX_ALLMULTI 0x00000080
122 #define AX_NETCFG_RX_BROAD 0x00000100
123 #define AX_NETCFG_FULLDUPLEX 0x00000200
124 #define AX_NETCFG_LOOPBACK 0x00000C00
125 #define AX_NETCFG_FORCECOLL 0x00001000
126 #define AX_NETCFG_TX_ON 0x00002000
127 #define AX_NETCFG_TX_THRESH 0x0000C000
128 #define AX_NETCFG_PORTSEL 0x00040000 /* 0 == SRL, 1 == MII/SYM */
129 #define AX_NETCFG_HEARTBEAT 0x00080000 /* 0 == ON, 1 == OFF */
130 #define AX_NETCFG_STORENFWD 0x00200000
131 #define AX_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
132 #define AX_NETCFG_PCS 0x00800000
133 #define AX_NETCFG_SCRAMBLER 0x01000000
134 #define AX_NETCFG_RX_ALL 0x40000000
135
136 #define AX_OPMODE_NORM 0x00000000
137 #define AX_OPMODE_INTLOOP 0x00000400
138 #define AX_OPMODE_EXTLOOP 0x00000800
139
140 #define AX_TXTHRESH_72BYTES 0x00000000
141 #define AX_TXTHRESH_96BYTES 0x00004000
142 #define AX_TXTHRESH_128BYTES 0x00008000
143 #define AX_TXTHRESH_160BYTES 0x0000C000
144
145 /*
146 * Interrupt mask bits.
147 */
148 #define AX_IMR_TX_OK 0x00000001
149 #define AX_IMR_TX_IDLE 0x00000002
150 #define AX_IMR_TX_NOBUF 0x00000004
151 #define AX_IMR_TX_JABBERTIMEO 0x00000008
152 #define AX_IMR_TX_UNDERRUN 0x00000020
153 #define AX_IMR_RX_OK 0x00000040
154 #define AX_IMR_RX_NOBUF 0x00000080
155 #define AX_IMR_RX_IDLE 0x00000100
156 #define AX_IMR_RX_WATDOGTIMEO 0x00000200
157 #define AX_IMR_TX_EARLY 0x00000400
158 #define AX_IMR_TIMER_EXPIRED 0x00000800
159 #define AX_IMR_BUS_ERR 0x00002000
160 #define AX_IMR_RX_EARLY 0x00004000
161 #define AX_IMR_ABNORMAL 0x00008000
162 #define AX_IMR_NORMAL 0x00010000
163
164 #define AX_INTRS \
165 (AX_IMR_RX_OK|AX_IMR_TX_OK|AX_IMR_RX_NOBUF|AX_IMR_RX_WATDOGTIMEO|\
166 AX_IMR_TX_NOBUF|AX_IMR_TX_UNDERRUN|AX_IMR_BUS_ERR| \
167 AX_IMR_ABNORMAL|AX_IMR_NORMAL|/*AX_IMR_TX_EARLY*/ \
168 AX_IMR_TX_IDLE|AX_IMR_RX_IDLE)
169
170 /*
171 * Serial I/O (EEPROM/ROM) bits.
172 */
173 #define AX_SIO_EE_CS 0x00000001 /* EEPROM chip select */
174 #define AX_SIO_EE_CLK 0x00000002 /* EEPROM clock */
175 #define AX_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
176 #define AX_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
177 #define AX_SIO_EESEL 0x00000800
178 #define AX_SIO_ROMSEL 0x00001000
179 #define AX_SIO_ROMCTL_WRITE 0x00002000
180 #define AX_SIO_ROMCTL_READ 0x00004000
181 #define AX_SIO_MII_CLK 0x00010000 /* MDIO clock */
182 #define AX_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
183 #define AX_SIO_MII_DIR 0x00040000 /* MDIO dir */
184 #define AX_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
185
186 #define AX_EECMD_WRITE 0x140
187 #define AX_EECMD_READ 0x180
188 #define AX_EECMD_ERASE 0x1c0
189
190 #define AX_EE_NODEADDR_OFFSET 0x70
191 #define AX_EE_NODEADDR 10
192
193 /*
194 * General purpose timer register
195 */
196 #define AX_TIMER_VALUE 0x0000FFFF
197 #define AX_TIMER_CONTINUOUS 0x00010000
198
199 /*
200 * RX Filter Index Register values
201 */
202 #define AX_FILTIDX_PAR0 0x00000000
203 #define AX_FILTIDX_PAR1 0x00000001
204 #define AX_FILTIDX_MAR0 0x00000002
205 #define AX_FILTIDX_MAR1 0x00000003
206
207 /*
208 * ASIX TX/RX list structure.
209 */
210
211 struct ax_desc {
212 volatile u_int32_t ax_status;
213 volatile u_int32_t ax_ctl;
214 volatile u_int32_t ax_ptr1;
215 volatile u_int32_t ax_ptr2;
216 };
217
218 #define ax_data ax_ptr1
219 #define ax_next ax_ptr2
220
221 #define AX_RXSTAT_FIFOOFLOW 0x00000001
222 #define AX_RXSTAT_CRCERR 0x00000002
223 #define AX_RXSTAT_DRIBBLE 0x00000004
224 #define AX_RXSTAT_WATCHDOG 0x00000010
225 #define AX_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
226 #define AX_RXSTAT_COLLSEEN 0x00000040
227 #define AX_RXSTAT_GIANT 0x00000080
228 #define AX_RXSTAT_LASTFRAG 0x00000100
229 #define AX_RXSTAT_FIRSTFRAG 0x00000200
230 #define AX_RXSTAT_MULTICAST 0x00000400
231 #define AX_RXSTAT_RUNT 0x00000800
232 #define AX_RXSTAT_RXTYPE 0x00003000
233 #define AX_RXSTAT_RXERR 0x00008000
234 #define AX_RXSTAT_RXLEN 0x3FFF0000
235 #define AX_RXSTAT_OWN 0x80000000
236
237 #define AX_RXBYTES(x) ((x & AX_RXSTAT_RXLEN) >> 16)
238 #define AX_RXSTAT (AX_RXSTAT_FIRSTFRAG|AX_RXSTAT_LASTFRAG|AX_RXSTAT_OWN)
239
240 #define AX_RXCTL_BUFLEN1 0x00000FFF
241 #define AX_RXCTL_BUFLEN2 0x00FFF000
242 #define AX_RXCTL_RLAST 0x02000000
243
244 #define AX_TXSTAT_DEFER 0x00000001
245 #define AX_TXSTAT_UNDERRUN 0x00000002
246 #define AX_TXSTAT_LINKFAIL 0x00000003
247 #define AX_TXSTAT_COLLCNT 0x00000078
248 #define AX_TXSTAT_SQE 0x00000080
249 #define AX_TXSTAT_EXCESSCOLL 0x00000100
250 #define AX_TXSTAT_LATECOLL 0x00000200
251 #define AX_TXSTAT_NOCARRIER 0x00000400
252 #define AX_TXSTAT_CARRLOST 0x00000800
253 #define AX_TXSTAT_JABTIMEO 0x00004000
254 #define AX_TXSTAT_ERRSUM 0x00008000
255 #define AX_TXSTAT_OWN 0x80000000
256
257 #define AX_TXCTL_BUFLEN1 0x000007FF
258 #define AX_TXCTL_BUFLEN2 0x003FF800
259 #define AX_TXCTL_PAD 0x00800000
260 #define AX_TXCTL_TLAST 0x02000000
261 #define AX_TXCTL_NOCRC 0x04000000
262 #define AX_TXCTL_FIRSTFRAG 0x20000000
263 #define AX_TXCTL_LASTFRAG 0x40000000
264 #define AX_TXCTL_FINT 0x80000000
265
266 #define AX_MAXFRAGS 16
267 #define AX_RX_LIST_CNT 64
268 #define AX_TX_LIST_CNT 128
269 #define AX_MIN_FRAMELEN 60
270
271 /*
272 * A tx 'super descriptor' is actually 16 regular descriptors
273 * back to back.
274 */
275 struct ax_txdesc {
276 volatile struct ax_desc ax_frag[AX_MAXFRAGS];
277 };
278
279 #define AX_TXNEXT(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_next
280 #define AX_TXSTATUS(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_status
281 #define AX_TXCTL(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_ctl
282 #define AX_TXDATA(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_data
283
284 #define AX_TXOWN(x) x->ax_ptr->ax_frag[0].ax_status
285
286 #define AX_UNSENT 0x12341234
287
288 struct ax_list_data {
289 volatile struct ax_desc ax_rx_list[AX_RX_LIST_CNT];
290 volatile struct ax_txdesc ax_tx_list[AX_TX_LIST_CNT];
291 };
292
293 struct ax_chain {
294 volatile struct ax_txdesc *ax_ptr;
295 struct mbuf *ax_mbuf;
296 struct ax_chain *ax_nextdesc;
297 u_int8_t ax_lastdesc;
298 };
299
300 struct ax_chain_onefrag {
301 volatile struct ax_desc *ax_ptr;
302 struct mbuf *ax_mbuf;
303 struct ax_chain_onefrag *ax_nextdesc;
304 };
305
306 struct ax_chain_data {
307 struct ax_chain_onefrag ax_rx_chain[AX_RX_LIST_CNT];
308 struct ax_chain ax_tx_chain[AX_TX_LIST_CNT];
309
310 struct ax_chain_onefrag *ax_rx_head;
311
312 struct ax_chain *ax_tx_head;
313 struct ax_chain *ax_tx_tail;
314 struct ax_chain *ax_tx_free;
315 };
316
317 struct ax_type {
318 u_int16_t ax_vid;
319 u_int16_t ax_did;
320 char *ax_name;
321 };
322
323 struct ax_mii_frame {
324 u_int8_t mii_stdelim;
325 u_int8_t mii_opcode;
326 u_int8_t mii_phyaddr;
327 u_int8_t mii_regaddr;
328 u_int8_t mii_turnaround;
329 u_int16_t mii_data;
330 };
331
332 /*
333 * MII constants
334 */
335 #define AX_MII_STARTDELIM 0x01
336 #define AX_MII_READOP 0x02
337 #define AX_MII_WRITEOP 0x01
338 #define AX_MII_TURNAROUND 0x02
339
340 #define AX_FLAG_FORCEDELAY 1
341 #define AX_FLAG_SCHEDDELAY 2
342 #define AX_FLAG_DELAYTIMEO 3
343
344 struct ax_softc {
345 struct arpcom arpcom; /* interface info */
346 struct ifmedia ifmedia; /* media info */
347 bus_space_handle_t ax_bhandle; /* bus space handle */
348 bus_space_tag_t ax_btag; /* bus space tag */
349 struct ax_type *ax_info; /* ASIX adapter info */
350 struct ax_type *ax_pinfo; /* phy info */
351 u_int8_t ax_unit; /* interface number */
352 u_int8_t ax_type;
353 u_int8_t ax_phy_addr; /* PHY address */
354 u_int8_t ax_tx_pend; /* TX pending */
355 u_int8_t ax_want_auto;
356 u_int8_t ax_autoneg;
357 caddr_t ax_ldata_ptr;
358 struct ax_list_data *ax_ldata;
359 struct ax_chain_data ax_cdata;
360 };
361
362 /*
363 * register space access macros
364 */
365 #define CSR_WRITE_4(sc, reg, val) \
366 bus_space_write_4(sc->ax_btag, sc->ax_bhandle, reg, val)
367 #define CSR_WRITE_2(sc, reg, val) \
368 bus_space_write_2(sc->ax_btag, sc->ax_bbhandle, reg, val)
369 #define CSR_WRITE_1(sc, reg, val) \
370 bus_space_write_1(sc->ax_btag, sc->ax_bhandle, reg, val)
371
372 #define CSR_READ_4(sc, reg) \
373 bus_space_read_4(sc->ax_btag, sc->ax_bhandle, reg)
374 #define CSR_READ_2(sc, reg) \
375 bus_space_read_2(sc->ax_btag, sc->ax_bhandle, reg)
376 #define CSR_READ_1(sc, reg) \
377 bus_space_read_1(sc->ax_btag, sc->ax_bhandle, reg)
378
379 #define AX_TIMEOUT 1000
380
381 /*
382 * General constants that are fun to know.
383 *
384 * ASIX PCI vendor ID
385 */
386 #define AX_VENDORID 0x125B
387
388 /*
389 * ASIX device IDs.
390 */
391 #define AX_DEVICEID_AX88140A 0x1400
392
393 /*
394 * The ASIX AX88140 and ASIX AX88141 have the same vendor and
395 * device IDs but different revision values.
396 */
397 #define AX_REVISION_88140 0x00
398 #define AX_REVISION_88141 0x10
399
400 /*
401 * Texas Instruments PHY identifiers
402 */
403 #define TI_PHY_VENDORID 0x4000
404 #define TI_PHY_10BT 0x501F
405 #define TI_PHY_100VGPMI 0x502F
406
407 /*
408 * These ID values are for the NS DP83840A 10/100 PHY
409 */
410 #define NS_PHY_VENDORID 0x2000
411 #define NS_PHY_83840A 0x5C0F
412
413 /*
414 * Level 1 10/100 PHY
415 */
416 #define LEVEL1_PHY_VENDORID 0x7810
417 #define LEVEL1_PHY_LXT970 0x000F
418
419 /*
420 * Intel 82555 10/100 PHY
421 */
422 #define INTEL_PHY_VENDORID 0x0A28
423 #define INTEL_PHY_82555 0x015F
424
425 /*
426 * SEEQ 80220 10/100 PHY
427 */
428 #define SEEQ_PHY_VENDORID 0x0016
429 #define SEEQ_PHY_80220 0xF83F
430
431
432 /*
433 * PCI low memory base and low I/O base register, and
434 * other PCI registers.
435 */
436
437 #define AX_PCI_VENDOR_ID 0x00
438 #define AX_PCI_DEVICE_ID 0x02
439 #define AX_PCI_COMMAND 0x04
440 #define AX_PCI_STATUS 0x06
441 #define AX_PCI_REVID 0x08
442 #define AX_PCI_CLASSCODE 0x09
443 #define AX_PCI_LATENCY_TIMER 0x0D
444 #define AX_PCI_HEADER_TYPE 0x0E
445 #define AX_PCI_LOIO 0x10
446 #define AX_PCI_LOMEM 0x14
447 #define AX_PCI_BIOSROM 0x30
448 #define AX_PCI_INTLINE 0x3C
449 #define AX_PCI_INTPIN 0x3D
450 #define AX_PCI_MINGNT 0x3E
451 #define AX_PCI_MINLAT 0x0F
452 #define AX_PCI_RESETOPT 0x48
453 #define AX_PCI_EEPROM_DATA 0x4C
454
455 /* power management registers */
456 #define AX_PCI_CAPID 0x44 /* 8 bits */
457 #define AX_PCI_NEXTPTR 0x45 /* 8 bits */
458 #define AX_PCI_PWRMGMTCAP 0x46 /* 16 bits */
459 #define AX_PCI_PWRMGMTCTRL 0x48 /* 16 bits */
460
461 #define AX_PSTATE_MASK 0x0003
462 #define AX_PSTATE_D0 0x0000
463 #define AX_PSTATE_D1 0x0001
464 #define AX_PSTATE_D2 0x0002
465 #define AX_PSTATE_D3 0x0003
466 #define AX_PME_EN 0x0010
467 #define AX_PME_STATUS 0x8000
468
469 #define PHY_UNKNOWN 6
470
471 #define AX_PHYADDR_MIN 0x00
472 #define AX_PHYADDR_MAX 0x1F
473
474 #define PHY_BMCR 0x00
475 #define PHY_BMSR 0x01
476 #define PHY_VENID 0x02
477 #define PHY_DEVID 0x03
478 #define PHY_ANAR 0x04
479 #define PHY_LPAR 0x05
480 #define PHY_ANEXP 0x06
481
482 #define PHY_ANAR_NEXTPAGE 0x8000
483 #define PHY_ANAR_RSVD0 0x4000
484 #define PHY_ANAR_TLRFLT 0x2000
485 #define PHY_ANAR_RSVD1 0x1000
486 #define PHY_ANAR_RSVD2 0x0800
487 #define PHY_ANAR_RSVD3 0x0400
488 #define PHY_ANAR_100BT4 0x0200
489 #define PHY_ANAR_100BTXFULL 0x0100
490 #define PHY_ANAR_100BTXHALF 0x0080
491 #define PHY_ANAR_10BTFULL 0x0040
492 #define PHY_ANAR_10BTHALF 0x0020
493 #define PHY_ANAR_PROTO4 0x0010
494 #define PHY_ANAR_PROTO3 0x0008
495 #define PHY_ANAR_PROTO2 0x0004
496 #define PHY_ANAR_PROTO1 0x0002
497 #define PHY_ANAR_PROTO0 0x0001
498
499 /*
500 * These are the register definitions for the PHY (physical layer
501 * interface chip).
502 */
503 /*
504 * PHY BMCR Basic Mode Control Register
505 */
506 #define PHY_BMCR_RESET 0x8000
507 #define PHY_BMCR_LOOPBK 0x4000
508 #define PHY_BMCR_SPEEDSEL 0x2000
509 #define PHY_BMCR_AUTONEGENBL 0x1000
510 #define PHY_BMCR_RSVD0 0x0800 /* write as zero */
511 #define PHY_BMCR_ISOLATE 0x0400
512 #define PHY_BMCR_AUTONEGRSTR 0x0200
513 #define PHY_BMCR_DUPLEX 0x0100
514 #define PHY_BMCR_COLLTEST 0x0080
515 #define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
516 #define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
517 #define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
518 #define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
519 #define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
520 #define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
521 #define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
522 /*
523 * RESET: 1 == software reset, 0 == normal operation
524 * Resets status and control registers to default values.
525 * Relatches all hardware config values.
526 *
527 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
528 *
529 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
530 * Link speed is selected byt his bit or if auto-negotiation if bit
531 * 12 (AUTONEGENBL) is set (in which case the value of this register
532 * is ignored).
533 *
534 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
535 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
536 * determine speed and mode. Should be cleared and then set if PHY configured
537 * for no autoneg on startup.
538 *
539 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
540 *
541 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
542 *
543 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
544 *
545 * COLLTEST: 1 == collision test enabled, 0 == normal operation
546 */
547
548 /*
549 * PHY, BMSR Basic Mode Status Register
550 */
551 #define PHY_BMSR_100BT4 0x8000
552 #define PHY_BMSR_100BTXFULL 0x4000
553 #define PHY_BMSR_100BTXHALF 0x2000
554 #define PHY_BMSR_10BTFULL 0x1000
555 #define PHY_BMSR_10BTHALF 0x0800
556 #define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
557 #define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
558 #define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
559 #define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
560 #define PHY_BMSR_MFPRESUP 0x0040
561 #define PHY_BMSR_AUTONEGCOMP 0x0020
562 #define PHY_BMSR_REMFAULT 0x0010
563 #define PHY_BMSR_CANAUTONEG 0x0008
564 #define PHY_BMSR_LINKSTAT 0x0004
565 #define PHY_BMSR_JABBER 0x0002
566 #define PHY_BMSR_EXTENDED 0x0001
567
568 #ifdef __alpha__
569 #undef vtophys
570 #define vtophys(va) (pmap_kextract(((vm_offset_t) (va))) \
571 + 1*1024*1024*1024)
572 #endif
Cache object: dbb0748217c5f8d66775b83618df122f
|