Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/pci/if_dc.c
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Conexant LANfinity (www.conexant.com) 49 * 50 * Datasheets for the 21143 are available at developer.intel.com. 51 * Datasheets for the clone parts can be found at their respective sites. 52 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 53 * The PNIC II is essentially a Macronix 98715A chip; the only difference 54 * worth noting is that its multicast hash table is only 128 bits wide 55 * instead of 512. 56 * 57 * Written by Bill Paul <wpaul@ee.columbia.edu> 58 * Electrical Engineering Department 59 * Columbia University, New York City 60 */ 61 62 /* 63 * The Intel 21143 is the successor to the DEC 21140. It is basically 64 * the same as the 21140 but with a few new features. The 21143 supports 65 * three kinds of media attachments: 66 * 67 * o MII port, for 10Mbps and 100Mbps support and NWAY 68 * autonegotiation provided by an external PHY. 69 * o SYM port, for symbol mode 100Mbps support. 70 * o 10baseT port. 71 * o AUI/BNC port. 72 * 73 * The 100Mbps SYM port and 10baseT port can be used together in 74 * combination with the internal NWAY support to create a 10/100 75 * autosensing configuration. 76 * 77 * Note that not all tulip workalikes are handled in this driver: we only 78 * deal with those which are relatively well behaved. The Winbond is 79 * handled separately due to its different register offsets and the 80 * special handling needed for its various bugs. The PNIC is handled 81 * here, but I'm not thrilled about it. 82 * 83 * All of the workalike chips use some form of MII transceiver support 84 * with the exception of the Macronix chips, which also have a SYM port. 85 * The ASIX AX88140A is also documented to have a SYM port, but all 86 * the cards I've seen use an MII transceiver, probably because the 87 * AX88140A doesn't support internal NWAY. 88 */ 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/sysctl.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/ethernet.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_types.h> 105 #include <net/if_vlan_var.h> 106 107 #include <net/bpf.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 #include <machine/clock.h> /* for DELAY */ 112 #include <machine/bus_pio.h> 113 #include <machine/bus_memio.h> 114 #include <machine/bus.h> 115 #include <machine/resource.h> 116 #include <sys/bus.h> 117 #include <sys/rman.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 122 #include <pci/pcireg.h> 123 #include <pci/pcivar.h> 124 125 #define DC_USEIOSPACE 126 #ifdef __alpha__ 127 #define SRM_MEDIA 128 #endif 129 130 #include <pci/if_dcreg.h> 131 132 /* "controller miibus0" required. See GENERIC if you get errors here. */ 133 #include "miibus_if.h" 134 135 #ifndef lint 136 static const char rcsid[] = 137 "$FreeBSD$"; 138 #endif 139 140 /* 141 * Various supported device vendors/types and their names. 142 */ 143 static struct dc_type dc_devs[] = { 144 { DC_VENDORID_DEC, DC_DEVICEID_21143, 145 "Intel 21143 10/100BaseTX" }, 146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 147 "Davicom DM9009 10/100BaseTX" }, 148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 149 "Davicom DM9100 10/100BaseTX" }, 150 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 151 "Davicom DM9102 10/100BaseTX" }, 152 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 153 "Davicom DM9102A 10/100BaseTX" }, 154 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 155 "ADMtek AL981 10/100BaseTX" }, 156 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 157 "ADMtek AN985 10/100BaseTX" }, 158 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 159 "ADMtek ADM9511 10/100BaseTX" }, 160 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 161 "ADMtek ADM9513 10/100BaseTX" }, 162 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 163 "ASIX AX88140A 10/100BaseTX" }, 164 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 165 "ASIX AX88141 10/100BaseTX" }, 166 { DC_VENDORID_MX, DC_DEVICEID_98713, 167 "Macronix 98713 10/100BaseTX" }, 168 { DC_VENDORID_MX, DC_DEVICEID_98713, 169 "Macronix 98713A 10/100BaseTX" }, 170 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 171 "Compex RL100-TX 10/100BaseTX" }, 172 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 173 "Compex RL100-TX 10/100BaseTX" }, 174 { DC_VENDORID_MX, DC_DEVICEID_987x5, 175 "Macronix 98715/98715A 10/100BaseTX" }, 176 { DC_VENDORID_MX, DC_DEVICEID_987x5, 177 "Macronix 98715AEC-C 10/100BaseTX" }, 178 { DC_VENDORID_MX, DC_DEVICEID_987x5, 179 "Macronix 98725 10/100BaseTX" }, 180 { DC_VENDORID_MX, DC_DEVICEID_98727, 181 "Macronix 98727/98732 10/100BaseTX" }, 182 { DC_VENDORID_LO, DC_DEVICEID_82C115, 183 "LC82C115 PNIC II 10/100BaseTX" }, 184 { DC_VENDORID_LO, DC_DEVICEID_82C168, 185 "82c168 PNIC 10/100BaseTX" }, 186 { DC_VENDORID_LO, DC_DEVICEID_82C168, 187 "82c169 PNIC 10/100BaseTX" }, 188 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 189 "Accton EN1217 10/100BaseTX" }, 190 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 191 "Accton EN2242 MiniPCI 10/100BaseTX" }, 192 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 193 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 194 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 195 "3Com OfficeConnect 10/100B" }, 196 { 0, 0, NULL } 197 }; 198 199 static int dc_probe __P((device_t)); 200 static int dc_attach __P((device_t)); 201 static int dc_detach __P((device_t)); 202 static int dc_suspend __P((device_t)); 203 static int dc_resume __P((device_t)); 204 static void dc_acpi __P((device_t)); 205 static struct dc_type *dc_devtype __P((device_t)); 206 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 207 static int dc_encap __P((struct dc_softc *, struct mbuf **, 208 u_int32_t *)); 209 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 210 static int dc_rx_resync __P((struct dc_softc *)); 211 static void dc_rxeof __P((struct dc_softc *)); 212 static void dc_txeof __P((struct dc_softc *)); 213 static void dc_tick __P((void *)); 214 static void dc_tx_underrun __P((struct dc_softc *)); 215 static void dc_intr __P((void *)); 216 static void dc_start __P((struct ifnet *)); 217 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 218 static void dc_init __P((void *)); 219 static void dc_stop __P((struct dc_softc *)); 220 static void dc_watchdog __P((struct ifnet *)); 221 static void dc_shutdown __P((device_t)); 222 static int dc_ifmedia_upd __P((struct ifnet *)); 223 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 224 225 static void dc_delay __P((struct dc_softc *)); 226 static void dc_eeprom_idle __P((struct dc_softc *)); 227 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 228 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 229 static void dc_eeprom_getword_pnic 230 __P((struct dc_softc *, int, u_int16_t *)); 231 static void dc_eeprom_width __P((struct dc_softc *)); 232 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 233 int, int)); 234 235 static void dc_mii_writebit __P((struct dc_softc *, int)); 236 static int dc_mii_readbit __P((struct dc_softc *)); 237 static void dc_mii_sync __P((struct dc_softc *)); 238 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 239 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 240 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 241 static int dc_miibus_readreg __P((device_t, int, int)); 242 static int dc_miibus_writereg __P((device_t, int, int, int)); 243 static void dc_miibus_statchg __P((device_t)); 244 static void dc_miibus_mediainit __P((device_t)); 245 246 static void dc_setcfg __P((struct dc_softc *, int)); 247 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 248 static u_int32_t dc_crc_be __P((caddr_t)); 249 static void dc_setfilt_21143 __P((struct dc_softc *)); 250 static void dc_setfilt_asix __P((struct dc_softc *)); 251 static void dc_setfilt_admtek __P((struct dc_softc *)); 252 253 static void dc_setfilt __P((struct dc_softc *)); 254 255 static void dc_reset __P((struct dc_softc *)); 256 static int dc_list_rx_init __P((struct dc_softc *)); 257 static int dc_list_tx_init __P((struct dc_softc *)); 258 259 static void dc_read_srom __P((struct dc_softc *, int)); 260 static void dc_parse_21143_srom __P((struct dc_softc *)); 261 static void dc_decode_leaf_sia __P((struct dc_softc *, 262 struct dc_eblock_sia *)); 263 static void dc_decode_leaf_mii __P((struct dc_softc *, 264 struct dc_eblock_mii *)); 265 static void dc_decode_leaf_sym __P((struct dc_softc *, 266 struct dc_eblock_sym *)); 267 static void dc_apply_fixup __P((struct dc_softc *, int)); 268 269 #ifdef DC_USEIOSPACE 270 #define DC_RES SYS_RES_IOPORT 271 #define DC_RID DC_PCI_CFBIO 272 #else 273 #define DC_RES SYS_RES_MEMORY 274 #define DC_RID DC_PCI_CFBMA 275 #endif 276 277 static device_method_t dc_methods[] = { 278 /* Device interface */ 279 DEVMETHOD(device_probe, dc_probe), 280 DEVMETHOD(device_attach, dc_attach), 281 DEVMETHOD(device_detach, dc_detach), 282 DEVMETHOD(device_suspend, dc_suspend), 283 DEVMETHOD(device_resume, dc_resume), 284 DEVMETHOD(device_shutdown, dc_shutdown), 285 286 /* bus interface */ 287 DEVMETHOD(bus_print_child, bus_generic_print_child), 288 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 289 290 /* MII interface */ 291 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 292 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 293 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 294 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 295 296 { 0, 0 } 297 }; 298 299 static driver_t dc_driver = { 300 "dc", 301 dc_methods, 302 sizeof(struct dc_softc) 303 }; 304 305 static devclass_t dc_devclass; 306 307 #ifdef __i386__ 308 static int dc_quick=1; 309 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 310 &dc_quick,0,"do not mdevget in dc driver"); 311 #endif 312 313 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 314 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 315 316 #define DC_SETBIT(sc, reg, x) \ 317 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 318 319 #define DC_CLRBIT(sc, reg, x) \ 320 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 321 322 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 323 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 324 325 static void dc_delay(sc) 326 struct dc_softc *sc; 327 { 328 int idx; 329 330 for (idx = (300 / 33) + 1; idx > 0; idx--) 331 CSR_READ_4(sc, DC_BUSCTL); 332 } 333 334 static void dc_eeprom_width(sc) 335 struct dc_softc *sc; 336 { 337 int i; 338 339 /* Force EEPROM to idle state. */ 340 dc_eeprom_idle(sc); 341 342 /* Enter EEPROM access mode. */ 343 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 344 dc_delay(sc); 345 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 346 dc_delay(sc); 347 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 348 dc_delay(sc); 349 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 350 dc_delay(sc); 351 352 for (i = 3; i--;) { 353 if (6 & (1 << i)) 354 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 355 else 356 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 357 dc_delay(sc); 358 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 359 dc_delay(sc); 360 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 361 dc_delay(sc); 362 } 363 364 for (i = 1; i <= 12; i++) { 365 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 366 dc_delay(sc); 367 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 368 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 369 dc_delay(sc); 370 break; 371 } 372 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 373 dc_delay(sc); 374 } 375 376 /* Turn off EEPROM access mode. */ 377 dc_eeprom_idle(sc); 378 379 if (i < 4 || i > 12) 380 sc->dc_romwidth = 6; 381 else 382 sc->dc_romwidth = i; 383 384 /* Enter EEPROM access mode. */ 385 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 386 dc_delay(sc); 387 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 388 dc_delay(sc); 389 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 390 dc_delay(sc); 391 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 392 dc_delay(sc); 393 394 /* Turn off EEPROM access mode. */ 395 dc_eeprom_idle(sc); 396 } 397 398 static void dc_eeprom_idle(sc) 399 struct dc_softc *sc; 400 { 401 register int i; 402 403 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 404 dc_delay(sc); 405 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 406 dc_delay(sc); 407 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 408 dc_delay(sc); 409 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 410 dc_delay(sc); 411 412 for (i = 0; i < 25; i++) { 413 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 414 dc_delay(sc); 415 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 416 dc_delay(sc); 417 } 418 419 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 420 dc_delay(sc); 421 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 422 dc_delay(sc); 423 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 424 425 return; 426 } 427 428 /* 429 * Send a read command and address to the EEPROM, check for ACK. 430 */ 431 static void dc_eeprom_putbyte(sc, addr) 432 struct dc_softc *sc; 433 int addr; 434 { 435 register int d, i; 436 437 d = DC_EECMD_READ >> 6; 438 for (i = 3; i--; ) { 439 if (d & (1 << i)) 440 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 441 else 442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 443 dc_delay(sc); 444 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 445 dc_delay(sc); 446 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 447 dc_delay(sc); 448 } 449 450 /* 451 * Feed in each bit and strobe the clock. 452 */ 453 for (i = sc->dc_romwidth; i--;) { 454 if (addr & (1 << i)) { 455 SIO_SET(DC_SIO_EE_DATAIN); 456 } else { 457 SIO_CLR(DC_SIO_EE_DATAIN); 458 } 459 dc_delay(sc); 460 SIO_SET(DC_SIO_EE_CLK); 461 dc_delay(sc); 462 SIO_CLR(DC_SIO_EE_CLK); 463 dc_delay(sc); 464 } 465 466 return; 467 } 468 469 /* 470 * Read a word of data stored in the EEPROM at address 'addr.' 471 * The PNIC 82c168/82c169 has its own non-standard way to read 472 * the EEPROM. 473 */ 474 static void dc_eeprom_getword_pnic(sc, addr, dest) 475 struct dc_softc *sc; 476 int addr; 477 u_int16_t *dest; 478 { 479 register int i; 480 u_int32_t r; 481 482 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 483 484 for (i = 0; i < DC_TIMEOUT; i++) { 485 DELAY(1); 486 r = CSR_READ_4(sc, DC_SIO); 487 if (!(r & DC_PN_SIOCTL_BUSY)) { 488 *dest = (u_int16_t)(r & 0xFFFF); 489 return; 490 } 491 } 492 493 return; 494 } 495 496 /* 497 * Read a word of data stored in the EEPROM at address 'addr.' 498 */ 499 static void dc_eeprom_getword(sc, addr, dest) 500 struct dc_softc *sc; 501 int addr; 502 u_int16_t *dest; 503 { 504 register int i; 505 u_int16_t word = 0; 506 507 /* Force EEPROM to idle state. */ 508 dc_eeprom_idle(sc); 509 510 /* Enter EEPROM access mode. */ 511 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 512 dc_delay(sc); 513 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 514 dc_delay(sc); 515 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 516 dc_delay(sc); 517 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 518 dc_delay(sc); 519 520 /* 521 * Send address of word we want to read. 522 */ 523 dc_eeprom_putbyte(sc, addr); 524 525 /* 526 * Start reading bits from EEPROM. 527 */ 528 for (i = 0x8000; i; i >>= 1) { 529 SIO_SET(DC_SIO_EE_CLK); 530 dc_delay(sc); 531 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 532 word |= i; 533 dc_delay(sc); 534 SIO_CLR(DC_SIO_EE_CLK); 535 dc_delay(sc); 536 } 537 538 /* Turn off EEPROM access mode. */ 539 dc_eeprom_idle(sc); 540 541 *dest = word; 542 543 return; 544 } 545 546 /* 547 * Read a sequence of words from the EEPROM. 548 */ 549 static void dc_read_eeprom(sc, dest, off, cnt, swap) 550 struct dc_softc *sc; 551 caddr_t dest; 552 int off; 553 int cnt; 554 int swap; 555 { 556 int i; 557 u_int16_t word = 0, *ptr; 558 559 for (i = 0; i < cnt; i++) { 560 if (DC_IS_PNIC(sc)) 561 dc_eeprom_getword_pnic(sc, off + i, &word); 562 else 563 dc_eeprom_getword(sc, off + i, &word); 564 ptr = (u_int16_t *)(dest + (i * 2)); 565 if (swap) 566 *ptr = ntohs(word); 567 else 568 *ptr = word; 569 } 570 571 return; 572 } 573 574 /* 575 * The following two routines are taken from the Macronix 98713 576 * Application Notes pp.19-21. 577 */ 578 /* 579 * Write a bit to the MII bus. 580 */ 581 static void dc_mii_writebit(sc, bit) 582 struct dc_softc *sc; 583 int bit; 584 { 585 if (bit) 586 CSR_WRITE_4(sc, DC_SIO, 587 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 588 else 589 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 590 591 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 592 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 593 594 return; 595 } 596 597 /* 598 * Read a bit from the MII bus. 599 */ 600 static int dc_mii_readbit(sc) 601 struct dc_softc *sc; 602 { 603 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 604 CSR_READ_4(sc, DC_SIO); 605 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 606 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 607 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 608 return(1); 609 610 return(0); 611 } 612 613 /* 614 * Sync the PHYs by setting data bit and strobing the clock 32 times. 615 */ 616 static void dc_mii_sync(sc) 617 struct dc_softc *sc; 618 { 619 register int i; 620 621 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 622 623 for (i = 0; i < 32; i++) 624 dc_mii_writebit(sc, 1); 625 626 return; 627 } 628 629 /* 630 * Clock a series of bits through the MII. 631 */ 632 static void dc_mii_send(sc, bits, cnt) 633 struct dc_softc *sc; 634 u_int32_t bits; 635 int cnt; 636 { 637 int i; 638 639 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 640 dc_mii_writebit(sc, bits & i); 641 } 642 643 /* 644 * Read an PHY register through the MII. 645 */ 646 static int dc_mii_readreg(sc, frame) 647 struct dc_softc *sc; 648 struct dc_mii_frame *frame; 649 650 { 651 int i, ack, s; 652 653 s = splimp(); 654 655 /* 656 * Set up frame for RX. 657 */ 658 frame->mii_stdelim = DC_MII_STARTDELIM; 659 frame->mii_opcode = DC_MII_READOP; 660 frame->mii_turnaround = 0; 661 frame->mii_data = 0; 662 663 /* 664 * Sync the PHYs. 665 */ 666 dc_mii_sync(sc); 667 668 /* 669 * Send command/address info. 670 */ 671 dc_mii_send(sc, frame->mii_stdelim, 2); 672 dc_mii_send(sc, frame->mii_opcode, 2); 673 dc_mii_send(sc, frame->mii_phyaddr, 5); 674 dc_mii_send(sc, frame->mii_regaddr, 5); 675 676 #ifdef notdef 677 /* Idle bit */ 678 dc_mii_writebit(sc, 1); 679 dc_mii_writebit(sc, 0); 680 #endif 681 682 /* Check for ack */ 683 ack = dc_mii_readbit(sc); 684 685 /* 686 * Now try reading data bits. If the ack failed, we still 687 * need to clock through 16 cycles to keep the PHY(s) in sync. 688 */ 689 if (ack) { 690 for(i = 0; i < 16; i++) { 691 dc_mii_readbit(sc); 692 } 693 goto fail; 694 } 695 696 for (i = 0x8000; i; i >>= 1) { 697 if (!ack) { 698 if (dc_mii_readbit(sc)) 699 frame->mii_data |= i; 700 } 701 } 702 703 fail: 704 705 dc_mii_writebit(sc, 0); 706 dc_mii_writebit(sc, 0); 707 708 splx(s); 709 710 if (ack) 711 return(1); 712 return(0); 713 } 714 715 /* 716 * Write to a PHY register through the MII. 717 */ 718 static int dc_mii_writereg(sc, frame) 719 struct dc_softc *sc; 720 struct dc_mii_frame *frame; 721 722 { 723 int s; 724 725 s = splimp(); 726 /* 727 * Set up frame for TX. 728 */ 729 730 frame->mii_stdelim = DC_MII_STARTDELIM; 731 frame->mii_opcode = DC_MII_WRITEOP; 732 frame->mii_turnaround = DC_MII_TURNAROUND; 733 734 /* 735 * Sync the PHYs. 736 */ 737 dc_mii_sync(sc); 738 739 dc_mii_send(sc, frame->mii_stdelim, 2); 740 dc_mii_send(sc, frame->mii_opcode, 2); 741 dc_mii_send(sc, frame->mii_phyaddr, 5); 742 dc_mii_send(sc, frame->mii_regaddr, 5); 743 dc_mii_send(sc, frame->mii_turnaround, 2); 744 dc_mii_send(sc, frame->mii_data, 16); 745 746 /* Idle bit. */ 747 dc_mii_writebit(sc, 0); 748 dc_mii_writebit(sc, 0); 749 750 splx(s); 751 752 return(0); 753 } 754 755 static int dc_miibus_readreg(dev, phy, reg) 756 device_t dev; 757 int phy, reg; 758 { 759 struct dc_mii_frame frame; 760 struct dc_softc *sc; 761 int i, rval, phy_reg = 0; 762 763 sc = device_get_softc(dev); 764 bzero((char *)&frame, sizeof(frame)); 765 766 /* 767 * Note: both the AL981 and AN985 have internal PHYs, 768 * however the AL981 provides direct access to the PHY 769 * registers while the AN985 uses a serial MII interface. 770 * The AN985's MII interface is also buggy in that you 771 * can read from any MII address (0 to 31), but only address 1 772 * behaves normally. To deal with both cases, we pretend 773 * that the PHY is at MII address 1. 774 */ 775 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 776 return(0); 777 778 /* 779 * Note: the ukphy probes of the RS7112 report a PHY at 780 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 781 * so we only respond to correct one. 782 */ 783 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 784 return(0); 785 786 if (sc->dc_pmode != DC_PMODE_MII) { 787 if (phy == (MII_NPHY - 1)) { 788 switch(reg) { 789 case MII_BMSR: 790 /* 791 * Fake something to make the probe 792 * code think there's a PHY here. 793 */ 794 return(BMSR_MEDIAMASK); 795 break; 796 case MII_PHYIDR1: 797 if (DC_IS_PNIC(sc)) 798 return(DC_VENDORID_LO); 799 return(DC_VENDORID_DEC); 800 break; 801 case MII_PHYIDR2: 802 if (DC_IS_PNIC(sc)) 803 return(DC_DEVICEID_82C168); 804 return(DC_DEVICEID_21143); 805 break; 806 default: 807 return(0); 808 break; 809 } 810 } else 811 return(0); 812 } 813 814 if (DC_IS_PNIC(sc)) { 815 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 816 (phy << 23) | (reg << 18)); 817 for (i = 0; i < DC_TIMEOUT; i++) { 818 DELAY(1); 819 rval = CSR_READ_4(sc, DC_PN_MII); 820 if (!(rval & DC_PN_MII_BUSY)) { 821 rval &= 0xFFFF; 822 return(rval == 0xFFFF ? 0 : rval); 823 } 824 } 825 return(0); 826 } 827 828 if (DC_IS_COMET(sc)) { 829 switch(reg) { 830 case MII_BMCR: 831 phy_reg = DC_AL_BMCR; 832 break; 833 case MII_BMSR: 834 phy_reg = DC_AL_BMSR; 835 break; 836 case MII_PHYIDR1: 837 phy_reg = DC_AL_VENID; 838 break; 839 case MII_PHYIDR2: 840 phy_reg = DC_AL_DEVID; 841 break; 842 case MII_ANAR: 843 phy_reg = DC_AL_ANAR; 844 break; 845 case MII_ANLPAR: 846 phy_reg = DC_AL_LPAR; 847 break; 848 case MII_ANER: 849 phy_reg = DC_AL_ANER; 850 break; 851 default: 852 printf("dc%d: phy_read: bad phy register %x\n", 853 sc->dc_unit, reg); 854 return(0); 855 break; 856 } 857 858 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 859 860 if (rval == 0xFFFF) 861 return(0); 862 return(rval); 863 } 864 865 frame.mii_phyaddr = phy; 866 frame.mii_regaddr = reg; 867 if (sc->dc_type == DC_TYPE_98713) { 868 phy_reg = CSR_READ_4(sc, DC_NETCFG); 869 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 870 } 871 dc_mii_readreg(sc, &frame); 872 if (sc->dc_type == DC_TYPE_98713) 873 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 874 875 return(frame.mii_data); 876 } 877 878 static int dc_miibus_writereg(dev, phy, reg, data) 879 device_t dev; 880 int phy, reg, data; 881 { 882 struct dc_softc *sc; 883 struct dc_mii_frame frame; 884 int i, phy_reg = 0; 885 886 sc = device_get_softc(dev); 887 bzero((char *)&frame, sizeof(frame)); 888 889 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 890 return(0); 891 892 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 893 return(0); 894 895 if (DC_IS_PNIC(sc)) { 896 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 897 (phy << 23) | (reg << 10) | data); 898 for (i = 0; i < DC_TIMEOUT; i++) { 899 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 900 break; 901 } 902 return(0); 903 } 904 905 if (DC_IS_COMET(sc)) { 906 switch(reg) { 907 case MII_BMCR: 908 phy_reg = DC_AL_BMCR; 909 break; 910 case MII_BMSR: 911 phy_reg = DC_AL_BMSR; 912 break; 913 case MII_PHYIDR1: 914 phy_reg = DC_AL_VENID; 915 break; 916 case MII_PHYIDR2: 917 phy_reg = DC_AL_DEVID; 918 break; 919 case MII_ANAR: 920 phy_reg = DC_AL_ANAR; 921 break; 922 case MII_ANLPAR: 923 phy_reg = DC_AL_LPAR; 924 break; 925 case MII_ANER: 926 phy_reg = DC_AL_ANER; 927 break; 928 default: 929 printf("dc%d: phy_write: bad phy register %x\n", 930 sc->dc_unit, reg); 931 return(0); 932 break; 933 } 934 935 CSR_WRITE_4(sc, phy_reg, data); 936 return(0); 937 } 938 939 frame.mii_phyaddr = phy; 940 frame.mii_regaddr = reg; 941 frame.mii_data = data; 942 943 if (sc->dc_type == DC_TYPE_98713) { 944 phy_reg = CSR_READ_4(sc, DC_NETCFG); 945 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 946 } 947 dc_mii_writereg(sc, &frame); 948 if (sc->dc_type == DC_TYPE_98713) 949 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 950 951 return(0); 952 } 953 954 static void dc_miibus_statchg(dev) 955 device_t dev; 956 { 957 struct dc_softc *sc; 958 struct mii_data *mii; 959 struct ifmedia *ifm; 960 961 sc = device_get_softc(dev); 962 if (DC_IS_ADMTEK(sc)) 963 return; 964 965 mii = device_get_softc(sc->dc_miibus); 966 ifm = &mii->mii_media; 967 if (DC_IS_DAVICOM(sc) && 968 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 969 dc_setcfg(sc, ifm->ifm_media); 970 sc->dc_if_media = ifm->ifm_media; 971 } else { 972 dc_setcfg(sc, mii->mii_media_active); 973 sc->dc_if_media = mii->mii_media_active; 974 } 975 976 return; 977 } 978 979 /* 980 * Special support for DM9102A cards with HomePNA PHYs. Note: 981 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 982 * to be impossible to talk to the management interface of the DM9801 983 * PHY (its MDIO pin is not connected to anything). Consequently, 984 * the driver has to just 'know' about the additional mode and deal 985 * with it itself. *sigh* 986 */ 987 static void dc_miibus_mediainit(dev) 988 device_t dev; 989 { 990 struct dc_softc *sc; 991 struct mii_data *mii; 992 struct ifmedia *ifm; 993 int rev; 994 995 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 996 997 sc = device_get_softc(dev); 998 mii = device_get_softc(sc->dc_miibus); 999 ifm = &mii->mii_media; 1000 1001 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1002 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 1003 1004 return; 1005 } 1006 1007 #define DC_POLY 0xEDB88320 1008 #define DC_BITS_512 9 1009 #define DC_BITS_128 7 1010 #define DC_BITS_64 6 1011 1012 static u_int32_t dc_crc_le(sc, addr) 1013 struct dc_softc *sc; 1014 caddr_t addr; 1015 { 1016 u_int32_t idx, bit, data, crc; 1017 1018 /* Compute CRC for the address value. */ 1019 crc = 0xFFFFFFFF; /* initial value */ 1020 1021 for (idx = 0; idx < 6; idx++) { 1022 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1023 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1024 } 1025 1026 /* 1027 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1028 * chips is only 128 bits wide. 1029 */ 1030 if (sc->dc_flags & DC_128BIT_HASH) 1031 return (crc & ((1 << DC_BITS_128) - 1)); 1032 1033 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1034 if (sc->dc_flags & DC_64BIT_HASH) 1035 return (crc & ((1 << DC_BITS_64) - 1)); 1036 1037 return (crc & ((1 << DC_BITS_512) - 1)); 1038 } 1039 1040 /* 1041 * Calculate CRC of a multicast group address, return the lower 6 bits. 1042 */ 1043 static u_int32_t dc_crc_be(addr) 1044 caddr_t addr; 1045 { 1046 u_int32_t crc, carry; 1047 int i, j; 1048 u_int8_t c; 1049 1050 /* Compute CRC for the address value. */ 1051 crc = 0xFFFFFFFF; /* initial value */ 1052 1053 for (i = 0; i < 6; i++) { 1054 c = *(addr + i); 1055 for (j = 0; j < 8; j++) { 1056 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1057 crc <<= 1; 1058 c >>= 1; 1059 if (carry) 1060 crc = (crc ^ 0x04c11db6) | carry; 1061 } 1062 } 1063 1064 /* return the filter bit position */ 1065 return((crc >> 26) & 0x0000003F); 1066 } 1067 1068 /* 1069 * 21143-style RX filter setup routine. Filter programming is done by 1070 * downloading a special setup frame into the TX engine. 21143, Macronix, 1071 * PNIC, PNIC II and Davicom chips are programmed this way. 1072 * 1073 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1074 * address (our node address) and a 512-bit hash filter for multicast 1075 * frames. We also sneak the broadcast address into the hash filter since 1076 * we need that too. 1077 */ 1078 void dc_setfilt_21143(sc) 1079 struct dc_softc *sc; 1080 { 1081 struct dc_desc *sframe; 1082 u_int32_t h, *sp; 1083 struct ifmultiaddr *ifma; 1084 struct ifnet *ifp; 1085 int i; 1086 1087 ifp = &sc->arpcom.ac_if; 1088 1089 i = sc->dc_cdata.dc_tx_prod; 1090 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1091 sc->dc_cdata.dc_tx_cnt++; 1092 sframe = &sc->dc_ldata->dc_tx_list[i]; 1093 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1094 bzero((char *)sp, DC_SFRAME_LEN); 1095 1096 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1097 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1098 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1099 1100 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1101 1102 /* If we want promiscuous mode, set the allframes bit. */ 1103 if (ifp->if_flags & IFF_PROMISC) 1104 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1105 else 1106 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1107 1108 if (ifp->if_flags & IFF_ALLMULTI) 1109 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1110 else 1111 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1112 1113 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1114 ifma = ifma->ifma_link.le_next) { 1115 if (ifma->ifma_addr->sa_family != AF_LINK) 1116 continue; 1117 h = dc_crc_le(sc, 1118 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1119 sp[h >> 4] |= 1 << (h & 0xF); 1120 } 1121 1122 if (ifp->if_flags & IFF_BROADCAST) { 1123 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1124 sp[h >> 4] |= 1 << (h & 0xF); 1125 } 1126 1127 /* Set our MAC address */ 1128 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1129 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1130 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1131 1132 sframe->dc_status = DC_TXSTAT_OWN; 1133 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1134 1135 /* 1136 * The PNIC takes an exceedingly long time to process its 1137 * setup frame; wait 10ms after posting the setup frame 1138 * before proceeding, just so it has time to swallow its 1139 * medicine. 1140 */ 1141 DELAY(10000); 1142 1143 ifp->if_timer = 5; 1144 1145 return; 1146 } 1147 1148 void dc_setfilt_admtek(sc) 1149 struct dc_softc *sc; 1150 { 1151 struct ifnet *ifp; 1152 int h = 0; 1153 u_int32_t hashes[2] = { 0, 0 }; 1154 struct ifmultiaddr *ifma; 1155 1156 ifp = &sc->arpcom.ac_if; 1157 1158 /* Init our MAC address */ 1159 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1160 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1161 1162 /* If we want promiscuous mode, set the allframes bit. */ 1163 if (ifp->if_flags & IFF_PROMISC) 1164 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1165 else 1166 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1167 1168 if (ifp->if_flags & IFF_ALLMULTI) 1169 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1170 else 1171 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1172 1173 /* first, zot all the existing hash bits */ 1174 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1175 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1176 1177 /* 1178 * If we're already in promisc or allmulti mode, we 1179 * don't have to bother programming the multicast filter. 1180 */ 1181 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1182 return; 1183 1184 /* now program new ones */ 1185 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1186 ifma = ifma->ifma_link.le_next) { 1187 if (ifma->ifma_addr->sa_family != AF_LINK) 1188 continue; 1189 if (DC_IS_CENTAUR(sc)) 1190 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1191 else 1192 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1193 if (h < 32) 1194 hashes[0] |= (1 << h); 1195 else 1196 hashes[1] |= (1 << (h - 32)); 1197 } 1198 1199 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1200 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1201 1202 return; 1203 } 1204 1205 void dc_setfilt_asix(sc) 1206 struct dc_softc *sc; 1207 { 1208 struct ifnet *ifp; 1209 int h = 0; 1210 u_int32_t hashes[2] = { 0, 0 }; 1211 struct ifmultiaddr *ifma; 1212 1213 ifp = &sc->arpcom.ac_if; 1214 1215 /* Init our MAC address */ 1216 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1217 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1218 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1219 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1220 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1221 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1222 1223 /* If we want promiscuous mode, set the allframes bit. */ 1224 if (ifp->if_flags & IFF_PROMISC) 1225 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1226 else 1227 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1228 1229 if (ifp->if_flags & IFF_ALLMULTI) 1230 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1231 else 1232 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1233 1234 /* 1235 * The ASIX chip has a special bit to enable reception 1236 * of broadcast frames. 1237 */ 1238 if (ifp->if_flags & IFF_BROADCAST) 1239 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1240 else 1241 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1242 1243 /* first, zot all the existing hash bits */ 1244 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1245 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1246 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1247 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1248 1249 /* 1250 * If we're already in promisc or allmulti mode, we 1251 * don't have to bother programming the multicast filter. 1252 */ 1253 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1254 return; 1255 1256 /* now program new ones */ 1257 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1258 ifma = ifma->ifma_link.le_next) { 1259 if (ifma->ifma_addr->sa_family != AF_LINK) 1260 continue; 1261 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1262 if (h < 32) 1263 hashes[0] |= (1 << h); 1264 else 1265 hashes[1] |= (1 << (h - 32)); 1266 } 1267 1268 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1269 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1270 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1271 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1272 1273 return; 1274 } 1275 1276 static void dc_setfilt(sc) 1277 struct dc_softc *sc; 1278 { 1279 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1280 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1281 dc_setfilt_21143(sc); 1282 1283 if (DC_IS_ASIX(sc)) 1284 dc_setfilt_asix(sc); 1285 1286 if (DC_IS_ADMTEK(sc)) 1287 dc_setfilt_admtek(sc); 1288 1289 return; 1290 } 1291 1292 /* 1293 * In order to fiddle with the 1294 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1295 * first have to put the transmit and/or receive logic in the idle state. 1296 */ 1297 static void dc_setcfg(sc, media) 1298 struct dc_softc *sc; 1299 int media; 1300 { 1301 int i, restart = 0; 1302 u_int32_t isr; 1303 1304 if (IFM_SUBTYPE(media) == IFM_NONE) 1305 return; 1306 1307 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1308 restart = 1; 1309 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1310 1311 for (i = 0; i < DC_TIMEOUT; i++) { 1312 isr = CSR_READ_4(sc, DC_ISR); 1313 if (isr & DC_ISR_TX_IDLE || 1314 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1315 break; 1316 DELAY(10); 1317 } 1318 1319 if (i == DC_TIMEOUT) 1320 printf("dc%d: failed to force tx and " 1321 "rx to idle state\n", sc->dc_unit); 1322 } 1323 1324 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1325 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1326 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1327 if (sc->dc_pmode == DC_PMODE_MII) { 1328 int watchdogreg; 1329 1330 if (DC_IS_INTEL(sc)) { 1331 /* there's a write enable bit here that reads as 1 */ 1332 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1333 watchdogreg &= ~DC_WDOG_CTLWREN; 1334 watchdogreg |= DC_WDOG_JABBERDIS; 1335 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1336 } else { 1337 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1338 } 1339 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1340 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1341 if (sc->dc_type == DC_TYPE_98713) 1342 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1343 DC_NETCFG_SCRAMBLER)); 1344 if (!DC_IS_DAVICOM(sc)) 1345 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1346 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1347 if (DC_IS_INTEL(sc)) 1348 dc_apply_fixup(sc, IFM_AUTO); 1349 } else { 1350 if (DC_IS_PNIC(sc)) { 1351 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1352 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1353 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1354 } 1355 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1356 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1357 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1358 if (DC_IS_INTEL(sc)) 1359 dc_apply_fixup(sc, 1360 (media & IFM_GMASK) == IFM_FDX ? 1361 IFM_100_TX|IFM_FDX : IFM_100_TX); 1362 } 1363 } 1364 1365 if (IFM_SUBTYPE(media) == IFM_10_T) { 1366 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1367 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1368 if (sc->dc_pmode == DC_PMODE_MII) { 1369 int watchdogreg; 1370 1371 /* there's a write enable bit here that reads as 1 */ 1372 if (DC_IS_INTEL(sc)) { 1373 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1374 watchdogreg &= ~DC_WDOG_CTLWREN; 1375 watchdogreg |= DC_WDOG_JABBERDIS; 1376 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1377 } else { 1378 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1379 } 1380 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1381 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1382 if (sc->dc_type == DC_TYPE_98713) 1383 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1384 if (!DC_IS_DAVICOM(sc)) 1385 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1386 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1387 if (DC_IS_INTEL(sc)) 1388 dc_apply_fixup(sc, IFM_AUTO); 1389 } else { 1390 if (DC_IS_PNIC(sc)) { 1391 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1392 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1393 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1394 } 1395 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1396 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1397 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1398 if (DC_IS_INTEL(sc)) { 1399 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1400 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1401 if ((media & IFM_GMASK) == IFM_FDX) 1402 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1403 else 1404 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1405 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1406 DC_CLRBIT(sc, DC_10BTCTRL, 1407 DC_TCTL_AUTONEGENBL); 1408 dc_apply_fixup(sc, 1409 (media & IFM_GMASK) == IFM_FDX ? 1410 IFM_10_T|IFM_FDX : IFM_10_T); 1411 DELAY(20000); 1412 } 1413 } 1414 } 1415 1416 /* 1417 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1418 * PHY and we want HomePNA mode, set the portsel bit to turn 1419 * on the external MII port. 1420 */ 1421 if (DC_IS_DAVICOM(sc)) { 1422 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1423 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1424 sc->dc_link = 1; 1425 } else { 1426 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1427 } 1428 } 1429 1430 if ((media & IFM_GMASK) == IFM_FDX) { 1431 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1432 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1433 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1434 } else { 1435 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1436 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1437 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1438 } 1439 1440 if (restart) 1441 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1442 1443 return; 1444 } 1445 1446 static void dc_reset(sc) 1447 struct dc_softc *sc; 1448 { 1449 register int i; 1450 1451 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1452 1453 for (i = 0; i < DC_TIMEOUT; i++) { 1454 DELAY(10); 1455 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1456 break; 1457 } 1458 1459 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) { 1460 DELAY(10000); 1461 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1462 i = 0; 1463 } 1464 1465 if (i == DC_TIMEOUT) 1466 printf("dc%d: reset never completed!\n", sc->dc_unit); 1467 1468 /* Wait a little while for the chip to get its brains in order. */ 1469 DELAY(1000); 1470 1471 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1472 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1473 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1474 1475 /* 1476 * Bring the SIA out of reset. In some cases, it looks 1477 * like failing to unreset the SIA soon enough gets it 1478 * into a state where it will never come out of reset 1479 * until we reset the whole chip again. 1480 */ 1481 if (DC_IS_INTEL(sc)) { 1482 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1483 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1484 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1485 } 1486 1487 return; 1488 } 1489 1490 static struct dc_type *dc_devtype(dev) 1491 device_t dev; 1492 { 1493 struct dc_type *t; 1494 u_int32_t rev; 1495 1496 t = dc_devs; 1497 1498 while(t->dc_name != NULL) { 1499 if ((pci_get_vendor(dev) == t->dc_vid) && 1500 (pci_get_device(dev) == t->dc_did)) { 1501 /* Check the PCI revision */ 1502 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1503 if (t->dc_did == DC_DEVICEID_98713 && 1504 rev >= DC_REVISION_98713A) 1505 t++; 1506 if (t->dc_did == DC_DEVICEID_98713_CP && 1507 rev >= DC_REVISION_98713A) 1508 t++; 1509 if (t->dc_did == DC_DEVICEID_987x5 && 1510 rev >= DC_REVISION_98715AEC_C) 1511 t++; 1512 if (t->dc_did == DC_DEVICEID_987x5 && 1513 rev >= DC_REVISION_98725) 1514 t++; 1515 if (t->dc_did == DC_DEVICEID_AX88140A && 1516 rev >= DC_REVISION_88141) 1517 t++; 1518 if (t->dc_did == DC_DEVICEID_82C168 && 1519 rev >= DC_REVISION_82C169) 1520 t++; 1521 if (t->dc_did == DC_DEVICEID_DM9102 && 1522 rev >= DC_REVISION_DM9102A) 1523 t++; 1524 return(t); 1525 } 1526 t++; 1527 } 1528 1529 return(NULL); 1530 } 1531 1532 /* 1533 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1534 * IDs against our list and return a device name if we find a match. 1535 * We do a little bit of extra work to identify the exact type of 1536 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1537 * but different revision IDs. The same is true for 98715/98715A 1538 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1539 * cases, the exact chip revision affects driver behavior. 1540 */ 1541 static int dc_probe(dev) 1542 device_t dev; 1543 { 1544 struct dc_type *t; 1545 1546 t = dc_devtype(dev); 1547 1548 if (t != NULL) { 1549 device_set_desc(dev, t->dc_name); 1550 return(0); 1551 } 1552 1553 return(ENXIO); 1554 } 1555 1556 static void dc_acpi(dev) 1557 device_t dev; 1558 { 1559 u_int32_t r, cptr; 1560 int unit; 1561 1562 unit = device_get_unit(dev); 1563 1564 /* Find the location of the capabilities block */ 1565 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1566 1567 r = pci_read_config(dev, cptr, 4) & 0xFF; 1568 if (r == 0x01) { 1569 1570 r = pci_read_config(dev, cptr + 4, 4); 1571 if (r & DC_PSTATE_D3) { 1572 u_int32_t iobase, membase, irq; 1573 1574 /* Save important PCI config data. */ 1575 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1576 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1577 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1578 1579 /* Reset the power state. */ 1580 printf("dc%d: chip is in D%d power mode " 1581 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1582 r &= 0xFFFFFFFC; 1583 pci_write_config(dev, cptr + 4, r, 4); 1584 1585 /* Restore PCI config data. */ 1586 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1587 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1588 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1589 } 1590 } 1591 return; 1592 } 1593 1594 static void dc_apply_fixup(sc, media) 1595 struct dc_softc *sc; 1596 int media; 1597 { 1598 struct dc_mediainfo *m; 1599 u_int8_t *p; 1600 int i; 1601 u_int32_t reg; 1602 1603 m = sc->dc_mi; 1604 1605 while (m != NULL) { 1606 if (m->dc_media == media) 1607 break; 1608 m = m->dc_next; 1609 } 1610 1611 if (m == NULL) 1612 return; 1613 1614 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1615 reg = (p[0] | (p[1] << 8)) << 16; 1616 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1617 } 1618 1619 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1620 reg = (p[0] | (p[1] << 8)) << 16; 1621 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1622 } 1623 1624 return; 1625 } 1626 1627 static void dc_decode_leaf_sia(sc, l) 1628 struct dc_softc *sc; 1629 struct dc_eblock_sia *l; 1630 { 1631 struct dc_mediainfo *m; 1632 1633 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1634 bzero(m, sizeof(struct dc_mediainfo)); 1635 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1636 case DC_SIA_CODE_10BT: 1637 m->dc_media = IFM_10_T; 1638 break; 1639 case DC_SIA_CODE_10BT_FDX: 1640 m->dc_media = IFM_10_T|IFM_FDX; 1641 break; 1642 case DC_SIA_CODE_10B2: 1643 m->dc_media = IFM_10_2; 1644 break; 1645 case DC_SIA_CODE_10B5: 1646 m->dc_media = IFM_10_5; 1647 break; 1648 } 1649 1650 /* 1651 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1652 * Things apparently already work for cards that do 1653 * supply Media Specific Data. 1654 */ 1655 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1656 m->dc_gp_len = 2; 1657 m->dc_gp_ptr = 1658 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1659 } else { 1660 m->dc_gp_len = 2; 1661 m->dc_gp_ptr = 1662 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1663 } 1664 1665 m->dc_next = sc->dc_mi; 1666 sc->dc_mi = m; 1667 1668 sc->dc_pmode = DC_PMODE_SIA; 1669 1670 return; 1671 } 1672 1673 static void dc_decode_leaf_sym(sc, l) 1674 struct dc_softc *sc; 1675 struct dc_eblock_sym *l; 1676 { 1677 struct dc_mediainfo *m; 1678 1679 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1680 bzero(m, sizeof(struct dc_mediainfo)); 1681 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1682 m->dc_media = IFM_100_TX; 1683 1684 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1685 m->dc_media = IFM_100_TX|IFM_FDX; 1686 1687 m->dc_gp_len = 2; 1688 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1689 1690 m->dc_next = sc->dc_mi; 1691 sc->dc_mi = m; 1692 1693 sc->dc_pmode = DC_PMODE_SYM; 1694 1695 return; 1696 } 1697 1698 static void dc_decode_leaf_mii(sc, l) 1699 struct dc_softc *sc; 1700 struct dc_eblock_mii *l; 1701 { 1702 u_int8_t *p; 1703 struct dc_mediainfo *m; 1704 1705 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1706 bzero(m, sizeof(struct dc_mediainfo)); 1707 /* We abuse IFM_AUTO to represent MII. */ 1708 m->dc_media = IFM_AUTO; 1709 m->dc_gp_len = l->dc_gpr_len; 1710 1711 p = (u_int8_t *)l; 1712 p += sizeof(struct dc_eblock_mii); 1713 m->dc_gp_ptr = p; 1714 p += 2 * l->dc_gpr_len; 1715 m->dc_reset_len = *p; 1716 p++; 1717 m->dc_reset_ptr = p; 1718 1719 m->dc_next = sc->dc_mi; 1720 sc->dc_mi = m; 1721 1722 return; 1723 } 1724 1725 static void dc_read_srom(sc, bits) 1726 struct dc_softc *sc; 1727 int bits; 1728 { 1729 int size; 1730 1731 size = 2 << bits; 1732 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1733 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1734 } 1735 1736 static void dc_parse_21143_srom(sc) 1737 struct dc_softc *sc; 1738 { 1739 struct dc_leaf_hdr *lhdr; 1740 struct dc_eblock_hdr *hdr; 1741 int i, loff; 1742 char *ptr; 1743 int have_mii; 1744 1745 have_mii = 0; 1746 loff = sc->dc_srom[27]; 1747 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1748 1749 ptr = (char *)lhdr; 1750 ptr += sizeof(struct dc_leaf_hdr) - 1; 1751 /* 1752 * Look if we got a MII media block. 1753 */ 1754 for (i = 0; i < lhdr->dc_mcnt; i++) { 1755 hdr = (struct dc_eblock_hdr *)ptr; 1756 if (hdr->dc_type == DC_EBLOCK_MII) 1757 have_mii++; 1758 1759 ptr += (hdr->dc_len & 0x7F); 1760 ptr++; 1761 } 1762 1763 /* 1764 * Do the same thing again. Only use SIA and SYM media 1765 * blocks if no MII media block is available. 1766 */ 1767 ptr = (char *)lhdr; 1768 ptr += sizeof(struct dc_leaf_hdr) - 1; 1769 for (i = 0; i < lhdr->dc_mcnt; i++) { 1770 hdr = (struct dc_eblock_hdr *)ptr; 1771 switch(hdr->dc_type) { 1772 case DC_EBLOCK_MII: 1773 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1774 break; 1775 case DC_EBLOCK_SIA: 1776 if (! have_mii) 1777 dc_decode_leaf_sia(sc, 1778 (struct dc_eblock_sia *)hdr); 1779 break; 1780 case DC_EBLOCK_SYM: 1781 if (! have_mii) 1782 dc_decode_leaf_sym(sc, 1783 (struct dc_eblock_sym *)hdr); 1784 break; 1785 default: 1786 /* Don't care. Yet. */ 1787 break; 1788 } 1789 ptr += (hdr->dc_len & 0x7F); 1790 ptr++; 1791 } 1792 1793 return; 1794 } 1795 1796 /* 1797 * Attach the interface. Allocate softc structures, do ifmedia 1798 * setup and ethernet/BPF attach. 1799 */ 1800 static int dc_attach(dev) 1801 device_t dev; 1802 { 1803 int s, tmp = 0; 1804 u_char eaddr[ETHER_ADDR_LEN]; 1805 u_int32_t command; 1806 struct dc_softc *sc; 1807 struct ifnet *ifp; 1808 u_int32_t revision; 1809 int unit, error = 0, rid, mac_offset; 1810 1811 s = splimp(); 1812 1813 sc = device_get_softc(dev); 1814 unit = device_get_unit(dev); 1815 bzero(sc, sizeof(struct dc_softc)); 1816 1817 /* 1818 * Handle power management nonsense. 1819 */ 1820 dc_acpi(dev); 1821 1822 /* 1823 * Map control/status registers. 1824 */ 1825 command = pci_read_config(dev, PCIR_COMMAND, 4); 1826 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1827 pci_write_config(dev, PCIR_COMMAND, command, 4); 1828 command = pci_read_config(dev, PCIR_COMMAND, 4); 1829 1830 #ifdef DC_USEIOSPACE 1831 if (!(command & PCIM_CMD_PORTEN)) { 1832 printf("dc%d: failed to enable I/O ports!\n", unit); 1833 error = ENXIO; 1834 goto fail; 1835 } 1836 #else 1837 if (!(command & PCIM_CMD_MEMEN)) { 1838 printf("dc%d: failed to enable memory mapping!\n", unit); 1839 error = ENXIO; 1840 goto fail; 1841 } 1842 #endif 1843 1844 rid = DC_RID; 1845 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1846 0, ~0, 1, RF_ACTIVE); 1847 1848 if (sc->dc_res == NULL) { 1849 printf("dc%d: couldn't map ports/memory\n", unit); 1850 error = ENXIO; 1851 goto fail; 1852 } 1853 1854 sc->dc_btag = rman_get_bustag(sc->dc_res); 1855 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1856 1857 /* Allocate interrupt */ 1858 rid = 0; 1859 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1860 RF_SHAREABLE | RF_ACTIVE); 1861 1862 if (sc->dc_irq == NULL) { 1863 printf("dc%d: couldn't map interrupt\n", unit); 1864 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1865 error = ENXIO; 1866 goto fail; 1867 } 1868 1869 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1870 dc_intr, sc, &sc->dc_intrhand); 1871 1872 if (error) { 1873 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1874 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1875 printf("dc%d: couldn't set up irq\n", unit); 1876 goto fail; 1877 } 1878 1879 /* Need this info to decide on a chip type. */ 1880 sc->dc_info = dc_devtype(dev); 1881 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1882 1883 /* Get the eeprom width, but PNIC has diff eeprom */ 1884 if (sc->dc_info->dc_did != DC_DEVICEID_82C168) 1885 dc_eeprom_width(sc); 1886 1887 switch(sc->dc_info->dc_did) { 1888 case DC_DEVICEID_21143: 1889 sc->dc_type = DC_TYPE_21143; 1890 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1891 sc->dc_flags |= DC_REDUCED_MII_POLL; 1892 /* Save EEPROM contents so we can parse them later. */ 1893 dc_read_srom(sc, sc->dc_romwidth); 1894 break; 1895 case DC_DEVICEID_DM9009: 1896 case DC_DEVICEID_DM9100: 1897 case DC_DEVICEID_DM9102: 1898 sc->dc_type = DC_TYPE_DM9102; 1899 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1900 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1901 sc->dc_flags |= DC_TX_ALIGN; 1902 sc->dc_pmode = DC_PMODE_MII; 1903 /* Increase the latency timer value. */ 1904 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1905 command &= 0xFFFF00FF; 1906 command |= 0x00008000; 1907 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1908 break; 1909 case DC_DEVICEID_AL981: 1910 sc->dc_type = DC_TYPE_AL981; 1911 sc->dc_flags |= DC_TX_USE_TX_INTR; 1912 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1913 sc->dc_pmode = DC_PMODE_MII; 1914 dc_read_srom(sc, sc->dc_romwidth); 1915 break; 1916 case DC_DEVICEID_AN985: 1917 case DC_DEVICEID_EN2242: 1918 case DC_DEVICEID_3CSOHOB: 1919 sc->dc_type = DC_TYPE_AN985; 1920 sc->dc_flags |= DC_64BIT_HASH; 1921 sc->dc_flags |= DC_TX_USE_TX_INTR; 1922 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1923 sc->dc_pmode = DC_PMODE_MII; 1924 /* Don't read SROM for - auto-loaded on reset */ 1925 break; 1926 case DC_DEVICEID_98713: 1927 case DC_DEVICEID_98713_CP: 1928 if (revision < DC_REVISION_98713A) { 1929 sc->dc_type = DC_TYPE_98713; 1930 } 1931 if (revision >= DC_REVISION_98713A) { 1932 sc->dc_type = DC_TYPE_98713A; 1933 sc->dc_flags |= DC_21143_NWAY; 1934 } 1935 sc->dc_flags |= DC_REDUCED_MII_POLL; 1936 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1937 break; 1938 case DC_DEVICEID_987x5: 1939 case DC_DEVICEID_EN1217: 1940 /* 1941 * Macronix MX98715AEC-C/D/E parts have only a 1942 * 128-bit hash table. We need to deal with these 1943 * in the same manner as the PNIC II so that we 1944 * get the right number of bits out of the 1945 * CRC routine. 1946 */ 1947 if (revision >= DC_REVISION_98715AEC_C && 1948 revision < DC_REVISION_98725) 1949 sc->dc_flags |= DC_128BIT_HASH; 1950 sc->dc_type = DC_TYPE_987x5; 1951 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1952 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1953 break; 1954 case DC_DEVICEID_98727: 1955 sc->dc_type = DC_TYPE_987x5; 1956 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1957 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1958 break; 1959 case DC_DEVICEID_82C115: 1960 sc->dc_type = DC_TYPE_PNICII; 1961 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1962 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1963 break; 1964 case DC_DEVICEID_82C168: 1965 sc->dc_type = DC_TYPE_PNIC; 1966 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1967 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1968 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1969 if (revision < DC_REVISION_82C169) 1970 sc->dc_pmode = DC_PMODE_SYM; 1971 break; 1972 case DC_DEVICEID_AX88140A: 1973 sc->dc_type = DC_TYPE_ASIX; 1974 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1975 sc->dc_flags |= DC_REDUCED_MII_POLL; 1976 sc->dc_pmode = DC_PMODE_MII; 1977 break; 1978 case DC_DEVICEID_RS7112: 1979 sc->dc_type = DC_TYPE_CONEXANT; 1980 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1981 sc->dc_flags |= DC_REDUCED_MII_POLL; 1982 sc->dc_pmode = DC_PMODE_MII; 1983 dc_read_srom(sc, sc->dc_romwidth); 1984 break; 1985 default: 1986 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1987 sc->dc_info->dc_did); 1988 break; 1989 } 1990 1991 /* Save the cache line size. */ 1992 if (DC_IS_DAVICOM(sc)) 1993 sc->dc_cachesize = 0; 1994 else 1995 sc->dc_cachesize = pci_read_config(dev, 1996 DC_PCI_CFLT, 4) & 0xFF; 1997 1998 /* Reset the adapter. */ 1999 dc_reset(sc); 2000 2001 /* Take 21143 out of snooze mode */ 2002 if (DC_IS_INTEL(sc)) { 2003 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2004 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2005 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2006 } 2007 2008 /* 2009 * Try to learn something about the supported media. 2010 * We know that ASIX and ADMtek and Davicom devices 2011 * will *always* be using MII media, so that's a no-brainer. 2012 * The tricky ones are the Macronix/PNIC II and the 2013 * Intel 21143. 2014 */ 2015 if (DC_IS_INTEL(sc)) 2016 dc_parse_21143_srom(sc); 2017 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2018 if (sc->dc_type == DC_TYPE_98713) 2019 sc->dc_pmode = DC_PMODE_MII; 2020 else 2021 sc->dc_pmode = DC_PMODE_SYM; 2022 } else if (!sc->dc_pmode) 2023 sc->dc_pmode = DC_PMODE_MII; 2024 2025 /* 2026 * Get station address from the EEPROM. 2027 */ 2028 switch(sc->dc_type) { 2029 case DC_TYPE_98713: 2030 case DC_TYPE_98713A: 2031 case DC_TYPE_987x5: 2032 case DC_TYPE_PNICII: 2033 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2034 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2035 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2036 break; 2037 case DC_TYPE_PNIC: 2038 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2039 break; 2040 case DC_TYPE_DM9102: 2041 case DC_TYPE_21143: 2042 case DC_TYPE_ASIX: 2043 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2044 break; 2045 case DC_TYPE_AL981: 2046 case DC_TYPE_AN985: 2047 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2048 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2049 break; 2050 case DC_TYPE_CONEXANT: 2051 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2052 break; 2053 default: 2054 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2055 break; 2056 } 2057 2058 /* 2059 * A 21143 or clone chip was detected. Inform the world. 2060 */ 2061 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2062 2063 sc->dc_unit = unit; 2064 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2065 2066 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2067 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2068 2069 if (sc->dc_ldata == NULL) { 2070 printf("dc%d: no memory for list buffers!\n", unit); 2071 if (sc->dc_pnic_rx_buf != NULL) 2072 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2073 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2074 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2075 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2076 error = ENXIO; 2077 goto fail; 2078 } 2079 2080 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2081 2082 ifp = &sc->arpcom.ac_if; 2083 ifp->if_softc = sc; 2084 ifp->if_unit = unit; 2085 ifp->if_name = "dc"; 2086 ifp->if_mtu = ETHERMTU; 2087 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2088 ifp->if_ioctl = dc_ioctl; 2089 ifp->if_output = ether_output; 2090 ifp->if_start = dc_start; 2091 ifp->if_watchdog = dc_watchdog; 2092 ifp->if_init = dc_init; 2093 ifp->if_baudrate = 10000000; 2094 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2095 2096 /* 2097 * Do MII setup. If this is a 21143, check for a PHY on the 2098 * MII bus after applying any necessary fixups to twiddle the 2099 * GPIO bits. If we don't end up finding a PHY, restore the 2100 * old selection (SIA only or SIA/SYM) and attach the dcphy 2101 * driver instead. 2102 */ 2103 if (DC_IS_INTEL(sc)) { 2104 dc_apply_fixup(sc, IFM_AUTO); 2105 tmp = sc->dc_pmode; 2106 sc->dc_pmode = DC_PMODE_MII; 2107 } 2108 2109 error = mii_phy_probe(dev, &sc->dc_miibus, 2110 dc_ifmedia_upd, dc_ifmedia_sts); 2111 2112 if (error && DC_IS_INTEL(sc)) { 2113 sc->dc_pmode = tmp; 2114 if (sc->dc_pmode != DC_PMODE_SIA) 2115 sc->dc_pmode = DC_PMODE_SYM; 2116 sc->dc_flags |= DC_21143_NWAY; 2117 mii_phy_probe(dev, &sc->dc_miibus, 2118 dc_ifmedia_upd, dc_ifmedia_sts); 2119 /* 2120 * For non-MII cards, we need to have the 21143 2121 * drive the LEDs. Except there are some systems 2122 * like the NEC VersaPro NoteBook PC which have no 2123 * LEDs, and twiddling these bits has adverse effects 2124 * on them. (I.e. you suddenly can't get a link.) 2125 */ 2126 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2127 sc->dc_flags |= DC_TULIP_LEDS; 2128 error = 0; 2129 } 2130 2131 if (error) { 2132 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2133 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), 2134 M_DEVBUF); 2135 if (sc->dc_pnic_rx_buf != NULL) 2136 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2137 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2138 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2139 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2140 error = ENXIO; 2141 goto fail; 2142 } 2143 2144 /* 2145 * Call MI attach routine. 2146 */ 2147 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2148 callout_handle_init(&sc->dc_stat_ch); 2149 2150 if (DC_IS_ADMTEK(sc)) { 2151 /* 2152 * Set automatic TX underrun recovery for the ADMtek chips 2153 */ 2154 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2155 } 2156 2157 /* 2158 * Tell the upper layer(s) we support long frames. 2159 */ 2160 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2161 #ifdef DEVICE_POLLING 2162 ifp->if_capabilities |= IFCAP_POLLING; 2163 #endif 2164 ifp->if_capenable = ifp->if_capabilities; 2165 2166 #ifdef SRM_MEDIA 2167 sc->dc_srm_media = 0; 2168 2169 /* Remember the SRM console media setting */ 2170 if (DC_IS_INTEL(sc)) { 2171 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2172 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2173 switch ((command >> 8) & 0xff) { 2174 case 3: 2175 sc->dc_srm_media = IFM_10_T; 2176 break; 2177 case 4: 2178 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2179 break; 2180 case 5: 2181 sc->dc_srm_media = IFM_100_TX; 2182 break; 2183 case 6: 2184 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2185 break; 2186 } 2187 if (sc->dc_srm_media) 2188 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2189 } 2190 #endif 2191 2192 2193 fail: 2194 splx(s); 2195 2196 return(error); 2197 } 2198 2199 static int dc_detach(dev) 2200 device_t dev; 2201 { 2202 struct dc_softc *sc; 2203 struct ifnet *ifp; 2204 int s; 2205 struct dc_mediainfo *m; 2206 2207 s = splimp(); 2208 2209 sc = device_get_softc(dev); 2210 ifp = &sc->arpcom.ac_if; 2211 2212 dc_stop(sc); 2213 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2214 2215 bus_generic_detach(dev); 2216 device_delete_child(dev, sc->dc_miibus); 2217 2218 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2219 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2220 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2221 2222 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2223 if (sc->dc_pnic_rx_buf != NULL) 2224 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2225 2226 while(sc->dc_mi != NULL) { 2227 m = sc->dc_mi->dc_next; 2228 free(sc->dc_mi, M_DEVBUF); 2229 sc->dc_mi = m; 2230 } 2231 free(sc->dc_srom, M_DEVBUF); 2232 2233 splx(s); 2234 2235 return(0); 2236 } 2237 2238 /* 2239 * Initialize the transmit descriptors. 2240 */ 2241 static int dc_list_tx_init(sc) 2242 struct dc_softc *sc; 2243 { 2244 struct dc_chain_data *cd; 2245 struct dc_list_data *ld; 2246 int i; 2247 2248 cd = &sc->dc_cdata; 2249 ld = sc->dc_ldata; 2250 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2251 if (i == (DC_TX_LIST_CNT - 1)) { 2252 ld->dc_tx_list[i].dc_next = 2253 vtophys(&ld->dc_tx_list[0]); 2254 } else { 2255 ld->dc_tx_list[i].dc_next = 2256 vtophys(&ld->dc_tx_list[i + 1]); 2257 } 2258 cd->dc_tx_chain[i] = NULL; 2259 ld->dc_tx_list[i].dc_data = 0; 2260 ld->dc_tx_list[i].dc_ctl = 0; 2261 } 2262 2263 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2264 2265 return(0); 2266 } 2267 2268 2269 /* 2270 * Initialize the RX descriptors and allocate mbufs for them. Note that 2271 * we arrange the descriptors in a closed ring, so that the last descriptor 2272 * points back to the first. 2273 */ 2274 static int dc_list_rx_init(sc) 2275 struct dc_softc *sc; 2276 { 2277 struct dc_chain_data *cd; 2278 struct dc_list_data *ld; 2279 int i; 2280 2281 cd = &sc->dc_cdata; 2282 ld = sc->dc_ldata; 2283 2284 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2285 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2286 return(ENOBUFS); 2287 if (i == (DC_RX_LIST_CNT - 1)) { 2288 ld->dc_rx_list[i].dc_next = 2289 vtophys(&ld->dc_rx_list[0]); 2290 } else { 2291 ld->dc_rx_list[i].dc_next = 2292 vtophys(&ld->dc_rx_list[i + 1]); 2293 } 2294 } 2295 2296 cd->dc_rx_prod = 0; 2297 2298 return(0); 2299 } 2300 2301 /* 2302 * Initialize an RX descriptor and attach an MBUF cluster. 2303 */ 2304 static int dc_newbuf(sc, i, m) 2305 struct dc_softc *sc; 2306 int i; 2307 struct mbuf *m; 2308 { 2309 struct mbuf *m_new = NULL; 2310 struct dc_desc *c; 2311 2312 c = &sc->dc_ldata->dc_rx_list[i]; 2313 2314 if (m == NULL) { 2315 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2316 if (m_new == NULL) 2317 return(ENOBUFS); 2318 2319 MCLGET(m_new, M_DONTWAIT); 2320 if (!(m_new->m_flags & M_EXT)) { 2321 m_freem(m_new); 2322 return(ENOBUFS); 2323 } 2324 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2325 } else { 2326 m_new = m; 2327 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2328 m_new->m_data = m_new->m_ext.ext_buf; 2329 } 2330 2331 m_adj(m_new, sizeof(u_int64_t)); 2332 2333 /* 2334 * If this is a PNIC chip, zero the buffer. This is part 2335 * of the workaround for the receive bug in the 82c168 and 2336 * 82c169 chips. 2337 */ 2338 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2339 bzero((char *)mtod(m_new, char *), m_new->m_len); 2340 2341 sc->dc_cdata.dc_rx_chain[i] = m_new; 2342 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2343 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2344 c->dc_status = DC_RXSTAT_OWN; 2345 2346 return(0); 2347 } 2348 2349 /* 2350 * Grrrrr. 2351 * The PNIC chip has a terrible bug in it that manifests itself during 2352 * periods of heavy activity. The exact mode of failure if difficult to 2353 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2354 * will happen on slow machines. The bug is that sometimes instead of 2355 * uploading one complete frame during reception, it uploads what looks 2356 * like the entire contents of its FIFO memory. The frame we want is at 2357 * the end of the whole mess, but we never know exactly how much data has 2358 * been uploaded, so salvaging the frame is hard. 2359 * 2360 * There is only one way to do it reliably, and it's disgusting. 2361 * Here's what we know: 2362 * 2363 * - We know there will always be somewhere between one and three extra 2364 * descriptors uploaded. 2365 * 2366 * - We know the desired received frame will always be at the end of the 2367 * total data upload. 2368 * 2369 * - We know the size of the desired received frame because it will be 2370 * provided in the length field of the status word in the last descriptor. 2371 * 2372 * Here's what we do: 2373 * 2374 * - When we allocate buffers for the receive ring, we bzero() them. 2375 * This means that we know that the buffer contents should be all 2376 * zeros, except for data uploaded by the chip. 2377 * 2378 * - We also force the PNIC chip to upload frames that include the 2379 * ethernet CRC at the end. 2380 * 2381 * - We gather all of the bogus frame data into a single buffer. 2382 * 2383 * - We then position a pointer at the end of this buffer and scan 2384 * backwards until we encounter the first non-zero byte of data. 2385 * This is the end of the received frame. We know we will encounter 2386 * some data at the end of the frame because the CRC will always be 2387 * there, so even if the sender transmits a packet of all zeros, 2388 * we won't be fooled. 2389 * 2390 * - We know the size of the actual received frame, so we subtract 2391 * that value from the current pointer location. This brings us 2392 * to the start of the actual received packet. 2393 * 2394 * - We copy this into an mbuf and pass it on, along with the actual 2395 * frame length. 2396 * 2397 * The performance hit is tremendous, but it beats dropping frames all 2398 * the time. 2399 */ 2400 2401 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2402 static void dc_pnic_rx_bug_war(sc, idx) 2403 struct dc_softc *sc; 2404 int idx; 2405 { 2406 struct dc_desc *cur_rx; 2407 struct dc_desc *c = NULL; 2408 struct mbuf *m = NULL; 2409 unsigned char *ptr; 2410 int i, total_len; 2411 u_int32_t rxstat = 0; 2412 2413 i = sc->dc_pnic_rx_bug_save; 2414 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2415 ptr = sc->dc_pnic_rx_buf; 2416 bzero(ptr, DC_RXLEN * 5); 2417 2418 /* Copy all the bytes from the bogus buffers. */ 2419 while (1) { 2420 c = &sc->dc_ldata->dc_rx_list[i]; 2421 rxstat = c->dc_status; 2422 m = sc->dc_cdata.dc_rx_chain[i]; 2423 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2424 ptr += DC_RXLEN; 2425 /* If this is the last buffer, break out. */ 2426 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2427 break; 2428 dc_newbuf(sc, i, m); 2429 DC_INC(i, DC_RX_LIST_CNT); 2430 } 2431 2432 /* Find the length of the actual receive frame. */ 2433 total_len = DC_RXBYTES(rxstat); 2434 2435 /* Scan backwards until we hit a non-zero byte. */ 2436 while(*ptr == 0x00) 2437 ptr--; 2438 2439 /* Round off. */ 2440 if ((uintptr_t)(ptr) & 0x3) 2441 ptr -= 1; 2442 2443 /* Now find the start of the frame. */ 2444 ptr -= total_len; 2445 if (ptr < sc->dc_pnic_rx_buf) 2446 ptr = sc->dc_pnic_rx_buf; 2447 2448 /* 2449 * Now copy the salvaged frame to the last mbuf and fake up 2450 * the status word to make it look like a successful 2451 * frame reception. 2452 */ 2453 dc_newbuf(sc, i, m); 2454 bcopy(ptr, mtod(m, char *), total_len); 2455 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2456 2457 return; 2458 } 2459 2460 /* 2461 * This routine searches the RX ring for dirty descriptors in the 2462 * event that the rxeof routine falls out of sync with the chip's 2463 * current descriptor pointer. This may happen sometimes as a result 2464 * of a "no RX buffer available" condition that happens when the chip 2465 * consumes all of the RX buffers before the driver has a chance to 2466 * process the RX ring. This routine may need to be called more than 2467 * once to bring the driver back in sync with the chip, however we 2468 * should still be getting RX DONE interrupts to drive the search 2469 * for new packets in the RX ring, so we should catch up eventually. 2470 */ 2471 static int dc_rx_resync(sc) 2472 struct dc_softc *sc; 2473 { 2474 int i, pos; 2475 struct dc_desc *cur_rx; 2476 2477 pos = sc->dc_cdata.dc_rx_prod; 2478 2479 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2480 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2481 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2482 break; 2483 DC_INC(pos, DC_RX_LIST_CNT); 2484 } 2485 2486 /* If the ring really is empty, then just return. */ 2487 if (i == DC_RX_LIST_CNT) 2488 return(0); 2489 2490 /* We've fallen behing the chip: catch it. */ 2491 sc->dc_cdata.dc_rx_prod = pos; 2492 2493 return(EAGAIN); 2494 } 2495 2496 /* 2497 * A frame has been uploaded: pass the resulting mbuf chain up to 2498 * the higher level protocols. 2499 */ 2500 static void dc_rxeof(sc) 2501 struct dc_softc *sc; 2502 { 2503 struct ether_header *eh; 2504 struct mbuf *m; 2505 struct ifnet *ifp; 2506 struct dc_desc *cur_rx; 2507 int i, total_len = 0; 2508 u_int32_t rxstat; 2509 2510 ifp = &sc->arpcom.ac_if; 2511 i = sc->dc_cdata.dc_rx_prod; 2512 2513 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2514 2515 #ifdef DEVICE_POLLING 2516 if (ifp->if_ipending & IFF_POLLING) { 2517 if (sc->rxcycles <= 0) 2518 break; 2519 sc->rxcycles--; 2520 } 2521 #endif /* DEVICE_POLLING */ 2522 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2523 rxstat = cur_rx->dc_status; 2524 m = sc->dc_cdata.dc_rx_chain[i]; 2525 total_len = DC_RXBYTES(rxstat); 2526 2527 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2528 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2529 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2530 sc->dc_pnic_rx_bug_save = i; 2531 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2532 DC_INC(i, DC_RX_LIST_CNT); 2533 continue; 2534 } 2535 dc_pnic_rx_bug_war(sc, i); 2536 rxstat = cur_rx->dc_status; 2537 total_len = DC_RXBYTES(rxstat); 2538 } 2539 } 2540 2541 sc->dc_cdata.dc_rx_chain[i] = NULL; 2542 2543 /* 2544 * If an error occurs, update stats, clear the 2545 * status word and leave the mbuf cluster in place: 2546 * it should simply get re-used next time this descriptor 2547 * comes up in the ring. However, don't report long 2548 * frames as errors since they could be vlans 2549 */ 2550 if ((rxstat & DC_RXSTAT_RXERR)){ 2551 if (!(rxstat & DC_RXSTAT_GIANT) || 2552 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2553 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2554 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2555 ifp->if_ierrors++; 2556 if (rxstat & DC_RXSTAT_COLLSEEN) 2557 ifp->if_collisions++; 2558 dc_newbuf(sc, i, m); 2559 if (rxstat & DC_RXSTAT_CRCERR) { 2560 DC_INC(i, DC_RX_LIST_CNT); 2561 continue; 2562 } else { 2563 dc_init(sc); 2564 return; 2565 } 2566 } 2567 } 2568 2569 /* No errors; receive the packet. */ 2570 total_len -= ETHER_CRC_LEN; 2571 2572 #ifdef __i386__ 2573 /* 2574 * On the x86 we do not have alignment problems, so try to 2575 * allocate a new buffer for the receive ring, and pass up 2576 * the one where the packet is already, saving the expensive 2577 * copy done in m_devget(). 2578 * If we are on an architecture with alignment problems, or 2579 * if the allocation fails, then use m_devget and leave the 2580 * existing buffer in the receive ring. 2581 */ 2582 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2583 m->m_pkthdr.rcvif = ifp; 2584 m->m_pkthdr.len = m->m_len = total_len; 2585 DC_INC(i, DC_RX_LIST_CNT); 2586 } else 2587 #endif 2588 { 2589 struct mbuf *m0; 2590 2591 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2592 total_len + ETHER_ALIGN, 0, ifp, NULL); 2593 dc_newbuf(sc, i, m); 2594 DC_INC(i, DC_RX_LIST_CNT); 2595 if (m0 == NULL) { 2596 ifp->if_ierrors++; 2597 continue; 2598 } 2599 m_adj(m0, ETHER_ALIGN); 2600 m = m0; 2601 } 2602 2603 ifp->if_ipackets++; 2604 eh = mtod(m, struct ether_header *); 2605 2606 /* Remove header from mbuf and pass it on. */ 2607 m_adj(m, sizeof(struct ether_header)); 2608 ether_input(ifp, eh, m); 2609 } 2610 2611 sc->dc_cdata.dc_rx_prod = i; 2612 } 2613 2614 /* 2615 * A frame was downloaded to the chip. It's safe for us to clean up 2616 * the list buffers. 2617 */ 2618 2619 static void 2620 dc_txeof(sc) 2621 struct dc_softc *sc; 2622 { 2623 struct dc_desc *cur_tx = NULL; 2624 struct ifnet *ifp; 2625 int idx; 2626 2627 ifp = &sc->arpcom.ac_if; 2628 2629 /* 2630 * Go through our tx list and free mbufs for those 2631 * frames that have been transmitted. 2632 */ 2633 idx = sc->dc_cdata.dc_tx_cons; 2634 while(idx != sc->dc_cdata.dc_tx_prod) { 2635 u_int32_t txstat; 2636 2637 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2638 txstat = cur_tx->dc_status; 2639 2640 if (txstat & DC_TXSTAT_OWN) 2641 break; 2642 2643 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2644 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2645 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2646 /* 2647 * Yes, the PNIC is so brain damaged 2648 * that it will sometimes generate a TX 2649 * underrun error while DMAing the RX 2650 * filter setup frame. If we detect this, 2651 * we have to send the setup frame again, 2652 * or else the filter won't be programmed 2653 * correctly. 2654 */ 2655 if (DC_IS_PNIC(sc)) { 2656 if (txstat & DC_TXSTAT_ERRSUM) 2657 dc_setfilt(sc); 2658 } 2659 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2660 } 2661 sc->dc_cdata.dc_tx_cnt--; 2662 DC_INC(idx, DC_TX_LIST_CNT); 2663 continue; 2664 } 2665 2666 if (DC_IS_CONEXANT(sc)) { 2667 /* 2668 * For some reason Conexant chips like 2669 * setting the CARRLOST flag even when 2670 * the carrier is there. In CURRENT we 2671 * have the same problem for Xircom 2672 * cards ! 2673 */ 2674 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2675 sc->dc_pmode == DC_PMODE_MII && 2676 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2677 DC_TXSTAT_NOCARRIER))) 2678 txstat &= ~DC_TXSTAT_ERRSUM; 2679 } else { 2680 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2681 sc->dc_pmode == DC_PMODE_MII && 2682 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2683 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2684 txstat &= ~DC_TXSTAT_ERRSUM; 2685 } 2686 2687 if (txstat & DC_TXSTAT_ERRSUM) { 2688 ifp->if_oerrors++; 2689 if (txstat & DC_TXSTAT_EXCESSCOLL) 2690 ifp->if_collisions++; 2691 if (txstat & DC_TXSTAT_LATECOLL) 2692 ifp->if_collisions++; 2693 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2694 dc_init(sc); 2695 return; 2696 } 2697 } 2698 2699 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2700 2701 ifp->if_opackets++; 2702 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2703 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2704 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2705 } 2706 2707 sc->dc_cdata.dc_tx_cnt--; 2708 DC_INC(idx, DC_TX_LIST_CNT); 2709 } 2710 2711 if (idx != sc->dc_cdata.dc_tx_cons) { 2712 /* some buffers have been freed */ 2713 sc->dc_cdata.dc_tx_cons = idx; 2714 ifp->if_flags &= ~IFF_OACTIVE; 2715 } 2716 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2717 2718 return; 2719 } 2720 2721 static void dc_tick(xsc) 2722 void *xsc; 2723 { 2724 struct dc_softc *sc; 2725 struct mii_data *mii; 2726 struct ifnet *ifp; 2727 int s; 2728 u_int32_t r; 2729 2730 s = splimp(); 2731 2732 sc = xsc; 2733 ifp = &sc->arpcom.ac_if; 2734 mii = device_get_softc(sc->dc_miibus); 2735 2736 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2737 if (sc->dc_flags & DC_21143_NWAY) { 2738 r = CSR_READ_4(sc, DC_10BTSTAT); 2739 if (IFM_SUBTYPE(mii->mii_media_active) == 2740 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2741 sc->dc_link = 0; 2742 mii_mediachg(mii); 2743 } 2744 if (IFM_SUBTYPE(mii->mii_media_active) == 2745 IFM_10_T && (r & DC_TSTAT_LS10)) { 2746 sc->dc_link = 0; 2747 mii_mediachg(mii); 2748 } 2749 if (sc->dc_link == 0) 2750 mii_tick(mii); 2751 } else { 2752 r = CSR_READ_4(sc, DC_ISR); 2753 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2754 sc->dc_cdata.dc_tx_cnt == 0) 2755 mii_tick(mii); 2756 if (!(mii->mii_media_status & IFM_ACTIVE)) 2757 sc->dc_link = 0; 2758 } 2759 } else 2760 mii_tick(mii); 2761 2762 /* 2763 * When the init routine completes, we expect to be able to send 2764 * packets right away, and in fact the network code will send a 2765 * gratuitous ARP the moment the init routine marks the interface 2766 * as running. However, even though the MAC may have been initialized, 2767 * there may be a delay of a few seconds before the PHY completes 2768 * autonegotiation and the link is brought up. Any transmissions 2769 * made during that delay will be lost. Dealing with this is tricky: 2770 * we can't just pause in the init routine while waiting for the 2771 * PHY to come ready since that would bring the whole system to 2772 * a screeching halt for several seconds. 2773 * 2774 * What we do here is prevent the TX start routine from sending 2775 * any packets until a link has been established. After the 2776 * interface has been initialized, the tick routine will poll 2777 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2778 * that time, packets will stay in the send queue, and once the 2779 * link comes up, they will be flushed out to the wire. 2780 */ 2781 if (!sc->dc_link) { 2782 mii_pollstat(mii); 2783 if (mii->mii_media_status & IFM_ACTIVE && 2784 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2785 sc->dc_link++; 2786 if (ifp->if_snd.ifq_head != NULL) 2787 dc_start(ifp); 2788 } 2789 } 2790 2791 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2792 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 2793 else 2794 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2795 2796 splx(s); 2797 2798 return; 2799 } 2800 2801 /* 2802 * A transmit underrun has occurred. Back off the transmit threshold, 2803 * or switch to store and forward mode if we have to. 2804 */ 2805 static void dc_tx_underrun(sc) 2806 struct dc_softc *sc; 2807 { 2808 u_int32_t isr; 2809 int i; 2810 2811 if (DC_IS_DAVICOM(sc)) 2812 dc_init(sc); 2813 2814 if (DC_IS_INTEL(sc)) { 2815 /* 2816 * The real 21143 requires that the transmitter be idle 2817 * in order to change the transmit threshold or store 2818 * and forward state. 2819 */ 2820 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2821 2822 for (i = 0; i < DC_TIMEOUT; i++) { 2823 isr = CSR_READ_4(sc, DC_ISR); 2824 if (isr & DC_ISR_TX_IDLE) 2825 break; 2826 DELAY(10); 2827 } 2828 if (i == DC_TIMEOUT) { 2829 printf("dc%d: failed to force tx to idle state\n", 2830 sc->dc_unit); 2831 dc_init(sc); 2832 } 2833 } 2834 2835 printf("dc%d: TX underrun -- ", sc->dc_unit); 2836 sc->dc_txthresh += DC_TXTHRESH_INC; 2837 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2838 printf("using store and forward mode\n"); 2839 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2840 } else { 2841 printf("increasing TX threshold\n"); 2842 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2843 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2844 } 2845 2846 if (DC_IS_INTEL(sc)) 2847 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2848 2849 return; 2850 } 2851 2852 #ifdef DEVICE_POLLING 2853 static poll_handler_t dc_poll; 2854 2855 static void 2856 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2857 { 2858 struct dc_softc *sc = ifp->if_softc; 2859 2860 if (!(ifp->if_capenable & IFCAP_POLLING)) { 2861 ether_poll_deregister(ifp); 2862 cmd = POLL_DEREGISTER; 2863 } 2864 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2865 /* Re-enable interrupts. */ 2866 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2867 return; 2868 } 2869 sc->rxcycles = count; 2870 dc_rxeof(sc); 2871 dc_txeof(sc); 2872 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2873 dc_start(ifp); 2874 2875 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2876 u_int32_t status; 2877 2878 status = CSR_READ_4(sc, DC_ISR); 2879 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2880 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2881 DC_ISR_BUS_ERR); 2882 if (!status) 2883 return ; 2884 /* ack what we have */ 2885 CSR_WRITE_4(sc, DC_ISR, status); 2886 2887 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) { 2888 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2889 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2890 2891 if (dc_rx_resync(sc)) 2892 dc_rxeof(sc); 2893 } 2894 /* restart transmit unit if necessary */ 2895 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2896 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2897 2898 if (status & DC_ISR_TX_UNDERRUN) 2899 dc_tx_underrun(sc); 2900 2901 if (status & DC_ISR_BUS_ERR) { 2902 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 2903 dc_reset(sc); 2904 dc_init(sc); 2905 } 2906 } 2907 } 2908 #endif /* DEVICE_POLLING */ 2909 2910 static void dc_intr(arg) 2911 void *arg; 2912 { 2913 struct dc_softc *sc; 2914 struct ifnet *ifp; 2915 u_int32_t status; 2916 2917 sc = arg; 2918 2919 if (sc->suspended) { 2920 return; 2921 } 2922 2923 ifp = &sc->arpcom.ac_if; 2924 2925 #ifdef DEVICE_POLLING 2926 if (ifp->if_ipending & IFF_POLLING) 2927 return; 2928 if ((ifp->if_capenable & IFCAP_POLLING) && 2929 ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 2930 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2931 return; 2932 } 2933 #endif /* DEVICE_POLLING */ 2934 2935 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2936 return ; 2937 2938 /* Suppress unwanted interrupts */ 2939 if (!(ifp->if_flags & IFF_UP)) { 2940 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2941 dc_stop(sc); 2942 return; 2943 } 2944 2945 /* Disable interrupts. */ 2946 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2947 2948 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2949 2950 CSR_WRITE_4(sc, DC_ISR, status); 2951 2952 if (status & DC_ISR_RX_OK) { 2953 int curpkts; 2954 curpkts = ifp->if_ipackets; 2955 dc_rxeof(sc); 2956 if (curpkts == ifp->if_ipackets) { 2957 while(dc_rx_resync(sc)) 2958 dc_rxeof(sc); 2959 } 2960 } 2961 2962 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2963 dc_txeof(sc); 2964 2965 if (status & DC_ISR_TX_IDLE) { 2966 dc_txeof(sc); 2967 if (sc->dc_cdata.dc_tx_cnt) { 2968 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2969 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2970 } 2971 } 2972 2973 if (status & DC_ISR_TX_UNDERRUN) 2974 dc_tx_underrun(sc); 2975 2976 if ((status & DC_ISR_RX_WATDOGTIMEO) 2977 || (status & DC_ISR_RX_NOBUF)) { 2978 int curpkts; 2979 curpkts = ifp->if_ipackets; 2980 dc_rxeof(sc); 2981 if (curpkts == ifp->if_ipackets) { 2982 while(dc_rx_resync(sc)) 2983 dc_rxeof(sc); 2984 } 2985 } 2986 2987 if (status & DC_ISR_BUS_ERR) { 2988 dc_reset(sc); 2989 dc_init(sc); 2990 } 2991 } 2992 2993 /* Re-enable interrupts. */ 2994 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2995 2996 if (ifp->if_snd.ifq_head != NULL) 2997 dc_start(ifp); 2998 2999 return; 3000 } 3001 3002 /* 3003 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3004 * pointers to the fragment pointers. 3005 */ 3006 static int dc_encap(sc, m_head, txidx) 3007 struct dc_softc *sc; 3008 struct mbuf **m_head; 3009 u_int32_t *txidx; 3010 { 3011 struct dc_desc *f = NULL; 3012 struct mbuf *m; 3013 int frag, cur, cnt = 0, chainlen = 0; 3014 3015 /* 3016 * If there's no way we can send any packets, return now. 3017 */ 3018 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3019 return (ENOBUFS); 3020 3021 /* 3022 * Count the number of frags in this chain to see if 3023 * we need to m_defrag. Since the descriptor list is shared 3024 * by all packets, we'll m_defrag long chains so that they 3025 * do not use up the entire list, even if they would fit. 3026 */ 3027 3028 for (m = *m_head; m != NULL; m = m->m_next) 3029 chainlen++; 3030 3031 if ((chainlen > DC_TX_LIST_CNT / 4) || 3032 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3033 m = m_defrag(*m_head, M_DONTWAIT); 3034 if (m == NULL) 3035 return (ENOBUFS); 3036 *m_head = m; 3037 } 3038 3039 /* 3040 * Start packing the mbufs in this chain into 3041 * the fragment pointers. Stop when we run out 3042 * of fragments or hit the end of the mbuf chain. 3043 */ 3044 m = *m_head; 3045 cur = frag = *txidx; 3046 3047 for (m = *m_head; m != NULL; m = m->m_next) { 3048 if (m->m_len != 0) { 3049 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 3050 if (*txidx != sc->dc_cdata.dc_tx_prod && 3051 frag == (DC_TX_LIST_CNT - 1)) 3052 return(ENOBUFS); 3053 } 3054 if ((DC_TX_LIST_CNT - 3055 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3056 return(ENOBUFS); 3057 3058 f = &sc->dc_ldata->dc_tx_list[frag]; 3059 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3060 if (cnt == 0) { 3061 f->dc_status = 0; 3062 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3063 } else 3064 f->dc_status = DC_TXSTAT_OWN; 3065 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3066 cur = frag; 3067 DC_INC(frag, DC_TX_LIST_CNT); 3068 cnt++; 3069 } 3070 } 3071 3072 if (m != NULL) 3073 return(ENOBUFS); 3074 3075 sc->dc_cdata.dc_tx_cnt += cnt; 3076 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3077 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3078 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3079 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3080 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3081 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3082 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3083 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3084 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3085 *txidx = frag; 3086 3087 return(0); 3088 } 3089 3090 /* 3091 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3092 * to the mbuf data regions directly in the transmit lists. We also save a 3093 * copy of the pointers since the transmit list fragment pointers are 3094 * physical addresses. 3095 */ 3096 3097 static void dc_start(ifp) 3098 struct ifnet *ifp; 3099 { 3100 struct dc_softc *sc; 3101 struct mbuf *m_head = NULL, *m; 3102 int idx; 3103 3104 sc = ifp->if_softc; 3105 3106 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3107 return; 3108 3109 if (ifp->if_flags & IFF_OACTIVE) 3110 return; 3111 3112 idx = sc->dc_cdata.dc_tx_prod; 3113 3114 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3115 IF_DEQUEUE(&ifp->if_snd, m_head); 3116 if (m_head == NULL) 3117 break; 3118 3119 if (sc->dc_flags & DC_TX_COALESCE && 3120 (m_head->m_next != NULL || 3121 sc->dc_flags & DC_TX_ALIGN)) { 3122 m = m_defrag(m_head, M_DONTWAIT); 3123 if (m == NULL) { 3124 IF_PREPEND(&ifp->if_snd, m_head); 3125 ifp->if_flags |= IFF_OACTIVE; 3126 break; 3127 } else { 3128 m_head = m; 3129 } 3130 } 3131 3132 if (dc_encap(sc, &m_head, &idx)) { 3133 IF_PREPEND(&ifp->if_snd, m_head); 3134 ifp->if_flags |= IFF_OACTIVE; 3135 break; 3136 } 3137 3138 /* 3139 * If there's a BPF listener, bounce a copy of this frame 3140 * to him. 3141 */ 3142 if (ifp->if_bpf) 3143 bpf_mtap(ifp, m_head); 3144 3145 if (sc->dc_flags & DC_TX_ONE) { 3146 ifp->if_flags |= IFF_OACTIVE; 3147 break; 3148 } 3149 } 3150 3151 /* Transmit */ 3152 sc->dc_cdata.dc_tx_prod = idx; 3153 if (!(sc->dc_flags & DC_TX_POLL)) 3154 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3155 3156 /* 3157 * Set a timeout in case the chip goes out to lunch. 3158 */ 3159 ifp->if_timer = 5; 3160 3161 return; 3162 } 3163 3164 static void dc_init(xsc) 3165 void *xsc; 3166 { 3167 struct dc_softc *sc = xsc; 3168 struct ifnet *ifp = &sc->arpcom.ac_if; 3169 struct mii_data *mii; 3170 int s; 3171 3172 s = splimp(); 3173 3174 mii = device_get_softc(sc->dc_miibus); 3175 3176 /* 3177 * Cancel pending I/O and free all RX/TX buffers. 3178 */ 3179 dc_stop(sc); 3180 dc_reset(sc); 3181 3182 /* 3183 * Set cache alignment and burst length. 3184 */ 3185 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3186 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3187 else 3188 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3189 /* 3190 * Evenly share the bus between receive and transmit process. 3191 */ 3192 if (DC_IS_INTEL(sc)) 3193 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3194 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3195 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3196 } else { 3197 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3198 } 3199 if (sc->dc_flags & DC_TX_POLL) 3200 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3201 switch(sc->dc_cachesize) { 3202 case 32: 3203 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3204 break; 3205 case 16: 3206 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3207 break; 3208 case 8: 3209 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3210 break; 3211 case 0: 3212 default: 3213 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3214 break; 3215 } 3216 3217 if (sc->dc_flags & DC_TX_STORENFWD) 3218 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3219 else { 3220 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3221 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3222 } else { 3223 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3224 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3225 } 3226 } 3227 3228 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3229 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3230 3231 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3232 /* 3233 * The app notes for the 98713 and 98715A say that 3234 * in order to have the chips operate properly, a magic 3235 * number must be written to CSR16. Macronix does not 3236 * document the meaning of these bits so there's no way 3237 * to know exactly what they do. The 98713 has a magic 3238 * number all its own; the rest all use a different one. 3239 */ 3240 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3241 if (sc->dc_type == DC_TYPE_98713) 3242 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3243 else 3244 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3245 } 3246 3247 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3248 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3249 3250 /* Init circular RX list. */ 3251 if (dc_list_rx_init(sc) == ENOBUFS) { 3252 printf("dc%d: initialization failed: no " 3253 "memory for rx buffers\n", sc->dc_unit); 3254 dc_stop(sc); 3255 (void)splx(s); 3256 return; 3257 } 3258 3259 /* 3260 * Init tx descriptors. 3261 */ 3262 dc_list_tx_init(sc); 3263 3264 /* 3265 * Load the address of the RX list. 3266 */ 3267 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3268 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3269 3270 /* 3271 * Enable interrupts. 3272 */ 3273 #ifdef DEVICE_POLLING 3274 /* 3275 * ... but only if we are not polling, and make sure they are off in 3276 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3277 * after a reset. 3278 */ 3279 if (ifp->if_ipending & IFF_POLLING) 3280 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3281 else 3282 #endif 3283 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3284 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3285 3286 /* Enable transmitter. */ 3287 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3288 3289 /* 3290 * If this is an Intel 21143 and we're not using the 3291 * MII port, program the LED control pins so we get 3292 * link and activity indications. 3293 */ 3294 if (sc->dc_flags & DC_TULIP_LEDS) { 3295 CSR_WRITE_4(sc, DC_WATCHDOG, 3296 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3297 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3298 } 3299 3300 /* 3301 * Load the RX/multicast filter. We do this sort of late 3302 * because the filter programming scheme on the 21143 and 3303 * some clones requires DMAing a setup frame via the TX 3304 * engine, and we need the transmitter enabled for that. 3305 */ 3306 dc_setfilt(sc); 3307 3308 /* Enable receiver. */ 3309 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3310 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3311 3312 mii_mediachg(mii); 3313 dc_setcfg(sc, sc->dc_if_media); 3314 3315 ifp->if_flags |= IFF_RUNNING; 3316 ifp->if_flags &= ~IFF_OACTIVE; 3317 3318 (void)splx(s); 3319 3320 /* Don't start the ticker if this is a homePNA link. */ 3321 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3322 sc->dc_link = 1; 3323 else { 3324 if (sc->dc_flags & DC_21143_NWAY) 3325 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 3326 else 3327 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 3328 } 3329 3330 #ifdef SRM_MEDIA 3331 if(sc->dc_srm_media) { 3332 struct ifreq ifr; 3333 3334 ifr.ifr_media = sc->dc_srm_media; 3335 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3336 sc->dc_srm_media = 0; 3337 } 3338 #endif 3339 return; 3340 } 3341 3342 /* 3343 * Set media options. 3344 */ 3345 static int dc_ifmedia_upd(ifp) 3346 struct ifnet *ifp; 3347 { 3348 struct dc_softc *sc; 3349 struct mii_data *mii; 3350 struct ifmedia *ifm; 3351 3352 sc = ifp->if_softc; 3353 mii = device_get_softc(sc->dc_miibus); 3354 mii_mediachg(mii); 3355 ifm = &mii->mii_media; 3356 3357 if (DC_IS_DAVICOM(sc) && 3358 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3359 dc_setcfg(sc, ifm->ifm_media); 3360 else 3361 sc->dc_link = 0; 3362 3363 return(0); 3364 } 3365 3366 /* 3367 * Report current media status. 3368 */ 3369 static void dc_ifmedia_sts(ifp, ifmr) 3370 struct ifnet *ifp; 3371 struct ifmediareq *ifmr; 3372 { 3373 struct dc_softc *sc; 3374 struct mii_data *mii; 3375 struct ifmedia *ifm; 3376 3377 sc = ifp->if_softc; 3378 mii = device_get_softc(sc->dc_miibus); 3379 mii_pollstat(mii); 3380 ifm = &mii->mii_media; 3381 if (DC_IS_DAVICOM(sc)) { 3382 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3383 ifmr->ifm_active = ifm->ifm_media; 3384 ifmr->ifm_status = 0; 3385 return; 3386 } 3387 } 3388 ifmr->ifm_active = mii->mii_media_active; 3389 ifmr->ifm_status = mii->mii_media_status; 3390 3391 return; 3392 } 3393 3394 static int dc_ioctl(ifp, command, data) 3395 struct ifnet *ifp; 3396 u_long command; 3397 caddr_t data; 3398 { 3399 struct dc_softc *sc = ifp->if_softc; 3400 struct ifreq *ifr = (struct ifreq *) data; 3401 struct mii_data *mii; 3402 int s, error = 0; 3403 3404 s = splimp(); 3405 3406 switch(command) { 3407 case SIOCSIFADDR: 3408 case SIOCGIFADDR: 3409 case SIOCSIFMTU: 3410 error = ether_ioctl(ifp, command, data); 3411 break; 3412 case SIOCSIFFLAGS: 3413 if (ifp->if_flags & IFF_UP) { 3414 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3415 (IFF_PROMISC | IFF_ALLMULTI); 3416 if (ifp->if_flags & IFF_RUNNING) { 3417 if (need_setfilt) 3418 dc_setfilt(sc); 3419 } else { 3420 sc->dc_txthresh = 0; 3421 dc_init(sc); 3422 } 3423 } else { 3424 if (ifp->if_flags & IFF_RUNNING) 3425 dc_stop(sc); 3426 } 3427 sc->dc_if_flags = ifp->if_flags; 3428 error = 0; 3429 break; 3430 case SIOCADDMULTI: 3431 case SIOCDELMULTI: 3432 dc_setfilt(sc); 3433 error = 0; 3434 break; 3435 case SIOCGIFMEDIA: 3436 case SIOCSIFMEDIA: 3437 mii = device_get_softc(sc->dc_miibus); 3438 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3439 #ifdef SRM_MEDIA 3440 if (sc->dc_srm_media) 3441 sc->dc_srm_media = 0; 3442 #endif 3443 break; 3444 case SIOCSIFCAP: 3445 ifp->if_capenable = ifr->ifr_reqcap; 3446 break; 3447 default: 3448 error = EINVAL; 3449 break; 3450 } 3451 3452 (void)splx(s); 3453 3454 return(error); 3455 } 3456 3457 static void dc_watchdog(ifp) 3458 struct ifnet *ifp; 3459 { 3460 struct dc_softc *sc; 3461 3462 sc = ifp->if_softc; 3463 3464 ifp->if_oerrors++; 3465 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3466 3467 dc_stop(sc); 3468 dc_reset(sc); 3469 dc_init(sc); 3470 3471 if (ifp->if_snd.ifq_head != NULL) 3472 dc_start(ifp); 3473 3474 return; 3475 } 3476 3477 /* 3478 * Stop the adapter and free any mbufs allocated to the 3479 * RX and TX lists. 3480 */ 3481 static void dc_stop(sc) 3482 struct dc_softc *sc; 3483 { 3484 register int i; 3485 struct ifnet *ifp; 3486 3487 ifp = &sc->arpcom.ac_if; 3488 ifp->if_timer = 0; 3489 3490 untimeout(dc_tick, sc, sc->dc_stat_ch); 3491 3492 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3493 #ifdef DEVICE_POLLING 3494 ether_poll_deregister(ifp); 3495 #endif 3496 3497 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3498 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3499 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3500 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3501 sc->dc_link = 0; 3502 3503 /* 3504 * Free data in the RX lists. 3505 */ 3506 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3507 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3508 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3509 sc->dc_cdata.dc_rx_chain[i] = NULL; 3510 } 3511 } 3512 bzero((char *)&sc->dc_ldata->dc_rx_list, 3513 sizeof(sc->dc_ldata->dc_rx_list)); 3514 3515 /* 3516 * Free the TX list buffers. 3517 */ 3518 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3519 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3520 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl & 3521 DC_TXCTL_SETUP) || 3522 !(sc->dc_ldata->dc_tx_list[i].dc_ctl & 3523 DC_TXCTL_LASTFRAG)) { 3524 sc->dc_cdata.dc_tx_chain[i] = NULL; 3525 continue; 3526 } 3527 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3528 sc->dc_cdata.dc_tx_chain[i] = NULL; 3529 } 3530 } 3531 3532 bzero((char *)&sc->dc_ldata->dc_tx_list, 3533 sizeof(sc->dc_ldata->dc_tx_list)); 3534 3535 return; 3536 } 3537 3538 /* 3539 * Stop all chip I/O so that the kernel's probe routines don't 3540 * get confused by errant DMAs when rebooting. 3541 */ 3542 static void dc_shutdown(dev) 3543 device_t dev; 3544 { 3545 struct dc_softc *sc; 3546 3547 sc = device_get_softc(dev); 3548 3549 dc_stop(sc); 3550 3551 return; 3552 } 3553 3554 /* 3555 * Device suspend routine. Stop the interface and save some PCI 3556 * settings in case the BIOS doesn't restore them properly on 3557 * resume. 3558 */ 3559 static int dc_suspend(dev) 3560 device_t dev; 3561 { 3562 register int i; 3563 int s; 3564 struct dc_softc *sc; 3565 3566 s = splimp(); 3567 3568 sc = device_get_softc(dev); 3569 3570 dc_stop(sc); 3571 3572 for (i = 0; i < 5; i++) 3573 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3574 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3575 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3576 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3577 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3578 3579 sc->suspended = 1; 3580 3581 splx(s); 3582 return (0); 3583 } 3584 3585 /* 3586 * Device resume routine. Restore some PCI settings in case the BIOS 3587 * doesn't, re-enable busmastering, and restart the interface if 3588 * appropriate. 3589 */ 3590 static int dc_resume(dev) 3591 device_t dev; 3592 { 3593 register int i; 3594 int s; 3595 struct dc_softc *sc; 3596 struct ifnet *ifp; 3597 3598 s = splimp(); 3599 3600 sc = device_get_softc(dev); 3601 ifp = &sc->arpcom.ac_if; 3602 3603 dc_acpi(dev); 3604 3605 /* better way to do this? */ 3606 for (i = 0; i < 5; i++) 3607 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3608 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3609 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3610 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3611 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3612 3613 /* reenable busmastering */ 3614 pci_enable_busmaster(dev); 3615 pci_enable_io(dev, DC_RES); 3616 3617 /* reinitialize interface if necessary */ 3618 if (ifp->if_flags & IFF_UP) 3619 dc_init(sc); 3620 3621 sc->suspended = 0; 3622 3623 splx(s); 3624 return (0); 3625 }
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