FreeBSD/Linux Kernel Cross Reference
sys/pci/if_dc.c
1 /*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: releng/5.0/sys/pci/if_dc.c 107302 2002-11-27 07:04:10Z imp $
33 */
34
35 /*
36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
37 * series chips and several workalikes including the following:
38 *
39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
41 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
42 * ASIX Electronics AX88140A (www.asix.com.tw)
43 * ASIX Electronics AX88141 (www.asix.com.tw)
44 * ADMtek AL981 (www.admtek.com.tw)
45 * ADMtek AN985 (www.admtek.com.tw)
46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
47 * Accton EN1217 (www.accton.com)
48 * Xircom X3201 (www.xircom.com)
49 * Abocom FE2500
50 * Conexant LANfinity (www.conexant.com)
51 *
52 * Datasheets for the 21143 are available at developer.intel.com.
53 * Datasheets for the clone parts can be found at their respective sites.
54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
55 * The PNIC II is essentially a Macronix 98715A chip; the only difference
56 * worth noting is that its multicast hash table is only 128 bits wide
57 * instead of 512.
58 *
59 * Written by Bill Paul <wpaul@ee.columbia.edu>
60 * Electrical Engineering Department
61 * Columbia University, New York City
62 */
63
64 /*
65 * The Intel 21143 is the successor to the DEC 21140. It is basically
66 * the same as the 21140 but with a few new features. The 21143 supports
67 * three kinds of media attachments:
68 *
69 * o MII port, for 10Mbps and 100Mbps support and NWAY
70 * autonegotiation provided by an external PHY.
71 * o SYM port, for symbol mode 100Mbps support.
72 * o 10baseT port.
73 * o AUI/BNC port.
74 *
75 * The 100Mbps SYM port and 10baseT port can be used together in
76 * combination with the internal NWAY support to create a 10/100
77 * autosensing configuration.
78 *
79 * Note that not all tulip workalikes are handled in this driver: we only
80 * deal with those which are relatively well behaved. The Winbond is
81 * handled separately due to its different register offsets and the
82 * special handling needed for its various bugs. The PNIC is handled
83 * here, but I'm not thrilled about it.
84 *
85 * All of the workalike chips use some form of MII transceiver support
86 * with the exception of the Macronix chips, which also have a SYM port.
87 * The ASIX AX88140A is also documented to have a SYM port, but all
88 * the cards I've seen use an MII transceiver, probably because the
89 * AX88140A doesn't support internal NWAY.
90 */
91
92 #include <sys/param.h>
93 #include <sys/systm.h>
94 #include <sys/sockio.h>
95 #include <sys/mbuf.h>
96 #include <sys/malloc.h>
97 #include <sys/kernel.h>
98 #include <sys/socket.h>
99 #include <sys/sysctl.h>
100
101 #include <net/if.h>
102 #include <net/if_arp.h>
103 #include <net/ethernet.h>
104 #include <net/if_dl.h>
105 #include <net/if_media.h>
106 #include <net/if_types.h>
107 #include <net/if_vlan_var.h>
108
109 #include <net/bpf.h>
110
111 #include <vm/vm.h> /* for vtophys */
112 #include <vm/pmap.h> /* for vtophys */
113 #include <machine/bus_pio.h>
114 #include <machine/bus_memio.h>
115 #include <machine/bus.h>
116 #include <machine/resource.h>
117 #include <sys/bus.h>
118 #include <sys/rman.h>
119
120 #include <dev/mii/mii.h>
121 #include <dev/mii/miivar.h>
122
123 #include <pci/pcireg.h>
124 #include <pci/pcivar.h>
125
126 #define DC_USEIOSPACE
127 #ifdef __alpha__
128 #define SRM_MEDIA
129 #endif
130
131 #include <pci/if_dcreg.h>
132
133 MODULE_DEPEND(dc, miibus, 1, 1, 1);
134
135 /* "controller miibus0" required. See GENERIC if you get errors here. */
136 #include "miibus_if.h"
137
138 #ifndef lint
139 static const char rcsid[] =
140 "$FreeBSD: releng/5.0/sys/pci/if_dc.c 107302 2002-11-27 07:04:10Z imp $";
141 #endif
142
143 /*
144 * Various supported device vendors/types and their names.
145 */
146 static struct dc_type dc_devs[] = {
147 { DC_VENDORID_DEC, DC_DEVICEID_21143,
148 "Intel 21143 10/100BaseTX" },
149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
150 "Davicom DM9100 10/100BaseTX" },
151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
152 "Davicom DM9102 10/100BaseTX" },
153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
154 "Davicom DM9102A 10/100BaseTX" },
155 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
156 "ADMtek AL981 10/100BaseTX" },
157 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
158 "ADMtek AN985 10/100BaseTX" },
159 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
160 "ASIX AX88140A 10/100BaseTX" },
161 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
162 "ASIX AX88141 10/100BaseTX" },
163 { DC_VENDORID_MX, DC_DEVICEID_98713,
164 "Macronix 98713 10/100BaseTX" },
165 { DC_VENDORID_MX, DC_DEVICEID_98713,
166 "Macronix 98713A 10/100BaseTX" },
167 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
168 "Compex RL100-TX 10/100BaseTX" },
169 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
170 "Compex RL100-TX 10/100BaseTX" },
171 { DC_VENDORID_MX, DC_DEVICEID_987x5,
172 "Macronix 98715/98715A 10/100BaseTX" },
173 { DC_VENDORID_MX, DC_DEVICEID_987x5,
174 "Macronix 98715AEC-C 10/100BaseTX" },
175 { DC_VENDORID_MX, DC_DEVICEID_987x5,
176 "Macronix 98725 10/100BaseTX" },
177 { DC_VENDORID_MX, DC_DEVICEID_98727,
178 "Macronix 98727/98732 10/100BaseTX" },
179 { DC_VENDORID_LO, DC_DEVICEID_82C115,
180 "LC82C115 PNIC II 10/100BaseTX" },
181 { DC_VENDORID_LO, DC_DEVICEID_82C168,
182 "82c168 PNIC 10/100BaseTX" },
183 { DC_VENDORID_LO, DC_DEVICEID_82C168,
184 "82c169 PNIC 10/100BaseTX" },
185 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
186 "Accton EN1217 10/100BaseTX" },
187 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
188 "Accton EN2242 MiniPCI 10/100BaseTX" },
189 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201,
190 "Xircom X3201 10/100BaseTX" },
191 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500,
192 "Abocom FE2500 10/100BaseTX" },
193 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
194 "Conexant LANfinity MiniPCI 10/100BaseTX" },
195 { 0, 0, NULL }
196 };
197
198 static int dc_probe (device_t);
199 static int dc_attach (device_t);
200 static int dc_detach (device_t);
201 static int dc_suspend (device_t);
202 static int dc_resume (device_t);
203 static void dc_acpi (device_t);
204 static struct dc_type *dc_devtype (device_t);
205 static int dc_newbuf (struct dc_softc *, int, struct mbuf *);
206 static int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *);
207 static int dc_coal (struct dc_softc *, struct mbuf **);
208 static void dc_pnic_rx_bug_war (struct dc_softc *, int);
209 static int dc_rx_resync (struct dc_softc *);
210 static void dc_rxeof (struct dc_softc *);
211 static void dc_txeof (struct dc_softc *);
212 static void dc_tick (void *);
213 static void dc_tx_underrun (struct dc_softc *);
214 static void dc_intr (void *);
215 static void dc_start (struct ifnet *);
216 static int dc_ioctl (struct ifnet *, u_long, caddr_t);
217 static void dc_init (void *);
218 static void dc_stop (struct dc_softc *);
219 static void dc_watchdog (struct ifnet *);
220 static void dc_shutdown (device_t);
221 static int dc_ifmedia_upd (struct ifnet *);
222 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *);
223
224 static void dc_delay (struct dc_softc *);
225 static void dc_eeprom_idle (struct dc_softc *);
226 static void dc_eeprom_putbyte (struct dc_softc *, int);
227 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *);
228 static void dc_eeprom_getword_pnic
229 (struct dc_softc *, int, u_int16_t *);
230 static void dc_eeprom_getword_xircom
231 (struct dc_softc *, int, u_int16_t *);
232 static void dc_eeprom_width (struct dc_softc *);
233 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int);
234
235 static void dc_mii_writebit (struct dc_softc *, int);
236 static int dc_mii_readbit (struct dc_softc *);
237 static void dc_mii_sync (struct dc_softc *);
238 static void dc_mii_send (struct dc_softc *, u_int32_t, int);
239 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *);
240 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *);
241 static int dc_miibus_readreg (device_t, int, int);
242 static int dc_miibus_writereg (device_t, int, int, int);
243 static void dc_miibus_statchg (device_t);
244 static void dc_miibus_mediainit (device_t);
245
246 static void dc_setcfg (struct dc_softc *, int);
247 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t);
248 static u_int32_t dc_crc_be (caddr_t);
249 static void dc_setfilt_21143 (struct dc_softc *);
250 static void dc_setfilt_asix (struct dc_softc *);
251 static void dc_setfilt_admtek (struct dc_softc *);
252 static void dc_setfilt_xircom (struct dc_softc *);
253
254 static void dc_setfilt (struct dc_softc *);
255
256 static void dc_reset (struct dc_softc *);
257 static int dc_list_rx_init (struct dc_softc *);
258 static int dc_list_tx_init (struct dc_softc *);
259
260 static void dc_read_srom (struct dc_softc *, int);
261 static void dc_parse_21143_srom (struct dc_softc *);
262 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *);
263 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *);
264 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *);
265 static void dc_apply_fixup (struct dc_softc *, int);
266
267 #ifdef DC_USEIOSPACE
268 #define DC_RES SYS_RES_IOPORT
269 #define DC_RID DC_PCI_CFBIO
270 #else
271 #define DC_RES SYS_RES_MEMORY
272 #define DC_RID DC_PCI_CFBMA
273 #endif
274
275 static device_method_t dc_methods[] = {
276 /* Device interface */
277 DEVMETHOD(device_probe, dc_probe),
278 DEVMETHOD(device_attach, dc_attach),
279 DEVMETHOD(device_detach, dc_detach),
280 DEVMETHOD(device_suspend, dc_suspend),
281 DEVMETHOD(device_resume, dc_resume),
282 DEVMETHOD(device_shutdown, dc_shutdown),
283
284 /* bus interface */
285 DEVMETHOD(bus_print_child, bus_generic_print_child),
286 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
287
288 /* MII interface */
289 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
290 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
291 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
292 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
293
294 { 0, 0 }
295 };
296
297 static driver_t dc_driver = {
298 "dc",
299 dc_methods,
300 sizeof(struct dc_softc)
301 };
302
303 static devclass_t dc_devclass;
304 #ifdef __i386__
305 static int dc_quick=1;
306 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
307 &dc_quick,0,"do not mdevget in dc driver");
308 #endif
309
310 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0);
311 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
312 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
313
314 #define DC_SETBIT(sc, reg, x) \
315 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
316
317 #define DC_CLRBIT(sc, reg, x) \
318 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
319
320 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
321 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
322
323 #define IS_MPSAFE 0
324
325 static void
326 dc_delay(sc)
327 struct dc_softc *sc;
328 {
329 int idx;
330
331 for (idx = (300 / 33) + 1; idx > 0; idx--)
332 CSR_READ_4(sc, DC_BUSCTL);
333 }
334
335 static void
336 dc_eeprom_width(sc)
337 struct dc_softc *sc;
338 {
339 int i;
340
341 /* Force EEPROM to idle state. */
342 dc_eeprom_idle(sc);
343
344 /* Enter EEPROM access mode. */
345 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
346 dc_delay(sc);
347 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
348 dc_delay(sc);
349 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
350 dc_delay(sc);
351 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
352 dc_delay(sc);
353
354 for (i = 3; i--;) {
355 if (6 & (1 << i))
356 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
357 else
358 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
359 dc_delay(sc);
360 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
361 dc_delay(sc);
362 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
363 dc_delay(sc);
364 }
365
366 for (i = 1; i <= 12; i++) {
367 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
368 dc_delay(sc);
369 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
370 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
371 dc_delay(sc);
372 break;
373 }
374 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
375 dc_delay(sc);
376 }
377
378 /* Turn off EEPROM access mode. */
379 dc_eeprom_idle(sc);
380
381 if (i < 4 || i > 12)
382 sc->dc_romwidth = 6;
383 else
384 sc->dc_romwidth = i;
385
386 /* Enter EEPROM access mode. */
387 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
388 dc_delay(sc);
389 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
390 dc_delay(sc);
391 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
392 dc_delay(sc);
393 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
394 dc_delay(sc);
395
396 /* Turn off EEPROM access mode. */
397 dc_eeprom_idle(sc);
398 }
399
400 static void
401 dc_eeprom_idle(sc)
402 struct dc_softc *sc;
403 {
404 register int i;
405
406 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
407 dc_delay(sc);
408 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
409 dc_delay(sc);
410 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
411 dc_delay(sc);
412 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
413 dc_delay(sc);
414
415 for (i = 0; i < 25; i++) {
416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
417 dc_delay(sc);
418 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
419 dc_delay(sc);
420 }
421
422 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
423 dc_delay(sc);
424 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
425 dc_delay(sc);
426 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
427
428 return;
429 }
430
431 /*
432 * Send a read command and address to the EEPROM, check for ACK.
433 */
434 static void
435 dc_eeprom_putbyte(sc, addr)
436 struct dc_softc *sc;
437 int addr;
438 {
439 register int d, i;
440
441 d = DC_EECMD_READ >> 6;
442 for (i = 3; i--; ) {
443 if (d & (1 << i))
444 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
445 else
446 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
447 dc_delay(sc);
448 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
449 dc_delay(sc);
450 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
451 dc_delay(sc);
452 }
453
454 /*
455 * Feed in each bit and strobe the clock.
456 */
457 for (i = sc->dc_romwidth; i--;) {
458 if (addr & (1 << i)) {
459 SIO_SET(DC_SIO_EE_DATAIN);
460 } else {
461 SIO_CLR(DC_SIO_EE_DATAIN);
462 }
463 dc_delay(sc);
464 SIO_SET(DC_SIO_EE_CLK);
465 dc_delay(sc);
466 SIO_CLR(DC_SIO_EE_CLK);
467 dc_delay(sc);
468 }
469
470 return;
471 }
472
473 /*
474 * Read a word of data stored in the EEPROM at address 'addr.'
475 * The PNIC 82c168/82c169 has its own non-standard way to read
476 * the EEPROM.
477 */
478 static void
479 dc_eeprom_getword_pnic(sc, addr, dest)
480 struct dc_softc *sc;
481 int addr;
482 u_int16_t *dest;
483 {
484 register int i;
485 u_int32_t r;
486
487 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr);
488
489 for (i = 0; i < DC_TIMEOUT; i++) {
490 DELAY(1);
491 r = CSR_READ_4(sc, DC_SIO);
492 if (!(r & DC_PN_SIOCTL_BUSY)) {
493 *dest = (u_int16_t)(r & 0xFFFF);
494 return;
495 }
496 }
497
498 return;
499 }
500
501 /*
502 * Read a word of data stored in the EEPROM at address 'addr.'
503 * The Xircom X3201 has its own non-standard way to read
504 * the EEPROM, too.
505 */
506 static void
507 dc_eeprom_getword_xircom(sc, addr, dest)
508 struct dc_softc *sc;
509 int addr;
510 u_int16_t *dest;
511 {
512 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
513
514 addr *= 2;
515 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
516 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff;
517 addr += 1;
518 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
519 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8;
520
521 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
522 return;
523 }
524
525 /*
526 * Read a word of data stored in the EEPROM at address 'addr.'
527 */
528 static void
529 dc_eeprom_getword(sc, addr, dest)
530 struct dc_softc *sc;
531 int addr;
532 u_int16_t *dest;
533 {
534 register int i;
535 u_int16_t word = 0;
536
537 /* Force EEPROM to idle state. */
538 dc_eeprom_idle(sc);
539
540 /* Enter EEPROM access mode. */
541 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
542 dc_delay(sc);
543 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
544 dc_delay(sc);
545 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
546 dc_delay(sc);
547 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
548 dc_delay(sc);
549
550 /*
551 * Send address of word we want to read.
552 */
553 dc_eeprom_putbyte(sc, addr);
554
555 /*
556 * Start reading bits from EEPROM.
557 */
558 for (i = 0x8000; i; i >>= 1) {
559 SIO_SET(DC_SIO_EE_CLK);
560 dc_delay(sc);
561 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
562 word |= i;
563 dc_delay(sc);
564 SIO_CLR(DC_SIO_EE_CLK);
565 dc_delay(sc);
566 }
567
568 /* Turn off EEPROM access mode. */
569 dc_eeprom_idle(sc);
570
571 *dest = word;
572
573 return;
574 }
575
576 /*
577 * Read a sequence of words from the EEPROM.
578 */
579 static void
580 dc_read_eeprom(sc, dest, off, cnt, swap)
581 struct dc_softc *sc;
582 caddr_t dest;
583 int off;
584 int cnt;
585 int swap;
586 {
587 int i;
588 u_int16_t word = 0, *ptr;
589
590 for (i = 0; i < cnt; i++) {
591 if (DC_IS_PNIC(sc))
592 dc_eeprom_getword_pnic(sc, off + i, &word);
593 else if (DC_IS_XIRCOM(sc))
594 dc_eeprom_getword_xircom(sc, off + i, &word);
595 else
596 dc_eeprom_getword(sc, off + i, &word);
597 ptr = (u_int16_t *)(dest + (i * 2));
598 if (swap)
599 *ptr = ntohs(word);
600 else
601 *ptr = word;
602 }
603
604 return;
605 }
606
607 /*
608 * The following two routines are taken from the Macronix 98713
609 * Application Notes pp.19-21.
610 */
611 /*
612 * Write a bit to the MII bus.
613 */
614 static void
615 dc_mii_writebit(sc, bit)
616 struct dc_softc *sc;
617 int bit;
618 {
619 if (bit)
620 CSR_WRITE_4(sc, DC_SIO,
621 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT);
622 else
623 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
624
625 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
626 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
627
628 return;
629 }
630
631 /*
632 * Read a bit from the MII bus.
633 */
634 static int
635 dc_mii_readbit(sc)
636 struct dc_softc *sc;
637 {
638 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR);
639 CSR_READ_4(sc, DC_SIO);
640 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
641 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
642 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
643 return(1);
644
645 return(0);
646 }
647
648 /*
649 * Sync the PHYs by setting data bit and strobing the clock 32 times.
650 */
651 static void
652 dc_mii_sync(sc)
653 struct dc_softc *sc;
654 {
655 register int i;
656
657 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
658
659 for (i = 0; i < 32; i++)
660 dc_mii_writebit(sc, 1);
661
662 return;
663 }
664
665 /*
666 * Clock a series of bits through the MII.
667 */
668 static void
669 dc_mii_send(sc, bits, cnt)
670 struct dc_softc *sc;
671 u_int32_t bits;
672 int cnt;
673 {
674 int i;
675
676 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
677 dc_mii_writebit(sc, bits & i);
678 }
679
680 /*
681 * Read an PHY register through the MII.
682 */
683 static int
684 dc_mii_readreg(sc, frame)
685 struct dc_softc *sc;
686 struct dc_mii_frame *frame;
687
688 {
689 int i, ack;
690
691 DC_LOCK(sc);
692
693 /*
694 * Set up frame for RX.
695 */
696 frame->mii_stdelim = DC_MII_STARTDELIM;
697 frame->mii_opcode = DC_MII_READOP;
698 frame->mii_turnaround = 0;
699 frame->mii_data = 0;
700
701 /*
702 * Sync the PHYs.
703 */
704 dc_mii_sync(sc);
705
706 /*
707 * Send command/address info.
708 */
709 dc_mii_send(sc, frame->mii_stdelim, 2);
710 dc_mii_send(sc, frame->mii_opcode, 2);
711 dc_mii_send(sc, frame->mii_phyaddr, 5);
712 dc_mii_send(sc, frame->mii_regaddr, 5);
713
714 #ifdef notdef
715 /* Idle bit */
716 dc_mii_writebit(sc, 1);
717 dc_mii_writebit(sc, 0);
718 #endif
719
720 /* Check for ack */
721 ack = dc_mii_readbit(sc);
722
723 /*
724 * Now try reading data bits. If the ack failed, we still
725 * need to clock through 16 cycles to keep the PHY(s) in sync.
726 */
727 if (ack) {
728 for(i = 0; i < 16; i++) {
729 dc_mii_readbit(sc);
730 }
731 goto fail;
732 }
733
734 for (i = 0x8000; i; i >>= 1) {
735 if (!ack) {
736 if (dc_mii_readbit(sc))
737 frame->mii_data |= i;
738 }
739 }
740
741 fail:
742
743 dc_mii_writebit(sc, 0);
744 dc_mii_writebit(sc, 0);
745
746 DC_UNLOCK(sc);
747
748 if (ack)
749 return(1);
750 return(0);
751 }
752
753 /*
754 * Write to a PHY register through the MII.
755 */
756 static int
757 dc_mii_writereg(sc, frame)
758 struct dc_softc *sc;
759 struct dc_mii_frame *frame;
760
761 {
762 DC_LOCK(sc);
763 /*
764 * Set up frame for TX.
765 */
766
767 frame->mii_stdelim = DC_MII_STARTDELIM;
768 frame->mii_opcode = DC_MII_WRITEOP;
769 frame->mii_turnaround = DC_MII_TURNAROUND;
770
771 /*
772 * Sync the PHYs.
773 */
774 dc_mii_sync(sc);
775
776 dc_mii_send(sc, frame->mii_stdelim, 2);
777 dc_mii_send(sc, frame->mii_opcode, 2);
778 dc_mii_send(sc, frame->mii_phyaddr, 5);
779 dc_mii_send(sc, frame->mii_regaddr, 5);
780 dc_mii_send(sc, frame->mii_turnaround, 2);
781 dc_mii_send(sc, frame->mii_data, 16);
782
783 /* Idle bit. */
784 dc_mii_writebit(sc, 0);
785 dc_mii_writebit(sc, 0);
786
787 DC_UNLOCK(sc);
788
789 return(0);
790 }
791
792 static int
793 dc_miibus_readreg(dev, phy, reg)
794 device_t dev;
795 int phy, reg;
796 {
797 struct dc_mii_frame frame;
798 struct dc_softc *sc;
799 int i, rval, phy_reg = 0;
800
801 sc = device_get_softc(dev);
802 bzero((char *)&frame, sizeof(frame));
803
804 /*
805 * Note: both the AL981 and AN985 have internal PHYs,
806 * however the AL981 provides direct access to the PHY
807 * registers while the AN985 uses a serial MII interface.
808 * The AN985's MII interface is also buggy in that you
809 * can read from any MII address (0 to 31), but only address 1
810 * behaves normally. To deal with both cases, we pretend
811 * that the PHY is at MII address 1.
812 */
813 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
814 return(0);
815
816 /*
817 * Note: the ukphy probes of the RS7112 report a PHY at
818 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
819 * so we only respond to correct one.
820 */
821 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
822 return(0);
823
824 if (sc->dc_pmode != DC_PMODE_MII) {
825 if (phy == (MII_NPHY - 1)) {
826 switch(reg) {
827 case MII_BMSR:
828 /*
829 * Fake something to make the probe
830 * code think there's a PHY here.
831 */
832 return(BMSR_MEDIAMASK);
833 break;
834 case MII_PHYIDR1:
835 if (DC_IS_PNIC(sc))
836 return(DC_VENDORID_LO);
837 return(DC_VENDORID_DEC);
838 break;
839 case MII_PHYIDR2:
840 if (DC_IS_PNIC(sc))
841 return(DC_DEVICEID_82C168);
842 return(DC_DEVICEID_21143);
843 break;
844 default:
845 return(0);
846 break;
847 }
848 } else
849 return(0);
850 }
851
852 if (DC_IS_PNIC(sc)) {
853 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
854 (phy << 23) | (reg << 18));
855 for (i = 0; i < DC_TIMEOUT; i++) {
856 DELAY(1);
857 rval = CSR_READ_4(sc, DC_PN_MII);
858 if (!(rval & DC_PN_MII_BUSY)) {
859 rval &= 0xFFFF;
860 return(rval == 0xFFFF ? 0 : rval);
861 }
862 }
863 return(0);
864 }
865
866 if (DC_IS_COMET(sc)) {
867 switch(reg) {
868 case MII_BMCR:
869 phy_reg = DC_AL_BMCR;
870 break;
871 case MII_BMSR:
872 phy_reg = DC_AL_BMSR;
873 break;
874 case MII_PHYIDR1:
875 phy_reg = DC_AL_VENID;
876 break;
877 case MII_PHYIDR2:
878 phy_reg = DC_AL_DEVID;
879 break;
880 case MII_ANAR:
881 phy_reg = DC_AL_ANAR;
882 break;
883 case MII_ANLPAR:
884 phy_reg = DC_AL_LPAR;
885 break;
886 case MII_ANER:
887 phy_reg = DC_AL_ANER;
888 break;
889 default:
890 printf("dc%d: phy_read: bad phy register %x\n",
891 sc->dc_unit, reg);
892 return(0);
893 break;
894 }
895
896 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
897
898 if (rval == 0xFFFF)
899 return(0);
900 return(rval);
901 }
902
903 frame.mii_phyaddr = phy;
904 frame.mii_regaddr = reg;
905 if (sc->dc_type == DC_TYPE_98713) {
906 phy_reg = CSR_READ_4(sc, DC_NETCFG);
907 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
908 }
909 dc_mii_readreg(sc, &frame);
910 if (sc->dc_type == DC_TYPE_98713)
911 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
912
913 return(frame.mii_data);
914 }
915
916 static int
917 dc_miibus_writereg(dev, phy, reg, data)
918 device_t dev;
919 int phy, reg, data;
920 {
921 struct dc_softc *sc;
922 struct dc_mii_frame frame;
923 int i, phy_reg = 0;
924
925 sc = device_get_softc(dev);
926 bzero((char *)&frame, sizeof(frame));
927
928 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
929 return(0);
930
931 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
932 return(0);
933
934 if (DC_IS_PNIC(sc)) {
935 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
936 (phy << 23) | (reg << 10) | data);
937 for (i = 0; i < DC_TIMEOUT; i++) {
938 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
939 break;
940 }
941 return(0);
942 }
943
944 if (DC_IS_COMET(sc)) {
945 switch(reg) {
946 case MII_BMCR:
947 phy_reg = DC_AL_BMCR;
948 break;
949 case MII_BMSR:
950 phy_reg = DC_AL_BMSR;
951 break;
952 case MII_PHYIDR1:
953 phy_reg = DC_AL_VENID;
954 break;
955 case MII_PHYIDR2:
956 phy_reg = DC_AL_DEVID;
957 break;
958 case MII_ANAR:
959 phy_reg = DC_AL_ANAR;
960 break;
961 case MII_ANLPAR:
962 phy_reg = DC_AL_LPAR;
963 break;
964 case MII_ANER:
965 phy_reg = DC_AL_ANER;
966 break;
967 default:
968 printf("dc%d: phy_write: bad phy register %x\n",
969 sc->dc_unit, reg);
970 return(0);
971 break;
972 }
973
974 CSR_WRITE_4(sc, phy_reg, data);
975 return(0);
976 }
977
978 frame.mii_phyaddr = phy;
979 frame.mii_regaddr = reg;
980 frame.mii_data = data;
981
982 if (sc->dc_type == DC_TYPE_98713) {
983 phy_reg = CSR_READ_4(sc, DC_NETCFG);
984 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
985 }
986 dc_mii_writereg(sc, &frame);
987 if (sc->dc_type == DC_TYPE_98713)
988 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
989
990 return(0);
991 }
992
993 static void
994 dc_miibus_statchg(dev)
995 device_t dev;
996 {
997 struct dc_softc *sc;
998 struct mii_data *mii;
999 struct ifmedia *ifm;
1000
1001 sc = device_get_softc(dev);
1002 if (DC_IS_ADMTEK(sc))
1003 return;
1004
1005 mii = device_get_softc(sc->dc_miibus);
1006 ifm = &mii->mii_media;
1007 if (DC_IS_DAVICOM(sc) &&
1008 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
1009 dc_setcfg(sc, ifm->ifm_media);
1010 sc->dc_if_media = ifm->ifm_media;
1011 } else {
1012 dc_setcfg(sc, mii->mii_media_active);
1013 sc->dc_if_media = mii->mii_media_active;
1014 }
1015
1016 return;
1017 }
1018
1019 /*
1020 * Special support for DM9102A cards with HomePNA PHYs. Note:
1021 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
1022 * to be impossible to talk to the management interface of the DM9801
1023 * PHY (its MDIO pin is not connected to anything). Consequently,
1024 * the driver has to just 'know' about the additional mode and deal
1025 * with it itself. *sigh*
1026 */
1027 static void
1028 dc_miibus_mediainit(dev)
1029 device_t dev;
1030 {
1031 struct dc_softc *sc;
1032 struct mii_data *mii;
1033 struct ifmedia *ifm;
1034 int rev;
1035
1036 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1037
1038 sc = device_get_softc(dev);
1039 mii = device_get_softc(sc->dc_miibus);
1040 ifm = &mii->mii_media;
1041
1042 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1043 ifmedia_add(ifm, IFM_ETHER|IFM_HPNA_1, 0, NULL);
1044
1045 return;
1046 }
1047
1048 #define DC_POLY 0xEDB88320
1049 #define DC_BITS_512 9
1050 #define DC_BITS_128 7
1051 #define DC_BITS_64 6
1052
1053 static u_int32_t
1054 dc_crc_le(sc, addr)
1055 struct dc_softc *sc;
1056 caddr_t addr;
1057 {
1058 u_int32_t idx, bit, data, crc;
1059
1060 /* Compute CRC for the address value. */
1061 crc = 0xFFFFFFFF; /* initial value */
1062
1063 for (idx = 0; idx < 6; idx++) {
1064 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
1065 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
1066 }
1067
1068 /*
1069 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1070 * chips is only 128 bits wide.
1071 */
1072 if (sc->dc_flags & DC_128BIT_HASH)
1073 return (crc & ((1 << DC_BITS_128) - 1));
1074
1075 /* The hash table on the MX98715BEC is only 64 bits wide. */
1076 if (sc->dc_flags & DC_64BIT_HASH)
1077 return (crc & ((1 << DC_BITS_64) - 1));
1078
1079 /* Xircom's hash filtering table is different (read: weird) */
1080 /* Xircom uses the LEAST significant bits */
1081 if (DC_IS_XIRCOM(sc)) {
1082 if ((crc & 0x180) == 0x180)
1083 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4);
1084 else
1085 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4);
1086 }
1087
1088 return (crc & ((1 << DC_BITS_512) - 1));
1089 }
1090
1091 /*
1092 * Calculate CRC of a multicast group address, return the lower 6 bits.
1093 */
1094 static u_int32_t
1095 dc_crc_be(addr)
1096 caddr_t addr;
1097 {
1098 u_int32_t crc, carry;
1099 int i, j;
1100 u_int8_t c;
1101
1102 /* Compute CRC for the address value. */
1103 crc = 0xFFFFFFFF; /* initial value */
1104
1105 for (i = 0; i < 6; i++) {
1106 c = *(addr + i);
1107 for (j = 0; j < 8; j++) {
1108 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
1109 crc <<= 1;
1110 c >>= 1;
1111 if (carry)
1112 crc = (crc ^ 0x04c11db6) | carry;
1113 }
1114 }
1115
1116 /* return the filter bit position */
1117 return((crc >> 26) & 0x0000003F);
1118 }
1119
1120 /*
1121 * 21143-style RX filter setup routine. Filter programming is done by
1122 * downloading a special setup frame into the TX engine. 21143, Macronix,
1123 * PNIC, PNIC II and Davicom chips are programmed this way.
1124 *
1125 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1126 * address (our node address) and a 512-bit hash filter for multicast
1127 * frames. We also sneak the broadcast address into the hash filter since
1128 * we need that too.
1129 */
1130 static void
1131 dc_setfilt_21143(sc)
1132 struct dc_softc *sc;
1133 {
1134 struct dc_desc *sframe;
1135 u_int32_t h, *sp;
1136 struct ifmultiaddr *ifma;
1137 struct ifnet *ifp;
1138 int i;
1139
1140 ifp = &sc->arpcom.ac_if;
1141
1142 i = sc->dc_cdata.dc_tx_prod;
1143 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1144 sc->dc_cdata.dc_tx_cnt++;
1145 sframe = &sc->dc_ldata->dc_tx_list[i];
1146 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1147 bzero((char *)sp, DC_SFRAME_LEN);
1148
1149 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1150 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1151 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1152
1153 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1154
1155 /* If we want promiscuous mode, set the allframes bit. */
1156 if (ifp->if_flags & IFF_PROMISC)
1157 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1158 else
1159 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1160
1161 if (ifp->if_flags & IFF_ALLMULTI)
1162 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1163 else
1164 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1165
1166 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1167 if (ifma->ifma_addr->sa_family != AF_LINK)
1168 continue;
1169 h = dc_crc_le(sc,
1170 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1171 sp[h >> 4] |= 1 << (h & 0xF);
1172 }
1173
1174 if (ifp->if_flags & IFF_BROADCAST) {
1175 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr);
1176 sp[h >> 4] |= 1 << (h & 0xF);
1177 }
1178
1179 /* Set our MAC address */
1180 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1181 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1182 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1183
1184 sframe->dc_status = DC_TXSTAT_OWN;
1185 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1186
1187 /*
1188 * The PNIC takes an exceedingly long time to process its
1189 * setup frame; wait 10ms after posting the setup frame
1190 * before proceeding, just so it has time to swallow its
1191 * medicine.
1192 */
1193 DELAY(10000);
1194
1195 ifp->if_timer = 5;
1196
1197 return;
1198 }
1199
1200 static void
1201 dc_setfilt_admtek(sc)
1202 struct dc_softc *sc;
1203 {
1204 struct ifnet *ifp;
1205 int h = 0;
1206 u_int32_t hashes[2] = { 0, 0 };
1207 struct ifmultiaddr *ifma;
1208
1209 ifp = &sc->arpcom.ac_if;
1210
1211 /* Init our MAC address */
1212 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1213 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1214
1215 /* If we want promiscuous mode, set the allframes bit. */
1216 if (ifp->if_flags & IFF_PROMISC)
1217 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1218 else
1219 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1220
1221 if (ifp->if_flags & IFF_ALLMULTI)
1222 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1223 else
1224 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1225
1226 /* first, zot all the existing hash bits */
1227 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1228 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1229
1230 /*
1231 * If we're already in promisc or allmulti mode, we
1232 * don't have to bother programming the multicast filter.
1233 */
1234 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1235 return;
1236
1237 /* now program new ones */
1238 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1239 if (ifma->ifma_addr->sa_family != AF_LINK)
1240 continue;
1241 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1242 if (h < 32)
1243 hashes[0] |= (1 << h);
1244 else
1245 hashes[1] |= (1 << (h - 32));
1246 }
1247
1248 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1249 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1250
1251 return;
1252 }
1253
1254 static void
1255 dc_setfilt_asix(sc)
1256 struct dc_softc *sc;
1257 {
1258 struct ifnet *ifp;
1259 int h = 0;
1260 u_int32_t hashes[2] = { 0, 0 };
1261 struct ifmultiaddr *ifma;
1262
1263 ifp = &sc->arpcom.ac_if;
1264
1265 /* Init our MAC address */
1266 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1267 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1268 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1269 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1270 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1271 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1272
1273 /* If we want promiscuous mode, set the allframes bit. */
1274 if (ifp->if_flags & IFF_PROMISC)
1275 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1276 else
1277 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1278
1279 if (ifp->if_flags & IFF_ALLMULTI)
1280 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1281 else
1282 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1283
1284 /*
1285 * The ASIX chip has a special bit to enable reception
1286 * of broadcast frames.
1287 */
1288 if (ifp->if_flags & IFF_BROADCAST)
1289 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1290 else
1291 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1292
1293 /* first, zot all the existing hash bits */
1294 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1295 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1296 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1297 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1298
1299 /*
1300 * If we're already in promisc or allmulti mode, we
1301 * don't have to bother programming the multicast filter.
1302 */
1303 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1304 return;
1305
1306 /* now program new ones */
1307 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1308 if (ifma->ifma_addr->sa_family != AF_LINK)
1309 continue;
1310 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1311 if (h < 32)
1312 hashes[0] |= (1 << h);
1313 else
1314 hashes[1] |= (1 << (h - 32));
1315 }
1316
1317 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1318 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1319 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1320 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1321
1322 return;
1323 }
1324
1325 static void
1326 dc_setfilt_xircom(sc)
1327 struct dc_softc *sc;
1328 {
1329 struct dc_desc *sframe;
1330 u_int32_t h, *sp;
1331 struct ifmultiaddr *ifma;
1332 struct ifnet *ifp;
1333 int i;
1334
1335 ifp = &sc->arpcom.ac_if;
1336 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1337
1338 i = sc->dc_cdata.dc_tx_prod;
1339 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1340 sc->dc_cdata.dc_tx_cnt++;
1341 sframe = &sc->dc_ldata->dc_tx_list[i];
1342 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1343 bzero((char *)sp, DC_SFRAME_LEN);
1344
1345 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1346 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1347 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1348
1349 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1350
1351 /* If we want promiscuous mode, set the allframes bit. */
1352 if (ifp->if_flags & IFF_PROMISC)
1353 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1354 else
1355 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1356
1357 if (ifp->if_flags & IFF_ALLMULTI)
1358 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1359 else
1360 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1361
1362 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1363 if (ifma->ifma_addr->sa_family != AF_LINK)
1364 continue;
1365 h = dc_crc_le(sc,
1366 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1367 sp[h >> 4] |= 1 << (h & 0xF);
1368 }
1369
1370 if (ifp->if_flags & IFF_BROADCAST) {
1371 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr);
1372 sp[h >> 4] |= 1 << (h & 0xF);
1373 }
1374
1375 /* Set our MAC address */
1376 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1377 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1378 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1379
1380 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1381 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1382 ifp->if_flags |= IFF_RUNNING;
1383 sframe->dc_status = DC_TXSTAT_OWN;
1384 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1385
1386 /*
1387 * wait some time...
1388 */
1389 DELAY(1000);
1390
1391 ifp->if_timer = 5;
1392
1393 return;
1394 }
1395
1396 static void
1397 dc_setfilt(sc)
1398 struct dc_softc *sc;
1399 {
1400 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1401 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1402 dc_setfilt_21143(sc);
1403
1404 if (DC_IS_ASIX(sc))
1405 dc_setfilt_asix(sc);
1406
1407 if (DC_IS_ADMTEK(sc))
1408 dc_setfilt_admtek(sc);
1409
1410 if (DC_IS_XIRCOM(sc))
1411 dc_setfilt_xircom(sc);
1412
1413 return;
1414 }
1415
1416 /*
1417 * In order to fiddle with the
1418 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
1419 * first have to put the transmit and/or receive logic in the idle state.
1420 */
1421 static void
1422 dc_setcfg(sc, media)
1423 struct dc_softc *sc;
1424 int media;
1425 {
1426 int i, restart = 0;
1427 u_int32_t isr;
1428
1429 if (IFM_SUBTYPE(media) == IFM_NONE)
1430 return;
1431
1432 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {
1433 restart = 1;
1434 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1435
1436 for (i = 0; i < DC_TIMEOUT; i++) {
1437 isr = CSR_READ_4(sc, DC_ISR);
1438 if (isr & DC_ISR_TX_IDLE &&
1439 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1440 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1441 break;
1442 DELAY(10);
1443 }
1444
1445 if (i == DC_TIMEOUT)
1446 printf("dc%d: failed to force tx and "
1447 "rx to idle state\n", sc->dc_unit);
1448 }
1449
1450 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1451 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1452 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1453 if (sc->dc_pmode == DC_PMODE_MII) {
1454 int watchdogreg;
1455
1456 if (DC_IS_INTEL(sc)) {
1457 /* there's a write enable bit here that reads as 1 */
1458 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1459 watchdogreg &= ~DC_WDOG_CTLWREN;
1460 watchdogreg |= DC_WDOG_JABBERDIS;
1461 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1462 } else {
1463 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1464 }
1465 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1466 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1467 if (sc->dc_type == DC_TYPE_98713)
1468 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1469 DC_NETCFG_SCRAMBLER));
1470 if (!DC_IS_DAVICOM(sc))
1471 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1472 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1473 if (DC_IS_INTEL(sc))
1474 dc_apply_fixup(sc, IFM_AUTO);
1475 } else {
1476 if (DC_IS_PNIC(sc)) {
1477 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1478 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1479 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1480 }
1481 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1482 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1483 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1484 if (DC_IS_INTEL(sc))
1485 dc_apply_fixup(sc,
1486 (media & IFM_GMASK) == IFM_FDX ?
1487 IFM_100_TX|IFM_FDX : IFM_100_TX);
1488 }
1489 }
1490
1491 if (IFM_SUBTYPE(media) == IFM_10_T) {
1492 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1493 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1494 if (sc->dc_pmode == DC_PMODE_MII) {
1495 int watchdogreg;
1496
1497 /* there's a write enable bit here that reads as 1 */
1498 if (DC_IS_INTEL(sc)) {
1499 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1500 watchdogreg &= ~DC_WDOG_CTLWREN;
1501 watchdogreg |= DC_WDOG_JABBERDIS;
1502 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1503 } else {
1504 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1505 }
1506 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1507 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1508 if (sc->dc_type == DC_TYPE_98713)
1509 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1510 if (!DC_IS_DAVICOM(sc))
1511 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1512 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1513 if (DC_IS_INTEL(sc))
1514 dc_apply_fixup(sc, IFM_AUTO);
1515 } else {
1516 if (DC_IS_PNIC(sc)) {
1517 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1518 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1519 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1520 }
1521 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1522 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1523 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1524 if (DC_IS_INTEL(sc)) {
1525 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1526 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1527 if ((media & IFM_GMASK) == IFM_FDX)
1528 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1529 else
1530 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1531 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1532 DC_CLRBIT(sc, DC_10BTCTRL,
1533 DC_TCTL_AUTONEGENBL);
1534 dc_apply_fixup(sc,
1535 (media & IFM_GMASK) == IFM_FDX ?
1536 IFM_10_T|IFM_FDX : IFM_10_T);
1537 DELAY(20000);
1538 }
1539 }
1540 }
1541
1542 /*
1543 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1544 * PHY and we want HomePNA mode, set the portsel bit to turn
1545 * on the external MII port.
1546 */
1547 if (DC_IS_DAVICOM(sc)) {
1548 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1549 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1550 sc->dc_link = 1;
1551 } else {
1552 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1553 }
1554 }
1555
1556 if (DC_IS_ADMTEK(sc))
1557 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
1558
1559 if ((media & IFM_GMASK) == IFM_FDX) {
1560 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1561 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1562 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1563 } else {
1564 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1565 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1566 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1567 }
1568
1569 if (restart)
1570 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON);
1571
1572 return;
1573 }
1574
1575 static void
1576 dc_reset(sc)
1577 struct dc_softc *sc;
1578 {
1579 register int i;
1580
1581 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1582
1583 for (i = 0; i < DC_TIMEOUT; i++) {
1584 DELAY(10);
1585 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1586 break;
1587 }
1588
1589 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) ||
1590 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) {
1591 DELAY(10000);
1592 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1593 i = 0;
1594 }
1595
1596 if (i == DC_TIMEOUT)
1597 printf("dc%d: reset never completed!\n", sc->dc_unit);
1598
1599 /* Wait a little while for the chip to get its brains in order. */
1600 DELAY(1000);
1601
1602 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1603 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1604 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1605
1606 /*
1607 * Bring the SIA out of reset. In some cases, it looks
1608 * like failing to unreset the SIA soon enough gets it
1609 * into a state where it will never come out of reset
1610 * until we reset the whole chip again.
1611 */
1612 if (DC_IS_INTEL(sc)) {
1613 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1614 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1615 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1616 }
1617
1618 return;
1619 }
1620
1621 static struct dc_type *
1622 dc_devtype(dev)
1623 device_t dev;
1624 {
1625 struct dc_type *t;
1626 u_int32_t rev;
1627
1628 t = dc_devs;
1629
1630 while(t->dc_name != NULL) {
1631 if ((pci_get_vendor(dev) == t->dc_vid) &&
1632 (pci_get_device(dev) == t->dc_did)) {
1633 /* Check the PCI revision */
1634 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1635 if (t->dc_did == DC_DEVICEID_98713 &&
1636 rev >= DC_REVISION_98713A)
1637 t++;
1638 if (t->dc_did == DC_DEVICEID_98713_CP &&
1639 rev >= DC_REVISION_98713A)
1640 t++;
1641 if (t->dc_did == DC_DEVICEID_987x5 &&
1642 rev >= DC_REVISION_98715AEC_C)
1643 t++;
1644 if (t->dc_did == DC_DEVICEID_987x5 &&
1645 rev >= DC_REVISION_98725)
1646 t++;
1647 if (t->dc_did == DC_DEVICEID_AX88140A &&
1648 rev >= DC_REVISION_88141)
1649 t++;
1650 if (t->dc_did == DC_DEVICEID_82C168 &&
1651 rev >= DC_REVISION_82C169)
1652 t++;
1653 if (t->dc_did == DC_DEVICEID_DM9102 &&
1654 rev >= DC_REVISION_DM9102A)
1655 t++;
1656 return(t);
1657 }
1658 t++;
1659 }
1660
1661 return(NULL);
1662 }
1663
1664 /*
1665 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1666 * IDs against our list and return a device name if we find a match.
1667 * We do a little bit of extra work to identify the exact type of
1668 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1669 * but different revision IDs. The same is true for 98715/98715A
1670 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1671 * cases, the exact chip revision affects driver behavior.
1672 */
1673 static int
1674 dc_probe(dev)
1675 device_t dev;
1676 {
1677 struct dc_type *t;
1678
1679 t = dc_devtype(dev);
1680
1681 if (t != NULL) {
1682 device_set_desc(dev, t->dc_name);
1683 return(0);
1684 }
1685
1686 return(ENXIO);
1687 }
1688
1689 static void
1690 dc_acpi(dev)
1691 device_t dev;
1692 {
1693 int unit;
1694
1695 unit = device_get_unit(dev);
1696
1697 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1698 u_int32_t iobase, membase, irq;
1699
1700 /* Save important PCI config data. */
1701 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1702 membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1703 irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1704
1705 /* Reset the power state. */
1706 printf("dc%d: chip is in D%d power mode "
1707 "-- setting to D0\n", unit,
1708 pci_get_powerstate(dev));
1709 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1710
1711 /* Restore PCI config data. */
1712 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1713 pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1714 pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1715 }
1716
1717 return;
1718 }
1719
1720 static void
1721 dc_apply_fixup(sc, media)
1722 struct dc_softc *sc;
1723 int media;
1724 {
1725 struct dc_mediainfo *m;
1726 u_int8_t *p;
1727 int i;
1728 u_int32_t reg;
1729
1730 m = sc->dc_mi;
1731
1732 while (m != NULL) {
1733 if (m->dc_media == media)
1734 break;
1735 m = m->dc_next;
1736 }
1737
1738 if (m == NULL)
1739 return;
1740
1741 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1742 reg = (p[0] | (p[1] << 8)) << 16;
1743 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1744 }
1745
1746 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1747 reg = (p[0] | (p[1] << 8)) << 16;
1748 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1749 }
1750
1751 return;
1752 }
1753
1754 static void
1755 dc_decode_leaf_sia(sc, l)
1756 struct dc_softc *sc;
1757 struct dc_eblock_sia *l;
1758 {
1759 struct dc_mediainfo *m;
1760
1761 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1762 bzero(m, sizeof(struct dc_mediainfo));
1763 if (l->dc_sia_code == DC_SIA_CODE_10BT)
1764 m->dc_media = IFM_10_T;
1765
1766 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX)
1767 m->dc_media = IFM_10_T|IFM_FDX;
1768
1769 if (l->dc_sia_code == DC_SIA_CODE_10B2)
1770 m->dc_media = IFM_10_2;
1771
1772 if (l->dc_sia_code == DC_SIA_CODE_10B5)
1773 m->dc_media = IFM_10_5;
1774
1775 m->dc_gp_len = 2;
1776 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl;
1777
1778 m->dc_next = sc->dc_mi;
1779 sc->dc_mi = m;
1780
1781 sc->dc_pmode = DC_PMODE_SIA;
1782
1783 return;
1784 }
1785
1786 static void
1787 dc_decode_leaf_sym(sc, l)
1788 struct dc_softc *sc;
1789 struct dc_eblock_sym *l;
1790 {
1791 struct dc_mediainfo *m;
1792
1793 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1794 bzero(m, sizeof(struct dc_mediainfo));
1795 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1796 m->dc_media = IFM_100_TX;
1797
1798 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1799 m->dc_media = IFM_100_TX|IFM_FDX;
1800
1801 m->dc_gp_len = 2;
1802 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1803
1804 m->dc_next = sc->dc_mi;
1805 sc->dc_mi = m;
1806
1807 sc->dc_pmode = DC_PMODE_SYM;
1808
1809 return;
1810 }
1811
1812 static void
1813 dc_decode_leaf_mii(sc, l)
1814 struct dc_softc *sc;
1815 struct dc_eblock_mii *l;
1816 {
1817 u_int8_t *p;
1818 struct dc_mediainfo *m;
1819
1820 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1821 bzero(m, sizeof(struct dc_mediainfo));
1822 /* We abuse IFM_AUTO to represent MII. */
1823 m->dc_media = IFM_AUTO;
1824 m->dc_gp_len = l->dc_gpr_len;
1825
1826 p = (u_int8_t *)l;
1827 p += sizeof(struct dc_eblock_mii);
1828 m->dc_gp_ptr = p;
1829 p += 2 * l->dc_gpr_len;
1830 m->dc_reset_len = *p;
1831 p++;
1832 m->dc_reset_ptr = p;
1833
1834 m->dc_next = sc->dc_mi;
1835 sc->dc_mi = m;
1836
1837 return;
1838 }
1839
1840 static void
1841 dc_read_srom(sc, bits)
1842 struct dc_softc *sc;
1843 int bits;
1844 {
1845 int size;
1846
1847 size = 2 << bits;
1848 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1849 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1850 }
1851
1852 static void
1853 dc_parse_21143_srom(sc)
1854 struct dc_softc *sc;
1855 {
1856 struct dc_leaf_hdr *lhdr;
1857 struct dc_eblock_hdr *hdr;
1858 int i, loff;
1859 char *ptr;
1860
1861 loff = sc->dc_srom[27];
1862 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1863
1864 ptr = (char *)lhdr;
1865 ptr += sizeof(struct dc_leaf_hdr) - 1;
1866 for (i = 0; i < lhdr->dc_mcnt; i++) {
1867 hdr = (struct dc_eblock_hdr *)ptr;
1868 switch(hdr->dc_type) {
1869 case DC_EBLOCK_MII:
1870 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1871 break;
1872 case DC_EBLOCK_SIA:
1873 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr);
1874 break;
1875 case DC_EBLOCK_SYM:
1876 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr);
1877 break;
1878 default:
1879 /* Don't care. Yet. */
1880 break;
1881 }
1882 ptr += (hdr->dc_len & 0x7F);
1883 ptr++;
1884 }
1885
1886 return;
1887 }
1888
1889 /*
1890 * Attach the interface. Allocate softc structures, do ifmedia
1891 * setup and ethernet/BPF attach.
1892 */
1893 static int
1894 dc_attach(dev)
1895 device_t dev;
1896 {
1897 int tmp = 0;
1898 u_char eaddr[ETHER_ADDR_LEN];
1899 u_int32_t command;
1900 struct dc_softc *sc;
1901 struct ifnet *ifp;
1902 u_int32_t revision;
1903 int unit, error = 0, rid, mac_offset;
1904 u_int8_t *mac;
1905
1906 sc = device_get_softc(dev);
1907 unit = device_get_unit(dev);
1908 bzero(sc, sizeof(struct dc_softc));
1909
1910 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1911 MTX_DEF | MTX_RECURSE);
1912
1913 /*
1914 * Handle power management nonsense.
1915 */
1916 dc_acpi(dev);
1917
1918 /*
1919 * Map control/status registers.
1920 */
1921 pci_enable_busmaster(dev);
1922 pci_enable_io(dev, SYS_RES_IOPORT);
1923 pci_enable_io(dev, SYS_RES_MEMORY);
1924 command = pci_read_config(dev, PCIR_COMMAND, 4);
1925
1926 #ifdef DC_USEIOSPACE
1927 if (!(command & PCIM_CMD_PORTEN)) {
1928 printf("dc%d: failed to enable I/O ports!\n", unit);
1929 error = ENXIO;
1930 goto fail_nolock;
1931 }
1932 #else
1933 if (!(command & PCIM_CMD_MEMEN)) {
1934 printf("dc%d: failed to enable memory mapping!\n", unit);
1935 error = ENXIO;
1936 goto fail_nolock;
1937 }
1938 #endif
1939
1940 rid = DC_RID;
1941 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid,
1942 0, ~0, 1, RF_ACTIVE);
1943
1944 if (sc->dc_res == NULL) {
1945 printf("dc%d: couldn't map ports/memory\n", unit);
1946 error = ENXIO;
1947 goto fail_nolock;
1948 }
1949
1950 sc->dc_btag = rman_get_bustag(sc->dc_res);
1951 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1952
1953 /* Allocate interrupt */
1954 rid = 0;
1955 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1956 RF_SHAREABLE | RF_ACTIVE);
1957
1958 if (sc->dc_irq == NULL) {
1959 printf("dc%d: couldn't map interrupt\n", unit);
1960 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
1961 error = ENXIO;
1962 goto fail_nolock;
1963 }
1964
1965 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET |
1966 (IS_MPSAFE ? INTR_MPSAFE : 0),
1967 dc_intr, sc, &sc->dc_intrhand);
1968
1969 if (error) {
1970 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
1971 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
1972 printf("dc%d: couldn't set up irq\n", unit);
1973 goto fail_nolock;
1974 }
1975 DC_LOCK(sc);
1976
1977 /* Need this info to decide on a chip type. */
1978 sc->dc_info = dc_devtype(dev);
1979 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF;
1980
1981 switch(sc->dc_info->dc_did) {
1982 case DC_DEVICEID_21143:
1983 sc->dc_type = DC_TYPE_21143;
1984 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1985 sc->dc_flags |= DC_REDUCED_MII_POLL;
1986 /* Save EEPROM contents so we can parse them later. */
1987 dc_eeprom_width(sc);
1988 dc_read_srom(sc, sc->dc_romwidth);
1989 break;
1990 case DC_DEVICEID_DM9100:
1991 case DC_DEVICEID_DM9102:
1992 sc->dc_type = DC_TYPE_DM9102;
1993 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS;
1994 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD;
1995 sc->dc_pmode = DC_PMODE_MII;
1996 /* Increase the latency timer value. */
1997 command = pci_read_config(dev, DC_PCI_CFLT, 4);
1998 command &= 0xFFFF00FF;
1999 command |= 0x00008000;
2000 pci_write_config(dev, DC_PCI_CFLT, command, 4);
2001 break;
2002 case DC_DEVICEID_AL981:
2003 sc->dc_type = DC_TYPE_AL981;
2004 sc->dc_flags |= DC_TX_USE_TX_INTR;
2005 sc->dc_flags |= DC_TX_ADMTEK_WAR;
2006 sc->dc_pmode = DC_PMODE_MII;
2007 dc_eeprom_width(sc);
2008 dc_read_srom(sc, sc->dc_romwidth);
2009 break;
2010 case DC_DEVICEID_AN985:
2011 case DC_DEVICEID_FE2500:
2012 case DC_DEVICEID_EN2242:
2013 sc->dc_type = DC_TYPE_AN985;
2014 sc->dc_flags |= DC_TX_USE_TX_INTR;
2015 sc->dc_flags |= DC_TX_ADMTEK_WAR;
2016 sc->dc_pmode = DC_PMODE_MII;
2017 dc_eeprom_width(sc);
2018 dc_read_srom(sc, sc->dc_romwidth);
2019 break;
2020 case DC_DEVICEID_98713:
2021 case DC_DEVICEID_98713_CP:
2022 if (revision < DC_REVISION_98713A) {
2023 sc->dc_type = DC_TYPE_98713;
2024 }
2025 if (revision >= DC_REVISION_98713A) {
2026 sc->dc_type = DC_TYPE_98713A;
2027 sc->dc_flags |= DC_21143_NWAY;
2028 }
2029 sc->dc_flags |= DC_REDUCED_MII_POLL;
2030 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
2031 break;
2032 case DC_DEVICEID_987x5:
2033 case DC_DEVICEID_EN1217:
2034 /*
2035 * Macronix MX98715AEC-C/D/E parts have only a
2036 * 128-bit hash table. We need to deal with these
2037 * in the same manner as the PNIC II so that we
2038 * get the right number of bits out of the
2039 * CRC routine.
2040 */
2041 if (revision >= DC_REVISION_98715AEC_C &&
2042 revision < DC_REVISION_98725)
2043 sc->dc_flags |= DC_128BIT_HASH;
2044 sc->dc_type = DC_TYPE_987x5;
2045 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
2046 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
2047 break;
2048 case DC_DEVICEID_98727:
2049 sc->dc_type = DC_TYPE_987x5;
2050 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
2051 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
2052 break;
2053 case DC_DEVICEID_82C115:
2054 sc->dc_type = DC_TYPE_PNICII;
2055 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH;
2056 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
2057 break;
2058 case DC_DEVICEID_82C168:
2059 sc->dc_type = DC_TYPE_PNIC;
2060 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS;
2061 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
2062 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
2063 if (revision < DC_REVISION_82C169)
2064 sc->dc_pmode = DC_PMODE_SYM;
2065 break;
2066 case DC_DEVICEID_AX88140A:
2067 sc->dc_type = DC_TYPE_ASIX;
2068 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG;
2069 sc->dc_flags |= DC_REDUCED_MII_POLL;
2070 sc->dc_pmode = DC_PMODE_MII;
2071 break;
2072 case DC_DEVICEID_X3201:
2073 sc->dc_type = DC_TYPE_XIRCOM;
2074 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
2075 DC_TX_ALIGN;
2076 /*
2077 * We don't actually need to coalesce, but we're doing
2078 * it to obtain a double word aligned buffer.
2079 * The DC_TX_COALESCE flag is required.
2080 */
2081 sc->dc_pmode = DC_PMODE_MII;
2082 break;
2083 case DC_DEVICEID_RS7112:
2084 sc->dc_type = DC_TYPE_CONEXANT;
2085 sc->dc_flags |= DC_TX_INTR_ALWAYS;
2086 sc->dc_flags |= DC_REDUCED_MII_POLL;
2087 sc->dc_pmode = DC_PMODE_MII;
2088 dc_eeprom_width(sc);
2089 dc_read_srom(sc, sc->dc_romwidth);
2090 break;
2091 default:
2092 printf("dc%d: unknown device: %x\n", sc->dc_unit,
2093 sc->dc_info->dc_did);
2094 break;
2095 }
2096
2097 /* Save the cache line size. */
2098 if (DC_IS_DAVICOM(sc))
2099 sc->dc_cachesize = 0;
2100 else
2101 sc->dc_cachesize = pci_read_config(dev,
2102 DC_PCI_CFLT, 4) & 0xFF;
2103
2104 /* Reset the adapter. */
2105 dc_reset(sc);
2106
2107 /* Take 21143 out of snooze mode */
2108 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2109 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2110 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
2111 pci_write_config(dev, DC_PCI_CFDD, command, 4);
2112 }
2113
2114 /*
2115 * Try to learn something about the supported media.
2116 * We know that ASIX and ADMtek and Davicom devices
2117 * will *always* be using MII media, so that's a no-brainer.
2118 * The tricky ones are the Macronix/PNIC II and the
2119 * Intel 21143.
2120 */
2121 if (DC_IS_INTEL(sc))
2122 dc_parse_21143_srom(sc);
2123 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2124 if (sc->dc_type == DC_TYPE_98713)
2125 sc->dc_pmode = DC_PMODE_MII;
2126 else
2127 sc->dc_pmode = DC_PMODE_SYM;
2128 } else if (!sc->dc_pmode)
2129 sc->dc_pmode = DC_PMODE_MII;
2130
2131 /*
2132 * Get station address from the EEPROM.
2133 */
2134 switch(sc->dc_type) {
2135 case DC_TYPE_98713:
2136 case DC_TYPE_98713A:
2137 case DC_TYPE_987x5:
2138 case DC_TYPE_PNICII:
2139 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2140 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2141 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2142 break;
2143 case DC_TYPE_PNIC:
2144 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2145 break;
2146 case DC_TYPE_DM9102:
2147 case DC_TYPE_21143:
2148 case DC_TYPE_ASIX:
2149 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2150 break;
2151 case DC_TYPE_AL981:
2152 case DC_TYPE_AN985:
2153 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr,
2154 ETHER_ADDR_LEN);
2155 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0);
2156 break;
2157 case DC_TYPE_CONEXANT:
2158 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2159 break;
2160 case DC_TYPE_XIRCOM:
2161 /* The MAC comes from the CIS */
2162 mac = pci_get_ether(dev);
2163 if (!mac) {
2164 device_printf(dev, "No station address in CIS!\n");
2165 goto fail;
2166 }
2167 bcopy(mac, eaddr, ETHER_ADDR_LEN);
2168 break;
2169 default:
2170 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2171 break;
2172 }
2173
2174 /*
2175 * A 21143 or clone chip was detected. Inform the world.
2176 */
2177 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":");
2178
2179 sc->dc_unit = unit;
2180 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
2181
2182 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF,
2183 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
2184
2185 if (sc->dc_ldata == NULL) {
2186 printf("dc%d: no memory for list buffers!\n", unit);
2187 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2188 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2189 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2190 error = ENXIO;
2191 goto fail;
2192 }
2193
2194 bzero(sc->dc_ldata, sizeof(struct dc_list_data));
2195
2196 ifp = &sc->arpcom.ac_if;
2197 ifp->if_softc = sc;
2198 ifp->if_unit = unit;
2199 ifp->if_name = "dc";
2200 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */
2201 ifp->if_mtu = ETHERMTU;
2202 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2203 ifp->if_ioctl = dc_ioctl;
2204 ifp->if_output = ether_output;
2205 ifp->if_start = dc_start;
2206 ifp->if_watchdog = dc_watchdog;
2207 ifp->if_init = dc_init;
2208 ifp->if_baudrate = 10000000;
2209 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1;
2210
2211 /*
2212 * Do MII setup. If this is a 21143, check for a PHY on the
2213 * MII bus after applying any necessary fixups to twiddle the
2214 * GPIO bits. If we don't end up finding a PHY, restore the
2215 * old selection (SIA only or SIA/SYM) and attach the dcphy
2216 * driver instead.
2217 */
2218 if (DC_IS_INTEL(sc)) {
2219 dc_apply_fixup(sc, IFM_AUTO);
2220 tmp = sc->dc_pmode;
2221 sc->dc_pmode = DC_PMODE_MII;
2222 }
2223
2224 error = mii_phy_probe(dev, &sc->dc_miibus,
2225 dc_ifmedia_upd, dc_ifmedia_sts);
2226
2227 if (error && DC_IS_INTEL(sc)) {
2228 sc->dc_pmode = tmp;
2229 if (sc->dc_pmode != DC_PMODE_SIA)
2230 sc->dc_pmode = DC_PMODE_SYM;
2231 sc->dc_flags |= DC_21143_NWAY;
2232 mii_phy_probe(dev, &sc->dc_miibus,
2233 dc_ifmedia_upd, dc_ifmedia_sts);
2234 /*
2235 * For non-MII cards, we need to have the 21143
2236 * drive the LEDs. Except there are some systems
2237 * like the NEC VersaPro NoteBook PC which have no
2238 * LEDs, and twiddling these bits has adverse effects
2239 * on them. (I.e. you suddenly can't get a link.)
2240 */
2241 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2242 sc->dc_flags |= DC_TULIP_LEDS;
2243 error = 0;
2244 }
2245
2246 if (error) {
2247 printf("dc%d: MII without any PHY!\n", sc->dc_unit);
2248 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2249 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2250 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2251 error = ENXIO;
2252 goto fail;
2253 }
2254
2255 if (DC_IS_XIRCOM(sc)) {
2256 /*
2257 * setup General Purpose Port mode and data so the tulip
2258 * can talk to the MII.
2259 */
2260 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2261 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2262 DELAY(10);
2263 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2264 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2265 DELAY(10);
2266 }
2267
2268 /*
2269 * Call MI attach routine.
2270 */
2271 ether_ifattach(ifp, eaddr);
2272
2273 /*
2274 * Tell the upper layer(s) we support long frames.
2275 */
2276 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2277 ifp->if_capabilities |= IFCAP_VLAN_MTU;
2278
2279 callout_init(&sc->dc_stat_ch, IS_MPSAFE);
2280
2281 #ifdef SRM_MEDIA
2282 sc->dc_srm_media = 0;
2283
2284 /* Remember the SRM console media setting */
2285 if (DC_IS_INTEL(sc)) {
2286 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2287 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
2288 switch ((command >> 8) & 0xff) {
2289 case 3:
2290 sc->dc_srm_media = IFM_10_T;
2291 break;
2292 case 4:
2293 sc->dc_srm_media = IFM_10_T | IFM_FDX;
2294 break;
2295 case 5:
2296 sc->dc_srm_media = IFM_100_TX;
2297 break;
2298 case 6:
2299 sc->dc_srm_media = IFM_100_TX | IFM_FDX;
2300 break;
2301 }
2302 if (sc->dc_srm_media)
2303 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER;
2304 }
2305 #endif
2306
2307 DC_UNLOCK(sc);
2308 return(0);
2309
2310 fail:
2311 DC_UNLOCK(sc);
2312 fail_nolock:
2313 mtx_destroy(&sc->dc_mtx);
2314 return(error);
2315 }
2316
2317 static int
2318 dc_detach(dev)
2319 device_t dev;
2320 {
2321 struct dc_softc *sc;
2322 struct ifnet *ifp;
2323 struct dc_mediainfo *m;
2324
2325 sc = device_get_softc(dev);
2326
2327 DC_LOCK(sc);
2328
2329 ifp = &sc->arpcom.ac_if;
2330
2331 dc_stop(sc);
2332 ether_ifdetach(ifp);
2333
2334 bus_generic_detach(dev);
2335 device_delete_child(dev, sc->dc_miibus);
2336
2337 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2338 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2339 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2340
2341 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2342 if (sc->dc_pnic_rx_buf != NULL)
2343 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2344
2345 while(sc->dc_mi != NULL) {
2346 m = sc->dc_mi->dc_next;
2347 free(sc->dc_mi, M_DEVBUF);
2348 sc->dc_mi = m;
2349 }
2350 free(sc->dc_srom, M_DEVBUF);
2351
2352 DC_UNLOCK(sc);
2353 mtx_destroy(&sc->dc_mtx);
2354
2355 return(0);
2356 }
2357
2358 /*
2359 * Initialize the transmit descriptors.
2360 */
2361 static int
2362 dc_list_tx_init(sc)
2363 struct dc_softc *sc;
2364 {
2365 struct dc_chain_data *cd;
2366 struct dc_list_data *ld;
2367 int i, nexti;
2368
2369 cd = &sc->dc_cdata;
2370 ld = sc->dc_ldata;
2371 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2372 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1;
2373 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]);
2374 cd->dc_tx_chain[i] = NULL;
2375 ld->dc_tx_list[i].dc_data = 0;
2376 ld->dc_tx_list[i].dc_ctl = 0;
2377 }
2378
2379 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2380
2381 return(0);
2382 }
2383
2384
2385 /*
2386 * Initialize the RX descriptors and allocate mbufs for them. Note that
2387 * we arrange the descriptors in a closed ring, so that the last descriptor
2388 * points back to the first.
2389 */
2390 static int
2391 dc_list_rx_init(sc)
2392 struct dc_softc *sc;
2393 {
2394 struct dc_chain_data *cd;
2395 struct dc_list_data *ld;
2396 int i, nexti;
2397
2398 cd = &sc->dc_cdata;
2399 ld = sc->dc_ldata;
2400
2401 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2402 if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2403 return(ENOBUFS);
2404 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1;
2405 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]);
2406 }
2407
2408 cd->dc_rx_prod = 0;
2409
2410 return(0);
2411 }
2412
2413 /*
2414 * Initialize an RX descriptor and attach an MBUF cluster.
2415 */
2416 static int
2417 dc_newbuf(sc, i, m)
2418 struct dc_softc *sc;
2419 int i;
2420 struct mbuf *m;
2421 {
2422 struct mbuf *m_new = NULL;
2423 struct dc_desc *c;
2424
2425 c = &sc->dc_ldata->dc_rx_list[i];
2426
2427 if (m == NULL) {
2428 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2429 if (m_new == NULL)
2430 return(ENOBUFS);
2431
2432 MCLGET(m_new, M_DONTWAIT);
2433 if (!(m_new->m_flags & M_EXT)) {
2434 m_freem(m_new);
2435 return(ENOBUFS);
2436 }
2437 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2438 } else {
2439 m_new = m;
2440 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2441 m_new->m_data = m_new->m_ext.ext_buf;
2442 }
2443
2444 m_adj(m_new, sizeof(u_int64_t));
2445
2446 /*
2447 * If this is a PNIC chip, zero the buffer. This is part
2448 * of the workaround for the receive bug in the 82c168 and
2449 * 82c169 chips.
2450 */
2451 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2452 bzero((char *)mtod(m_new, char *), m_new->m_len);
2453
2454 sc->dc_cdata.dc_rx_chain[i] = m_new;
2455 c->dc_data = vtophys(mtod(m_new, caddr_t));
2456 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN;
2457 c->dc_status = DC_RXSTAT_OWN;
2458
2459 return(0);
2460 }
2461
2462 /*
2463 * Grrrrr.
2464 * The PNIC chip has a terrible bug in it that manifests itself during
2465 * periods of heavy activity. The exact mode of failure if difficult to
2466 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2467 * will happen on slow machines. The bug is that sometimes instead of
2468 * uploading one complete frame during reception, it uploads what looks
2469 * like the entire contents of its FIFO memory. The frame we want is at
2470 * the end of the whole mess, but we never know exactly how much data has
2471 * been uploaded, so salvaging the frame is hard.
2472 *
2473 * There is only one way to do it reliably, and it's disgusting.
2474 * Here's what we know:
2475 *
2476 * - We know there will always be somewhere between one and three extra
2477 * descriptors uploaded.
2478 *
2479 * - We know the desired received frame will always be at the end of the
2480 * total data upload.
2481 *
2482 * - We know the size of the desired received frame because it will be
2483 * provided in the length field of the status word in the last descriptor.
2484 *
2485 * Here's what we do:
2486 *
2487 * - When we allocate buffers for the receive ring, we bzero() them.
2488 * This means that we know that the buffer contents should be all
2489 * zeros, except for data uploaded by the chip.
2490 *
2491 * - We also force the PNIC chip to upload frames that include the
2492 * ethernet CRC at the end.
2493 *
2494 * - We gather all of the bogus frame data into a single buffer.
2495 *
2496 * - We then position a pointer at the end of this buffer and scan
2497 * backwards until we encounter the first non-zero byte of data.
2498 * This is the end of the received frame. We know we will encounter
2499 * some data at the end of the frame because the CRC will always be
2500 * there, so even if the sender transmits a packet of all zeros,
2501 * we won't be fooled.
2502 *
2503 * - We know the size of the actual received frame, so we subtract
2504 * that value from the current pointer location. This brings us
2505 * to the start of the actual received packet.
2506 *
2507 * - We copy this into an mbuf and pass it on, along with the actual
2508 * frame length.
2509 *
2510 * The performance hit is tremendous, but it beats dropping frames all
2511 * the time.
2512 */
2513
2514 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG)
2515 static void
2516 dc_pnic_rx_bug_war(sc, idx)
2517 struct dc_softc *sc;
2518 int idx;
2519 {
2520 struct dc_desc *cur_rx;
2521 struct dc_desc *c = NULL;
2522 struct mbuf *m = NULL;
2523 unsigned char *ptr;
2524 int i, total_len;
2525 u_int32_t rxstat = 0;
2526
2527 i = sc->dc_pnic_rx_bug_save;
2528 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2529 ptr = sc->dc_pnic_rx_buf;
2530 bzero(ptr, sizeof(DC_RXLEN * 5));
2531
2532 /* Copy all the bytes from the bogus buffers. */
2533 while (1) {
2534 c = &sc->dc_ldata->dc_rx_list[i];
2535 rxstat = c->dc_status;
2536 m = sc->dc_cdata.dc_rx_chain[i];
2537 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2538 ptr += DC_RXLEN;
2539 /* If this is the last buffer, break out. */
2540 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2541 break;
2542 dc_newbuf(sc, i, m);
2543 DC_INC(i, DC_RX_LIST_CNT);
2544 }
2545
2546 /* Find the length of the actual receive frame. */
2547 total_len = DC_RXBYTES(rxstat);
2548
2549 /* Scan backwards until we hit a non-zero byte. */
2550 while(*ptr == 0x00)
2551 ptr--;
2552
2553 /* Round off. */
2554 if ((uintptr_t)(ptr) & 0x3)
2555 ptr -= 1;
2556
2557 /* Now find the start of the frame. */
2558 ptr -= total_len;
2559 if (ptr < sc->dc_pnic_rx_buf)
2560 ptr = sc->dc_pnic_rx_buf;
2561
2562 /*
2563 * Now copy the salvaged frame to the last mbuf and fake up
2564 * the status word to make it look like a successful
2565 * frame reception.
2566 */
2567 dc_newbuf(sc, i, m);
2568 bcopy(ptr, mtod(m, char *), total_len);
2569 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG;
2570
2571 return;
2572 }
2573
2574 /*
2575 * This routine searches the RX ring for dirty descriptors in the
2576 * event that the rxeof routine falls out of sync with the chip's
2577 * current descriptor pointer. This may happen sometimes as a result
2578 * of a "no RX buffer available" condition that happens when the chip
2579 * consumes all of the RX buffers before the driver has a chance to
2580 * process the RX ring. This routine may need to be called more than
2581 * once to bring the driver back in sync with the chip, however we
2582 * should still be getting RX DONE interrupts to drive the search
2583 * for new packets in the RX ring, so we should catch up eventually.
2584 */
2585 static int
2586 dc_rx_resync(sc)
2587 struct dc_softc *sc;
2588 {
2589 int i, pos;
2590 struct dc_desc *cur_rx;
2591
2592 pos = sc->dc_cdata.dc_rx_prod;
2593
2594 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2595 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2596 if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2597 break;
2598 DC_INC(pos, DC_RX_LIST_CNT);
2599 }
2600
2601 /* If the ring really is empty, then just return. */
2602 if (i == DC_RX_LIST_CNT)
2603 return(0);
2604
2605 /* We've fallen behing the chip: catch it. */
2606 sc->dc_cdata.dc_rx_prod = pos;
2607
2608 return(EAGAIN);
2609 }
2610
2611 /*
2612 * A frame has been uploaded: pass the resulting mbuf chain up to
2613 * the higher level protocols.
2614 */
2615 static void
2616 dc_rxeof(sc)
2617 struct dc_softc *sc;
2618 {
2619 struct mbuf *m;
2620 struct ifnet *ifp;
2621 struct dc_desc *cur_rx;
2622 int i, total_len = 0;
2623 u_int32_t rxstat;
2624
2625 ifp = &sc->arpcom.ac_if;
2626 i = sc->dc_cdata.dc_rx_prod;
2627
2628 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2629
2630 #ifdef DEVICE_POLLING
2631 if (ifp->if_flags & IFF_POLLING) {
2632 if (sc->rxcycles <= 0)
2633 break;
2634 sc->rxcycles--;
2635 }
2636 #endif /* DEVICE_POLLING */
2637 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2638 rxstat = cur_rx->dc_status;
2639 m = sc->dc_cdata.dc_rx_chain[i];
2640 total_len = DC_RXBYTES(rxstat);
2641
2642 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2643 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2644 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2645 sc->dc_pnic_rx_bug_save = i;
2646 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2647 DC_INC(i, DC_RX_LIST_CNT);
2648 continue;
2649 }
2650 dc_pnic_rx_bug_war(sc, i);
2651 rxstat = cur_rx->dc_status;
2652 total_len = DC_RXBYTES(rxstat);
2653 }
2654 }
2655
2656 sc->dc_cdata.dc_rx_chain[i] = NULL;
2657
2658 /*
2659 * If an error occurs, update stats, clear the
2660 * status word and leave the mbuf cluster in place:
2661 * it should simply get re-used next time this descriptor
2662 * comes up in the ring. However, don't report long
2663 * frames as errors since they could be vlans
2664 */
2665 if ((rxstat & DC_RXSTAT_RXERR)){
2666 if (!(rxstat & DC_RXSTAT_GIANT) ||
2667 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2668 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2669 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2670 ifp->if_ierrors++;
2671 if (rxstat & DC_RXSTAT_COLLSEEN)
2672 ifp->if_collisions++;
2673 dc_newbuf(sc, i, m);
2674 if (rxstat & DC_RXSTAT_CRCERR) {
2675 DC_INC(i, DC_RX_LIST_CNT);
2676 continue;
2677 } else {
2678 dc_init(sc);
2679 return;
2680 }
2681 }
2682 }
2683
2684 /* No errors; receive the packet. */
2685 total_len -= ETHER_CRC_LEN;
2686 #ifdef __i386__
2687 /*
2688 * On the x86 we do not have alignment problems, so try to
2689 * allocate a new buffer for the receive ring, and pass up
2690 * the one where the packet is already, saving the expensive
2691 * copy done in m_devget().
2692 * If we are on an architecture with alignment problems, or
2693 * if the allocation fails, then use m_devget and leave the
2694 * existing buffer in the receive ring.
2695 */
2696 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2697 m->m_pkthdr.rcvif = ifp;
2698 m->m_pkthdr.len = m->m_len = total_len;
2699 DC_INC(i, DC_RX_LIST_CNT);
2700 } else
2701 #endif
2702 {
2703 struct mbuf *m0;
2704
2705 m0 = m_devget(mtod(m, char *), total_len,
2706 ETHER_ALIGN, ifp, NULL);
2707 dc_newbuf(sc, i, m);
2708 DC_INC(i, DC_RX_LIST_CNT);
2709 if (m0 == NULL) {
2710 ifp->if_ierrors++;
2711 continue;
2712 }
2713 m = m0;
2714 }
2715
2716 ifp->if_ipackets++;
2717 (*ifp->if_input)(ifp, m);
2718 }
2719
2720 sc->dc_cdata.dc_rx_prod = i;
2721 }
2722
2723 /*
2724 * A frame was downloaded to the chip. It's safe for us to clean up
2725 * the list buffers.
2726 */
2727
2728 static void
2729 dc_txeof(sc)
2730 struct dc_softc *sc;
2731 {
2732 struct dc_desc *cur_tx = NULL;
2733 struct ifnet *ifp;
2734 int idx;
2735
2736 ifp = &sc->arpcom.ac_if;
2737
2738 /*
2739 * Go through our tx list and free mbufs for those
2740 * frames that have been transmitted.
2741 */
2742 idx = sc->dc_cdata.dc_tx_cons;
2743 while(idx != sc->dc_cdata.dc_tx_prod) {
2744 u_int32_t txstat;
2745
2746 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2747 txstat = cur_tx->dc_status;
2748
2749 if (txstat & DC_TXSTAT_OWN)
2750 break;
2751
2752 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) ||
2753 cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2754 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2755 /*
2756 * Yes, the PNIC is so brain damaged
2757 * that it will sometimes generate a TX
2758 * underrun error while DMAing the RX
2759 * filter setup frame. If we detect this,
2760 * we have to send the setup frame again,
2761 * or else the filter won't be programmed
2762 * correctly.
2763 */
2764 if (DC_IS_PNIC(sc)) {
2765 if (txstat & DC_TXSTAT_ERRSUM)
2766 dc_setfilt(sc);
2767 }
2768 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2769 }
2770 sc->dc_cdata.dc_tx_cnt--;
2771 DC_INC(idx, DC_TX_LIST_CNT);
2772 continue;
2773 }
2774
2775 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2776 /*
2777 * XXX: Why does my Xircom taunt me so?
2778 * For some reason it likes setting the CARRLOST flag
2779 * even when the carrier is there. wtf?!?
2780 * Who knows, but Conexant chips have the
2781 * same problem. Maybe they took lessons
2782 * from Xircom.
2783 */
2784 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2785 sc->dc_pmode == DC_PMODE_MII &&
2786 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2787 DC_TXSTAT_NOCARRIER)))
2788 txstat &= ~DC_TXSTAT_ERRSUM;
2789 } else {
2790 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2791 sc->dc_pmode == DC_PMODE_MII &&
2792 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2793 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST)))
2794 txstat &= ~DC_TXSTAT_ERRSUM;
2795 }
2796
2797 if (txstat & DC_TXSTAT_ERRSUM) {
2798 ifp->if_oerrors++;
2799 if (txstat & DC_TXSTAT_EXCESSCOLL)
2800 ifp->if_collisions++;
2801 if (txstat & DC_TXSTAT_LATECOLL)
2802 ifp->if_collisions++;
2803 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2804 dc_init(sc);
2805 return;
2806 }
2807 }
2808
2809 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2810
2811 ifp->if_opackets++;
2812 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2813 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2814 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2815 }
2816
2817 sc->dc_cdata.dc_tx_cnt--;
2818 DC_INC(idx, DC_TX_LIST_CNT);
2819 }
2820
2821 if (idx != sc->dc_cdata.dc_tx_cons) {
2822 /* some buffers have been freed */
2823 sc->dc_cdata.dc_tx_cons = idx;
2824 ifp->if_flags &= ~IFF_OACTIVE;
2825 }
2826 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2827
2828 return;
2829 }
2830
2831 static void
2832 dc_tick(xsc)
2833 void *xsc;
2834 {
2835 struct dc_softc *sc;
2836 struct mii_data *mii;
2837 struct ifnet *ifp;
2838 u_int32_t r;
2839
2840 sc = xsc;
2841 DC_LOCK(sc);
2842 ifp = &sc->arpcom.ac_if;
2843 mii = device_get_softc(sc->dc_miibus);
2844
2845 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2846 if (sc->dc_flags & DC_21143_NWAY) {
2847 r = CSR_READ_4(sc, DC_10BTSTAT);
2848 if (IFM_SUBTYPE(mii->mii_media_active) ==
2849 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2850 sc->dc_link = 0;
2851 mii_mediachg(mii);
2852 }
2853 if (IFM_SUBTYPE(mii->mii_media_active) ==
2854 IFM_10_T && (r & DC_TSTAT_LS10)) {
2855 sc->dc_link = 0;
2856 mii_mediachg(mii);
2857 }
2858 if (sc->dc_link == 0)
2859 mii_tick(mii);
2860 } else {
2861 r = CSR_READ_4(sc, DC_ISR);
2862 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2863 sc->dc_cdata.dc_tx_cnt == 0)
2864 mii_tick(mii);
2865 if (!(mii->mii_media_status & IFM_ACTIVE))
2866 sc->dc_link = 0;
2867 }
2868 } else
2869 mii_tick(mii);
2870
2871 /*
2872 * When the init routine completes, we expect to be able to send
2873 * packets right away, and in fact the network code will send a
2874 * gratuitous ARP the moment the init routine marks the interface
2875 * as running. However, even though the MAC may have been initialized,
2876 * there may be a delay of a few seconds before the PHY completes
2877 * autonegotiation and the link is brought up. Any transmissions
2878 * made during that delay will be lost. Dealing with this is tricky:
2879 * we can't just pause in the init routine while waiting for the
2880 * PHY to come ready since that would bring the whole system to
2881 * a screeching halt for several seconds.
2882 *
2883 * What we do here is prevent the TX start routine from sending
2884 * any packets until a link has been established. After the
2885 * interface has been initialized, the tick routine will poll
2886 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2887 * that time, packets will stay in the send queue, and once the
2888 * link comes up, they will be flushed out to the wire.
2889 */
2890 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE &&
2891 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2892 sc->dc_link++;
2893 if (ifp->if_snd.ifq_head != NULL)
2894 dc_start(ifp);
2895 }
2896
2897 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2898 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
2899 else
2900 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
2901
2902 DC_UNLOCK(sc);
2903
2904 return;
2905 }
2906
2907 /*
2908 * A transmit underrun has occurred. Back off the transmit threshold,
2909 * or switch to store and forward mode if we have to.
2910 */
2911 static void
2912 dc_tx_underrun(sc)
2913 struct dc_softc *sc;
2914 {
2915 u_int32_t isr;
2916 int i;
2917
2918 if (DC_IS_DAVICOM(sc))
2919 dc_init(sc);
2920
2921 if (DC_IS_INTEL(sc)) {
2922 /*
2923 * The real 21143 requires that the transmitter be idle
2924 * in order to change the transmit threshold or store
2925 * and forward state.
2926 */
2927 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2928
2929 for (i = 0; i < DC_TIMEOUT; i++) {
2930 isr = CSR_READ_4(sc, DC_ISR);
2931 if (isr & DC_ISR_TX_IDLE)
2932 break;
2933 DELAY(10);
2934 }
2935 if (i == DC_TIMEOUT) {
2936 printf("dc%d: failed to force tx to idle state\n",
2937 sc->dc_unit);
2938 dc_init(sc);
2939 }
2940 }
2941
2942 printf("dc%d: TX underrun -- ", sc->dc_unit);
2943 sc->dc_txthresh += DC_TXTHRESH_INC;
2944 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2945 printf("using store and forward mode\n");
2946 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2947 } else {
2948 printf("increasing TX threshold\n");
2949 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2950 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2951 }
2952
2953 if (DC_IS_INTEL(sc))
2954 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2955
2956 return;
2957 }
2958
2959 #ifdef DEVICE_POLLING
2960 static poll_handler_t dc_poll;
2961
2962 static void
2963 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2964 {
2965 struct dc_softc *sc = ifp->if_softc;
2966
2967 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
2968 /* Re-enable interrupts. */
2969 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2970 return;
2971 }
2972 sc->rxcycles = count;
2973 dc_rxeof(sc);
2974 dc_txeof(sc);
2975 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE))
2976 dc_start(ifp);
2977
2978 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2979 u_int32_t status;
2980
2981 status = CSR_READ_4(sc, DC_ISR);
2982 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF|
2983 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN|
2984 DC_ISR_BUS_ERR);
2985 if (!status)
2986 return;
2987 /* ack what we have */
2988 CSR_WRITE_4(sc, DC_ISR, status);
2989
2990 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF)) {
2991 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
2992 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
2993
2994 if (dc_rx_resync(sc))
2995 dc_rxeof(sc);
2996 }
2997 /* restart transmit unit if necessary */
2998 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
2999 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3000
3001 if (status & DC_ISR_TX_UNDERRUN)
3002 dc_tx_underrun(sc);
3003
3004 if (status & DC_ISR_BUS_ERR) {
3005 printf("dc_poll: dc%d bus error\n", sc->dc_unit);
3006 dc_reset(sc);
3007 dc_init(sc);
3008 }
3009 }
3010 }
3011 #endif /* DEVICE_POLLING */
3012
3013 static void
3014 dc_intr(arg)
3015 void *arg;
3016 {
3017 struct dc_softc *sc;
3018 struct ifnet *ifp;
3019 u_int32_t status;
3020
3021 sc = arg;
3022
3023 if (sc->suspended) {
3024 return;
3025 }
3026
3027 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
3028 return;
3029
3030 DC_LOCK(sc);
3031 ifp = &sc->arpcom.ac_if;
3032 #ifdef DEVICE_POLLING
3033 if (ifp->if_flags & IFF_POLLING)
3034 goto done;
3035 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */
3036 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3037 goto done;
3038 }
3039 #endif /* DEVICE_POLLING */
3040
3041 /* Suppress unwanted interrupts */
3042 if (!(ifp->if_flags & IFF_UP)) {
3043 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
3044 dc_stop(sc);
3045 DC_UNLOCK(sc);
3046 return;
3047 }
3048
3049 /* Disable interrupts. */
3050 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3051
3052 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS)
3053 && status != 0xFFFFFFFF) {
3054
3055 CSR_WRITE_4(sc, DC_ISR, status);
3056
3057 if (status & DC_ISR_RX_OK) {
3058 int curpkts;
3059 curpkts = ifp->if_ipackets;
3060 dc_rxeof(sc);
3061 if (curpkts == ifp->if_ipackets) {
3062 while(dc_rx_resync(sc))
3063 dc_rxeof(sc);
3064 }
3065 }
3066
3067 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF))
3068 dc_txeof(sc);
3069
3070 if (status & DC_ISR_TX_IDLE) {
3071 dc_txeof(sc);
3072 if (sc->dc_cdata.dc_tx_cnt) {
3073 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3074 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3075 }
3076 }
3077
3078 if (status & DC_ISR_TX_UNDERRUN)
3079 dc_tx_underrun(sc);
3080
3081 if ((status & DC_ISR_RX_WATDOGTIMEO)
3082 || (status & DC_ISR_RX_NOBUF)) {
3083 int curpkts;
3084 curpkts = ifp->if_ipackets;
3085 dc_rxeof(sc);
3086 if (curpkts == ifp->if_ipackets) {
3087 while(dc_rx_resync(sc))
3088 dc_rxeof(sc);
3089 }
3090 }
3091
3092 if (status & DC_ISR_BUS_ERR) {
3093 dc_reset(sc);
3094 dc_init(sc);
3095 }
3096 }
3097
3098 /* Re-enable interrupts. */
3099 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3100
3101 if (ifp->if_snd.ifq_head != NULL)
3102 dc_start(ifp);
3103
3104 #ifdef DEVICE_POLLING
3105 done:
3106 #endif /* DEVICE_POLLING */
3107
3108 DC_UNLOCK(sc);
3109
3110 return;
3111 }
3112
3113 /*
3114 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3115 * pointers to the fragment pointers.
3116 */
3117 static int
3118 dc_encap(sc, m_head, txidx)
3119 struct dc_softc *sc;
3120 struct mbuf *m_head;
3121 u_int32_t *txidx;
3122 {
3123 struct dc_desc *f = NULL;
3124 struct mbuf *m;
3125 int frag, cur, cnt = 0;
3126
3127 /*
3128 * Start packing the mbufs in this chain into
3129 * the fragment pointers. Stop when we run out
3130 * of fragments or hit the end of the mbuf chain.
3131 */
3132 m = m_head;
3133 cur = frag = *txidx;
3134
3135 for (m = m_head; m != NULL; m = m->m_next) {
3136 if (m->m_len != 0) {
3137 if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
3138 if (*txidx != sc->dc_cdata.dc_tx_prod &&
3139 frag == (DC_TX_LIST_CNT - 1))
3140 return(ENOBUFS);
3141 }
3142 if ((DC_TX_LIST_CNT -
3143 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
3144 return(ENOBUFS);
3145
3146 f = &sc->dc_ldata->dc_tx_list[frag];
3147 f->dc_ctl = DC_TXCTL_TLINK | m->m_len;
3148 if (cnt == 0) {
3149 f->dc_status = 0;
3150 f->dc_ctl |= DC_TXCTL_FIRSTFRAG;
3151 } else
3152 f->dc_status = DC_TXSTAT_OWN;
3153 f->dc_data = vtophys(mtod(m, vm_offset_t));
3154 cur = frag;
3155 DC_INC(frag, DC_TX_LIST_CNT);
3156 cnt++;
3157 }
3158 }
3159
3160 if (m != NULL)
3161 return(ENOBUFS);
3162
3163 sc->dc_cdata.dc_tx_cnt += cnt;
3164 sc->dc_cdata.dc_tx_chain[cur] = m_head;
3165 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG;
3166 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3167 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT;
3168 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3169 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3170 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3171 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3172 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
3173 *txidx = frag;
3174
3175 return(0);
3176 }
3177
3178 /*
3179 * Coalesce an mbuf chain into a single mbuf cluster buffer.
3180 * Needed for some really badly behaved chips that just can't
3181 * do scatter/gather correctly.
3182 */
3183 static int
3184 dc_coal(sc, m_head)
3185 struct dc_softc *sc;
3186 struct mbuf **m_head;
3187 {
3188 struct mbuf *m_new, *m;
3189
3190 m = *m_head;
3191 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
3192 if (m_new == NULL)
3193 return(ENOBUFS);
3194 if (m->m_pkthdr.len > MHLEN) {
3195 MCLGET(m_new, M_DONTWAIT);
3196 if (!(m_new->m_flags & M_EXT)) {
3197 m_freem(m_new);
3198 return(ENOBUFS);
3199 }
3200 }
3201 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t));
3202 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len;
3203 m_freem(m);
3204 *m_head = m_new;
3205
3206 return(0);
3207 }
3208
3209 /*
3210 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3211 * to the mbuf data regions directly in the transmit lists. We also save a
3212 * copy of the pointers since the transmit list fragment pointers are
3213 * physical addresses.
3214 */
3215
3216 static void
3217 dc_start(ifp)
3218 struct ifnet *ifp;
3219 {
3220 struct dc_softc *sc;
3221 struct mbuf *m_head = NULL;
3222 int idx;
3223
3224 sc = ifp->if_softc;
3225
3226 DC_LOCK(sc);
3227
3228 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) {
3229 DC_UNLOCK(sc);
3230 return;
3231 }
3232
3233 if (ifp->if_flags & IFF_OACTIVE) {
3234 DC_UNLOCK(sc);
3235 return;
3236 }
3237
3238 idx = sc->dc_cdata.dc_tx_prod;
3239
3240 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3241 IF_DEQUEUE(&ifp->if_snd, m_head);
3242 if (m_head == NULL)
3243 break;
3244
3245 if (sc->dc_flags & DC_TX_COALESCE &&
3246 (m_head->m_next != NULL ||
3247 sc->dc_flags & DC_TX_ALIGN)) {
3248 if (dc_coal(sc, &m_head)) {
3249 IF_PREPEND(&ifp->if_snd, m_head);
3250 ifp->if_flags |= IFF_OACTIVE;
3251 break;
3252 }
3253 }
3254
3255 if (dc_encap(sc, m_head, &idx)) {
3256 IF_PREPEND(&ifp->if_snd, m_head);
3257 ifp->if_flags |= IFF_OACTIVE;
3258 break;
3259 }
3260
3261 /*
3262 * If there's a BPF listener, bounce a copy of this frame
3263 * to him.
3264 */
3265 BPF_MTAP(ifp, m_head);
3266
3267 if (sc->dc_flags & DC_TX_ONE) {
3268 ifp->if_flags |= IFF_OACTIVE;
3269 break;
3270 }
3271 }
3272
3273 /* Transmit */
3274 sc->dc_cdata.dc_tx_prod = idx;
3275 if (!(sc->dc_flags & DC_TX_POLL))
3276 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3277
3278 /*
3279 * Set a timeout in case the chip goes out to lunch.
3280 */
3281 ifp->if_timer = 5;
3282
3283 DC_UNLOCK(sc);
3284
3285 return;
3286 }
3287
3288 static void
3289 dc_init(xsc)
3290 void *xsc;
3291 {
3292 struct dc_softc *sc = xsc;
3293 struct ifnet *ifp = &sc->arpcom.ac_if;
3294 struct mii_data *mii;
3295
3296 DC_LOCK(sc);
3297
3298 mii = device_get_softc(sc->dc_miibus);
3299
3300 /*
3301 * Cancel pending I/O and free all RX/TX buffers.
3302 */
3303 dc_stop(sc);
3304 dc_reset(sc);
3305
3306 /*
3307 * Set cache alignment and burst length.
3308 */
3309 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3310 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3311 else
3312 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
3313 /*
3314 * Evenly share the bus between receive and transmit process.
3315 */
3316 if (DC_IS_INTEL(sc))
3317 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3318 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3319 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3320 } else {
3321 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3322 }
3323 if (sc->dc_flags & DC_TX_POLL)
3324 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3325 switch(sc->dc_cachesize) {
3326 case 32:
3327 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3328 break;
3329 case 16:
3330 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3331 break;
3332 case 8:
3333 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3334 break;
3335 case 0:
3336 default:
3337 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3338 break;
3339 }
3340
3341 if (sc->dc_flags & DC_TX_STORENFWD)
3342 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3343 else {
3344 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3345 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3346 } else {
3347 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3348 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3349 }
3350 }
3351
3352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3353 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3354
3355 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3356 /*
3357 * The app notes for the 98713 and 98715A say that
3358 * in order to have the chips operate properly, a magic
3359 * number must be written to CSR16. Macronix does not
3360 * document the meaning of these bits so there's no way
3361 * to know exactly what they do. The 98713 has a magic
3362 * number all its own; the rest all use a different one.
3363 */
3364 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3365 if (sc->dc_type == DC_TYPE_98713)
3366 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3367 else
3368 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3369 }
3370
3371 if (DC_IS_XIRCOM(sc)) {
3372 /*
3373 * setup General Purpose Port mode and data so the tulip
3374 * can talk to the MII.
3375 */
3376 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3377 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3378 DELAY(10);
3379 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3380 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3381 DELAY(10);
3382 }
3383
3384 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3385 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3386
3387 /* Init circular RX list. */
3388 if (dc_list_rx_init(sc) == ENOBUFS) {
3389 printf("dc%d: initialization failed: no "
3390 "memory for rx buffers\n", sc->dc_unit);
3391 dc_stop(sc);
3392 DC_UNLOCK(sc);
3393 return;
3394 }
3395
3396 /*
3397 * Init tx descriptors.
3398 */
3399 dc_list_tx_init(sc);
3400
3401 /*
3402 * Load the address of the RX list.
3403 */
3404 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3405 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3406
3407 /*
3408 * Enable interrupts.
3409 */
3410 #ifdef DEVICE_POLLING
3411 /*
3412 * ... but only if we are not polling, and make sure they are off in
3413 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3414 * after a reset.
3415 */
3416 if (ifp->if_flags & IFF_POLLING)
3417 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3418 else
3419 #endif
3420 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3421 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3422
3423 /* Enable transmitter. */
3424 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3425
3426 /*
3427 * If this is an Intel 21143 and we're not using the
3428 * MII port, program the LED control pins so we get
3429 * link and activity indications.
3430 */
3431 if (sc->dc_flags & DC_TULIP_LEDS) {
3432 CSR_WRITE_4(sc, DC_WATCHDOG,
3433 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY);
3434 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3435 }
3436
3437 /*
3438 * Load the RX/multicast filter. We do this sort of late
3439 * because the filter programming scheme on the 21143 and
3440 * some clones requires DMAing a setup frame via the TX
3441 * engine, and we need the transmitter enabled for that.
3442 */
3443 dc_setfilt(sc);
3444
3445 /* Enable receiver. */
3446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3447 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3448
3449 mii_mediachg(mii);
3450 dc_setcfg(sc, sc->dc_if_media);
3451
3452 ifp->if_flags |= IFF_RUNNING;
3453 ifp->if_flags &= ~IFF_OACTIVE;
3454
3455 /* Don't start the ticker if this is a homePNA link. */
3456 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3457 sc->dc_link = 1;
3458 else {
3459 if (sc->dc_flags & DC_21143_NWAY)
3460 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3461 else
3462 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3463 }
3464
3465 #ifdef SRM_MEDIA
3466 if(sc->dc_srm_media) {
3467 struct ifreq ifr;
3468
3469 ifr.ifr_media = sc->dc_srm_media;
3470 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA);
3471 sc->dc_srm_media = 0;
3472 }
3473 #endif
3474 DC_UNLOCK(sc);
3475 return;
3476 }
3477
3478 /*
3479 * Set media options.
3480 */
3481 static int
3482 dc_ifmedia_upd(ifp)
3483 struct ifnet *ifp;
3484 {
3485 struct dc_softc *sc;
3486 struct mii_data *mii;
3487 struct ifmedia *ifm;
3488
3489 sc = ifp->if_softc;
3490 mii = device_get_softc(sc->dc_miibus);
3491 mii_mediachg(mii);
3492 ifm = &mii->mii_media;
3493
3494 if (DC_IS_DAVICOM(sc) &&
3495 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3496 dc_setcfg(sc, ifm->ifm_media);
3497 else
3498 sc->dc_link = 0;
3499
3500 return(0);
3501 }
3502
3503 /*
3504 * Report current media status.
3505 */
3506 static void
3507 dc_ifmedia_sts(ifp, ifmr)
3508 struct ifnet *ifp;
3509 struct ifmediareq *ifmr;
3510 {
3511 struct dc_softc *sc;
3512 struct mii_data *mii;
3513 struct ifmedia *ifm;
3514
3515 sc = ifp->if_softc;
3516 mii = device_get_softc(sc->dc_miibus);
3517 mii_pollstat(mii);
3518 ifm = &mii->mii_media;
3519 if (DC_IS_DAVICOM(sc)) {
3520 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3521 ifmr->ifm_active = ifm->ifm_media;
3522 ifmr->ifm_status = 0;
3523 return;
3524 }
3525 }
3526 ifmr->ifm_active = mii->mii_media_active;
3527 ifmr->ifm_status = mii->mii_media_status;
3528
3529 return;
3530 }
3531
3532 static int
3533 dc_ioctl(ifp, command, data)
3534 struct ifnet *ifp;
3535 u_long command;
3536 caddr_t data;
3537 {
3538 struct dc_softc *sc = ifp->if_softc;
3539 struct ifreq *ifr = (struct ifreq *) data;
3540 struct mii_data *mii;
3541 int error = 0;
3542
3543 DC_LOCK(sc);
3544
3545 switch(command) {
3546 case SIOCSIFFLAGS:
3547 if (ifp->if_flags & IFF_UP) {
3548 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3549 (IFF_PROMISC | IFF_ALLMULTI);
3550
3551 if (ifp->if_flags & IFF_RUNNING) {
3552 if (need_setfilt)
3553 dc_setfilt(sc);
3554 } else {
3555 sc->dc_txthresh = 0;
3556 dc_init(sc);
3557 }
3558 } else {
3559 if (ifp->if_flags & IFF_RUNNING)
3560 dc_stop(sc);
3561 }
3562 sc->dc_if_flags = ifp->if_flags;
3563 error = 0;
3564 break;
3565 case SIOCADDMULTI:
3566 case SIOCDELMULTI:
3567 dc_setfilt(sc);
3568 error = 0;
3569 break;
3570 case SIOCGIFMEDIA:
3571 case SIOCSIFMEDIA:
3572 mii = device_get_softc(sc->dc_miibus);
3573 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3574 #ifdef SRM_MEDIA
3575 if (sc->dc_srm_media)
3576 sc->dc_srm_media = 0;
3577 #endif
3578 break;
3579 default:
3580 error = ether_ioctl(ifp, command, data);
3581 break;
3582 }
3583
3584 DC_UNLOCK(sc);
3585
3586 return(error);
3587 }
3588
3589 static void
3590 dc_watchdog(ifp)
3591 struct ifnet *ifp;
3592 {
3593 struct dc_softc *sc;
3594
3595 sc = ifp->if_softc;
3596
3597 DC_LOCK(sc);
3598
3599 ifp->if_oerrors++;
3600 printf("dc%d: watchdog timeout\n", sc->dc_unit);
3601
3602 dc_stop(sc);
3603 dc_reset(sc);
3604 dc_init(sc);
3605
3606 if (ifp->if_snd.ifq_head != NULL)
3607 dc_start(ifp);
3608
3609 DC_UNLOCK(sc);
3610
3611 return;
3612 }
3613
3614 /*
3615 * Stop the adapter and free any mbufs allocated to the
3616 * RX and TX lists.
3617 */
3618 static void
3619 dc_stop(sc)
3620 struct dc_softc *sc;
3621 {
3622 register int i;
3623 struct ifnet *ifp;
3624
3625 DC_LOCK(sc);
3626
3627 ifp = &sc->arpcom.ac_if;
3628 ifp->if_timer = 0;
3629
3630 callout_stop(&sc->dc_stat_ch);
3631
3632 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3633 #ifdef DEVICE_POLLING
3634 ether_poll_deregister(ifp);
3635 #endif
3636
3637 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON));
3638 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3639 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3640 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3641 sc->dc_link = 0;
3642
3643 /*
3644 * Free data in the RX lists.
3645 */
3646 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3647 if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3648 m_freem(sc->dc_cdata.dc_rx_chain[i]);
3649 sc->dc_cdata.dc_rx_chain[i] = NULL;
3650 }
3651 }
3652 bzero((char *)&sc->dc_ldata->dc_rx_list,
3653 sizeof(sc->dc_ldata->dc_rx_list));
3654
3655 /*
3656 * Free the TX list buffers.
3657 */
3658 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3659 if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3660 if (sc->dc_ldata->dc_tx_list[i].dc_ctl &
3661 DC_TXCTL_SETUP) {
3662 sc->dc_cdata.dc_tx_chain[i] = NULL;
3663 continue;
3664 }
3665 m_freem(sc->dc_cdata.dc_tx_chain[i]);
3666 sc->dc_cdata.dc_tx_chain[i] = NULL;
3667 }
3668 }
3669
3670 bzero((char *)&sc->dc_ldata->dc_tx_list,
3671 sizeof(sc->dc_ldata->dc_tx_list));
3672
3673 DC_UNLOCK(sc);
3674
3675 return;
3676 }
3677
3678 /*
3679 * Device suspend routine. Stop the interface and save some PCI
3680 * settings in case the BIOS doesn't restore them properly on
3681 * resume.
3682 */
3683 static int
3684 dc_suspend(dev)
3685 device_t dev;
3686 {
3687 register int i;
3688 int s;
3689 struct dc_softc *sc;
3690
3691 s = splimp();
3692
3693 sc = device_get_softc(dev);
3694
3695 dc_stop(sc);
3696
3697 for (i = 0; i < 5; i++)
3698 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3699 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3700 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3701 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3702 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3703
3704 sc->suspended = 1;
3705
3706 splx(s);
3707 return (0);
3708 }
3709
3710 /*
3711 * Device resume routine. Restore some PCI settings in case the BIOS
3712 * doesn't, re-enable busmastering, and restart the interface if
3713 * appropriate.
3714 */
3715 static int
3716 dc_resume(dev)
3717 device_t dev;
3718 {
3719 register int i;
3720 int s;
3721 struct dc_softc *sc;
3722 struct ifnet *ifp;
3723
3724 s = splimp();
3725
3726 sc = device_get_softc(dev);
3727 ifp = &sc->arpcom.ac_if;
3728
3729 dc_acpi(dev);
3730
3731 /* better way to do this? */
3732 for (i = 0; i < 5; i++)
3733 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3734 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3735 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3736 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3737 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3738
3739 /* reenable busmastering */
3740 pci_enable_busmaster(dev);
3741 pci_enable_io(dev, DC_RES);
3742
3743 /* reinitialize interface if necessary */
3744 if (ifp->if_flags & IFF_UP)
3745 dc_init(sc);
3746
3747 sc->suspended = 0;
3748
3749 splx(s);
3750 return (0);
3751 }
3752
3753 /*
3754 * Stop all chip I/O so that the kernel's probe routines don't
3755 * get confused by errant DMAs when rebooting.
3756 */
3757 static void
3758 dc_shutdown(dev)
3759 device_t dev;
3760 {
3761 struct dc_softc *sc;
3762
3763 sc = device_get_softc(dev);
3764
3765 dc_stop(sc);
3766
3767 return;
3768 }
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