Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/pci/if_dc.c
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 35 * series chips and several workalikes including the following: 36 * 37 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 38 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 39 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 40 * ASIX Electronics AX88140A (www.asix.com.tw) 41 * ASIX Electronics AX88141 (www.asix.com.tw) 42 * ADMtek AL981 (www.admtek.com.tw) 43 * ADMtek AN985 (www.admtek.com.tw) 44 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 45 * Accton EN1217 (www.accton.com) 46 * Xircom X3201 (www.xircom.com) 47 * Abocom FE2500 48 * Conexant LANfinity (www.conexant.com) 49 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 50 * 51 * Datasheets for the 21143 are available at developer.intel.com. 52 * Datasheets for the clone parts can be found at their respective sites. 53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 54 * The PNIC II is essentially a Macronix 98715A chip; the only difference 55 * worth noting is that its multicast hash table is only 128 bits wide 56 * instead of 512. 57 * 58 * Written by Bill Paul <wpaul@ee.columbia.edu> 59 * Electrical Engineering Department 60 * Columbia University, New York City 61 */ 62 63 /* 64 * The Intel 21143 is the successor to the DEC 21140. It is basically 65 * the same as the 21140 but with a few new features. The 21143 supports 66 * three kinds of media attachments: 67 * 68 * o MII port, for 10Mbps and 100Mbps support and NWAY 69 * autonegotiation provided by an external PHY. 70 * o SYM port, for symbol mode 100Mbps support. 71 * o 10baseT port. 72 * o AUI/BNC port. 73 * 74 * The 100Mbps SYM port and 10baseT port can be used together in 75 * combination with the internal NWAY support to create a 10/100 76 * autosensing configuration. 77 * 78 * Note that not all tulip workalikes are handled in this driver: we only 79 * deal with those which are relatively well behaved. The Winbond is 80 * handled separately due to its different register offsets and the 81 * special handling needed for its various bugs. The PNIC is handled 82 * here, but I'm not thrilled about it. 83 * 84 * All of the workalike chips use some form of MII transceiver support 85 * with the exception of the Macronix chips, which also have a SYM port. 86 * The ASIX AX88140A is also documented to have a SYM port, but all 87 * the cards I've seen use an MII transceiver, probably because the 88 * AX88140A doesn't support internal NWAY. 89 */ 90 91 #include <sys/cdefs.h> 92 __FBSDID("$FreeBSD: releng/5.1/sys/pci/if_dc.c 115029 2003-05-15 16:53:29Z mbr $"); 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/sockio.h> 97 #include <sys/mbuf.h> 98 #include <sys/malloc.h> 99 #include <sys/kernel.h> 100 #include <sys/socket.h> 101 #include <sys/sysctl.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/ethernet.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 #include <net/if_types.h> 109 #include <net/if_vlan_var.h> 110 111 #include <net/bpf.h> 112 113 #include <vm/vm.h> /* for vtophys */ 114 #include <vm/pmap.h> /* for vtophys */ 115 #include <machine/bus_pio.h> 116 #include <machine/bus_memio.h> 117 #include <machine/bus.h> 118 #include <machine/resource.h> 119 #include <sys/bus.h> 120 #include <sys/rman.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <pci/pcireg.h> 126 #include <pci/pcivar.h> 127 128 #define DC_USEIOSPACE 129 #ifdef __alpha__ 130 #define SRM_MEDIA 131 #endif 132 133 #include <pci/if_dcreg.h> 134 135 MODULE_DEPEND(dc, pci, 1, 1, 1); 136 MODULE_DEPEND(dc, ether, 1, 1, 1); 137 MODULE_DEPEND(dc, miibus, 1, 1, 1); 138 139 /* "controller miibus0" required. See GENERIC if you get errors here. */ 140 #include "miibus_if.h" 141 142 /* 143 * Various supported device vendors/types and their names. 144 */ 145 static struct dc_type dc_devs[] = { 146 { DC_VENDORID_DEC, DC_DEVICEID_21143, 147 "Intel 21143 10/100BaseTX" }, 148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 149 "Davicom DM9009 10/100BaseTX" }, 150 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 151 "Davicom DM9100 10/100BaseTX" }, 152 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 153 "Davicom DM9102 10/100BaseTX" }, 154 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 155 "Davicom DM9102A 10/100BaseTX" }, 156 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 157 "ADMtek AL981 10/100BaseTX" }, 158 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 159 "ADMtek AN985 10/100BaseTX" }, 160 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 161 "ASIX AX88140A 10/100BaseTX" }, 162 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 163 "ASIX AX88141 10/100BaseTX" }, 164 { DC_VENDORID_MX, DC_DEVICEID_98713, 165 "Macronix 98713 10/100BaseTX" }, 166 { DC_VENDORID_MX, DC_DEVICEID_98713, 167 "Macronix 98713A 10/100BaseTX" }, 168 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 169 "Compex RL100-TX 10/100BaseTX" }, 170 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 171 "Compex RL100-TX 10/100BaseTX" }, 172 { DC_VENDORID_MX, DC_DEVICEID_987x5, 173 "Macronix 98715/98715A 10/100BaseTX" }, 174 { DC_VENDORID_MX, DC_DEVICEID_987x5, 175 "Macronix 98715AEC-C 10/100BaseTX" }, 176 { DC_VENDORID_MX, DC_DEVICEID_987x5, 177 "Macronix 98725 10/100BaseTX" }, 178 { DC_VENDORID_MX, DC_DEVICEID_98727, 179 "Macronix 98727/98732 10/100BaseTX" }, 180 { DC_VENDORID_LO, DC_DEVICEID_82C115, 181 "LC82C115 PNIC II 10/100BaseTX" }, 182 { DC_VENDORID_LO, DC_DEVICEID_82C168, 183 "82c168 PNIC 10/100BaseTX" }, 184 { DC_VENDORID_LO, DC_DEVICEID_82C168, 185 "82c169 PNIC 10/100BaseTX" }, 186 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 187 "Accton EN1217 10/100BaseTX" }, 188 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 189 "Accton EN2242 MiniPCI 10/100BaseTX" }, 190 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 191 "Xircom X3201 10/100BaseTX" }, 192 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 193 "Abocom FE2500 10/100BaseTX" }, 194 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 195 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 196 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 197 "Hawking CB102 CardBus 10/100" }, 198 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 199 "PlaneX FNW-3602-T CardBus 10/100" }, 200 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 201 "3Com OfficeConnect 10/100B" }, 202 { 0, 0, NULL } 203 }; 204 205 static int dc_probe (device_t); 206 static int dc_attach (device_t); 207 static int dc_detach (device_t); 208 static int dc_suspend (device_t); 209 static int dc_resume (device_t); 210 static void dc_acpi (device_t); 211 static struct dc_type *dc_devtype (device_t); 212 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 213 static int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *); 214 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 215 static int dc_rx_resync (struct dc_softc *); 216 static void dc_rxeof (struct dc_softc *); 217 static void dc_txeof (struct dc_softc *); 218 static void dc_tick (void *); 219 static void dc_tx_underrun (struct dc_softc *); 220 static void dc_intr (void *); 221 static void dc_start (struct ifnet *); 222 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 223 static void dc_init (void *); 224 static void dc_stop (struct dc_softc *); 225 static void dc_watchdog (struct ifnet *); 226 static void dc_shutdown (device_t); 227 static int dc_ifmedia_upd (struct ifnet *); 228 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 229 230 static void dc_delay (struct dc_softc *); 231 static void dc_eeprom_idle (struct dc_softc *); 232 static void dc_eeprom_putbyte (struct dc_softc *, int); 233 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 234 static void dc_eeprom_getword_pnic 235 (struct dc_softc *, int, u_int16_t *); 236 static void dc_eeprom_getword_xircom 237 (struct dc_softc *, int, u_int16_t *); 238 static void dc_eeprom_width (struct dc_softc *); 239 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 240 241 static void dc_mii_writebit (struct dc_softc *, int); 242 static int dc_mii_readbit (struct dc_softc *); 243 static void dc_mii_sync (struct dc_softc *); 244 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 245 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 246 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 247 static int dc_miibus_readreg (device_t, int, int); 248 static int dc_miibus_writereg (device_t, int, int, int); 249 static void dc_miibus_statchg (device_t); 250 static void dc_miibus_mediainit (device_t); 251 252 static void dc_setcfg (struct dc_softc *, int); 253 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 254 static u_int32_t dc_crc_be (caddr_t); 255 static void dc_setfilt_21143 (struct dc_softc *); 256 static void dc_setfilt_asix (struct dc_softc *); 257 static void dc_setfilt_admtek (struct dc_softc *); 258 static void dc_setfilt_xircom (struct dc_softc *); 259 260 static void dc_setfilt (struct dc_softc *); 261 262 static void dc_reset (struct dc_softc *); 263 static int dc_list_rx_init (struct dc_softc *); 264 static int dc_list_tx_init (struct dc_softc *); 265 266 static void dc_read_srom (struct dc_softc *, int); 267 static void dc_parse_21143_srom (struct dc_softc *); 268 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 269 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 270 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 271 static void dc_apply_fixup (struct dc_softc *, int); 272 273 #ifdef DC_USEIOSPACE 274 #define DC_RES SYS_RES_IOPORT 275 #define DC_RID DC_PCI_CFBIO 276 #else 277 #define DC_RES SYS_RES_MEMORY 278 #define DC_RID DC_PCI_CFBMA 279 #endif 280 281 static device_method_t dc_methods[] = { 282 /* Device interface */ 283 DEVMETHOD(device_probe, dc_probe), 284 DEVMETHOD(device_attach, dc_attach), 285 DEVMETHOD(device_detach, dc_detach), 286 DEVMETHOD(device_suspend, dc_suspend), 287 DEVMETHOD(device_resume, dc_resume), 288 DEVMETHOD(device_shutdown, dc_shutdown), 289 290 /* bus interface */ 291 DEVMETHOD(bus_print_child, bus_generic_print_child), 292 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 293 294 /* MII interface */ 295 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 296 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 297 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 298 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 299 300 { 0, 0 } 301 }; 302 303 static driver_t dc_driver = { 304 "dc", 305 dc_methods, 306 sizeof(struct dc_softc) 307 }; 308 309 static devclass_t dc_devclass; 310 #ifdef __i386__ 311 static int dc_quick=1; 312 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 313 &dc_quick,0,"do not mdevget in dc driver"); 314 #endif 315 316 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 317 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 318 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 319 320 #define DC_SETBIT(sc, reg, x) \ 321 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 322 323 #define DC_CLRBIT(sc, reg, x) \ 324 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 325 326 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 327 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 328 329 #define IS_MPSAFE 0 330 331 static void 332 dc_delay(sc) 333 struct dc_softc *sc; 334 { 335 int idx; 336 337 for (idx = (300 / 33) + 1; idx > 0; idx--) 338 CSR_READ_4(sc, DC_BUSCTL); 339 } 340 341 static void 342 dc_eeprom_width(sc) 343 struct dc_softc *sc; 344 { 345 int i; 346 347 /* Force EEPROM to idle state. */ 348 dc_eeprom_idle(sc); 349 350 /* Enter EEPROM access mode. */ 351 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 352 dc_delay(sc); 353 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 354 dc_delay(sc); 355 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 356 dc_delay(sc); 357 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 358 dc_delay(sc); 359 360 for (i = 3; i--;) { 361 if (6 & (1 << i)) 362 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 363 else 364 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 365 dc_delay(sc); 366 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 367 dc_delay(sc); 368 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 369 dc_delay(sc); 370 } 371 372 for (i = 1; i <= 12; i++) { 373 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 374 dc_delay(sc); 375 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 376 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 377 dc_delay(sc); 378 break; 379 } 380 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 381 dc_delay(sc); 382 } 383 384 /* Turn off EEPROM access mode. */ 385 dc_eeprom_idle(sc); 386 387 if (i < 4 || i > 12) 388 sc->dc_romwidth = 6; 389 else 390 sc->dc_romwidth = i; 391 392 /* Enter EEPROM access mode. */ 393 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 394 dc_delay(sc); 395 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 396 dc_delay(sc); 397 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 398 dc_delay(sc); 399 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 400 dc_delay(sc); 401 402 /* Turn off EEPROM access mode. */ 403 dc_eeprom_idle(sc); 404 } 405 406 static void 407 dc_eeprom_idle(sc) 408 struct dc_softc *sc; 409 { 410 register int i; 411 412 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 413 dc_delay(sc); 414 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 415 dc_delay(sc); 416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 417 dc_delay(sc); 418 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 419 dc_delay(sc); 420 421 for (i = 0; i < 25; i++) { 422 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 423 dc_delay(sc); 424 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 425 dc_delay(sc); 426 } 427 428 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 429 dc_delay(sc); 430 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 431 dc_delay(sc); 432 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 433 434 return; 435 } 436 437 /* 438 * Send a read command and address to the EEPROM, check for ACK. 439 */ 440 static void 441 dc_eeprom_putbyte(sc, addr) 442 struct dc_softc *sc; 443 int addr; 444 { 445 register int d, i; 446 447 d = DC_EECMD_READ >> 6; 448 for (i = 3; i--; ) { 449 if (d & (1 << i)) 450 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 451 else 452 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 453 dc_delay(sc); 454 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 455 dc_delay(sc); 456 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 457 dc_delay(sc); 458 } 459 460 /* 461 * Feed in each bit and strobe the clock. 462 */ 463 for (i = sc->dc_romwidth; i--;) { 464 if (addr & (1 << i)) { 465 SIO_SET(DC_SIO_EE_DATAIN); 466 } else { 467 SIO_CLR(DC_SIO_EE_DATAIN); 468 } 469 dc_delay(sc); 470 SIO_SET(DC_SIO_EE_CLK); 471 dc_delay(sc); 472 SIO_CLR(DC_SIO_EE_CLK); 473 dc_delay(sc); 474 } 475 476 return; 477 } 478 479 /* 480 * Read a word of data stored in the EEPROM at address 'addr.' 481 * The PNIC 82c168/82c169 has its own non-standard way to read 482 * the EEPROM. 483 */ 484 static void 485 dc_eeprom_getword_pnic(sc, addr, dest) 486 struct dc_softc *sc; 487 int addr; 488 u_int16_t *dest; 489 { 490 register int i; 491 u_int32_t r; 492 493 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 494 495 for (i = 0; i < DC_TIMEOUT; i++) { 496 DELAY(1); 497 r = CSR_READ_4(sc, DC_SIO); 498 if (!(r & DC_PN_SIOCTL_BUSY)) { 499 *dest = (u_int16_t)(r & 0xFFFF); 500 return; 501 } 502 } 503 504 return; 505 } 506 507 /* 508 * Read a word of data stored in the EEPROM at address 'addr.' 509 * The Xircom X3201 has its own non-standard way to read 510 * the EEPROM, too. 511 */ 512 static void 513 dc_eeprom_getword_xircom(sc, addr, dest) 514 struct dc_softc *sc; 515 int addr; 516 u_int16_t *dest; 517 { 518 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 519 520 addr *= 2; 521 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 522 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 523 addr += 1; 524 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 525 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 526 527 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 528 return; 529 } 530 531 /* 532 * Read a word of data stored in the EEPROM at address 'addr.' 533 */ 534 static void 535 dc_eeprom_getword(sc, addr, dest) 536 struct dc_softc *sc; 537 int addr; 538 u_int16_t *dest; 539 { 540 register int i; 541 u_int16_t word = 0; 542 543 /* Force EEPROM to idle state. */ 544 dc_eeprom_idle(sc); 545 546 /* Enter EEPROM access mode. */ 547 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 548 dc_delay(sc); 549 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 550 dc_delay(sc); 551 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 552 dc_delay(sc); 553 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 554 dc_delay(sc); 555 556 /* 557 * Send address of word we want to read. 558 */ 559 dc_eeprom_putbyte(sc, addr); 560 561 /* 562 * Start reading bits from EEPROM. 563 */ 564 for (i = 0x8000; i; i >>= 1) { 565 SIO_SET(DC_SIO_EE_CLK); 566 dc_delay(sc); 567 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 568 word |= i; 569 dc_delay(sc); 570 SIO_CLR(DC_SIO_EE_CLK); 571 dc_delay(sc); 572 } 573 574 /* Turn off EEPROM access mode. */ 575 dc_eeprom_idle(sc); 576 577 *dest = word; 578 579 return; 580 } 581 582 /* 583 * Read a sequence of words from the EEPROM. 584 */ 585 static void 586 dc_read_eeprom(sc, dest, off, cnt, swap) 587 struct dc_softc *sc; 588 caddr_t dest; 589 int off; 590 int cnt; 591 int swap; 592 { 593 int i; 594 u_int16_t word = 0, *ptr; 595 596 for (i = 0; i < cnt; i++) { 597 if (DC_IS_PNIC(sc)) 598 dc_eeprom_getword_pnic(sc, off + i, &word); 599 else if (DC_IS_XIRCOM(sc)) 600 dc_eeprom_getword_xircom(sc, off + i, &word); 601 else 602 dc_eeprom_getword(sc, off + i, &word); 603 ptr = (u_int16_t *)(dest + (i * 2)); 604 if (swap) 605 *ptr = ntohs(word); 606 else 607 *ptr = word; 608 } 609 610 return; 611 } 612 613 /* 614 * The following two routines are taken from the Macronix 98713 615 * Application Notes pp.19-21. 616 */ 617 /* 618 * Write a bit to the MII bus. 619 */ 620 static void 621 dc_mii_writebit(sc, bit) 622 struct dc_softc *sc; 623 int bit; 624 { 625 if (bit) 626 CSR_WRITE_4(sc, DC_SIO, 627 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 628 else 629 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 630 631 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 632 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 633 634 return; 635 } 636 637 /* 638 * Read a bit from the MII bus. 639 */ 640 static int 641 dc_mii_readbit(sc) 642 struct dc_softc *sc; 643 { 644 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 645 CSR_READ_4(sc, DC_SIO); 646 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 647 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 648 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 649 return(1); 650 651 return(0); 652 } 653 654 /* 655 * Sync the PHYs by setting data bit and strobing the clock 32 times. 656 */ 657 static void 658 dc_mii_sync(sc) 659 struct dc_softc *sc; 660 { 661 register int i; 662 663 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 664 665 for (i = 0; i < 32; i++) 666 dc_mii_writebit(sc, 1); 667 668 return; 669 } 670 671 /* 672 * Clock a series of bits through the MII. 673 */ 674 static void 675 dc_mii_send(sc, bits, cnt) 676 struct dc_softc *sc; 677 u_int32_t bits; 678 int cnt; 679 { 680 int i; 681 682 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 683 dc_mii_writebit(sc, bits & i); 684 } 685 686 /* 687 * Read an PHY register through the MII. 688 */ 689 static int 690 dc_mii_readreg(sc, frame) 691 struct dc_softc *sc; 692 struct dc_mii_frame *frame; 693 694 { 695 int i, ack; 696 697 DC_LOCK(sc); 698 699 /* 700 * Set up frame for RX. 701 */ 702 frame->mii_stdelim = DC_MII_STARTDELIM; 703 frame->mii_opcode = DC_MII_READOP; 704 frame->mii_turnaround = 0; 705 frame->mii_data = 0; 706 707 /* 708 * Sync the PHYs. 709 */ 710 dc_mii_sync(sc); 711 712 /* 713 * Send command/address info. 714 */ 715 dc_mii_send(sc, frame->mii_stdelim, 2); 716 dc_mii_send(sc, frame->mii_opcode, 2); 717 dc_mii_send(sc, frame->mii_phyaddr, 5); 718 dc_mii_send(sc, frame->mii_regaddr, 5); 719 720 #ifdef notdef 721 /* Idle bit */ 722 dc_mii_writebit(sc, 1); 723 dc_mii_writebit(sc, 0); 724 #endif 725 726 /* Check for ack */ 727 ack = dc_mii_readbit(sc); 728 729 /* 730 * Now try reading data bits. If the ack failed, we still 731 * need to clock through 16 cycles to keep the PHY(s) in sync. 732 */ 733 if (ack) { 734 for(i = 0; i < 16; i++) { 735 dc_mii_readbit(sc); 736 } 737 goto fail; 738 } 739 740 for (i = 0x8000; i; i >>= 1) { 741 if (!ack) { 742 if (dc_mii_readbit(sc)) 743 frame->mii_data |= i; 744 } 745 } 746 747 fail: 748 749 dc_mii_writebit(sc, 0); 750 dc_mii_writebit(sc, 0); 751 752 DC_UNLOCK(sc); 753 754 if (ack) 755 return(1); 756 return(0); 757 } 758 759 /* 760 * Write to a PHY register through the MII. 761 */ 762 static int 763 dc_mii_writereg(sc, frame) 764 struct dc_softc *sc; 765 struct dc_mii_frame *frame; 766 767 { 768 DC_LOCK(sc); 769 /* 770 * Set up frame for TX. 771 */ 772 773 frame->mii_stdelim = DC_MII_STARTDELIM; 774 frame->mii_opcode = DC_MII_WRITEOP; 775 frame->mii_turnaround = DC_MII_TURNAROUND; 776 777 /* 778 * Sync the PHYs. 779 */ 780 dc_mii_sync(sc); 781 782 dc_mii_send(sc, frame->mii_stdelim, 2); 783 dc_mii_send(sc, frame->mii_opcode, 2); 784 dc_mii_send(sc, frame->mii_phyaddr, 5); 785 dc_mii_send(sc, frame->mii_regaddr, 5); 786 dc_mii_send(sc, frame->mii_turnaround, 2); 787 dc_mii_send(sc, frame->mii_data, 16); 788 789 /* Idle bit. */ 790 dc_mii_writebit(sc, 0); 791 dc_mii_writebit(sc, 0); 792 793 DC_UNLOCK(sc); 794 795 return(0); 796 } 797 798 static int 799 dc_miibus_readreg(dev, phy, reg) 800 device_t dev; 801 int phy, reg; 802 { 803 struct dc_mii_frame frame; 804 struct dc_softc *sc; 805 int i, rval, phy_reg = 0; 806 807 sc = device_get_softc(dev); 808 bzero((char *)&frame, sizeof(frame)); 809 810 /* 811 * Note: both the AL981 and AN985 have internal PHYs, 812 * however the AL981 provides direct access to the PHY 813 * registers while the AN985 uses a serial MII interface. 814 * The AN985's MII interface is also buggy in that you 815 * can read from any MII address (0 to 31), but only address 1 816 * behaves normally. To deal with both cases, we pretend 817 * that the PHY is at MII address 1. 818 */ 819 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 820 return(0); 821 822 /* 823 * Note: the ukphy probes of the RS7112 report a PHY at 824 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 825 * so we only respond to correct one. 826 */ 827 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 828 return(0); 829 830 if (sc->dc_pmode != DC_PMODE_MII) { 831 if (phy == (MII_NPHY - 1)) { 832 switch(reg) { 833 case MII_BMSR: 834 /* 835 * Fake something to make the probe 836 * code think there's a PHY here. 837 */ 838 return(BMSR_MEDIAMASK); 839 break; 840 case MII_PHYIDR1: 841 if (DC_IS_PNIC(sc)) 842 return(DC_VENDORID_LO); 843 return(DC_VENDORID_DEC); 844 break; 845 case MII_PHYIDR2: 846 if (DC_IS_PNIC(sc)) 847 return(DC_DEVICEID_82C168); 848 return(DC_DEVICEID_21143); 849 break; 850 default: 851 return(0); 852 break; 853 } 854 } else 855 return(0); 856 } 857 858 if (DC_IS_PNIC(sc)) { 859 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 860 (phy << 23) | (reg << 18)); 861 for (i = 0; i < DC_TIMEOUT; i++) { 862 DELAY(1); 863 rval = CSR_READ_4(sc, DC_PN_MII); 864 if (!(rval & DC_PN_MII_BUSY)) { 865 rval &= 0xFFFF; 866 return(rval == 0xFFFF ? 0 : rval); 867 } 868 } 869 return(0); 870 } 871 872 if (DC_IS_COMET(sc)) { 873 switch(reg) { 874 case MII_BMCR: 875 phy_reg = DC_AL_BMCR; 876 break; 877 case MII_BMSR: 878 phy_reg = DC_AL_BMSR; 879 break; 880 case MII_PHYIDR1: 881 phy_reg = DC_AL_VENID; 882 break; 883 case MII_PHYIDR2: 884 phy_reg = DC_AL_DEVID; 885 break; 886 case MII_ANAR: 887 phy_reg = DC_AL_ANAR; 888 break; 889 case MII_ANLPAR: 890 phy_reg = DC_AL_LPAR; 891 break; 892 case MII_ANER: 893 phy_reg = DC_AL_ANER; 894 break; 895 default: 896 printf("dc%d: phy_read: bad phy register %x\n", 897 sc->dc_unit, reg); 898 return(0); 899 break; 900 } 901 902 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 903 904 if (rval == 0xFFFF) 905 return(0); 906 return(rval); 907 } 908 909 frame.mii_phyaddr = phy; 910 frame.mii_regaddr = reg; 911 if (sc->dc_type == DC_TYPE_98713) { 912 phy_reg = CSR_READ_4(sc, DC_NETCFG); 913 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 914 } 915 dc_mii_readreg(sc, &frame); 916 if (sc->dc_type == DC_TYPE_98713) 917 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 918 919 return(frame.mii_data); 920 } 921 922 static int 923 dc_miibus_writereg(dev, phy, reg, data) 924 device_t dev; 925 int phy, reg, data; 926 { 927 struct dc_softc *sc; 928 struct dc_mii_frame frame; 929 int i, phy_reg = 0; 930 931 sc = device_get_softc(dev); 932 bzero((char *)&frame, sizeof(frame)); 933 934 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 935 return(0); 936 937 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 938 return(0); 939 940 if (DC_IS_PNIC(sc)) { 941 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 942 (phy << 23) | (reg << 10) | data); 943 for (i = 0; i < DC_TIMEOUT; i++) { 944 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 945 break; 946 } 947 return(0); 948 } 949 950 if (DC_IS_COMET(sc)) { 951 switch(reg) { 952 case MII_BMCR: 953 phy_reg = DC_AL_BMCR; 954 break; 955 case MII_BMSR: 956 phy_reg = DC_AL_BMSR; 957 break; 958 case MII_PHYIDR1: 959 phy_reg = DC_AL_VENID; 960 break; 961 case MII_PHYIDR2: 962 phy_reg = DC_AL_DEVID; 963 break; 964 case MII_ANAR: 965 phy_reg = DC_AL_ANAR; 966 break; 967 case MII_ANLPAR: 968 phy_reg = DC_AL_LPAR; 969 break; 970 case MII_ANER: 971 phy_reg = DC_AL_ANER; 972 break; 973 default: 974 printf("dc%d: phy_write: bad phy register %x\n", 975 sc->dc_unit, reg); 976 return(0); 977 break; 978 } 979 980 CSR_WRITE_4(sc, phy_reg, data); 981 return(0); 982 } 983 984 frame.mii_phyaddr = phy; 985 frame.mii_regaddr = reg; 986 frame.mii_data = data; 987 988 if (sc->dc_type == DC_TYPE_98713) { 989 phy_reg = CSR_READ_4(sc, DC_NETCFG); 990 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 991 } 992 dc_mii_writereg(sc, &frame); 993 if (sc->dc_type == DC_TYPE_98713) 994 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 995 996 return(0); 997 } 998 999 static void 1000 dc_miibus_statchg(dev) 1001 device_t dev; 1002 { 1003 struct dc_softc *sc; 1004 struct mii_data *mii; 1005 struct ifmedia *ifm; 1006 1007 sc = device_get_softc(dev); 1008 if (DC_IS_ADMTEK(sc)) 1009 return; 1010 1011 mii = device_get_softc(sc->dc_miibus); 1012 ifm = &mii->mii_media; 1013 if (DC_IS_DAVICOM(sc) && 1014 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 1015 dc_setcfg(sc, ifm->ifm_media); 1016 sc->dc_if_media = ifm->ifm_media; 1017 } else { 1018 dc_setcfg(sc, mii->mii_media_active); 1019 sc->dc_if_media = mii->mii_media_active; 1020 } 1021 1022 return; 1023 } 1024 1025 /* 1026 * Special support for DM9102A cards with HomePNA PHYs. Note: 1027 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 1028 * to be impossible to talk to the management interface of the DM9801 1029 * PHY (its MDIO pin is not connected to anything). Consequently, 1030 * the driver has to just 'know' about the additional mode and deal 1031 * with it itself. *sigh* 1032 */ 1033 static void 1034 dc_miibus_mediainit(dev) 1035 device_t dev; 1036 { 1037 struct dc_softc *sc; 1038 struct mii_data *mii; 1039 struct ifmedia *ifm; 1040 int rev; 1041 1042 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1043 1044 sc = device_get_softc(dev); 1045 mii = device_get_softc(sc->dc_miibus); 1046 ifm = &mii->mii_media; 1047 1048 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1049 ifmedia_add(ifm, IFM_ETHER|IFM_HPNA_1, 0, NULL); 1050 1051 return; 1052 } 1053 1054 #define DC_POLY 0xEDB88320 1055 #define DC_BITS_512 9 1056 #define DC_BITS_128 7 1057 #define DC_BITS_64 6 1058 1059 static u_int32_t 1060 dc_crc_le(sc, addr) 1061 struct dc_softc *sc; 1062 caddr_t addr; 1063 { 1064 u_int32_t idx, bit, data, crc; 1065 1066 /* Compute CRC for the address value. */ 1067 crc = 0xFFFFFFFF; /* initial value */ 1068 1069 for (idx = 0; idx < 6; idx++) { 1070 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1071 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1072 } 1073 1074 /* 1075 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1076 * chips is only 128 bits wide. 1077 */ 1078 if (sc->dc_flags & DC_128BIT_HASH) 1079 return (crc & ((1 << DC_BITS_128) - 1)); 1080 1081 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1082 if (sc->dc_flags & DC_64BIT_HASH) 1083 return (crc & ((1 << DC_BITS_64) - 1)); 1084 1085 /* Xircom's hash filtering table is different (read: weird) */ 1086 /* Xircom uses the LEAST significant bits */ 1087 if (DC_IS_XIRCOM(sc)) { 1088 if ((crc & 0x180) == 0x180) 1089 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 1090 else 1091 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 1092 } 1093 1094 return (crc & ((1 << DC_BITS_512) - 1)); 1095 } 1096 1097 /* 1098 * Calculate CRC of a multicast group address, return the lower 6 bits. 1099 */ 1100 static u_int32_t 1101 dc_crc_be(addr) 1102 caddr_t addr; 1103 { 1104 u_int32_t crc, carry; 1105 int i, j; 1106 u_int8_t c; 1107 1108 /* Compute CRC for the address value. */ 1109 crc = 0xFFFFFFFF; /* initial value */ 1110 1111 for (i = 0; i < 6; i++) { 1112 c = *(addr + i); 1113 for (j = 0; j < 8; j++) { 1114 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1115 crc <<= 1; 1116 c >>= 1; 1117 if (carry) 1118 crc = (crc ^ 0x04c11db6) | carry; 1119 } 1120 } 1121 1122 /* return the filter bit position */ 1123 return((crc >> 26) & 0x0000003F); 1124 } 1125 1126 /* 1127 * 21143-style RX filter setup routine. Filter programming is done by 1128 * downloading a special setup frame into the TX engine. 21143, Macronix, 1129 * PNIC, PNIC II and Davicom chips are programmed this way. 1130 * 1131 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1132 * address (our node address) and a 512-bit hash filter for multicast 1133 * frames. We also sneak the broadcast address into the hash filter since 1134 * we need that too. 1135 */ 1136 static void 1137 dc_setfilt_21143(sc) 1138 struct dc_softc *sc; 1139 { 1140 struct dc_desc *sframe; 1141 u_int32_t h, *sp; 1142 struct ifmultiaddr *ifma; 1143 struct ifnet *ifp; 1144 int i; 1145 1146 ifp = &sc->arpcom.ac_if; 1147 1148 i = sc->dc_cdata.dc_tx_prod; 1149 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1150 sc->dc_cdata.dc_tx_cnt++; 1151 sframe = &sc->dc_ldata->dc_tx_list[i]; 1152 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1153 bzero((char *)sp, DC_SFRAME_LEN); 1154 1155 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1156 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1157 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1158 1159 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1160 1161 /* If we want promiscuous mode, set the allframes bit. */ 1162 if (ifp->if_flags & IFF_PROMISC) 1163 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1164 else 1165 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1166 1167 if (ifp->if_flags & IFF_ALLMULTI) 1168 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1169 else 1170 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1171 1172 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1173 if (ifma->ifma_addr->sa_family != AF_LINK) 1174 continue; 1175 h = dc_crc_le(sc, 1176 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1177 sp[h >> 4] |= 1 << (h & 0xF); 1178 } 1179 1180 if (ifp->if_flags & IFF_BROADCAST) { 1181 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1182 sp[h >> 4] |= 1 << (h & 0xF); 1183 } 1184 1185 /* Set our MAC address */ 1186 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1187 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1188 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1189 1190 sframe->dc_status = DC_TXSTAT_OWN; 1191 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1192 1193 /* 1194 * The PNIC takes an exceedingly long time to process its 1195 * setup frame; wait 10ms after posting the setup frame 1196 * before proceeding, just so it has time to swallow its 1197 * medicine. 1198 */ 1199 DELAY(10000); 1200 1201 ifp->if_timer = 5; 1202 1203 return; 1204 } 1205 1206 static void 1207 dc_setfilt_admtek(sc) 1208 struct dc_softc *sc; 1209 { 1210 struct ifnet *ifp; 1211 int h = 0; 1212 u_int32_t hashes[2] = { 0, 0 }; 1213 struct ifmultiaddr *ifma; 1214 1215 ifp = &sc->arpcom.ac_if; 1216 1217 /* Init our MAC address */ 1218 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1219 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1220 1221 /* If we want promiscuous mode, set the allframes bit. */ 1222 if (ifp->if_flags & IFF_PROMISC) 1223 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1224 else 1225 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1226 1227 if (ifp->if_flags & IFF_ALLMULTI) 1228 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1229 else 1230 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1231 1232 /* first, zot all the existing hash bits */ 1233 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1234 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1235 1236 /* 1237 * If we're already in promisc or allmulti mode, we 1238 * don't have to bother programming the multicast filter. 1239 */ 1240 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1241 return; 1242 1243 /* now program new ones */ 1244 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1245 if (ifma->ifma_addr->sa_family != AF_LINK) 1246 continue; 1247 if (DC_IS_CENTAUR(sc)) 1248 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1249 else 1250 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1251 if (h < 32) 1252 hashes[0] |= (1 << h); 1253 else 1254 hashes[1] |= (1 << (h - 32)); 1255 } 1256 1257 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1258 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1259 1260 return; 1261 } 1262 1263 static void 1264 dc_setfilt_asix(sc) 1265 struct dc_softc *sc; 1266 { 1267 struct ifnet *ifp; 1268 int h = 0; 1269 u_int32_t hashes[2] = { 0, 0 }; 1270 struct ifmultiaddr *ifma; 1271 1272 ifp = &sc->arpcom.ac_if; 1273 1274 /* Init our MAC address */ 1275 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1276 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1277 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1278 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1279 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1280 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1281 1282 /* If we want promiscuous mode, set the allframes bit. */ 1283 if (ifp->if_flags & IFF_PROMISC) 1284 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1285 else 1286 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1287 1288 if (ifp->if_flags & IFF_ALLMULTI) 1289 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1290 else 1291 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1292 1293 /* 1294 * The ASIX chip has a special bit to enable reception 1295 * of broadcast frames. 1296 */ 1297 if (ifp->if_flags & IFF_BROADCAST) 1298 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1299 else 1300 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1301 1302 /* first, zot all the existing hash bits */ 1303 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1304 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1305 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1306 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1307 1308 /* 1309 * If we're already in promisc or allmulti mode, we 1310 * don't have to bother programming the multicast filter. 1311 */ 1312 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1313 return; 1314 1315 /* now program new ones */ 1316 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1317 if (ifma->ifma_addr->sa_family != AF_LINK) 1318 continue; 1319 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1320 if (h < 32) 1321 hashes[0] |= (1 << h); 1322 else 1323 hashes[1] |= (1 << (h - 32)); 1324 } 1325 1326 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1327 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1328 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1329 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1330 1331 return; 1332 } 1333 1334 static void 1335 dc_setfilt_xircom(sc) 1336 struct dc_softc *sc; 1337 { 1338 struct dc_desc *sframe; 1339 u_int32_t h, *sp; 1340 struct ifmultiaddr *ifma; 1341 struct ifnet *ifp; 1342 int i; 1343 1344 ifp = &sc->arpcom.ac_if; 1345 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1346 1347 i = sc->dc_cdata.dc_tx_prod; 1348 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1349 sc->dc_cdata.dc_tx_cnt++; 1350 sframe = &sc->dc_ldata->dc_tx_list[i]; 1351 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1352 bzero((char *)sp, DC_SFRAME_LEN); 1353 1354 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1355 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1356 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1357 1358 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1359 1360 /* If we want promiscuous mode, set the allframes bit. */ 1361 if (ifp->if_flags & IFF_PROMISC) 1362 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1363 else 1364 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1365 1366 if (ifp->if_flags & IFF_ALLMULTI) 1367 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1368 else 1369 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1370 1371 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1372 if (ifma->ifma_addr->sa_family != AF_LINK) 1373 continue; 1374 h = dc_crc_le(sc, 1375 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1376 sp[h >> 4] |= 1 << (h & 0xF); 1377 } 1378 1379 if (ifp->if_flags & IFF_BROADCAST) { 1380 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1381 sp[h >> 4] |= 1 << (h & 0xF); 1382 } 1383 1384 /* Set our MAC address */ 1385 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1386 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1387 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1388 1389 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1390 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1391 ifp->if_flags |= IFF_RUNNING; 1392 sframe->dc_status = DC_TXSTAT_OWN; 1393 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1394 1395 /* 1396 * wait some time... 1397 */ 1398 DELAY(1000); 1399 1400 ifp->if_timer = 5; 1401 1402 return; 1403 } 1404 1405 static void 1406 dc_setfilt(sc) 1407 struct dc_softc *sc; 1408 { 1409 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1410 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1411 dc_setfilt_21143(sc); 1412 1413 if (DC_IS_ASIX(sc)) 1414 dc_setfilt_asix(sc); 1415 1416 if (DC_IS_ADMTEK(sc)) 1417 dc_setfilt_admtek(sc); 1418 1419 if (DC_IS_XIRCOM(sc)) 1420 dc_setfilt_xircom(sc); 1421 1422 return; 1423 } 1424 1425 /* 1426 * In order to fiddle with the 1427 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1428 * first have to put the transmit and/or receive logic in the idle state. 1429 */ 1430 static void 1431 dc_setcfg(sc, media) 1432 struct dc_softc *sc; 1433 int media; 1434 { 1435 int i, restart = 0; 1436 u_int32_t isr; 1437 1438 if (IFM_SUBTYPE(media) == IFM_NONE) 1439 return; 1440 1441 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1442 restart = 1; 1443 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1444 1445 for (i = 0; i < DC_TIMEOUT; i++) { 1446 isr = CSR_READ_4(sc, DC_ISR); 1447 if (isr & DC_ISR_TX_IDLE && 1448 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1449 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1450 break; 1451 DELAY(10); 1452 } 1453 1454 if (i == DC_TIMEOUT) 1455 printf("dc%d: failed to force tx and " 1456 "rx to idle state\n", sc->dc_unit); 1457 } 1458 1459 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1460 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1461 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1462 if (sc->dc_pmode == DC_PMODE_MII) { 1463 int watchdogreg; 1464 1465 if (DC_IS_INTEL(sc)) { 1466 /* there's a write enable bit here that reads as 1 */ 1467 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1468 watchdogreg &= ~DC_WDOG_CTLWREN; 1469 watchdogreg |= DC_WDOG_JABBERDIS; 1470 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1471 } else { 1472 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1473 } 1474 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1475 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1476 if (sc->dc_type == DC_TYPE_98713) 1477 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1478 DC_NETCFG_SCRAMBLER)); 1479 if (!DC_IS_DAVICOM(sc)) 1480 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1481 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1482 if (DC_IS_INTEL(sc)) 1483 dc_apply_fixup(sc, IFM_AUTO); 1484 } else { 1485 if (DC_IS_PNIC(sc)) { 1486 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1487 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1488 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1489 } 1490 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1491 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1492 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1493 if (DC_IS_INTEL(sc)) 1494 dc_apply_fixup(sc, 1495 (media & IFM_GMASK) == IFM_FDX ? 1496 IFM_100_TX|IFM_FDX : IFM_100_TX); 1497 } 1498 } 1499 1500 if (IFM_SUBTYPE(media) == IFM_10_T) { 1501 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1502 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1503 if (sc->dc_pmode == DC_PMODE_MII) { 1504 int watchdogreg; 1505 1506 /* there's a write enable bit here that reads as 1 */ 1507 if (DC_IS_INTEL(sc)) { 1508 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1509 watchdogreg &= ~DC_WDOG_CTLWREN; 1510 watchdogreg |= DC_WDOG_JABBERDIS; 1511 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1512 } else { 1513 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1514 } 1515 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1516 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1517 if (sc->dc_type == DC_TYPE_98713) 1518 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1519 if (!DC_IS_DAVICOM(sc)) 1520 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1521 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1522 if (DC_IS_INTEL(sc)) 1523 dc_apply_fixup(sc, IFM_AUTO); 1524 } else { 1525 if (DC_IS_PNIC(sc)) { 1526 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1527 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1528 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1529 } 1530 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1531 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1532 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1533 if (DC_IS_INTEL(sc)) { 1534 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1535 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1536 if ((media & IFM_GMASK) == IFM_FDX) 1537 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1538 else 1539 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1540 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1541 DC_CLRBIT(sc, DC_10BTCTRL, 1542 DC_TCTL_AUTONEGENBL); 1543 dc_apply_fixup(sc, 1544 (media & IFM_GMASK) == IFM_FDX ? 1545 IFM_10_T|IFM_FDX : IFM_10_T); 1546 DELAY(20000); 1547 } 1548 } 1549 } 1550 1551 /* 1552 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1553 * PHY and we want HomePNA mode, set the portsel bit to turn 1554 * on the external MII port. 1555 */ 1556 if (DC_IS_DAVICOM(sc)) { 1557 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1558 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1559 sc->dc_link = 1; 1560 } else { 1561 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1562 } 1563 } 1564 1565 if ((media & IFM_GMASK) == IFM_FDX) { 1566 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1567 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1568 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1569 } else { 1570 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1571 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1572 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1573 } 1574 1575 if (restart) 1576 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1577 1578 return; 1579 } 1580 1581 static void 1582 dc_reset(sc) 1583 struct dc_softc *sc; 1584 { 1585 register int i; 1586 1587 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1588 1589 for (i = 0; i < DC_TIMEOUT; i++) { 1590 DELAY(10); 1591 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1592 break; 1593 } 1594 1595 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1596 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1597 DELAY(10000); 1598 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1599 i = 0; 1600 } 1601 1602 if (i == DC_TIMEOUT) 1603 printf("dc%d: reset never completed!\n", sc->dc_unit); 1604 1605 /* Wait a little while for the chip to get its brains in order. */ 1606 DELAY(1000); 1607 1608 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1609 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1610 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1611 1612 /* 1613 * Bring the SIA out of reset. In some cases, it looks 1614 * like failing to unreset the SIA soon enough gets it 1615 * into a state where it will never come out of reset 1616 * until we reset the whole chip again. 1617 */ 1618 if (DC_IS_INTEL(sc)) { 1619 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1620 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1621 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1622 } 1623 1624 return; 1625 } 1626 1627 static struct dc_type * 1628 dc_devtype(dev) 1629 device_t dev; 1630 { 1631 struct dc_type *t; 1632 u_int32_t rev; 1633 1634 t = dc_devs; 1635 1636 while(t->dc_name != NULL) { 1637 if ((pci_get_vendor(dev) == t->dc_vid) && 1638 (pci_get_device(dev) == t->dc_did)) { 1639 /* Check the PCI revision */ 1640 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1641 if (t->dc_did == DC_DEVICEID_98713 && 1642 rev >= DC_REVISION_98713A) 1643 t++; 1644 if (t->dc_did == DC_DEVICEID_98713_CP && 1645 rev >= DC_REVISION_98713A) 1646 t++; 1647 if (t->dc_did == DC_DEVICEID_987x5 && 1648 rev >= DC_REVISION_98715AEC_C) 1649 t++; 1650 if (t->dc_did == DC_DEVICEID_987x5 && 1651 rev >= DC_REVISION_98725) 1652 t++; 1653 if (t->dc_did == DC_DEVICEID_AX88140A && 1654 rev >= DC_REVISION_88141) 1655 t++; 1656 if (t->dc_did == DC_DEVICEID_82C168 && 1657 rev >= DC_REVISION_82C169) 1658 t++; 1659 if (t->dc_did == DC_DEVICEID_DM9102 && 1660 rev >= DC_REVISION_DM9102A) 1661 t++; 1662 return(t); 1663 } 1664 t++; 1665 } 1666 1667 return(NULL); 1668 } 1669 1670 /* 1671 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1672 * IDs against our list and return a device name if we find a match. 1673 * We do a little bit of extra work to identify the exact type of 1674 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1675 * but different revision IDs. The same is true for 98715/98715A 1676 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1677 * cases, the exact chip revision affects driver behavior. 1678 */ 1679 static int 1680 dc_probe(dev) 1681 device_t dev; 1682 { 1683 struct dc_type *t; 1684 1685 t = dc_devtype(dev); 1686 1687 if (t != NULL) { 1688 device_set_desc(dev, t->dc_name); 1689 return(0); 1690 } 1691 1692 return(ENXIO); 1693 } 1694 1695 static void 1696 dc_acpi(dev) 1697 device_t dev; 1698 { 1699 int unit; 1700 1701 unit = device_get_unit(dev); 1702 1703 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1704 u_int32_t iobase, membase, irq; 1705 1706 /* Save important PCI config data. */ 1707 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1708 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1709 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1710 1711 /* Reset the power state. */ 1712 printf("dc%d: chip is in D%d power mode " 1713 "-- setting to D0\n", unit, 1714 pci_get_powerstate(dev)); 1715 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1716 1717 /* Restore PCI config data. */ 1718 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1719 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1720 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1721 } 1722 1723 return; 1724 } 1725 1726 static void 1727 dc_apply_fixup(sc, media) 1728 struct dc_softc *sc; 1729 int media; 1730 { 1731 struct dc_mediainfo *m; 1732 u_int8_t *p; 1733 int i; 1734 u_int32_t reg; 1735 1736 m = sc->dc_mi; 1737 1738 while (m != NULL) { 1739 if (m->dc_media == media) 1740 break; 1741 m = m->dc_next; 1742 } 1743 1744 if (m == NULL) 1745 return; 1746 1747 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1748 reg = (p[0] | (p[1] << 8)) << 16; 1749 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1750 } 1751 1752 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1753 reg = (p[0] | (p[1] << 8)) << 16; 1754 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1755 } 1756 1757 return; 1758 } 1759 1760 static void 1761 dc_decode_leaf_sia(sc, l) 1762 struct dc_softc *sc; 1763 struct dc_eblock_sia *l; 1764 { 1765 struct dc_mediainfo *m; 1766 1767 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1768 bzero(m, sizeof(struct dc_mediainfo)); 1769 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1770 m->dc_media = IFM_10_T; 1771 1772 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1773 m->dc_media = IFM_10_T|IFM_FDX; 1774 1775 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1776 m->dc_media = IFM_10_2; 1777 1778 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1779 m->dc_media = IFM_10_5; 1780 1781 m->dc_gp_len = 2; 1782 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1783 1784 m->dc_next = sc->dc_mi; 1785 sc->dc_mi = m; 1786 1787 sc->dc_pmode = DC_PMODE_SIA; 1788 1789 return; 1790 } 1791 1792 static void 1793 dc_decode_leaf_sym(sc, l) 1794 struct dc_softc *sc; 1795 struct dc_eblock_sym *l; 1796 { 1797 struct dc_mediainfo *m; 1798 1799 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1800 bzero(m, sizeof(struct dc_mediainfo)); 1801 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1802 m->dc_media = IFM_100_TX; 1803 1804 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1805 m->dc_media = IFM_100_TX|IFM_FDX; 1806 1807 m->dc_gp_len = 2; 1808 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1809 1810 m->dc_next = sc->dc_mi; 1811 sc->dc_mi = m; 1812 1813 sc->dc_pmode = DC_PMODE_SYM; 1814 1815 return; 1816 } 1817 1818 static void 1819 dc_decode_leaf_mii(sc, l) 1820 struct dc_softc *sc; 1821 struct dc_eblock_mii *l; 1822 { 1823 u_int8_t *p; 1824 struct dc_mediainfo *m; 1825 1826 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1827 bzero(m, sizeof(struct dc_mediainfo)); 1828 /* We abuse IFM_AUTO to represent MII. */ 1829 m->dc_media = IFM_AUTO; 1830 m->dc_gp_len = l->dc_gpr_len; 1831 1832 p = (u_int8_t *)l; 1833 p += sizeof(struct dc_eblock_mii); 1834 m->dc_gp_ptr = p; 1835 p += 2 * l->dc_gpr_len; 1836 m->dc_reset_len = *p; 1837 p++; 1838 m->dc_reset_ptr = p; 1839 1840 m->dc_next = sc->dc_mi; 1841 sc->dc_mi = m; 1842 1843 return; 1844 } 1845 1846 static void 1847 dc_read_srom(sc, bits) 1848 struct dc_softc *sc; 1849 int bits; 1850 { 1851 int size; 1852 1853 size = 2 << bits; 1854 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1855 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1856 } 1857 1858 static void 1859 dc_parse_21143_srom(sc) 1860 struct dc_softc *sc; 1861 { 1862 struct dc_leaf_hdr *lhdr; 1863 struct dc_eblock_hdr *hdr; 1864 int i, loff; 1865 char *ptr; 1866 int have_mii; 1867 1868 have_mii = 0; 1869 loff = sc->dc_srom[27]; 1870 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1871 1872 ptr = (char *)lhdr; 1873 ptr += sizeof(struct dc_leaf_hdr) - 1; 1874 /* 1875 * Look if we got a MII media block. 1876 */ 1877 for (i = 0; i < lhdr->dc_mcnt; i++) { 1878 hdr = (struct dc_eblock_hdr *)ptr; 1879 if (hdr->dc_type == DC_EBLOCK_MII) 1880 have_mii++; 1881 1882 ptr += (hdr->dc_len & 0x7F); 1883 ptr++; 1884 } 1885 1886 /* 1887 * Do the same thing again. Only use SIA and SYM media 1888 * blocks if no MII media block is available. 1889 */ 1890 ptr = (char *)lhdr; 1891 ptr += sizeof(struct dc_leaf_hdr) - 1; 1892 for (i = 0; i < lhdr->dc_mcnt; i++) { 1893 hdr = (struct dc_eblock_hdr *)ptr; 1894 switch(hdr->dc_type) { 1895 case DC_EBLOCK_MII: 1896 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1897 break; 1898 case DC_EBLOCK_SIA: 1899 if (! have_mii) 1900 dc_decode_leaf_sia(sc, 1901 (struct dc_eblock_sia *)hdr); 1902 break; 1903 case DC_EBLOCK_SYM: 1904 if (! have_mii) 1905 dc_decode_leaf_sym(sc, 1906 (struct dc_eblock_sym *)hdr); 1907 break; 1908 default: 1909 /* Don't care. Yet. */ 1910 break; 1911 } 1912 ptr += (hdr->dc_len & 0x7F); 1913 ptr++; 1914 } 1915 1916 return; 1917 } 1918 1919 /* 1920 * Attach the interface. Allocate softc structures, do ifmedia 1921 * setup and ethernet/BPF attach. 1922 */ 1923 static int 1924 dc_attach(dev) 1925 device_t dev; 1926 { 1927 int tmp = 0; 1928 u_char eaddr[ETHER_ADDR_LEN]; 1929 u_int32_t command; 1930 struct dc_softc *sc; 1931 struct ifnet *ifp; 1932 u_int32_t revision; 1933 int unit, error = 0, rid, mac_offset; 1934 u_int8_t *mac; 1935 1936 sc = device_get_softc(dev); 1937 unit = device_get_unit(dev); 1938 1939 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1940 MTX_DEF | MTX_RECURSE); 1941 1942 /* 1943 * Handle power management nonsense. 1944 */ 1945 dc_acpi(dev); 1946 1947 /* 1948 * Map control/status registers. 1949 */ 1950 pci_enable_busmaster(dev); 1951 1952 rid = DC_RID; 1953 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1954 0, ~0, 1, RF_ACTIVE); 1955 1956 if (sc->dc_res == NULL) { 1957 printf("dc%d: couldn't map ports/memory\n", unit); 1958 error = ENXIO; 1959 goto fail; 1960 } 1961 1962 sc->dc_btag = rman_get_bustag(sc->dc_res); 1963 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1964 1965 /* Allocate interrupt */ 1966 rid = 0; 1967 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1968 RF_SHAREABLE | RF_ACTIVE); 1969 1970 if (sc->dc_irq == NULL) { 1971 printf("dc%d: couldn't map interrupt\n", unit); 1972 error = ENXIO; 1973 goto fail; 1974 } 1975 1976 /* Need this info to decide on a chip type. */ 1977 sc->dc_info = dc_devtype(dev); 1978 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1979 1980 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1981 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1982 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1983 dc_eeprom_width(sc); 1984 1985 switch(sc->dc_info->dc_did) { 1986 case DC_DEVICEID_21143: 1987 sc->dc_type = DC_TYPE_21143; 1988 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1989 sc->dc_flags |= DC_REDUCED_MII_POLL; 1990 /* Save EEPROM contents so we can parse them later. */ 1991 dc_read_srom(sc, sc->dc_romwidth); 1992 break; 1993 case DC_DEVICEID_DM9009: 1994 case DC_DEVICEID_DM9100: 1995 case DC_DEVICEID_DM9102: 1996 sc->dc_type = DC_TYPE_DM9102; 1997 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1998 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1999 sc->dc_pmode = DC_PMODE_MII; 2000 /* Increase the latency timer value. */ 2001 command = pci_read_config(dev, DC_PCI_CFLT, 4); 2002 command &= 0xFFFF00FF; 2003 command |= 0x00008000; 2004 pci_write_config(dev, DC_PCI_CFLT, command, 4); 2005 break; 2006 case DC_DEVICEID_AL981: 2007 sc->dc_type = DC_TYPE_AL981; 2008 sc->dc_flags |= DC_TX_USE_TX_INTR; 2009 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2010 sc->dc_pmode = DC_PMODE_MII; 2011 dc_read_srom(sc, sc->dc_romwidth); 2012 break; 2013 case DC_DEVICEID_AN985: 2014 case DC_DEVICEID_FE2500: 2015 case DC_DEVICEID_EN2242: 2016 case DC_DEVICEID_HAWKING_PN672TX: 2017 case DC_DEVICEID_3CSOHOB: 2018 sc->dc_type = DC_TYPE_AN985; 2019 sc->dc_flags |= DC_64BIT_HASH; 2020 sc->dc_flags |= DC_TX_USE_TX_INTR; 2021 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2022 sc->dc_pmode = DC_PMODE_MII; 2023 dc_read_srom(sc, sc->dc_romwidth); 2024 break; 2025 case DC_DEVICEID_98713: 2026 case DC_DEVICEID_98713_CP: 2027 if (revision < DC_REVISION_98713A) { 2028 sc->dc_type = DC_TYPE_98713; 2029 } 2030 if (revision >= DC_REVISION_98713A) { 2031 sc->dc_type = DC_TYPE_98713A; 2032 sc->dc_flags |= DC_21143_NWAY; 2033 } 2034 sc->dc_flags |= DC_REDUCED_MII_POLL; 2035 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2036 break; 2037 case DC_DEVICEID_987x5: 2038 case DC_DEVICEID_EN1217: 2039 /* 2040 * Macronix MX98715AEC-C/D/E parts have only a 2041 * 128-bit hash table. We need to deal with these 2042 * in the same manner as the PNIC II so that we 2043 * get the right number of bits out of the 2044 * CRC routine. 2045 */ 2046 if (revision >= DC_REVISION_98715AEC_C && 2047 revision < DC_REVISION_98725) 2048 sc->dc_flags |= DC_128BIT_HASH; 2049 sc->dc_type = DC_TYPE_987x5; 2050 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2051 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2052 break; 2053 case DC_DEVICEID_98727: 2054 sc->dc_type = DC_TYPE_987x5; 2055 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2056 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2057 break; 2058 case DC_DEVICEID_82C115: 2059 sc->dc_type = DC_TYPE_PNICII; 2060 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 2061 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2062 break; 2063 case DC_DEVICEID_82C168: 2064 sc->dc_type = DC_TYPE_PNIC; 2065 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 2066 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2067 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2068 if (revision < DC_REVISION_82C169) 2069 sc->dc_pmode = DC_PMODE_SYM; 2070 break; 2071 case DC_DEVICEID_AX88140A: 2072 sc->dc_type = DC_TYPE_ASIX; 2073 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 2074 sc->dc_flags |= DC_REDUCED_MII_POLL; 2075 sc->dc_pmode = DC_PMODE_MII; 2076 break; 2077 case DC_DEVICEID_X3201: 2078 sc->dc_type = DC_TYPE_XIRCOM; 2079 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2080 DC_TX_ALIGN; 2081 /* 2082 * We don't actually need to coalesce, but we're doing 2083 * it to obtain a double word aligned buffer. 2084 * The DC_TX_COALESCE flag is required. 2085 */ 2086 sc->dc_pmode = DC_PMODE_MII; 2087 break; 2088 case DC_DEVICEID_RS7112: 2089 sc->dc_type = DC_TYPE_CONEXANT; 2090 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2091 sc->dc_flags |= DC_REDUCED_MII_POLL; 2092 sc->dc_pmode = DC_PMODE_MII; 2093 dc_read_srom(sc, sc->dc_romwidth); 2094 break; 2095 default: 2096 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2097 sc->dc_info->dc_did); 2098 break; 2099 } 2100 2101 /* Save the cache line size. */ 2102 if (DC_IS_DAVICOM(sc)) 2103 sc->dc_cachesize = 0; 2104 else 2105 sc->dc_cachesize = pci_read_config(dev, 2106 DC_PCI_CFLT, 4) & 0xFF; 2107 2108 /* Reset the adapter. */ 2109 dc_reset(sc); 2110 2111 /* Take 21143 out of snooze mode */ 2112 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2113 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2114 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2115 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2116 } 2117 2118 /* 2119 * Try to learn something about the supported media. 2120 * We know that ASIX and ADMtek and Davicom devices 2121 * will *always* be using MII media, so that's a no-brainer. 2122 * The tricky ones are the Macronix/PNIC II and the 2123 * Intel 21143. 2124 */ 2125 if (DC_IS_INTEL(sc)) 2126 dc_parse_21143_srom(sc); 2127 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2128 if (sc->dc_type == DC_TYPE_98713) 2129 sc->dc_pmode = DC_PMODE_MII; 2130 else 2131 sc->dc_pmode = DC_PMODE_SYM; 2132 } else if (!sc->dc_pmode) 2133 sc->dc_pmode = DC_PMODE_MII; 2134 2135 /* 2136 * Get station address from the EEPROM. 2137 */ 2138 switch(sc->dc_type) { 2139 case DC_TYPE_98713: 2140 case DC_TYPE_98713A: 2141 case DC_TYPE_987x5: 2142 case DC_TYPE_PNICII: 2143 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2144 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2145 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2146 break; 2147 case DC_TYPE_PNIC: 2148 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2149 break; 2150 case DC_TYPE_DM9102: 2151 case DC_TYPE_21143: 2152 case DC_TYPE_ASIX: 2153 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2154 break; 2155 case DC_TYPE_AL981: 2156 case DC_TYPE_AN985: 2157 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr, 2158 ETHER_ADDR_LEN); 2159 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2160 break; 2161 case DC_TYPE_CONEXANT: 2162 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2163 break; 2164 case DC_TYPE_XIRCOM: 2165 /* The MAC comes from the CIS */ 2166 mac = pci_get_ether(dev); 2167 if (!mac) { 2168 device_printf(dev, "No station address in CIS!\n"); 2169 error = ENXIO; 2170 goto fail; 2171 } 2172 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2173 break; 2174 default: 2175 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2176 break; 2177 } 2178 2179 /* 2180 * A 21143 or clone chip was detected. Inform the world. 2181 */ 2182 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2183 2184 sc->dc_unit = unit; 2185 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2186 2187 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2188 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2189 2190 if (sc->dc_ldata == NULL) { 2191 printf("dc%d: no memory for list buffers!\n", unit); 2192 error = ENXIO; 2193 goto fail; 2194 } 2195 2196 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2197 2198 ifp = &sc->arpcom.ac_if; 2199 ifp->if_softc = sc; 2200 ifp->if_unit = unit; 2201 ifp->if_name = "dc"; 2202 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2203 ifp->if_mtu = ETHERMTU; 2204 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2205 ifp->if_ioctl = dc_ioctl; 2206 ifp->if_output = ether_output; 2207 ifp->if_start = dc_start; 2208 ifp->if_watchdog = dc_watchdog; 2209 ifp->if_init = dc_init; 2210 ifp->if_baudrate = 10000000; 2211 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2212 2213 /* 2214 * Do MII setup. If this is a 21143, check for a PHY on the 2215 * MII bus after applying any necessary fixups to twiddle the 2216 * GPIO bits. If we don't end up finding a PHY, restore the 2217 * old selection (SIA only or SIA/SYM) and attach the dcphy 2218 * driver instead. 2219 */ 2220 if (DC_IS_INTEL(sc)) { 2221 dc_apply_fixup(sc, IFM_AUTO); 2222 tmp = sc->dc_pmode; 2223 sc->dc_pmode = DC_PMODE_MII; 2224 } 2225 2226 error = mii_phy_probe(dev, &sc->dc_miibus, 2227 dc_ifmedia_upd, dc_ifmedia_sts); 2228 2229 if (error && DC_IS_INTEL(sc)) { 2230 sc->dc_pmode = tmp; 2231 if (sc->dc_pmode != DC_PMODE_SIA) 2232 sc->dc_pmode = DC_PMODE_SYM; 2233 sc->dc_flags |= DC_21143_NWAY; 2234 mii_phy_probe(dev, &sc->dc_miibus, 2235 dc_ifmedia_upd, dc_ifmedia_sts); 2236 /* 2237 * For non-MII cards, we need to have the 21143 2238 * drive the LEDs. Except there are some systems 2239 * like the NEC VersaPro NoteBook PC which have no 2240 * LEDs, and twiddling these bits has adverse effects 2241 * on them. (I.e. you suddenly can't get a link.) 2242 */ 2243 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2244 sc->dc_flags |= DC_TULIP_LEDS; 2245 error = 0; 2246 } 2247 2248 if (error) { 2249 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2250 goto fail; 2251 } 2252 2253 if (DC_IS_XIRCOM(sc)) { 2254 /* 2255 * setup General Purpose Port mode and data so the tulip 2256 * can talk to the MII. 2257 */ 2258 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2259 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2260 DELAY(10); 2261 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2262 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2263 DELAY(10); 2264 } 2265 2266 if (DC_IS_ADMTEK(sc)) { 2267 /* 2268 * Set automatic TX underrun recovery for the ADMtek chips 2269 */ 2270 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2271 } 2272 2273 /* 2274 * Tell the upper layer(s) we support long frames. 2275 */ 2276 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2277 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2278 2279 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2280 2281 #ifdef SRM_MEDIA 2282 sc->dc_srm_media = 0; 2283 2284 /* Remember the SRM console media setting */ 2285 if (DC_IS_INTEL(sc)) { 2286 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2287 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2288 switch ((command >> 8) & 0xff) { 2289 case 3: 2290 sc->dc_srm_media = IFM_10_T; 2291 break; 2292 case 4: 2293 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2294 break; 2295 case 5: 2296 sc->dc_srm_media = IFM_100_TX; 2297 break; 2298 case 6: 2299 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2300 break; 2301 } 2302 if (sc->dc_srm_media) 2303 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2304 } 2305 #endif 2306 2307 /* 2308 * Call MI attach routine. 2309 */ 2310 ether_ifattach(ifp, eaddr); 2311 2312 /* Hook interrupt last to avoid having to lock softc */ 2313 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2314 (IS_MPSAFE ? INTR_MPSAFE : 0), 2315 dc_intr, sc, &sc->dc_intrhand); 2316 2317 if (error) { 2318 printf("dc%d: couldn't set up irq\n", unit); 2319 ether_ifdetach(ifp); 2320 goto fail; 2321 } 2322 2323 fail: 2324 if (error) 2325 dc_detach(dev); 2326 return (error); 2327 } 2328 2329 /* 2330 * Shutdown hardware and free up resources. This can be called any 2331 * time after the mutex has been initialized. It is called in both 2332 * the error case in attach and the normal detach case so it needs 2333 * to be careful about only freeing resources that have actually been 2334 * allocated. 2335 */ 2336 static int 2337 dc_detach(dev) 2338 device_t dev; 2339 { 2340 struct dc_softc *sc; 2341 struct ifnet *ifp; 2342 struct dc_mediainfo *m; 2343 2344 sc = device_get_softc(dev); 2345 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2346 DC_LOCK(sc); 2347 2348 ifp = &sc->arpcom.ac_if; 2349 2350 /* These should only be active if attach succeeded */ 2351 if (device_is_attached(dev)) { 2352 dc_stop(sc); 2353 ether_ifdetach(ifp); 2354 } 2355 if (sc->dc_miibus) 2356 device_delete_child(dev, sc->dc_miibus); 2357 bus_generic_detach(dev); 2358 2359 if (sc->dc_intrhand) 2360 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2361 if (sc->dc_irq) 2362 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2363 if (sc->dc_res) 2364 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2365 2366 if (sc->dc_ldata) 2367 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2368 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2369 2370 while(sc->dc_mi != NULL) { 2371 m = sc->dc_mi->dc_next; 2372 free(sc->dc_mi, M_DEVBUF); 2373 sc->dc_mi = m; 2374 } 2375 free(sc->dc_srom, M_DEVBUF); 2376 2377 DC_UNLOCK(sc); 2378 mtx_destroy(&sc->dc_mtx); 2379 2380 return(0); 2381 } 2382 2383 /* 2384 * Initialize the transmit descriptors. 2385 */ 2386 static int 2387 dc_list_tx_init(sc) 2388 struct dc_softc *sc; 2389 { 2390 struct dc_chain_data *cd; 2391 struct dc_list_data *ld; 2392 int i, nexti; 2393 2394 cd = &sc->dc_cdata; 2395 ld = sc->dc_ldata; 2396 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2397 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2398 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2399 cd->dc_tx_chain[i] = NULL; 2400 ld->dc_tx_list[i].dc_data = 0; 2401 ld->dc_tx_list[i].dc_ctl = 0; 2402 } 2403 2404 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2405 2406 return(0); 2407 } 2408 2409 2410 /* 2411 * Initialize the RX descriptors and allocate mbufs for them. Note that 2412 * we arrange the descriptors in a closed ring, so that the last descriptor 2413 * points back to the first. 2414 */ 2415 static int 2416 dc_list_rx_init(sc) 2417 struct dc_softc *sc; 2418 { 2419 struct dc_chain_data *cd; 2420 struct dc_list_data *ld; 2421 int i, nexti; 2422 2423 cd = &sc->dc_cdata; 2424 ld = sc->dc_ldata; 2425 2426 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2427 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2428 return(ENOBUFS); 2429 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2430 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2431 } 2432 2433 cd->dc_rx_prod = 0; 2434 2435 return(0); 2436 } 2437 2438 /* 2439 * Initialize an RX descriptor and attach an MBUF cluster. 2440 */ 2441 static int 2442 dc_newbuf(sc, i, m) 2443 struct dc_softc *sc; 2444 int i; 2445 struct mbuf *m; 2446 { 2447 struct mbuf *m_new = NULL; 2448 struct dc_desc *c; 2449 2450 c = &sc->dc_ldata->dc_rx_list[i]; 2451 2452 if (m == NULL) { 2453 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2454 if (m_new == NULL) 2455 return(ENOBUFS); 2456 2457 MCLGET(m_new, M_DONTWAIT); 2458 if (!(m_new->m_flags & M_EXT)) { 2459 m_freem(m_new); 2460 return(ENOBUFS); 2461 } 2462 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2463 } else { 2464 m_new = m; 2465 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2466 m_new->m_data = m_new->m_ext.ext_buf; 2467 } 2468 2469 m_adj(m_new, sizeof(u_int64_t)); 2470 2471 /* 2472 * If this is a PNIC chip, zero the buffer. This is part 2473 * of the workaround for the receive bug in the 82c168 and 2474 * 82c169 chips. 2475 */ 2476 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2477 bzero((char *)mtod(m_new, char *), m_new->m_len); 2478 2479 sc->dc_cdata.dc_rx_chain[i] = m_new; 2480 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2481 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2482 c->dc_status = DC_RXSTAT_OWN; 2483 2484 return(0); 2485 } 2486 2487 /* 2488 * Grrrrr. 2489 * The PNIC chip has a terrible bug in it that manifests itself during 2490 * periods of heavy activity. The exact mode of failure if difficult to 2491 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2492 * will happen on slow machines. The bug is that sometimes instead of 2493 * uploading one complete frame during reception, it uploads what looks 2494 * like the entire contents of its FIFO memory. The frame we want is at 2495 * the end of the whole mess, but we never know exactly how much data has 2496 * been uploaded, so salvaging the frame is hard. 2497 * 2498 * There is only one way to do it reliably, and it's disgusting. 2499 * Here's what we know: 2500 * 2501 * - We know there will always be somewhere between one and three extra 2502 * descriptors uploaded. 2503 * 2504 * - We know the desired received frame will always be at the end of the 2505 * total data upload. 2506 * 2507 * - We know the size of the desired received frame because it will be 2508 * provided in the length field of the status word in the last descriptor. 2509 * 2510 * Here's what we do: 2511 * 2512 * - When we allocate buffers for the receive ring, we bzero() them. 2513 * This means that we know that the buffer contents should be all 2514 * zeros, except for data uploaded by the chip. 2515 * 2516 * - We also force the PNIC chip to upload frames that include the 2517 * ethernet CRC at the end. 2518 * 2519 * - We gather all of the bogus frame data into a single buffer. 2520 * 2521 * - We then position a pointer at the end of this buffer and scan 2522 * backwards until we encounter the first non-zero byte of data. 2523 * This is the end of the received frame. We know we will encounter 2524 * some data at the end of the frame because the CRC will always be 2525 * there, so even if the sender transmits a packet of all zeros, 2526 * we won't be fooled. 2527 * 2528 * - We know the size of the actual received frame, so we subtract 2529 * that value from the current pointer location. This brings us 2530 * to the start of the actual received packet. 2531 * 2532 * - We copy this into an mbuf and pass it on, along with the actual 2533 * frame length. 2534 * 2535 * The performance hit is tremendous, but it beats dropping frames all 2536 * the time. 2537 */ 2538 2539 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2540 static void 2541 dc_pnic_rx_bug_war(sc, idx) 2542 struct dc_softc *sc; 2543 int idx; 2544 { 2545 struct dc_desc *cur_rx; 2546 struct dc_desc *c = NULL; 2547 struct mbuf *m = NULL; 2548 unsigned char *ptr; 2549 int i, total_len; 2550 u_int32_t rxstat = 0; 2551 2552 i = sc->dc_pnic_rx_bug_save; 2553 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2554 ptr = sc->dc_pnic_rx_buf; 2555 bzero(ptr, sizeof(DC_RXLEN * 5)); 2556 2557 /* Copy all the bytes from the bogus buffers. */ 2558 while (1) { 2559 c = &sc->dc_ldata->dc_rx_list[i]; 2560 rxstat = c->dc_status; 2561 m = sc->dc_cdata.dc_rx_chain[i]; 2562 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2563 ptr += DC_RXLEN; 2564 /* If this is the last buffer, break out. */ 2565 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2566 break; 2567 dc_newbuf(sc, i, m); 2568 DC_INC(i, DC_RX_LIST_CNT); 2569 } 2570 2571 /* Find the length of the actual receive frame. */ 2572 total_len = DC_RXBYTES(rxstat); 2573 2574 /* Scan backwards until we hit a non-zero byte. */ 2575 while(*ptr == 0x00) 2576 ptr--; 2577 2578 /* Round off. */ 2579 if ((uintptr_t)(ptr) & 0x3) 2580 ptr -= 1; 2581 2582 /* Now find the start of the frame. */ 2583 ptr -= total_len; 2584 if (ptr < sc->dc_pnic_rx_buf) 2585 ptr = sc->dc_pnic_rx_buf; 2586 2587 /* 2588 * Now copy the salvaged frame to the last mbuf and fake up 2589 * the status word to make it look like a successful 2590 * frame reception. 2591 */ 2592 dc_newbuf(sc, i, m); 2593 bcopy(ptr, mtod(m, char *), total_len); 2594 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2595 2596 return; 2597 } 2598 2599 /* 2600 * This routine searches the RX ring for dirty descriptors in the 2601 * event that the rxeof routine falls out of sync with the chip's 2602 * current descriptor pointer. This may happen sometimes as a result 2603 * of a "no RX buffer available" condition that happens when the chip 2604 * consumes all of the RX buffers before the driver has a chance to 2605 * process the RX ring. This routine may need to be called more than 2606 * once to bring the driver back in sync with the chip, however we 2607 * should still be getting RX DONE interrupts to drive the search 2608 * for new packets in the RX ring, so we should catch up eventually. 2609 */ 2610 static int 2611 dc_rx_resync(sc) 2612 struct dc_softc *sc; 2613 { 2614 int i, pos; 2615 struct dc_desc *cur_rx; 2616 2617 pos = sc->dc_cdata.dc_rx_prod; 2618 2619 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2620 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2621 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2622 break; 2623 DC_INC(pos, DC_RX_LIST_CNT); 2624 } 2625 2626 /* If the ring really is empty, then just return. */ 2627 if (i == DC_RX_LIST_CNT) 2628 return(0); 2629 2630 /* We've fallen behing the chip: catch it. */ 2631 sc->dc_cdata.dc_rx_prod = pos; 2632 2633 return(EAGAIN); 2634 } 2635 2636 /* 2637 * A frame has been uploaded: pass the resulting mbuf chain up to 2638 * the higher level protocols. 2639 */ 2640 static void 2641 dc_rxeof(sc) 2642 struct dc_softc *sc; 2643 { 2644 struct mbuf *m; 2645 struct ifnet *ifp; 2646 struct dc_desc *cur_rx; 2647 int i, total_len = 0; 2648 u_int32_t rxstat; 2649 2650 ifp = &sc->arpcom.ac_if; 2651 i = sc->dc_cdata.dc_rx_prod; 2652 2653 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2654 2655 #ifdef DEVICE_POLLING 2656 if (ifp->if_flags & IFF_POLLING) { 2657 if (sc->rxcycles <= 0) 2658 break; 2659 sc->rxcycles--; 2660 } 2661 #endif /* DEVICE_POLLING */ 2662 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2663 rxstat = cur_rx->dc_status; 2664 m = sc->dc_cdata.dc_rx_chain[i]; 2665 total_len = DC_RXBYTES(rxstat); 2666 2667 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2668 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2669 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2670 sc->dc_pnic_rx_bug_save = i; 2671 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2672 DC_INC(i, DC_RX_LIST_CNT); 2673 continue; 2674 } 2675 dc_pnic_rx_bug_war(sc, i); 2676 rxstat = cur_rx->dc_status; 2677 total_len = DC_RXBYTES(rxstat); 2678 } 2679 } 2680 2681 sc->dc_cdata.dc_rx_chain[i] = NULL; 2682 2683 /* 2684 * If an error occurs, update stats, clear the 2685 * status word and leave the mbuf cluster in place: 2686 * it should simply get re-used next time this descriptor 2687 * comes up in the ring. However, don't report long 2688 * frames as errors since they could be vlans 2689 */ 2690 if ((rxstat & DC_RXSTAT_RXERR)){ 2691 if (!(rxstat & DC_RXSTAT_GIANT) || 2692 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2693 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2694 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2695 ifp->if_ierrors++; 2696 if (rxstat & DC_RXSTAT_COLLSEEN) 2697 ifp->if_collisions++; 2698 dc_newbuf(sc, i, m); 2699 if (rxstat & DC_RXSTAT_CRCERR) { 2700 DC_INC(i, DC_RX_LIST_CNT); 2701 continue; 2702 } else { 2703 dc_init(sc); 2704 return; 2705 } 2706 } 2707 } 2708 2709 /* No errors; receive the packet. */ 2710 total_len -= ETHER_CRC_LEN; 2711 #ifdef __i386__ 2712 /* 2713 * On the x86 we do not have alignment problems, so try to 2714 * allocate a new buffer for the receive ring, and pass up 2715 * the one where the packet is already, saving the expensive 2716 * copy done in m_devget(). 2717 * If we are on an architecture with alignment problems, or 2718 * if the allocation fails, then use m_devget and leave the 2719 * existing buffer in the receive ring. 2720 */ 2721 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2722 m->m_pkthdr.rcvif = ifp; 2723 m->m_pkthdr.len = m->m_len = total_len; 2724 DC_INC(i, DC_RX_LIST_CNT); 2725 } else 2726 #endif 2727 { 2728 struct mbuf *m0; 2729 2730 m0 = m_devget(mtod(m, char *), total_len, 2731 ETHER_ALIGN, ifp, NULL); 2732 dc_newbuf(sc, i, m); 2733 DC_INC(i, DC_RX_LIST_CNT); 2734 if (m0 == NULL) { 2735 ifp->if_ierrors++; 2736 continue; 2737 } 2738 m = m0; 2739 } 2740 2741 ifp->if_ipackets++; 2742 (*ifp->if_input)(ifp, m); 2743 } 2744 2745 sc->dc_cdata.dc_rx_prod = i; 2746 } 2747 2748 /* 2749 * A frame was downloaded to the chip. It's safe for us to clean up 2750 * the list buffers. 2751 */ 2752 2753 static void 2754 dc_txeof(sc) 2755 struct dc_softc *sc; 2756 { 2757 struct dc_desc *cur_tx = NULL; 2758 struct ifnet *ifp; 2759 int idx; 2760 2761 ifp = &sc->arpcom.ac_if; 2762 2763 /* 2764 * Go through our tx list and free mbufs for those 2765 * frames that have been transmitted. 2766 */ 2767 idx = sc->dc_cdata.dc_tx_cons; 2768 while(idx != sc->dc_cdata.dc_tx_prod) { 2769 u_int32_t txstat; 2770 2771 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2772 txstat = cur_tx->dc_status; 2773 2774 if (txstat & DC_TXSTAT_OWN) 2775 break; 2776 2777 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2778 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2779 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2780 /* 2781 * Yes, the PNIC is so brain damaged 2782 * that it will sometimes generate a TX 2783 * underrun error while DMAing the RX 2784 * filter setup frame. If we detect this, 2785 * we have to send the setup frame again, 2786 * or else the filter won't be programmed 2787 * correctly. 2788 */ 2789 if (DC_IS_PNIC(sc)) { 2790 if (txstat & DC_TXSTAT_ERRSUM) 2791 dc_setfilt(sc); 2792 } 2793 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2794 } 2795 sc->dc_cdata.dc_tx_cnt--; 2796 DC_INC(idx, DC_TX_LIST_CNT); 2797 continue; 2798 } 2799 2800 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2801 /* 2802 * XXX: Why does my Xircom taunt me so? 2803 * For some reason it likes setting the CARRLOST flag 2804 * even when the carrier is there. wtf?!? 2805 * Who knows, but Conexant chips have the 2806 * same problem. Maybe they took lessons 2807 * from Xircom. 2808 */ 2809 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2810 sc->dc_pmode == DC_PMODE_MII && 2811 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2812 DC_TXSTAT_NOCARRIER))) 2813 txstat &= ~DC_TXSTAT_ERRSUM; 2814 } else { 2815 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2816 sc->dc_pmode == DC_PMODE_MII && 2817 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2818 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2819 txstat &= ~DC_TXSTAT_ERRSUM; 2820 } 2821 2822 if (txstat & DC_TXSTAT_ERRSUM) { 2823 ifp->if_oerrors++; 2824 if (txstat & DC_TXSTAT_EXCESSCOLL) 2825 ifp->if_collisions++; 2826 if (txstat & DC_TXSTAT_LATECOLL) 2827 ifp->if_collisions++; 2828 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2829 dc_init(sc); 2830 return; 2831 } 2832 } 2833 2834 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2835 2836 ifp->if_opackets++; 2837 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2838 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2839 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2840 } 2841 2842 sc->dc_cdata.dc_tx_cnt--; 2843 DC_INC(idx, DC_TX_LIST_CNT); 2844 } 2845 2846 if (idx != sc->dc_cdata.dc_tx_cons) { 2847 /* some buffers have been freed */ 2848 sc->dc_cdata.dc_tx_cons = idx; 2849 ifp->if_flags &= ~IFF_OACTIVE; 2850 } 2851 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2852 2853 return; 2854 } 2855 2856 static void 2857 dc_tick(xsc) 2858 void *xsc; 2859 { 2860 struct dc_softc *sc; 2861 struct mii_data *mii; 2862 struct ifnet *ifp; 2863 u_int32_t r; 2864 2865 sc = xsc; 2866 DC_LOCK(sc); 2867 ifp = &sc->arpcom.ac_if; 2868 mii = device_get_softc(sc->dc_miibus); 2869 2870 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2871 if (sc->dc_flags & DC_21143_NWAY) { 2872 r = CSR_READ_4(sc, DC_10BTSTAT); 2873 if (IFM_SUBTYPE(mii->mii_media_active) == 2874 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2875 sc->dc_link = 0; 2876 mii_mediachg(mii); 2877 } 2878 if (IFM_SUBTYPE(mii->mii_media_active) == 2879 IFM_10_T && (r & DC_TSTAT_LS10)) { 2880 sc->dc_link = 0; 2881 mii_mediachg(mii); 2882 } 2883 if (sc->dc_link == 0) 2884 mii_tick(mii); 2885 } else { 2886 r = CSR_READ_4(sc, DC_ISR); 2887 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2888 sc->dc_cdata.dc_tx_cnt == 0) { 2889 mii_tick(mii); 2890 if (!(mii->mii_media_status & IFM_ACTIVE)) 2891 sc->dc_link = 0; 2892 } 2893 } 2894 } else 2895 mii_tick(mii); 2896 2897 /* 2898 * When the init routine completes, we expect to be able to send 2899 * packets right away, and in fact the network code will send a 2900 * gratuitous ARP the moment the init routine marks the interface 2901 * as running. However, even though the MAC may have been initialized, 2902 * there may be a delay of a few seconds before the PHY completes 2903 * autonegotiation and the link is brought up. Any transmissions 2904 * made during that delay will be lost. Dealing with this is tricky: 2905 * we can't just pause in the init routine while waiting for the 2906 * PHY to come ready since that would bring the whole system to 2907 * a screeching halt for several seconds. 2908 * 2909 * What we do here is prevent the TX start routine from sending 2910 * any packets until a link has been established. After the 2911 * interface has been initialized, the tick routine will poll 2912 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2913 * that time, packets will stay in the send queue, and once the 2914 * link comes up, they will be flushed out to the wire. 2915 */ 2916 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2917 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2918 sc->dc_link++; 2919 if (ifp->if_snd.ifq_head != NULL) 2920 dc_start(ifp); 2921 } 2922 2923 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2924 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2925 else 2926 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2927 2928 DC_UNLOCK(sc); 2929 2930 return; 2931 } 2932 2933 /* 2934 * A transmit underrun has occurred. Back off the transmit threshold, 2935 * or switch to store and forward mode if we have to. 2936 */ 2937 static void 2938 dc_tx_underrun(sc) 2939 struct dc_softc *sc; 2940 { 2941 u_int32_t isr; 2942 int i; 2943 2944 if (DC_IS_DAVICOM(sc)) 2945 dc_init(sc); 2946 2947 if (DC_IS_INTEL(sc)) { 2948 /* 2949 * The real 21143 requires that the transmitter be idle 2950 * in order to change the transmit threshold or store 2951 * and forward state. 2952 */ 2953 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2954 2955 for (i = 0; i < DC_TIMEOUT; i++) { 2956 isr = CSR_READ_4(sc, DC_ISR); 2957 if (isr & DC_ISR_TX_IDLE) 2958 break; 2959 DELAY(10); 2960 } 2961 if (i == DC_TIMEOUT) { 2962 printf("dc%d: failed to force tx to idle state\n", 2963 sc->dc_unit); 2964 dc_init(sc); 2965 } 2966 } 2967 2968 printf("dc%d: TX underrun -- ", sc->dc_unit); 2969 sc->dc_txthresh += DC_TXTHRESH_INC; 2970 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2971 printf("using store and forward mode\n"); 2972 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2973 } else { 2974 printf("increasing TX threshold\n"); 2975 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2976 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2977 } 2978 2979 if (DC_IS_INTEL(sc)) 2980 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2981 2982 return; 2983 } 2984 2985 #ifdef DEVICE_POLLING 2986 static poll_handler_t dc_poll; 2987 2988 static void 2989 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2990 { 2991 struct dc_softc *sc = ifp->if_softc; 2992 2993 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2994 /* Re-enable interrupts. */ 2995 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2996 return; 2997 } 2998 sc->rxcycles = count; 2999 dc_rxeof(sc); 3000 dc_txeof(sc); 3001 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 3002 dc_start(ifp); 3003 3004 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3005 u_int32_t status; 3006 3007 status = CSR_READ_4(sc, DC_ISR); 3008 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 3009 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 3010 DC_ISR_BUS_ERR); 3011 if (!status) 3012 return; 3013 /* ack what we have */ 3014 CSR_WRITE_4(sc, DC_ISR, status); 3015 3016 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF)) { 3017 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3018 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3019 3020 if (dc_rx_resync(sc)) 3021 dc_rxeof(sc); 3022 } 3023 /* restart transmit unit if necessary */ 3024 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3025 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3026 3027 if (status & DC_ISR_TX_UNDERRUN) 3028 dc_tx_underrun(sc); 3029 3030 if (status & DC_ISR_BUS_ERR) { 3031 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3032 dc_reset(sc); 3033 dc_init(sc); 3034 } 3035 } 3036 } 3037 #endif /* DEVICE_POLLING */ 3038 3039 static void 3040 dc_intr(arg) 3041 void *arg; 3042 { 3043 struct dc_softc *sc; 3044 struct ifnet *ifp; 3045 u_int32_t status; 3046 3047 sc = arg; 3048 3049 if (sc->suspended) { 3050 return; 3051 } 3052 3053 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3054 return; 3055 3056 DC_LOCK(sc); 3057 ifp = &sc->arpcom.ac_if; 3058 #ifdef DEVICE_POLLING 3059 if (ifp->if_flags & IFF_POLLING) 3060 goto done; 3061 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3062 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3063 goto done; 3064 } 3065 #endif /* DEVICE_POLLING */ 3066 3067 /* Suppress unwanted interrupts */ 3068 if (!(ifp->if_flags & IFF_UP)) { 3069 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3070 dc_stop(sc); 3071 DC_UNLOCK(sc); 3072 return; 3073 } 3074 3075 /* Disable interrupts. */ 3076 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3077 3078 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3079 && status != 0xFFFFFFFF) { 3080 3081 CSR_WRITE_4(sc, DC_ISR, status); 3082 3083 if (status & DC_ISR_RX_OK) { 3084 int curpkts; 3085 curpkts = ifp->if_ipackets; 3086 dc_rxeof(sc); 3087 if (curpkts == ifp->if_ipackets) { 3088 while(dc_rx_resync(sc)) 3089 dc_rxeof(sc); 3090 } 3091 } 3092 3093 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 3094 dc_txeof(sc); 3095 3096 if (status & DC_ISR_TX_IDLE) { 3097 dc_txeof(sc); 3098 if (sc->dc_cdata.dc_tx_cnt) { 3099 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3100 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3101 } 3102 } 3103 3104 if (status & DC_ISR_TX_UNDERRUN) 3105 dc_tx_underrun(sc); 3106 3107 if ((status & DC_ISR_RX_WATDOGTIMEO) 3108 || (status & DC_ISR_RX_NOBUF)) { 3109 int curpkts; 3110 curpkts = ifp->if_ipackets; 3111 dc_rxeof(sc); 3112 if (curpkts == ifp->if_ipackets) { 3113 while(dc_rx_resync(sc)) 3114 dc_rxeof(sc); 3115 } 3116 } 3117 3118 if (status & DC_ISR_BUS_ERR) { 3119 dc_reset(sc); 3120 dc_init(sc); 3121 } 3122 } 3123 3124 /* Re-enable interrupts. */ 3125 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3126 3127 if (ifp->if_snd.ifq_head != NULL) 3128 dc_start(ifp); 3129 3130 #ifdef DEVICE_POLLING 3131 done: 3132 #endif /* DEVICE_POLLING */ 3133 3134 DC_UNLOCK(sc); 3135 3136 return; 3137 } 3138 3139 /* 3140 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3141 * pointers to the fragment pointers. 3142 */ 3143 static int 3144 dc_encap(sc, m_head, txidx) 3145 struct dc_softc *sc; 3146 struct mbuf *m_head; 3147 u_int32_t *txidx; 3148 { 3149 struct dc_desc *f = NULL; 3150 struct mbuf *m; 3151 int frag, cur, cnt = 0, chainlen = 0; 3152 3153 /* 3154 * If there's no way we can send any packets, return now. 3155 */ 3156 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3157 return (ENOBUFS); 3158 3159 /* 3160 * Count the number of frags in this chain to see if 3161 * we need to m_defrag. Since the descriptor list is shared 3162 * by all packets, we'll m_defrag long chains so that they 3163 * do not use up the entire list, even if they would fit. 3164 */ 3165 3166 for (m = m_head; m != NULL; m = m->m_next) 3167 chainlen++; 3168 3169 if ((chainlen > DC_TX_LIST_CNT / 4) || 3170 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3171 m = m_defrag(m_head, M_DONTWAIT); 3172 if (m == NULL) 3173 return (ENOBUFS); 3174 m_head = m; 3175 } 3176 3177 /* 3178 * Start packing the mbufs in this chain into 3179 * the fragment pointers. Stop when we run out 3180 * of fragments or hit the end of the mbuf chain. 3181 */ 3182 m = m_head; 3183 cur = frag = *txidx; 3184 3185 for (m = m_head; m != NULL; m = m->m_next) { 3186 if (m->m_len != 0) { 3187 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 3188 if (*txidx != sc->dc_cdata.dc_tx_prod && 3189 frag == (DC_TX_LIST_CNT - 1)) 3190 return(ENOBUFS); 3191 } 3192 if ((DC_TX_LIST_CNT - 3193 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3194 return(ENOBUFS); 3195 3196 f = &sc->dc_ldata->dc_tx_list[frag]; 3197 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3198 if (cnt == 0) { 3199 f->dc_status = 0; 3200 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3201 } else 3202 f->dc_status = DC_TXSTAT_OWN; 3203 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3204 cur = frag; 3205 DC_INC(frag, DC_TX_LIST_CNT); 3206 cnt++; 3207 } 3208 } 3209 3210 if (m != NULL) 3211 return(ENOBUFS); 3212 3213 sc->dc_cdata.dc_tx_cnt += cnt; 3214 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3215 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3216 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3217 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3218 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3219 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3220 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3221 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3222 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3223 *txidx = frag; 3224 3225 return(0); 3226 } 3227 3228 /* 3229 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3230 * to the mbuf data regions directly in the transmit lists. We also save a 3231 * copy of the pointers since the transmit list fragment pointers are 3232 * physical addresses. 3233 */ 3234 3235 static void 3236 dc_start(ifp) 3237 struct ifnet *ifp; 3238 { 3239 struct dc_softc *sc; 3240 struct mbuf *m_head = NULL, *m; 3241 int idx; 3242 3243 sc = ifp->if_softc; 3244 3245 DC_LOCK(sc); 3246 3247 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3248 DC_UNLOCK(sc); 3249 return; 3250 } 3251 3252 if (ifp->if_flags & IFF_OACTIVE) { 3253 DC_UNLOCK(sc); 3254 return; 3255 } 3256 3257 idx = sc->dc_cdata.dc_tx_prod; 3258 3259 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3260 IF_DEQUEUE(&ifp->if_snd, m_head); 3261 if (m_head == NULL) 3262 break; 3263 3264 if (sc->dc_flags & DC_TX_COALESCE && 3265 (m_head->m_next != NULL || 3266 sc->dc_flags & DC_TX_ALIGN)) { 3267 m = m_defrag(m_head, M_DONTWAIT); 3268 if (m == NULL) { 3269 IF_PREPEND(&ifp->if_snd, m_head); 3270 ifp->if_flags |= IFF_OACTIVE; 3271 break; 3272 } else { 3273 m_head = m; 3274 } 3275 } 3276 3277 if (dc_encap(sc, m_head, &idx)) { 3278 IF_PREPEND(&ifp->if_snd, m_head); 3279 ifp->if_flags |= IFF_OACTIVE; 3280 break; 3281 } 3282 3283 /* 3284 * If there's a BPF listener, bounce a copy of this frame 3285 * to him. 3286 */ 3287 BPF_MTAP(ifp, m_head); 3288 3289 if (sc->dc_flags & DC_TX_ONE) { 3290 ifp->if_flags |= IFF_OACTIVE; 3291 break; 3292 } 3293 } 3294 3295 /* Transmit */ 3296 sc->dc_cdata.dc_tx_prod = idx; 3297 if (!(sc->dc_flags & DC_TX_POLL)) 3298 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3299 3300 /* 3301 * Set a timeout in case the chip goes out to lunch. 3302 */ 3303 ifp->if_timer = 5; 3304 3305 DC_UNLOCK(sc); 3306 3307 return; 3308 } 3309 3310 static void 3311 dc_init(xsc) 3312 void *xsc; 3313 { 3314 struct dc_softc *sc = xsc; 3315 struct ifnet *ifp = &sc->arpcom.ac_if; 3316 struct mii_data *mii; 3317 3318 DC_LOCK(sc); 3319 3320 mii = device_get_softc(sc->dc_miibus); 3321 3322 /* 3323 * Cancel pending I/O and free all RX/TX buffers. 3324 */ 3325 dc_stop(sc); 3326 dc_reset(sc); 3327 3328 /* 3329 * Set cache alignment and burst length. 3330 */ 3331 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3332 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3333 else 3334 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3335 /* 3336 * Evenly share the bus between receive and transmit process. 3337 */ 3338 if (DC_IS_INTEL(sc)) 3339 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3340 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3341 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3342 } else { 3343 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3344 } 3345 if (sc->dc_flags & DC_TX_POLL) 3346 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3347 switch(sc->dc_cachesize) { 3348 case 32: 3349 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3350 break; 3351 case 16: 3352 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3353 break; 3354 case 8: 3355 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3356 break; 3357 case 0: 3358 default: 3359 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3360 break; 3361 } 3362 3363 if (sc->dc_flags & DC_TX_STORENFWD) 3364 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3365 else { 3366 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3367 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3368 } else { 3369 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3370 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3371 } 3372 } 3373 3374 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3375 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3376 3377 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3378 /* 3379 * The app notes for the 98713 and 98715A say that 3380 * in order to have the chips operate properly, a magic 3381 * number must be written to CSR16. Macronix does not 3382 * document the meaning of these bits so there's no way 3383 * to know exactly what they do. The 98713 has a magic 3384 * number all its own; the rest all use a different one. 3385 */ 3386 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3387 if (sc->dc_type == DC_TYPE_98713) 3388 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3389 else 3390 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3391 } 3392 3393 if (DC_IS_XIRCOM(sc)) { 3394 /* 3395 * setup General Purpose Port mode and data so the tulip 3396 * can talk to the MII. 3397 */ 3398 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3399 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3400 DELAY(10); 3401 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3402 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3403 DELAY(10); 3404 } 3405 3406 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3407 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3408 3409 /* Init circular RX list. */ 3410 if (dc_list_rx_init(sc) == ENOBUFS) { 3411 printf("dc%d: initialization failed: no " 3412 "memory for rx buffers\n", sc->dc_unit); 3413 dc_stop(sc); 3414 DC_UNLOCK(sc); 3415 return; 3416 } 3417 3418 /* 3419 * Init tx descriptors. 3420 */ 3421 dc_list_tx_init(sc); 3422 3423 /* 3424 * Load the address of the RX list. 3425 */ 3426 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3427 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3428 3429 /* 3430 * Enable interrupts. 3431 */ 3432 #ifdef DEVICE_POLLING 3433 /* 3434 * ... but only if we are not polling, and make sure they are off in 3435 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3436 * after a reset. 3437 */ 3438 if (ifp->if_flags & IFF_POLLING) 3439 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3440 else 3441 #endif 3442 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3443 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3444 3445 /* Enable transmitter. */ 3446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3447 3448 /* 3449 * If this is an Intel 21143 and we're not using the 3450 * MII port, program the LED control pins so we get 3451 * link and activity indications. 3452 */ 3453 if (sc->dc_flags & DC_TULIP_LEDS) { 3454 CSR_WRITE_4(sc, DC_WATCHDOG, 3455 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3456 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3457 } 3458 3459 /* 3460 * Load the RX/multicast filter. We do this sort of late 3461 * because the filter programming scheme on the 21143 and 3462 * some clones requires DMAing a setup frame via the TX 3463 * engine, and we need the transmitter enabled for that. 3464 */ 3465 dc_setfilt(sc); 3466 3467 /* Enable receiver. */ 3468 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3469 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3470 3471 mii_mediachg(mii); 3472 dc_setcfg(sc, sc->dc_if_media); 3473 3474 ifp->if_flags |= IFF_RUNNING; 3475 ifp->if_flags &= ~IFF_OACTIVE; 3476 3477 /* Don't start the ticker if this is a homePNA link. */ 3478 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3479 sc->dc_link = 1; 3480 else { 3481 if (sc->dc_flags & DC_21143_NWAY) 3482 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3483 else 3484 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3485 } 3486 3487 #ifdef SRM_MEDIA 3488 if(sc->dc_srm_media) { 3489 struct ifreq ifr; 3490 3491 ifr.ifr_media = sc->dc_srm_media; 3492 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3493 sc->dc_srm_media = 0; 3494 } 3495 #endif 3496 DC_UNLOCK(sc); 3497 return; 3498 } 3499 3500 /* 3501 * Set media options. 3502 */ 3503 static int 3504 dc_ifmedia_upd(ifp) 3505 struct ifnet *ifp; 3506 { 3507 struct dc_softc *sc; 3508 struct mii_data *mii; 3509 struct ifmedia *ifm; 3510 3511 sc = ifp->if_softc; 3512 mii = device_get_softc(sc->dc_miibus); 3513 mii_mediachg(mii); 3514 ifm = &mii->mii_media; 3515 3516 if (DC_IS_DAVICOM(sc) && 3517 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3518 dc_setcfg(sc, ifm->ifm_media); 3519 else 3520 sc->dc_link = 0; 3521 3522 return(0); 3523 } 3524 3525 /* 3526 * Report current media status. 3527 */ 3528 static void 3529 dc_ifmedia_sts(ifp, ifmr) 3530 struct ifnet *ifp; 3531 struct ifmediareq *ifmr; 3532 { 3533 struct dc_softc *sc; 3534 struct mii_data *mii; 3535 struct ifmedia *ifm; 3536 3537 sc = ifp->if_softc; 3538 mii = device_get_softc(sc->dc_miibus); 3539 mii_pollstat(mii); 3540 ifm = &mii->mii_media; 3541 if (DC_IS_DAVICOM(sc)) { 3542 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3543 ifmr->ifm_active = ifm->ifm_media; 3544 ifmr->ifm_status = 0; 3545 return; 3546 } 3547 } 3548 ifmr->ifm_active = mii->mii_media_active; 3549 ifmr->ifm_status = mii->mii_media_status; 3550 3551 return; 3552 } 3553 3554 static int 3555 dc_ioctl(ifp, command, data) 3556 struct ifnet *ifp; 3557 u_long command; 3558 caddr_t data; 3559 { 3560 struct dc_softc *sc = ifp->if_softc; 3561 struct ifreq *ifr = (struct ifreq *) data; 3562 struct mii_data *mii; 3563 int error = 0; 3564 3565 DC_LOCK(sc); 3566 3567 switch(command) { 3568 case SIOCSIFFLAGS: 3569 if (ifp->if_flags & IFF_UP) { 3570 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3571 (IFF_PROMISC | IFF_ALLMULTI); 3572 3573 if (ifp->if_flags & IFF_RUNNING) { 3574 if (need_setfilt) 3575 dc_setfilt(sc); 3576 } else { 3577 sc->dc_txthresh = 0; 3578 dc_init(sc); 3579 } 3580 } else { 3581 if (ifp->if_flags & IFF_RUNNING) 3582 dc_stop(sc); 3583 } 3584 sc->dc_if_flags = ifp->if_flags; 3585 error = 0; 3586 break; 3587 case SIOCADDMULTI: 3588 case SIOCDELMULTI: 3589 dc_setfilt(sc); 3590 error = 0; 3591 break; 3592 case SIOCGIFMEDIA: 3593 case SIOCSIFMEDIA: 3594 mii = device_get_softc(sc->dc_miibus); 3595 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3596 #ifdef SRM_MEDIA 3597 if (sc->dc_srm_media) 3598 sc->dc_srm_media = 0; 3599 #endif 3600 break; 3601 default: 3602 error = ether_ioctl(ifp, command, data); 3603 break; 3604 } 3605 3606 DC_UNLOCK(sc); 3607 3608 return(error); 3609 } 3610 3611 static void 3612 dc_watchdog(ifp) 3613 struct ifnet *ifp; 3614 { 3615 struct dc_softc *sc; 3616 3617 sc = ifp->if_softc; 3618 3619 DC_LOCK(sc); 3620 3621 ifp->if_oerrors++; 3622 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3623 3624 dc_stop(sc); 3625 dc_reset(sc); 3626 dc_init(sc); 3627 3628 if (ifp->if_snd.ifq_head != NULL) 3629 dc_start(ifp); 3630 3631 DC_UNLOCK(sc); 3632 3633 return; 3634 } 3635 3636 /* 3637 * Stop the adapter and free any mbufs allocated to the 3638 * RX and TX lists. 3639 */ 3640 static void 3641 dc_stop(sc) 3642 struct dc_softc *sc; 3643 { 3644 register int i; 3645 struct ifnet *ifp; 3646 3647 DC_LOCK(sc); 3648 3649 ifp = &sc->arpcom.ac_if; 3650 ifp->if_timer = 0; 3651 3652 callout_stop(&sc->dc_stat_ch); 3653 3654 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3655 #ifdef DEVICE_POLLING 3656 ether_poll_deregister(ifp); 3657 #endif 3658 3659 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3660 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3661 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3662 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3663 sc->dc_link = 0; 3664 3665 /* 3666 * Free data in the RX lists. 3667 */ 3668 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3669 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3670 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3671 sc->dc_cdata.dc_rx_chain[i] = NULL; 3672 } 3673 } 3674 bzero((char *)&sc->dc_ldata->dc_rx_list, 3675 sizeof(sc->dc_ldata->dc_rx_list)); 3676 3677 /* 3678 * Free the TX list buffers. 3679 */ 3680 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3681 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3682 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3683 DC_TXCTL_SETUP) { 3684 sc->dc_cdata.dc_tx_chain[i] = NULL; 3685 continue; 3686 } 3687 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3688 sc->dc_cdata.dc_tx_chain[i] = NULL; 3689 } 3690 } 3691 3692 bzero((char *)&sc->dc_ldata->dc_tx_list, 3693 sizeof(sc->dc_ldata->dc_tx_list)); 3694 3695 DC_UNLOCK(sc); 3696 3697 return; 3698 } 3699 3700 /* 3701 * Device suspend routine. Stop the interface and save some PCI 3702 * settings in case the BIOS doesn't restore them properly on 3703 * resume. 3704 */ 3705 static int 3706 dc_suspend(dev) 3707 device_t dev; 3708 { 3709 register int i; 3710 int s; 3711 struct dc_softc *sc; 3712 3713 s = splimp(); 3714 3715 sc = device_get_softc(dev); 3716 3717 dc_stop(sc); 3718 3719 for (i = 0; i < 5; i++) 3720 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3721 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3722 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3723 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3724 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3725 3726 sc->suspended = 1; 3727 3728 splx(s); 3729 return (0); 3730 } 3731 3732 /* 3733 * Device resume routine. Restore some PCI settings in case the BIOS 3734 * doesn't, re-enable busmastering, and restart the interface if 3735 * appropriate. 3736 */ 3737 static int 3738 dc_resume(dev) 3739 device_t dev; 3740 { 3741 register int i; 3742 int s; 3743 struct dc_softc *sc; 3744 struct ifnet *ifp; 3745 3746 s = splimp(); 3747 3748 sc = device_get_softc(dev); 3749 ifp = &sc->arpcom.ac_if; 3750 3751 dc_acpi(dev); 3752 3753 /* better way to do this? */ 3754 for (i = 0; i < 5; i++) 3755 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3756 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3757 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3758 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3759 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3760 3761 /* reenable busmastering */ 3762 pci_enable_busmaster(dev); 3763 pci_enable_io(dev, DC_RES); 3764 3765 /* reinitialize interface if necessary */ 3766 if (ifp->if_flags & IFF_UP) 3767 dc_init(sc); 3768 3769 sc->suspended = 0; 3770 3771 splx(s); 3772 return (0); 3773 } 3774 3775 /* 3776 * Stop all chip I/O so that the kernel's probe routines don't 3777 * get confused by errant DMAs when rebooting. 3778 */ 3779 static void 3780 dc_shutdown(dev) 3781 device_t dev; 3782 { 3783 struct dc_softc *sc; 3784 3785 sc = device_get_softc(dev); 3786 3787 dc_stop(sc); 3788 3789 return; 3790 }
Cache object: 207713cb44f19a5f0148dc0e75133a11
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