Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/pci/if_dc.c
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1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/6.0/sys/pci/if_dc.c 151140 2005-10-09 04:11:20Z delphij $"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #ifdef HAVE_KERNEL_OPTION_HEADERS 95 #include "opt_device_polling.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/endian.h> 100 #include <sys/systm.h> 101 #include <sys/sockio.h> 102 #include <sys/mbuf.h> 103 #include <sys/malloc.h> 104 #include <sys/kernel.h> 105 #include <sys/module.h> 106 #include <sys/socket.h> 107 #include <sys/sysctl.h> 108 109 #include <net/if.h> 110 #include <net/if_arp.h> 111 #include <net/ethernet.h> 112 #include <net/if_dl.h> 113 #include <net/if_media.h> 114 #include <net/if_types.h> 115 #include <net/if_vlan_var.h> 116 117 #include <net/bpf.h> 118 119 #include <machine/bus.h> 120 #include <machine/resource.h> 121 #include <sys/bus.h> 122 #include <sys/rman.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 130 #define DC_USEIOSPACE 131 #ifdef __alpha__ 132 #define SRM_MEDIA 133 #endif 134 135 #include <pci/if_dcreg.h> 136 137 #ifdef __sparc64__ 138 #include <dev/ofw/openfirm.h> 139 #include <machine/ofw_machdep.h> 140 #endif 141 142 MODULE_DEPEND(dc, pci, 1, 1, 1); 143 MODULE_DEPEND(dc, ether, 1, 1, 1); 144 MODULE_DEPEND(dc, miibus, 1, 1, 1); 145 146 /* "controller miibus0" required. See GENERIC if you get errors here. */ 147 #include "miibus_if.h" 148 149 /* 150 * Various supported device vendors/types and their names. 151 */ 152 static struct dc_type dc_devs[] = { 153 { DC_VENDORID_DEC, DC_DEVICEID_21143, 154 "Intel 21143 10/100BaseTX" }, 155 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 156 "Davicom DM9009 10/100BaseTX" }, 157 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 158 "Davicom DM9100 10/100BaseTX" }, 159 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 160 "Davicom DM9102 10/100BaseTX" }, 161 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 162 "Davicom DM9102A 10/100BaseTX" }, 163 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 164 "ADMtek AL981 10/100BaseTX" }, 165 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 166 "ADMtek AN985 10/100BaseTX" }, 167 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 168 "ADMtek ADM9511 10/100BaseTX" }, 169 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 170 "ADMtek ADM9513 10/100BaseTX" }, 171 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 172 "Netgear FA511 10/100BaseTX" }, 173 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 174 "ASIX AX88140A 10/100BaseTX" }, 175 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 176 "ASIX AX88141 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98713, 178 "Macronix 98713 10/100BaseTX" }, 179 { DC_VENDORID_MX, DC_DEVICEID_98713, 180 "Macronix 98713A 10/100BaseTX" }, 181 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 182 "Compex RL100-TX 10/100BaseTX" }, 183 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 184 "Compex RL100-TX 10/100BaseTX" }, 185 { DC_VENDORID_MX, DC_DEVICEID_987x5, 186 "Macronix 98715/98715A 10/100BaseTX" }, 187 { DC_VENDORID_MX, DC_DEVICEID_987x5, 188 "Macronix 98715AEC-C 10/100BaseTX" }, 189 { DC_VENDORID_MX, DC_DEVICEID_987x5, 190 "Macronix 98725 10/100BaseTX" }, 191 { DC_VENDORID_MX, DC_DEVICEID_98727, 192 "Macronix 98727/98732 10/100BaseTX" }, 193 { DC_VENDORID_LO, DC_DEVICEID_82C115, 194 "LC82C115 PNIC II 10/100BaseTX" }, 195 { DC_VENDORID_LO, DC_DEVICEID_82C168, 196 "82c168 PNIC 10/100BaseTX" }, 197 { DC_VENDORID_LO, DC_DEVICEID_82C168, 198 "82c169 PNIC 10/100BaseTX" }, 199 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 200 "Accton EN1217 10/100BaseTX" }, 201 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 202 "Accton EN2242 MiniPCI 10/100BaseTX" }, 203 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 204 "Xircom X3201 10/100BaseTX" }, 205 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 206 "Abocom FE2500 10/100BaseTX" }, 207 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX, 208 "Abocom FE2500MX 10/100BaseTX" }, 209 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 210 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 211 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 212 "Hawking CB102 CardBus 10/100" }, 213 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 214 "PlaneX FNW-3602-T CardBus 10/100" }, 215 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 216 "3Com OfficeConnect 10/100B" }, 217 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 218 "Microsoft MN-120 CardBus 10/100" }, 219 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 220 "Microsoft MN-130 10/100" }, 221 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 222 "Microsoft MN-130 10/100" }, 223 { 0, 0, NULL } 224 }; 225 226 static int dc_probe(device_t); 227 static int dc_attach(device_t); 228 static int dc_detach(device_t); 229 static int dc_suspend(device_t); 230 static int dc_resume(device_t); 231 static struct dc_type *dc_devtype(device_t); 232 static int dc_newbuf(struct dc_softc *, int, int); 233 static int dc_encap(struct dc_softc *, struct mbuf **); 234 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 235 static int dc_rx_resync(struct dc_softc *); 236 static void dc_rxeof(struct dc_softc *); 237 static void dc_txeof(struct dc_softc *); 238 static void dc_tick(void *); 239 static void dc_tx_underrun(struct dc_softc *); 240 static void dc_intr(void *); 241 static void dc_start(struct ifnet *); 242 static void dc_start_locked(struct ifnet *); 243 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 244 static void dc_init(void *); 245 static void dc_init_locked(struct dc_softc *); 246 static void dc_stop(struct dc_softc *); 247 static void dc_watchdog(struct ifnet *); 248 static void dc_shutdown(device_t); 249 static int dc_ifmedia_upd(struct ifnet *); 250 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 251 252 static void dc_delay(struct dc_softc *); 253 static void dc_eeprom_idle(struct dc_softc *); 254 static void dc_eeprom_putbyte(struct dc_softc *, int); 255 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 256 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 257 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 258 static void dc_eeprom_width(struct dc_softc *); 259 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 260 261 static void dc_mii_writebit(struct dc_softc *, int); 262 static int dc_mii_readbit(struct dc_softc *); 263 static void dc_mii_sync(struct dc_softc *); 264 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 265 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 266 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 267 static int dc_miibus_readreg(device_t, int, int); 268 static int dc_miibus_writereg(device_t, int, int, int); 269 static void dc_miibus_statchg(device_t); 270 static void dc_miibus_mediainit(device_t); 271 272 static void dc_setcfg(struct dc_softc *, int); 273 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 274 static uint32_t dc_mchash_be(const uint8_t *); 275 static void dc_setfilt_21143(struct dc_softc *); 276 static void dc_setfilt_asix(struct dc_softc *); 277 static void dc_setfilt_admtek(struct dc_softc *); 278 static void dc_setfilt_xircom(struct dc_softc *); 279 280 static void dc_setfilt(struct dc_softc *); 281 282 static void dc_reset(struct dc_softc *); 283 static int dc_list_rx_init(struct dc_softc *); 284 static int dc_list_tx_init(struct dc_softc *); 285 286 static void dc_read_srom(struct dc_softc *, int); 287 static void dc_parse_21143_srom(struct dc_softc *); 288 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 289 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 290 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 291 static void dc_apply_fixup(struct dc_softc *, int); 292 293 static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 294 static void dc_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 295 296 #ifdef DC_USEIOSPACE 297 #define DC_RES SYS_RES_IOPORT 298 #define DC_RID DC_PCI_CFBIO 299 #else 300 #define DC_RES SYS_RES_MEMORY 301 #define DC_RID DC_PCI_CFBMA 302 #endif 303 304 static device_method_t dc_methods[] = { 305 /* Device interface */ 306 DEVMETHOD(device_probe, dc_probe), 307 DEVMETHOD(device_attach, dc_attach), 308 DEVMETHOD(device_detach, dc_detach), 309 DEVMETHOD(device_suspend, dc_suspend), 310 DEVMETHOD(device_resume, dc_resume), 311 DEVMETHOD(device_shutdown, dc_shutdown), 312 313 /* bus interface */ 314 DEVMETHOD(bus_print_child, bus_generic_print_child), 315 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 316 317 /* MII interface */ 318 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 319 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 320 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 321 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 322 323 { 0, 0 } 324 }; 325 326 static driver_t dc_driver = { 327 "dc", 328 dc_methods, 329 sizeof(struct dc_softc) 330 }; 331 332 static devclass_t dc_devclass; 333 #ifdef __i386__ 334 static int dc_quick = 1; 335 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 336 "do not m_devget() in dc driver"); 337 #endif 338 339 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 340 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 341 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 342 343 #define DC_SETBIT(sc, reg, x) \ 344 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 345 346 #define DC_CLRBIT(sc, reg, x) \ 347 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 348 349 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 350 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 351 352 static void 353 dc_delay(struct dc_softc *sc) 354 { 355 int idx; 356 357 for (idx = (300 / 33) + 1; idx > 0; idx--) 358 CSR_READ_4(sc, DC_BUSCTL); 359 } 360 361 static void 362 dc_eeprom_width(struct dc_softc *sc) 363 { 364 int i; 365 366 /* Force EEPROM to idle state. */ 367 dc_eeprom_idle(sc); 368 369 /* Enter EEPROM access mode. */ 370 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 371 dc_delay(sc); 372 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 373 dc_delay(sc); 374 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 375 dc_delay(sc); 376 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 377 dc_delay(sc); 378 379 for (i = 3; i--;) { 380 if (6 & (1 << i)) 381 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 382 else 383 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 384 dc_delay(sc); 385 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 386 dc_delay(sc); 387 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 388 dc_delay(sc); 389 } 390 391 for (i = 1; i <= 12; i++) { 392 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 393 dc_delay(sc); 394 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 395 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 396 dc_delay(sc); 397 break; 398 } 399 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 400 dc_delay(sc); 401 } 402 403 /* Turn off EEPROM access mode. */ 404 dc_eeprom_idle(sc); 405 406 if (i < 4 || i > 12) 407 sc->dc_romwidth = 6; 408 else 409 sc->dc_romwidth = i; 410 411 /* Enter EEPROM access mode. */ 412 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 413 dc_delay(sc); 414 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 415 dc_delay(sc); 416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 417 dc_delay(sc); 418 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 419 dc_delay(sc); 420 421 /* Turn off EEPROM access mode. */ 422 dc_eeprom_idle(sc); 423 } 424 425 static void 426 dc_eeprom_idle(struct dc_softc *sc) 427 { 428 int i; 429 430 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 431 dc_delay(sc); 432 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 433 dc_delay(sc); 434 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 435 dc_delay(sc); 436 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 437 dc_delay(sc); 438 439 for (i = 0; i < 25; i++) { 440 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 441 dc_delay(sc); 442 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 443 dc_delay(sc); 444 } 445 446 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 447 dc_delay(sc); 448 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 449 dc_delay(sc); 450 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 451 } 452 453 /* 454 * Send a read command and address to the EEPROM, check for ACK. 455 */ 456 static void 457 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 458 { 459 int d, i; 460 461 d = DC_EECMD_READ >> 6; 462 for (i = 3; i--; ) { 463 if (d & (1 << i)) 464 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 465 else 466 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 467 dc_delay(sc); 468 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 469 dc_delay(sc); 470 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 471 dc_delay(sc); 472 } 473 474 /* 475 * Feed in each bit and strobe the clock. 476 */ 477 for (i = sc->dc_romwidth; i--;) { 478 if (addr & (1 << i)) { 479 SIO_SET(DC_SIO_EE_DATAIN); 480 } else { 481 SIO_CLR(DC_SIO_EE_DATAIN); 482 } 483 dc_delay(sc); 484 SIO_SET(DC_SIO_EE_CLK); 485 dc_delay(sc); 486 SIO_CLR(DC_SIO_EE_CLK); 487 dc_delay(sc); 488 } 489 } 490 491 /* 492 * Read a word of data stored in the EEPROM at address 'addr.' 493 * The PNIC 82c168/82c169 has its own non-standard way to read 494 * the EEPROM. 495 */ 496 static void 497 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 498 { 499 int i; 500 u_int32_t r; 501 502 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 503 504 for (i = 0; i < DC_TIMEOUT; i++) { 505 DELAY(1); 506 r = CSR_READ_4(sc, DC_SIO); 507 if (!(r & DC_PN_SIOCTL_BUSY)) { 508 *dest = (u_int16_t)(r & 0xFFFF); 509 return; 510 } 511 } 512 } 513 514 /* 515 * Read a word of data stored in the EEPROM at address 'addr.' 516 * The Xircom X3201 has its own non-standard way to read 517 * the EEPROM, too. 518 */ 519 static void 520 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 521 { 522 523 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 524 525 addr *= 2; 526 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 527 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 528 addr += 1; 529 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 530 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 531 532 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 533 } 534 535 /* 536 * Read a word of data stored in the EEPROM at address 'addr.' 537 */ 538 static void 539 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 540 { 541 int i; 542 u_int16_t word = 0; 543 544 /* Force EEPROM to idle state. */ 545 dc_eeprom_idle(sc); 546 547 /* Enter EEPROM access mode. */ 548 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 549 dc_delay(sc); 550 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 551 dc_delay(sc); 552 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 553 dc_delay(sc); 554 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 555 dc_delay(sc); 556 557 /* 558 * Send address of word we want to read. 559 */ 560 dc_eeprom_putbyte(sc, addr); 561 562 /* 563 * Start reading bits from EEPROM. 564 */ 565 for (i = 0x8000; i; i >>= 1) { 566 SIO_SET(DC_SIO_EE_CLK); 567 dc_delay(sc); 568 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 569 word |= i; 570 dc_delay(sc); 571 SIO_CLR(DC_SIO_EE_CLK); 572 dc_delay(sc); 573 } 574 575 /* Turn off EEPROM access mode. */ 576 dc_eeprom_idle(sc); 577 578 *dest = word; 579 } 580 581 /* 582 * Read a sequence of words from the EEPROM. 583 */ 584 static void 585 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 586 { 587 int i; 588 u_int16_t word = 0, *ptr; 589 590 for (i = 0; i < cnt; i++) { 591 if (DC_IS_PNIC(sc)) 592 dc_eeprom_getword_pnic(sc, off + i, &word); 593 else if (DC_IS_XIRCOM(sc)) 594 dc_eeprom_getword_xircom(sc, off + i, &word); 595 else 596 dc_eeprom_getword(sc, off + i, &word); 597 ptr = (u_int16_t *)(dest + (i * 2)); 598 if (be) 599 *ptr = be16toh(word); 600 else 601 *ptr = le16toh(word); 602 } 603 } 604 605 /* 606 * The following two routines are taken from the Macronix 98713 607 * Application Notes pp.19-21. 608 */ 609 /* 610 * Write a bit to the MII bus. 611 */ 612 static void 613 dc_mii_writebit(struct dc_softc *sc, int bit) 614 { 615 616 if (bit) 617 CSR_WRITE_4(sc, DC_SIO, 618 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 619 else 620 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 621 622 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 623 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 624 } 625 626 /* 627 * Read a bit from the MII bus. 628 */ 629 static int 630 dc_mii_readbit(struct dc_softc *sc) 631 { 632 633 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 634 CSR_READ_4(sc, DC_SIO); 635 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 636 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 637 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 638 return (1); 639 640 return (0); 641 } 642 643 /* 644 * Sync the PHYs by setting data bit and strobing the clock 32 times. 645 */ 646 static void 647 dc_mii_sync(struct dc_softc *sc) 648 { 649 int i; 650 651 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 652 653 for (i = 0; i < 32; i++) 654 dc_mii_writebit(sc, 1); 655 } 656 657 /* 658 * Clock a series of bits through the MII. 659 */ 660 static void 661 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 662 { 663 int i; 664 665 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 666 dc_mii_writebit(sc, bits & i); 667 } 668 669 /* 670 * Read an PHY register through the MII. 671 */ 672 static int 673 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 674 { 675 int i, ack; 676 677 /* 678 * Set up frame for RX. 679 */ 680 frame->mii_stdelim = DC_MII_STARTDELIM; 681 frame->mii_opcode = DC_MII_READOP; 682 frame->mii_turnaround = 0; 683 frame->mii_data = 0; 684 685 /* 686 * Sync the PHYs. 687 */ 688 dc_mii_sync(sc); 689 690 /* 691 * Send command/address info. 692 */ 693 dc_mii_send(sc, frame->mii_stdelim, 2); 694 dc_mii_send(sc, frame->mii_opcode, 2); 695 dc_mii_send(sc, frame->mii_phyaddr, 5); 696 dc_mii_send(sc, frame->mii_regaddr, 5); 697 698 #ifdef notdef 699 /* Idle bit */ 700 dc_mii_writebit(sc, 1); 701 dc_mii_writebit(sc, 0); 702 #endif 703 704 /* Check for ack. */ 705 ack = dc_mii_readbit(sc); 706 707 /* 708 * Now try reading data bits. If the ack failed, we still 709 * need to clock through 16 cycles to keep the PHY(s) in sync. 710 */ 711 if (ack) { 712 for (i = 0; i < 16; i++) 713 dc_mii_readbit(sc); 714 goto fail; 715 } 716 717 for (i = 0x8000; i; i >>= 1) { 718 if (!ack) { 719 if (dc_mii_readbit(sc)) 720 frame->mii_data |= i; 721 } 722 } 723 724 fail: 725 726 dc_mii_writebit(sc, 0); 727 dc_mii_writebit(sc, 0); 728 729 if (ack) 730 return (1); 731 return (0); 732 } 733 734 /* 735 * Write to a PHY register through the MII. 736 */ 737 static int 738 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 739 { 740 741 /* 742 * Set up frame for TX. 743 */ 744 745 frame->mii_stdelim = DC_MII_STARTDELIM; 746 frame->mii_opcode = DC_MII_WRITEOP; 747 frame->mii_turnaround = DC_MII_TURNAROUND; 748 749 /* 750 * Sync the PHYs. 751 */ 752 dc_mii_sync(sc); 753 754 dc_mii_send(sc, frame->mii_stdelim, 2); 755 dc_mii_send(sc, frame->mii_opcode, 2); 756 dc_mii_send(sc, frame->mii_phyaddr, 5); 757 dc_mii_send(sc, frame->mii_regaddr, 5); 758 dc_mii_send(sc, frame->mii_turnaround, 2); 759 dc_mii_send(sc, frame->mii_data, 16); 760 761 /* Idle bit. */ 762 dc_mii_writebit(sc, 0); 763 dc_mii_writebit(sc, 0); 764 765 return (0); 766 } 767 768 static int 769 dc_miibus_readreg(device_t dev, int phy, int reg) 770 { 771 struct dc_mii_frame frame; 772 struct dc_softc *sc; 773 int i, rval, phy_reg = 0; 774 775 sc = device_get_softc(dev); 776 bzero(&frame, sizeof(frame)); 777 778 /* 779 * Note: both the AL981 and AN985 have internal PHYs, 780 * however the AL981 provides direct access to the PHY 781 * registers while the AN985 uses a serial MII interface. 782 * The AN985's MII interface is also buggy in that you 783 * can read from any MII address (0 to 31), but only address 1 784 * behaves normally. To deal with both cases, we pretend 785 * that the PHY is at MII address 1. 786 */ 787 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 788 return (0); 789 790 /* 791 * Note: the ukphy probes of the RS7112 report a PHY at 792 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 793 * so we only respond to correct one. 794 */ 795 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 796 return (0); 797 798 if (sc->dc_pmode != DC_PMODE_MII) { 799 if (phy == (MII_NPHY - 1)) { 800 switch (reg) { 801 case MII_BMSR: 802 /* 803 * Fake something to make the probe 804 * code think there's a PHY here. 805 */ 806 return (BMSR_MEDIAMASK); 807 break; 808 case MII_PHYIDR1: 809 if (DC_IS_PNIC(sc)) 810 return (DC_VENDORID_LO); 811 return (DC_VENDORID_DEC); 812 break; 813 case MII_PHYIDR2: 814 if (DC_IS_PNIC(sc)) 815 return (DC_DEVICEID_82C168); 816 return (DC_DEVICEID_21143); 817 break; 818 default: 819 return (0); 820 break; 821 } 822 } else 823 return (0); 824 } 825 826 if (DC_IS_PNIC(sc)) { 827 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 828 (phy << 23) | (reg << 18)); 829 for (i = 0; i < DC_TIMEOUT; i++) { 830 DELAY(1); 831 rval = CSR_READ_4(sc, DC_PN_MII); 832 if (!(rval & DC_PN_MII_BUSY)) { 833 rval &= 0xFFFF; 834 return (rval == 0xFFFF ? 0 : rval); 835 } 836 } 837 return (0); 838 } 839 840 if (DC_IS_COMET(sc)) { 841 switch (reg) { 842 case MII_BMCR: 843 phy_reg = DC_AL_BMCR; 844 break; 845 case MII_BMSR: 846 phy_reg = DC_AL_BMSR; 847 break; 848 case MII_PHYIDR1: 849 phy_reg = DC_AL_VENID; 850 break; 851 case MII_PHYIDR2: 852 phy_reg = DC_AL_DEVID; 853 break; 854 case MII_ANAR: 855 phy_reg = DC_AL_ANAR; 856 break; 857 case MII_ANLPAR: 858 phy_reg = DC_AL_LPAR; 859 break; 860 case MII_ANER: 861 phy_reg = DC_AL_ANER; 862 break; 863 default: 864 device_printf(dev, "phy_read: bad phy register %x\n", 865 reg); 866 return (0); 867 break; 868 } 869 870 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 871 872 if (rval == 0xFFFF) 873 return (0); 874 return (rval); 875 } 876 877 frame.mii_phyaddr = phy; 878 frame.mii_regaddr = reg; 879 if (sc->dc_type == DC_TYPE_98713) { 880 phy_reg = CSR_READ_4(sc, DC_NETCFG); 881 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 882 } 883 dc_mii_readreg(sc, &frame); 884 if (sc->dc_type == DC_TYPE_98713) 885 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 886 887 return (frame.mii_data); 888 } 889 890 static int 891 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 892 { 893 struct dc_softc *sc; 894 struct dc_mii_frame frame; 895 int i, phy_reg = 0; 896 897 sc = device_get_softc(dev); 898 bzero(&frame, sizeof(frame)); 899 900 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 901 return (0); 902 903 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 904 return (0); 905 906 if (DC_IS_PNIC(sc)) { 907 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 908 (phy << 23) | (reg << 10) | data); 909 for (i = 0; i < DC_TIMEOUT; i++) { 910 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 911 break; 912 } 913 return (0); 914 } 915 916 if (DC_IS_COMET(sc)) { 917 switch (reg) { 918 case MII_BMCR: 919 phy_reg = DC_AL_BMCR; 920 break; 921 case MII_BMSR: 922 phy_reg = DC_AL_BMSR; 923 break; 924 case MII_PHYIDR1: 925 phy_reg = DC_AL_VENID; 926 break; 927 case MII_PHYIDR2: 928 phy_reg = DC_AL_DEVID; 929 break; 930 case MII_ANAR: 931 phy_reg = DC_AL_ANAR; 932 break; 933 case MII_ANLPAR: 934 phy_reg = DC_AL_LPAR; 935 break; 936 case MII_ANER: 937 phy_reg = DC_AL_ANER; 938 break; 939 default: 940 device_printf(dev, "phy_write: bad phy register %x\n", 941 reg); 942 return (0); 943 break; 944 } 945 946 CSR_WRITE_4(sc, phy_reg, data); 947 return (0); 948 } 949 950 frame.mii_phyaddr = phy; 951 frame.mii_regaddr = reg; 952 frame.mii_data = data; 953 954 if (sc->dc_type == DC_TYPE_98713) { 955 phy_reg = CSR_READ_4(sc, DC_NETCFG); 956 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 957 } 958 dc_mii_writereg(sc, &frame); 959 if (sc->dc_type == DC_TYPE_98713) 960 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 961 962 return (0); 963 } 964 965 static void 966 dc_miibus_statchg(device_t dev) 967 { 968 struct dc_softc *sc; 969 struct mii_data *mii; 970 struct ifmedia *ifm; 971 972 sc = device_get_softc(dev); 973 if (DC_IS_ADMTEK(sc)) 974 return; 975 976 mii = device_get_softc(sc->dc_miibus); 977 ifm = &mii->mii_media; 978 if (DC_IS_DAVICOM(sc) && 979 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 980 dc_setcfg(sc, ifm->ifm_media); 981 sc->dc_if_media = ifm->ifm_media; 982 } else { 983 dc_setcfg(sc, mii->mii_media_active); 984 sc->dc_if_media = mii->mii_media_active; 985 } 986 } 987 988 /* 989 * Special support for DM9102A cards with HomePNA PHYs. Note: 990 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 991 * to be impossible to talk to the management interface of the DM9801 992 * PHY (its MDIO pin is not connected to anything). Consequently, 993 * the driver has to just 'know' about the additional mode and deal 994 * with it itself. *sigh* 995 */ 996 static void 997 dc_miibus_mediainit(device_t dev) 998 { 999 struct dc_softc *sc; 1000 struct mii_data *mii; 1001 struct ifmedia *ifm; 1002 int rev; 1003 1004 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1005 1006 sc = device_get_softc(dev); 1007 mii = device_get_softc(sc->dc_miibus); 1008 ifm = &mii->mii_media; 1009 1010 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1011 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1012 } 1013 1014 #define DC_BITS_512 9 1015 #define DC_BITS_128 7 1016 #define DC_BITS_64 6 1017 1018 static uint32_t 1019 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1020 { 1021 uint32_t crc; 1022 1023 /* Compute CRC for the address value. */ 1024 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1025 1026 /* 1027 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1028 * chips is only 128 bits wide. 1029 */ 1030 if (sc->dc_flags & DC_128BIT_HASH) 1031 return (crc & ((1 << DC_BITS_128) - 1)); 1032 1033 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1034 if (sc->dc_flags & DC_64BIT_HASH) 1035 return (crc & ((1 << DC_BITS_64) - 1)); 1036 1037 /* Xircom's hash filtering table is different (read: weird) */ 1038 /* Xircom uses the LEAST significant bits */ 1039 if (DC_IS_XIRCOM(sc)) { 1040 if ((crc & 0x180) == 0x180) 1041 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1042 else 1043 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1044 (12 << 4)); 1045 } 1046 1047 return (crc & ((1 << DC_BITS_512) - 1)); 1048 } 1049 1050 /* 1051 * Calculate CRC of a multicast group address, return the lower 6 bits. 1052 */ 1053 static uint32_t 1054 dc_mchash_be(const uint8_t *addr) 1055 { 1056 uint32_t crc; 1057 1058 /* Compute CRC for the address value. */ 1059 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1060 1061 /* Return the filter bit position. */ 1062 return ((crc >> 26) & 0x0000003F); 1063 } 1064 1065 /* 1066 * 21143-style RX filter setup routine. Filter programming is done by 1067 * downloading a special setup frame into the TX engine. 21143, Macronix, 1068 * PNIC, PNIC II and Davicom chips are programmed this way. 1069 * 1070 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1071 * address (our node address) and a 512-bit hash filter for multicast 1072 * frames. We also sneak the broadcast address into the hash filter since 1073 * we need that too. 1074 */ 1075 static void 1076 dc_setfilt_21143(struct dc_softc *sc) 1077 { 1078 struct dc_desc *sframe; 1079 u_int32_t h, *sp; 1080 struct ifmultiaddr *ifma; 1081 struct ifnet *ifp; 1082 int i; 1083 1084 ifp = sc->dc_ifp; 1085 1086 i = sc->dc_cdata.dc_tx_prod; 1087 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1088 sc->dc_cdata.dc_tx_cnt++; 1089 sframe = &sc->dc_ldata->dc_tx_list[i]; 1090 sp = sc->dc_cdata.dc_sbuf; 1091 bzero(sp, DC_SFRAME_LEN); 1092 1093 sframe->dc_data = htole32(sc->dc_saddr); 1094 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1095 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1096 1097 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1098 1099 /* If we want promiscuous mode, set the allframes bit. */ 1100 if (ifp->if_flags & IFF_PROMISC) 1101 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1102 else 1103 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1104 1105 if (ifp->if_flags & IFF_ALLMULTI) 1106 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1107 else 1108 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1109 1110 IF_ADDR_LOCK(ifp); 1111 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1112 if (ifma->ifma_addr->sa_family != AF_LINK) 1113 continue; 1114 h = dc_mchash_le(sc, 1115 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1116 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1117 } 1118 IF_ADDR_UNLOCK(ifp); 1119 1120 if (ifp->if_flags & IFF_BROADCAST) { 1121 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1122 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1123 } 1124 1125 /* Set our MAC address */ 1126 sp[39] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]); 1127 sp[40] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]); 1128 sp[41] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]); 1129 1130 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1131 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1132 1133 /* 1134 * The PNIC takes an exceedingly long time to process its 1135 * setup frame; wait 10ms after posting the setup frame 1136 * before proceeding, just so it has time to swallow its 1137 * medicine. 1138 */ 1139 DELAY(10000); 1140 1141 ifp->if_timer = 5; 1142 } 1143 1144 static void 1145 dc_setfilt_admtek(struct dc_softc *sc) 1146 { 1147 struct ifnet *ifp; 1148 struct ifmultiaddr *ifma; 1149 int h = 0; 1150 u_int32_t hashes[2] = { 0, 0 }; 1151 1152 ifp = sc->dc_ifp; 1153 1154 /* Init our MAC address. */ 1155 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[0])); 1156 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[4])); 1157 1158 /* If we want promiscuous mode, set the allframes bit. */ 1159 if (ifp->if_flags & IFF_PROMISC) 1160 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1161 else 1162 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1163 1164 if (ifp->if_flags & IFF_ALLMULTI) 1165 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1166 else 1167 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1168 1169 /* First, zot all the existing hash bits. */ 1170 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1171 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1172 1173 /* 1174 * If we're already in promisc or allmulti mode, we 1175 * don't have to bother programming the multicast filter. 1176 */ 1177 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1178 return; 1179 1180 /* Now program new ones. */ 1181 IF_ADDR_LOCK(ifp); 1182 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1183 if (ifma->ifma_addr->sa_family != AF_LINK) 1184 continue; 1185 if (DC_IS_CENTAUR(sc)) 1186 h = dc_mchash_le(sc, 1187 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1188 else 1189 h = dc_mchash_be( 1190 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1191 if (h < 32) 1192 hashes[0] |= (1 << h); 1193 else 1194 hashes[1] |= (1 << (h - 32)); 1195 } 1196 IF_ADDR_UNLOCK(ifp); 1197 1198 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1199 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1200 } 1201 1202 static void 1203 dc_setfilt_asix(struct dc_softc *sc) 1204 { 1205 struct ifnet *ifp; 1206 struct ifmultiaddr *ifma; 1207 int h = 0; 1208 u_int32_t hashes[2] = { 0, 0 }; 1209 1210 ifp = sc->dc_ifp; 1211 1212 /* Init our MAC address */ 1213 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1214 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1215 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[0])); 1216 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1217 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1218 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[4])); 1219 1220 /* If we want promiscuous mode, set the allframes bit. */ 1221 if (ifp->if_flags & IFF_PROMISC) 1222 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1223 else 1224 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1225 1226 if (ifp->if_flags & IFF_ALLMULTI) 1227 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1228 else 1229 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1230 1231 /* 1232 * The ASIX chip has a special bit to enable reception 1233 * of broadcast frames. 1234 */ 1235 if (ifp->if_flags & IFF_BROADCAST) 1236 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1237 else 1238 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1239 1240 /* first, zot all the existing hash bits */ 1241 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1242 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1243 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1244 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1245 1246 /* 1247 * If we're already in promisc or allmulti mode, we 1248 * don't have to bother programming the multicast filter. 1249 */ 1250 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1251 return; 1252 1253 /* now program new ones */ 1254 IF_ADDR_LOCK(ifp); 1255 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1256 if (ifma->ifma_addr->sa_family != AF_LINK) 1257 continue; 1258 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1259 if (h < 32) 1260 hashes[0] |= (1 << h); 1261 else 1262 hashes[1] |= (1 << (h - 32)); 1263 } 1264 IF_ADDR_UNLOCK(ifp); 1265 1266 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1267 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1268 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1269 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1270 } 1271 1272 static void 1273 dc_setfilt_xircom(struct dc_softc *sc) 1274 { 1275 struct ifnet *ifp; 1276 struct ifmultiaddr *ifma; 1277 struct dc_desc *sframe; 1278 u_int32_t h, *sp; 1279 int i; 1280 1281 ifp = sc->dc_ifp; 1282 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1283 1284 i = sc->dc_cdata.dc_tx_prod; 1285 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1286 sc->dc_cdata.dc_tx_cnt++; 1287 sframe = &sc->dc_ldata->dc_tx_list[i]; 1288 sp = sc->dc_cdata.dc_sbuf; 1289 bzero(sp, DC_SFRAME_LEN); 1290 1291 sframe->dc_data = htole32(sc->dc_saddr); 1292 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1293 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1294 1295 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1296 1297 /* If we want promiscuous mode, set the allframes bit. */ 1298 if (ifp->if_flags & IFF_PROMISC) 1299 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1300 else 1301 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1302 1303 if (ifp->if_flags & IFF_ALLMULTI) 1304 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1305 else 1306 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1307 1308 IF_ADDR_LOCK(ifp); 1309 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1310 if (ifma->ifma_addr->sa_family != AF_LINK) 1311 continue; 1312 h = dc_mchash_le(sc, 1313 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1314 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1315 } 1316 IF_ADDR_UNLOCK(ifp); 1317 1318 if (ifp->if_flags & IFF_BROADCAST) { 1319 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1320 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1321 } 1322 1323 /* Set our MAC address */ 1324 sp[0] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]); 1325 sp[1] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]); 1326 sp[2] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]); 1327 1328 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1329 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1330 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1331 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1332 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1333 1334 /* 1335 * Wait some time... 1336 */ 1337 DELAY(1000); 1338 1339 ifp->if_timer = 5; 1340 } 1341 1342 static void 1343 dc_setfilt(struct dc_softc *sc) 1344 { 1345 1346 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1347 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1348 dc_setfilt_21143(sc); 1349 1350 if (DC_IS_ASIX(sc)) 1351 dc_setfilt_asix(sc); 1352 1353 if (DC_IS_ADMTEK(sc)) 1354 dc_setfilt_admtek(sc); 1355 1356 if (DC_IS_XIRCOM(sc)) 1357 dc_setfilt_xircom(sc); 1358 } 1359 1360 /* 1361 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1362 * the netconfig register, we first have to put the transmit and/or 1363 * receive logic in the idle state. 1364 */ 1365 static void 1366 dc_setcfg(struct dc_softc *sc, int media) 1367 { 1368 int i, restart = 0, watchdogreg; 1369 u_int32_t isr; 1370 1371 if (IFM_SUBTYPE(media) == IFM_NONE) 1372 return; 1373 1374 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1375 restart = 1; 1376 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1377 1378 for (i = 0; i < DC_TIMEOUT; i++) { 1379 isr = CSR_READ_4(sc, DC_ISR); 1380 if (isr & DC_ISR_TX_IDLE && 1381 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1382 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1383 break; 1384 DELAY(10); 1385 } 1386 1387 if (i == DC_TIMEOUT) 1388 if_printf(sc->dc_ifp, 1389 "failed to force tx and rx to idle state\n"); 1390 } 1391 1392 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1393 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1394 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1395 if (sc->dc_pmode == DC_PMODE_MII) { 1396 if (DC_IS_INTEL(sc)) { 1397 /* There's a write enable bit here that reads as 1. */ 1398 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1399 watchdogreg &= ~DC_WDOG_CTLWREN; 1400 watchdogreg |= DC_WDOG_JABBERDIS; 1401 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1402 } else { 1403 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1404 } 1405 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1406 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1407 if (sc->dc_type == DC_TYPE_98713) 1408 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1409 DC_NETCFG_SCRAMBLER)); 1410 if (!DC_IS_DAVICOM(sc)) 1411 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1412 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1413 if (DC_IS_INTEL(sc)) 1414 dc_apply_fixup(sc, IFM_AUTO); 1415 } else { 1416 if (DC_IS_PNIC(sc)) { 1417 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1418 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1419 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1420 } 1421 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1422 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1423 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1424 if (DC_IS_INTEL(sc)) 1425 dc_apply_fixup(sc, 1426 (media & IFM_GMASK) == IFM_FDX ? 1427 IFM_100_TX | IFM_FDX : IFM_100_TX); 1428 } 1429 } 1430 1431 if (IFM_SUBTYPE(media) == IFM_10_T) { 1432 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1433 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1434 if (sc->dc_pmode == DC_PMODE_MII) { 1435 /* There's a write enable bit here that reads as 1. */ 1436 if (DC_IS_INTEL(sc)) { 1437 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1438 watchdogreg &= ~DC_WDOG_CTLWREN; 1439 watchdogreg |= DC_WDOG_JABBERDIS; 1440 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1441 } else { 1442 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1443 } 1444 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1445 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1446 if (sc->dc_type == DC_TYPE_98713) 1447 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1448 if (!DC_IS_DAVICOM(sc)) 1449 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1450 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1451 if (DC_IS_INTEL(sc)) 1452 dc_apply_fixup(sc, IFM_AUTO); 1453 } else { 1454 if (DC_IS_PNIC(sc)) { 1455 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1456 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1457 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1458 } 1459 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1460 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1461 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1462 if (DC_IS_INTEL(sc)) { 1463 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1464 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1465 if ((media & IFM_GMASK) == IFM_FDX) 1466 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1467 else 1468 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1469 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1470 DC_CLRBIT(sc, DC_10BTCTRL, 1471 DC_TCTL_AUTONEGENBL); 1472 dc_apply_fixup(sc, 1473 (media & IFM_GMASK) == IFM_FDX ? 1474 IFM_10_T | IFM_FDX : IFM_10_T); 1475 DELAY(20000); 1476 } 1477 } 1478 } 1479 1480 /* 1481 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1482 * PHY and we want HomePNA mode, set the portsel bit to turn 1483 * on the external MII port. 1484 */ 1485 if (DC_IS_DAVICOM(sc)) { 1486 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1487 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1488 sc->dc_link = 1; 1489 } else { 1490 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1491 } 1492 } 1493 1494 if ((media & IFM_GMASK) == IFM_FDX) { 1495 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1496 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1497 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1498 } else { 1499 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1500 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1501 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1502 } 1503 1504 if (restart) 1505 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1506 } 1507 1508 static void 1509 dc_reset(struct dc_softc *sc) 1510 { 1511 int i; 1512 1513 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1514 1515 for (i = 0; i < DC_TIMEOUT; i++) { 1516 DELAY(10); 1517 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1518 break; 1519 } 1520 1521 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1522 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1523 DELAY(10000); 1524 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1525 i = 0; 1526 } 1527 1528 if (i == DC_TIMEOUT) 1529 if_printf(sc->dc_ifp, "reset never completed!\n"); 1530 1531 /* Wait a little while for the chip to get its brains in order. */ 1532 DELAY(1000); 1533 1534 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1535 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1536 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1537 1538 /* 1539 * Bring the SIA out of reset. In some cases, it looks 1540 * like failing to unreset the SIA soon enough gets it 1541 * into a state where it will never come out of reset 1542 * until we reset the whole chip again. 1543 */ 1544 if (DC_IS_INTEL(sc)) { 1545 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1546 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1547 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1548 } 1549 } 1550 1551 static struct dc_type * 1552 dc_devtype(device_t dev) 1553 { 1554 struct dc_type *t; 1555 u_int32_t rev; 1556 1557 t = dc_devs; 1558 1559 while (t->dc_name != NULL) { 1560 if ((pci_get_vendor(dev) == t->dc_vid) && 1561 (pci_get_device(dev) == t->dc_did)) { 1562 /* Check the PCI revision */ 1563 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1564 if (t->dc_did == DC_DEVICEID_98713 && 1565 rev >= DC_REVISION_98713A) 1566 t++; 1567 if (t->dc_did == DC_DEVICEID_98713_CP && 1568 rev >= DC_REVISION_98713A) 1569 t++; 1570 if (t->dc_did == DC_DEVICEID_987x5 && 1571 rev >= DC_REVISION_98715AEC_C) 1572 t++; 1573 if (t->dc_did == DC_DEVICEID_987x5 && 1574 rev >= DC_REVISION_98725) 1575 t++; 1576 if (t->dc_did == DC_DEVICEID_AX88140A && 1577 rev >= DC_REVISION_88141) 1578 t++; 1579 if (t->dc_did == DC_DEVICEID_82C168 && 1580 rev >= DC_REVISION_82C169) 1581 t++; 1582 if (t->dc_did == DC_DEVICEID_DM9102 && 1583 rev >= DC_REVISION_DM9102A) 1584 t++; 1585 /* 1586 * The Microsoft MN-130 has a device ID of 0x0002, 1587 * which happens to be the same as the PNIC 82c168. 1588 * To keep dc_attach() from getting confused, we 1589 * pretend its ID is something different. 1590 * XXX: ideally, dc_attach() should be checking 1591 * vendorid+deviceid together to avoid such 1592 * collisions. 1593 */ 1594 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1595 t->dc_did == DC_DEVICEID_MSMN130) 1596 t++; 1597 return (t); 1598 } 1599 t++; 1600 } 1601 1602 return (NULL); 1603 } 1604 1605 /* 1606 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1607 * IDs against our list and return a device name if we find a match. 1608 * We do a little bit of extra work to identify the exact type of 1609 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1610 * but different revision IDs. The same is true for 98715/98715A 1611 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1612 * cases, the exact chip revision affects driver behavior. 1613 */ 1614 static int 1615 dc_probe(device_t dev) 1616 { 1617 struct dc_type *t; 1618 1619 t = dc_devtype(dev); 1620 1621 if (t != NULL) { 1622 device_set_desc(dev, t->dc_name); 1623 return (BUS_PROBE_DEFAULT); 1624 } 1625 1626 return (ENXIO); 1627 } 1628 1629 static void 1630 dc_apply_fixup(struct dc_softc *sc, int media) 1631 { 1632 struct dc_mediainfo *m; 1633 u_int8_t *p; 1634 int i; 1635 u_int32_t reg; 1636 1637 m = sc->dc_mi; 1638 1639 while (m != NULL) { 1640 if (m->dc_media == media) 1641 break; 1642 m = m->dc_next; 1643 } 1644 1645 if (m == NULL) 1646 return; 1647 1648 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1649 reg = (p[0] | (p[1] << 8)) << 16; 1650 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1651 } 1652 1653 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1654 reg = (p[0] | (p[1] << 8)) << 16; 1655 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1656 } 1657 } 1658 1659 static void 1660 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1661 { 1662 struct dc_mediainfo *m; 1663 1664 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1665 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1666 case DC_SIA_CODE_10BT: 1667 m->dc_media = IFM_10_T; 1668 break; 1669 case DC_SIA_CODE_10BT_FDX: 1670 m->dc_media = IFM_10_T | IFM_FDX; 1671 break; 1672 case DC_SIA_CODE_10B2: 1673 m->dc_media = IFM_10_2; 1674 break; 1675 case DC_SIA_CODE_10B5: 1676 m->dc_media = IFM_10_5; 1677 break; 1678 default: 1679 break; 1680 } 1681 1682 /* 1683 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1684 * Things apparently already work for cards that do 1685 * supply Media Specific Data. 1686 */ 1687 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1688 m->dc_gp_len = 2; 1689 m->dc_gp_ptr = 1690 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1691 } else { 1692 m->dc_gp_len = 2; 1693 m->dc_gp_ptr = 1694 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1695 } 1696 1697 m->dc_next = sc->dc_mi; 1698 sc->dc_mi = m; 1699 1700 sc->dc_pmode = DC_PMODE_SIA; 1701 } 1702 1703 static void 1704 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1705 { 1706 struct dc_mediainfo *m; 1707 1708 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1709 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1710 m->dc_media = IFM_100_TX; 1711 1712 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1713 m->dc_media = IFM_100_TX | IFM_FDX; 1714 1715 m->dc_gp_len = 2; 1716 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1717 1718 m->dc_next = sc->dc_mi; 1719 sc->dc_mi = m; 1720 1721 sc->dc_pmode = DC_PMODE_SYM; 1722 } 1723 1724 static void 1725 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1726 { 1727 struct dc_mediainfo *m; 1728 u_int8_t *p; 1729 1730 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1731 /* We abuse IFM_AUTO to represent MII. */ 1732 m->dc_media = IFM_AUTO; 1733 m->dc_gp_len = l->dc_gpr_len; 1734 1735 p = (u_int8_t *)l; 1736 p += sizeof(struct dc_eblock_mii); 1737 m->dc_gp_ptr = p; 1738 p += 2 * l->dc_gpr_len; 1739 m->dc_reset_len = *p; 1740 p++; 1741 m->dc_reset_ptr = p; 1742 1743 m->dc_next = sc->dc_mi; 1744 sc->dc_mi = m; 1745 } 1746 1747 static void 1748 dc_read_srom(struct dc_softc *sc, int bits) 1749 { 1750 int size; 1751 1752 size = 2 << bits; 1753 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1754 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1755 } 1756 1757 static void 1758 dc_parse_21143_srom(struct dc_softc *sc) 1759 { 1760 struct dc_leaf_hdr *lhdr; 1761 struct dc_eblock_hdr *hdr; 1762 int have_mii, i, loff; 1763 char *ptr; 1764 1765 have_mii = 0; 1766 loff = sc->dc_srom[27]; 1767 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1768 1769 ptr = (char *)lhdr; 1770 ptr += sizeof(struct dc_leaf_hdr) - 1; 1771 /* 1772 * Look if we got a MII media block. 1773 */ 1774 for (i = 0; i < lhdr->dc_mcnt; i++) { 1775 hdr = (struct dc_eblock_hdr *)ptr; 1776 if (hdr->dc_type == DC_EBLOCK_MII) 1777 have_mii++; 1778 1779 ptr += (hdr->dc_len & 0x7F); 1780 ptr++; 1781 } 1782 1783 /* 1784 * Do the same thing again. Only use SIA and SYM media 1785 * blocks if no MII media block is available. 1786 */ 1787 ptr = (char *)lhdr; 1788 ptr += sizeof(struct dc_leaf_hdr) - 1; 1789 for (i = 0; i < lhdr->dc_mcnt; i++) { 1790 hdr = (struct dc_eblock_hdr *)ptr; 1791 switch (hdr->dc_type) { 1792 case DC_EBLOCK_MII: 1793 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1794 break; 1795 case DC_EBLOCK_SIA: 1796 if (! have_mii) 1797 dc_decode_leaf_sia(sc, 1798 (struct dc_eblock_sia *)hdr); 1799 break; 1800 case DC_EBLOCK_SYM: 1801 if (! have_mii) 1802 dc_decode_leaf_sym(sc, 1803 (struct dc_eblock_sym *)hdr); 1804 break; 1805 default: 1806 /* Don't care. Yet. */ 1807 break; 1808 } 1809 ptr += (hdr->dc_len & 0x7F); 1810 ptr++; 1811 } 1812 } 1813 1814 static void 1815 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1816 { 1817 u_int32_t *paddr; 1818 1819 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1820 paddr = arg; 1821 *paddr = segs->ds_addr; 1822 } 1823 1824 /* 1825 * Attach the interface. Allocate softc structures, do ifmedia 1826 * setup and ethernet/BPF attach. 1827 */ 1828 static int 1829 dc_attach(device_t dev) 1830 { 1831 int tmp = 0; 1832 u_char eaddr[ETHER_ADDR_LEN]; 1833 u_int32_t command; 1834 struct dc_softc *sc; 1835 struct ifnet *ifp; 1836 u_int32_t revision; 1837 int error = 0, rid, mac_offset; 1838 int i; 1839 u_int8_t *mac; 1840 1841 sc = device_get_softc(dev); 1842 1843 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1844 MTX_DEF); 1845 1846 /* 1847 * Map control/status registers. 1848 */ 1849 pci_enable_busmaster(dev); 1850 1851 rid = DC_RID; 1852 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1853 1854 if (sc->dc_res == NULL) { 1855 device_printf(dev, "couldn't map ports/memory\n"); 1856 error = ENXIO; 1857 goto fail; 1858 } 1859 1860 sc->dc_btag = rman_get_bustag(sc->dc_res); 1861 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1862 1863 /* Allocate interrupt. */ 1864 rid = 0; 1865 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1866 RF_SHAREABLE | RF_ACTIVE); 1867 1868 if (sc->dc_irq == NULL) { 1869 device_printf(dev, "couldn't map interrupt\n"); 1870 error = ENXIO; 1871 goto fail; 1872 } 1873 1874 /* Need this info to decide on a chip type. */ 1875 sc->dc_info = dc_devtype(dev); 1876 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1877 1878 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1879 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1880 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1881 dc_eeprom_width(sc); 1882 1883 switch (sc->dc_info->dc_did) { 1884 case DC_DEVICEID_21143: 1885 sc->dc_type = DC_TYPE_21143; 1886 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1887 sc->dc_flags |= DC_REDUCED_MII_POLL; 1888 /* Save EEPROM contents so we can parse them later. */ 1889 dc_read_srom(sc, sc->dc_romwidth); 1890 break; 1891 case DC_DEVICEID_DM9009: 1892 case DC_DEVICEID_DM9100: 1893 case DC_DEVICEID_DM9102: 1894 sc->dc_type = DC_TYPE_DM9102; 1895 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1896 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1897 sc->dc_flags |= DC_TX_ALIGN; 1898 sc->dc_pmode = DC_PMODE_MII; 1899 /* Increase the latency timer value. */ 1900 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1901 command &= 0xFFFF00FF; 1902 command |= 0x00008000; 1903 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1904 break; 1905 case DC_DEVICEID_AL981: 1906 sc->dc_type = DC_TYPE_AL981; 1907 sc->dc_flags |= DC_TX_USE_TX_INTR; 1908 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1909 sc->dc_pmode = DC_PMODE_MII; 1910 dc_read_srom(sc, sc->dc_romwidth); 1911 break; 1912 case DC_DEVICEID_AN985: 1913 case DC_DEVICEID_ADM9511: 1914 case DC_DEVICEID_ADM9513: 1915 case DC_DEVICEID_FA511: 1916 case DC_DEVICEID_FE2500: 1917 case DC_DEVICEID_EN2242: 1918 case DC_DEVICEID_HAWKING_PN672TX: 1919 case DC_DEVICEID_3CSOHOB: 1920 case DC_DEVICEID_MSMN120: 1921 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1922 sc->dc_type = DC_TYPE_AN985; 1923 sc->dc_flags |= DC_64BIT_HASH; 1924 sc->dc_flags |= DC_TX_USE_TX_INTR; 1925 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1926 sc->dc_pmode = DC_PMODE_MII; 1927 /* Don't read SROM for - auto-loaded on reset */ 1928 break; 1929 case DC_DEVICEID_98713: 1930 case DC_DEVICEID_98713_CP: 1931 if (revision < DC_REVISION_98713A) { 1932 sc->dc_type = DC_TYPE_98713; 1933 } 1934 if (revision >= DC_REVISION_98713A) { 1935 sc->dc_type = DC_TYPE_98713A; 1936 sc->dc_flags |= DC_21143_NWAY; 1937 } 1938 sc->dc_flags |= DC_REDUCED_MII_POLL; 1939 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1940 break; 1941 case DC_DEVICEID_987x5: 1942 case DC_DEVICEID_EN1217: 1943 /* 1944 * Macronix MX98715AEC-C/D/E parts have only a 1945 * 128-bit hash table. We need to deal with these 1946 * in the same manner as the PNIC II so that we 1947 * get the right number of bits out of the 1948 * CRC routine. 1949 */ 1950 if (revision >= DC_REVISION_98715AEC_C && 1951 revision < DC_REVISION_98725) 1952 sc->dc_flags |= DC_128BIT_HASH; 1953 sc->dc_type = DC_TYPE_987x5; 1954 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1955 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1956 break; 1957 case DC_DEVICEID_98727: 1958 sc->dc_type = DC_TYPE_987x5; 1959 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1960 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1961 break; 1962 case DC_DEVICEID_82C115: 1963 sc->dc_type = DC_TYPE_PNICII; 1964 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1965 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1966 break; 1967 case DC_DEVICEID_82C168: 1968 sc->dc_type = DC_TYPE_PNIC; 1969 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1970 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1971 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1972 if (revision < DC_REVISION_82C169) 1973 sc->dc_pmode = DC_PMODE_SYM; 1974 break; 1975 case DC_DEVICEID_AX88140A: 1976 sc->dc_type = DC_TYPE_ASIX; 1977 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1978 sc->dc_flags |= DC_REDUCED_MII_POLL; 1979 sc->dc_pmode = DC_PMODE_MII; 1980 break; 1981 case DC_DEVICEID_X3201: 1982 sc->dc_type = DC_TYPE_XIRCOM; 1983 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1984 DC_TX_ALIGN; 1985 /* 1986 * We don't actually need to coalesce, but we're doing 1987 * it to obtain a double word aligned buffer. 1988 * The DC_TX_COALESCE flag is required. 1989 */ 1990 sc->dc_pmode = DC_PMODE_MII; 1991 break; 1992 case DC_DEVICEID_RS7112: 1993 sc->dc_type = DC_TYPE_CONEXANT; 1994 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1995 sc->dc_flags |= DC_REDUCED_MII_POLL; 1996 sc->dc_pmode = DC_PMODE_MII; 1997 dc_read_srom(sc, sc->dc_romwidth); 1998 break; 1999 default: 2000 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did); 2001 break; 2002 } 2003 2004 /* Save the cache line size. */ 2005 if (DC_IS_DAVICOM(sc)) 2006 sc->dc_cachesize = 0; 2007 else 2008 sc->dc_cachesize = pci_read_config(dev, 2009 DC_PCI_CFLT, 4) & 0xFF; 2010 2011 /* Reset the adapter. */ 2012 dc_reset(sc); 2013 2014 /* Take 21143 out of snooze mode */ 2015 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2016 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2017 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2018 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2019 } 2020 2021 /* 2022 * Try to learn something about the supported media. 2023 * We know that ASIX and ADMtek and Davicom devices 2024 * will *always* be using MII media, so that's a no-brainer. 2025 * The tricky ones are the Macronix/PNIC II and the 2026 * Intel 21143. 2027 */ 2028 if (DC_IS_INTEL(sc)) 2029 dc_parse_21143_srom(sc); 2030 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2031 if (sc->dc_type == DC_TYPE_98713) 2032 sc->dc_pmode = DC_PMODE_MII; 2033 else 2034 sc->dc_pmode = DC_PMODE_SYM; 2035 } else if (!sc->dc_pmode) 2036 sc->dc_pmode = DC_PMODE_MII; 2037 2038 /* 2039 * Get station address from the EEPROM. 2040 */ 2041 switch(sc->dc_type) { 2042 case DC_TYPE_98713: 2043 case DC_TYPE_98713A: 2044 case DC_TYPE_987x5: 2045 case DC_TYPE_PNICII: 2046 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2047 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2048 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2049 break; 2050 case DC_TYPE_PNIC: 2051 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2052 break; 2053 case DC_TYPE_DM9102: 2054 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2055 #ifdef __sparc64__ 2056 /* 2057 * If this is an onboard dc(4) the station address read from 2058 * the EEPROM is all zero and we have to get it from the fcode. 2059 */ 2060 for (i = 0; i < ETHER_ADDR_LEN; i++) 2061 if (eaddr[i] != 0x00) 2062 break; 2063 if (i >= ETHER_ADDR_LEN) 2064 OF_getetheraddr(dev, eaddr); 2065 #endif 2066 break; 2067 case DC_TYPE_21143: 2068 case DC_TYPE_ASIX: 2069 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2070 break; 2071 case DC_TYPE_AL981: 2072 case DC_TYPE_AN985: 2073 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2074 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2075 break; 2076 case DC_TYPE_CONEXANT: 2077 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2078 ETHER_ADDR_LEN); 2079 break; 2080 case DC_TYPE_XIRCOM: 2081 /* The MAC comes from the CIS. */ 2082 mac = pci_get_ether(dev); 2083 if (!mac) { 2084 device_printf(dev, "No station address in CIS!\n"); 2085 error = ENXIO; 2086 goto fail; 2087 } 2088 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2089 break; 2090 default: 2091 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2092 break; 2093 } 2094 2095 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2096 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2097 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2098 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2099 if (error) { 2100 device_printf(dev, "failed to allocate busdma tag\n"); 2101 error = ENXIO; 2102 goto fail; 2103 } 2104 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2105 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2106 if (error) { 2107 device_printf(dev, "failed to allocate DMA safe memory\n"); 2108 error = ENXIO; 2109 goto fail; 2110 } 2111 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2112 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2113 BUS_DMA_NOWAIT); 2114 if (error) { 2115 device_printf(dev, "cannot get address of the descriptors\n"); 2116 error = ENXIO; 2117 goto fail; 2118 } 2119 2120 /* 2121 * Allocate a busdma tag and DMA safe memory for the multicast 2122 * setup frame. 2123 */ 2124 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2125 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2126 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2127 if (error) { 2128 device_printf(dev, "failed to allocate busdma tag\n"); 2129 error = ENXIO; 2130 goto fail; 2131 } 2132 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2133 BUS_DMA_NOWAIT, &sc->dc_smap); 2134 if (error) { 2135 device_printf(dev, "failed to allocate DMA safe memory\n"); 2136 error = ENXIO; 2137 goto fail; 2138 } 2139 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2140 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2141 if (error) { 2142 device_printf(dev, "cannot get address of the descriptors\n"); 2143 error = ENXIO; 2144 goto fail; 2145 } 2146 2147 /* Allocate a busdma tag for mbufs. */ 2148 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 2149 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, DC_TX_LIST_CNT, MCLBYTES, 2150 0, NULL, NULL, &sc->dc_mtag); 2151 if (error) { 2152 device_printf(dev, "failed to allocate busdma tag\n"); 2153 error = ENXIO; 2154 goto fail; 2155 } 2156 2157 /* Create the TX/RX busdma maps. */ 2158 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2159 error = bus_dmamap_create(sc->dc_mtag, 0, 2160 &sc->dc_cdata.dc_tx_map[i]); 2161 if (error) { 2162 device_printf(dev, "failed to init TX ring\n"); 2163 error = ENXIO; 2164 goto fail; 2165 } 2166 } 2167 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2168 error = bus_dmamap_create(sc->dc_mtag, 0, 2169 &sc->dc_cdata.dc_rx_map[i]); 2170 if (error) { 2171 device_printf(dev, "failed to init RX ring\n"); 2172 error = ENXIO; 2173 goto fail; 2174 } 2175 } 2176 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2177 if (error) { 2178 device_printf(dev, "failed to init RX ring\n"); 2179 error = ENXIO; 2180 goto fail; 2181 } 2182 2183 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2184 if (ifp == NULL) { 2185 device_printf(dev, "can not if_alloc()\n"); 2186 error = ENOSPC; 2187 goto fail; 2188 } 2189 ifp->if_softc = sc; 2190 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2191 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2192 ifp->if_mtu = ETHERMTU; 2193 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2194 ifp->if_ioctl = dc_ioctl; 2195 ifp->if_start = dc_start; 2196 ifp->if_watchdog = dc_watchdog; 2197 ifp->if_init = dc_init; 2198 ifp->if_baudrate = 10000000; 2199 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2200 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2201 IFQ_SET_READY(&ifp->if_snd); 2202 2203 /* 2204 * Do MII setup. If this is a 21143, check for a PHY on the 2205 * MII bus after applying any necessary fixups to twiddle the 2206 * GPIO bits. If we don't end up finding a PHY, restore the 2207 * old selection (SIA only or SIA/SYM) and attach the dcphy 2208 * driver instead. 2209 */ 2210 if (DC_IS_INTEL(sc)) { 2211 dc_apply_fixup(sc, IFM_AUTO); 2212 tmp = sc->dc_pmode; 2213 sc->dc_pmode = DC_PMODE_MII; 2214 } 2215 2216 /* 2217 * Setup General Purpose port mode and data so the tulip can talk 2218 * to the MII. This needs to be done before mii_phy_probe so that 2219 * we can actually see them. 2220 */ 2221 if (DC_IS_XIRCOM(sc)) { 2222 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2223 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2224 DELAY(10); 2225 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2226 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2227 DELAY(10); 2228 } 2229 2230 error = mii_phy_probe(dev, &sc->dc_miibus, 2231 dc_ifmedia_upd, dc_ifmedia_sts); 2232 2233 if (error && DC_IS_INTEL(sc)) { 2234 sc->dc_pmode = tmp; 2235 if (sc->dc_pmode != DC_PMODE_SIA) 2236 sc->dc_pmode = DC_PMODE_SYM; 2237 sc->dc_flags |= DC_21143_NWAY; 2238 mii_phy_probe(dev, &sc->dc_miibus, 2239 dc_ifmedia_upd, dc_ifmedia_sts); 2240 /* 2241 * For non-MII cards, we need to have the 21143 2242 * drive the LEDs. Except there are some systems 2243 * like the NEC VersaPro NoteBook PC which have no 2244 * LEDs, and twiddling these bits has adverse effects 2245 * on them. (I.e. you suddenly can't get a link.) 2246 */ 2247 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2248 sc->dc_flags |= DC_TULIP_LEDS; 2249 error = 0; 2250 } 2251 2252 if (error) { 2253 device_printf(dev, "MII without any PHY!\n"); 2254 goto fail; 2255 } 2256 2257 if (DC_IS_ADMTEK(sc)) { 2258 /* 2259 * Set automatic TX underrun recovery for the ADMtek chips 2260 */ 2261 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2262 } 2263 2264 /* 2265 * Tell the upper layer(s) we support long frames. 2266 */ 2267 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2268 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2269 ifp->if_capenable = ifp->if_capabilities; 2270 #ifdef DEVICE_POLLING 2271 ifp->if_capabilities |= IFCAP_POLLING; 2272 #endif 2273 2274 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2275 2276 #ifdef SRM_MEDIA 2277 sc->dc_srm_media = 0; 2278 2279 /* Remember the SRM console media setting */ 2280 if (DC_IS_INTEL(sc)) { 2281 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2282 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2283 switch ((command >> 8) & 0xff) { 2284 case 3: 2285 sc->dc_srm_media = IFM_10_T; 2286 break; 2287 case 4: 2288 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2289 break; 2290 case 5: 2291 sc->dc_srm_media = IFM_100_TX; 2292 break; 2293 case 6: 2294 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2295 break; 2296 } 2297 if (sc->dc_srm_media) 2298 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2299 } 2300 #endif 2301 2302 /* 2303 * Call MI attach routine. 2304 */ 2305 ether_ifattach(ifp, eaddr); 2306 2307 /* Hook interrupt last to avoid having to lock softc */ 2308 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2309 dc_intr, sc, &sc->dc_intrhand); 2310 2311 if (error) { 2312 device_printf(dev, "couldn't set up irq\n"); 2313 ether_ifdetach(ifp); 2314 goto fail; 2315 } 2316 2317 fail: 2318 if (error) 2319 dc_detach(dev); 2320 return (error); 2321 } 2322 2323 /* 2324 * Shutdown hardware and free up resources. This can be called any 2325 * time after the mutex has been initialized. It is called in both 2326 * the error case in attach and the normal detach case so it needs 2327 * to be careful about only freeing resources that have actually been 2328 * allocated. 2329 */ 2330 static int 2331 dc_detach(device_t dev) 2332 { 2333 struct dc_softc *sc; 2334 struct ifnet *ifp; 2335 struct dc_mediainfo *m; 2336 int i; 2337 2338 sc = device_get_softc(dev); 2339 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2340 2341 ifp = sc->dc_ifp; 2342 2343 #ifdef DEVICE_POLLING 2344 if (ifp->if_capenable & IFCAP_POLLING) 2345 ether_poll_deregister(ifp); 2346 #endif 2347 2348 /* These should only be active if attach succeeded */ 2349 if (device_is_attached(dev)) { 2350 DC_LOCK(sc); 2351 dc_stop(sc); 2352 DC_UNLOCK(sc); 2353 callout_drain(&sc->dc_stat_ch); 2354 ether_ifdetach(ifp); 2355 } 2356 if (ifp) 2357 if_free(ifp); 2358 if (sc->dc_miibus) 2359 device_delete_child(dev, sc->dc_miibus); 2360 bus_generic_detach(dev); 2361 2362 if (sc->dc_intrhand) 2363 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2364 if (sc->dc_irq) 2365 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2366 if (sc->dc_res) 2367 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2368 2369 if (sc->dc_cdata.dc_sbuf != NULL) 2370 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2371 if (sc->dc_ldata != NULL) 2372 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2373 if (sc->dc_mtag) { 2374 for (i = 0; i < DC_TX_LIST_CNT; i++) 2375 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2376 bus_dmamap_destroy(sc->dc_mtag, 2377 sc->dc_cdata.dc_tx_map[i]); 2378 for (i = 0; i < DC_RX_LIST_CNT; i++) 2379 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2380 bus_dmamap_destroy(sc->dc_mtag, 2381 sc->dc_cdata.dc_rx_map[i]); 2382 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2383 } 2384 if (sc->dc_stag) 2385 bus_dma_tag_destroy(sc->dc_stag); 2386 if (sc->dc_mtag) 2387 bus_dma_tag_destroy(sc->dc_mtag); 2388 if (sc->dc_ltag) 2389 bus_dma_tag_destroy(sc->dc_ltag); 2390 2391 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2392 2393 while (sc->dc_mi != NULL) { 2394 m = sc->dc_mi->dc_next; 2395 free(sc->dc_mi, M_DEVBUF); 2396 sc->dc_mi = m; 2397 } 2398 free(sc->dc_srom, M_DEVBUF); 2399 2400 mtx_destroy(&sc->dc_mtx); 2401 2402 return (0); 2403 } 2404 2405 /* 2406 * Initialize the transmit descriptors. 2407 */ 2408 static int 2409 dc_list_tx_init(struct dc_softc *sc) 2410 { 2411 struct dc_chain_data *cd; 2412 struct dc_list_data *ld; 2413 int i, nexti; 2414 2415 cd = &sc->dc_cdata; 2416 ld = sc->dc_ldata; 2417 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2418 if (i == DC_TX_LIST_CNT - 1) 2419 nexti = 0; 2420 else 2421 nexti = i + 1; 2422 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2423 cd->dc_tx_chain[i] = NULL; 2424 ld->dc_tx_list[i].dc_data = 0; 2425 ld->dc_tx_list[i].dc_ctl = 0; 2426 } 2427 2428 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2429 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2430 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2431 return (0); 2432 } 2433 2434 2435 /* 2436 * Initialize the RX descriptors and allocate mbufs for them. Note that 2437 * we arrange the descriptors in a closed ring, so that the last descriptor 2438 * points back to the first. 2439 */ 2440 static int 2441 dc_list_rx_init(struct dc_softc *sc) 2442 { 2443 struct dc_chain_data *cd; 2444 struct dc_list_data *ld; 2445 int i, nexti; 2446 2447 cd = &sc->dc_cdata; 2448 ld = sc->dc_ldata; 2449 2450 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2451 if (dc_newbuf(sc, i, 1) != 0) 2452 return (ENOBUFS); 2453 if (i == DC_RX_LIST_CNT - 1) 2454 nexti = 0; 2455 else 2456 nexti = i + 1; 2457 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2458 } 2459 2460 cd->dc_rx_prod = 0; 2461 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2462 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2463 return (0); 2464 } 2465 2466 static void 2467 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2468 void *arg; 2469 bus_dma_segment_t *segs; 2470 int nseg; 2471 bus_size_t mapsize; 2472 int error; 2473 { 2474 struct dc_softc *sc; 2475 struct dc_desc *c; 2476 2477 sc = arg; 2478 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2479 if (error) { 2480 sc->dc_cdata.dc_rx_err = error; 2481 return; 2482 } 2483 2484 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2485 sc->dc_cdata.dc_rx_err = 0; 2486 c->dc_data = htole32(segs->ds_addr); 2487 } 2488 2489 /* 2490 * Initialize an RX descriptor and attach an MBUF cluster. 2491 */ 2492 static int 2493 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2494 { 2495 struct mbuf *m_new; 2496 bus_dmamap_t tmp; 2497 int error; 2498 2499 if (alloc) { 2500 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2501 if (m_new == NULL) 2502 return (ENOBUFS); 2503 } else { 2504 m_new = sc->dc_cdata.dc_rx_chain[i]; 2505 m_new->m_data = m_new->m_ext.ext_buf; 2506 } 2507 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2508 m_adj(m_new, sizeof(u_int64_t)); 2509 2510 /* 2511 * If this is a PNIC chip, zero the buffer. This is part 2512 * of the workaround for the receive bug in the 82c168 and 2513 * 82c169 chips. 2514 */ 2515 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2516 bzero(mtod(m_new, char *), m_new->m_len); 2517 2518 /* No need to remap the mbuf if we're reusing it. */ 2519 if (alloc) { 2520 sc->dc_cdata.dc_rx_cur = i; 2521 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2522 m_new, dc_dma_map_rxbuf, sc, 0); 2523 if (error) { 2524 m_freem(m_new); 2525 return (error); 2526 } 2527 if (sc->dc_cdata.dc_rx_err != 0) { 2528 m_freem(m_new); 2529 return (sc->dc_cdata.dc_rx_err); 2530 } 2531 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2532 tmp = sc->dc_cdata.dc_rx_map[i]; 2533 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2534 sc->dc_sparemap = tmp; 2535 sc->dc_cdata.dc_rx_chain[i] = m_new; 2536 } 2537 2538 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2539 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2540 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2541 BUS_DMASYNC_PREREAD); 2542 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2543 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2544 return (0); 2545 } 2546 2547 /* 2548 * Grrrrr. 2549 * The PNIC chip has a terrible bug in it that manifests itself during 2550 * periods of heavy activity. The exact mode of failure if difficult to 2551 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2552 * will happen on slow machines. The bug is that sometimes instead of 2553 * uploading one complete frame during reception, it uploads what looks 2554 * like the entire contents of its FIFO memory. The frame we want is at 2555 * the end of the whole mess, but we never know exactly how much data has 2556 * been uploaded, so salvaging the frame is hard. 2557 * 2558 * There is only one way to do it reliably, and it's disgusting. 2559 * Here's what we know: 2560 * 2561 * - We know there will always be somewhere between one and three extra 2562 * descriptors uploaded. 2563 * 2564 * - We know the desired received frame will always be at the end of the 2565 * total data upload. 2566 * 2567 * - We know the size of the desired received frame because it will be 2568 * provided in the length field of the status word in the last descriptor. 2569 * 2570 * Here's what we do: 2571 * 2572 * - When we allocate buffers for the receive ring, we bzero() them. 2573 * This means that we know that the buffer contents should be all 2574 * zeros, except for data uploaded by the chip. 2575 * 2576 * - We also force the PNIC chip to upload frames that include the 2577 * ethernet CRC at the end. 2578 * 2579 * - We gather all of the bogus frame data into a single buffer. 2580 * 2581 * - We then position a pointer at the end of this buffer and scan 2582 * backwards until we encounter the first non-zero byte of data. 2583 * This is the end of the received frame. We know we will encounter 2584 * some data at the end of the frame because the CRC will always be 2585 * there, so even if the sender transmits a packet of all zeros, 2586 * we won't be fooled. 2587 * 2588 * - We know the size of the actual received frame, so we subtract 2589 * that value from the current pointer location. This brings us 2590 * to the start of the actual received packet. 2591 * 2592 * - We copy this into an mbuf and pass it on, along with the actual 2593 * frame length. 2594 * 2595 * The performance hit is tremendous, but it beats dropping frames all 2596 * the time. 2597 */ 2598 2599 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2600 static void 2601 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2602 { 2603 struct dc_desc *cur_rx; 2604 struct dc_desc *c = NULL; 2605 struct mbuf *m = NULL; 2606 unsigned char *ptr; 2607 int i, total_len; 2608 u_int32_t rxstat = 0; 2609 2610 i = sc->dc_pnic_rx_bug_save; 2611 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2612 ptr = sc->dc_pnic_rx_buf; 2613 bzero(ptr, DC_RXLEN * 5); 2614 2615 /* Copy all the bytes from the bogus buffers. */ 2616 while (1) { 2617 c = &sc->dc_ldata->dc_rx_list[i]; 2618 rxstat = le32toh(c->dc_status); 2619 m = sc->dc_cdata.dc_rx_chain[i]; 2620 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2621 ptr += DC_RXLEN; 2622 /* If this is the last buffer, break out. */ 2623 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2624 break; 2625 dc_newbuf(sc, i, 0); 2626 DC_INC(i, DC_RX_LIST_CNT); 2627 } 2628 2629 /* Find the length of the actual receive frame. */ 2630 total_len = DC_RXBYTES(rxstat); 2631 2632 /* Scan backwards until we hit a non-zero byte. */ 2633 while (*ptr == 0x00) 2634 ptr--; 2635 2636 /* Round off. */ 2637 if ((uintptr_t)(ptr) & 0x3) 2638 ptr -= 1; 2639 2640 /* Now find the start of the frame. */ 2641 ptr -= total_len; 2642 if (ptr < sc->dc_pnic_rx_buf) 2643 ptr = sc->dc_pnic_rx_buf; 2644 2645 /* 2646 * Now copy the salvaged frame to the last mbuf and fake up 2647 * the status word to make it look like a successful 2648 * frame reception. 2649 */ 2650 dc_newbuf(sc, i, 0); 2651 bcopy(ptr, mtod(m, char *), total_len); 2652 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2653 } 2654 2655 /* 2656 * This routine searches the RX ring for dirty descriptors in the 2657 * event that the rxeof routine falls out of sync with the chip's 2658 * current descriptor pointer. This may happen sometimes as a result 2659 * of a "no RX buffer available" condition that happens when the chip 2660 * consumes all of the RX buffers before the driver has a chance to 2661 * process the RX ring. This routine may need to be called more than 2662 * once to bring the driver back in sync with the chip, however we 2663 * should still be getting RX DONE interrupts to drive the search 2664 * for new packets in the RX ring, so we should catch up eventually. 2665 */ 2666 static int 2667 dc_rx_resync(struct dc_softc *sc) 2668 { 2669 struct dc_desc *cur_rx; 2670 int i, pos; 2671 2672 pos = sc->dc_cdata.dc_rx_prod; 2673 2674 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2675 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2676 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2677 break; 2678 DC_INC(pos, DC_RX_LIST_CNT); 2679 } 2680 2681 /* If the ring really is empty, then just return. */ 2682 if (i == DC_RX_LIST_CNT) 2683 return (0); 2684 2685 /* We've fallen behing the chip: catch it. */ 2686 sc->dc_cdata.dc_rx_prod = pos; 2687 2688 return (EAGAIN); 2689 } 2690 2691 /* 2692 * A frame has been uploaded: pass the resulting mbuf chain up to 2693 * the higher level protocols. 2694 */ 2695 static void 2696 dc_rxeof(struct dc_softc *sc) 2697 { 2698 struct mbuf *m; 2699 struct ifnet *ifp; 2700 struct dc_desc *cur_rx; 2701 int i, total_len = 0; 2702 u_int32_t rxstat; 2703 2704 DC_LOCK_ASSERT(sc); 2705 2706 ifp = sc->dc_ifp; 2707 i = sc->dc_cdata.dc_rx_prod; 2708 2709 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2710 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2711 DC_RXSTAT_OWN)) { 2712 #ifdef DEVICE_POLLING 2713 if (ifp->if_capenable & IFCAP_POLLING) { 2714 if (sc->rxcycles <= 0) 2715 break; 2716 sc->rxcycles--; 2717 } 2718 #endif 2719 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2720 rxstat = le32toh(cur_rx->dc_status); 2721 m = sc->dc_cdata.dc_rx_chain[i]; 2722 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2723 BUS_DMASYNC_POSTREAD); 2724 total_len = DC_RXBYTES(rxstat); 2725 2726 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2727 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2728 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2729 sc->dc_pnic_rx_bug_save = i; 2730 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2731 DC_INC(i, DC_RX_LIST_CNT); 2732 continue; 2733 } 2734 dc_pnic_rx_bug_war(sc, i); 2735 rxstat = le32toh(cur_rx->dc_status); 2736 total_len = DC_RXBYTES(rxstat); 2737 } 2738 } 2739 2740 /* 2741 * If an error occurs, update stats, clear the 2742 * status word and leave the mbuf cluster in place: 2743 * it should simply get re-used next time this descriptor 2744 * comes up in the ring. However, don't report long 2745 * frames as errors since they could be vlans. 2746 */ 2747 if ((rxstat & DC_RXSTAT_RXERR)) { 2748 if (!(rxstat & DC_RXSTAT_GIANT) || 2749 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2750 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2751 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2752 ifp->if_ierrors++; 2753 if (rxstat & DC_RXSTAT_COLLSEEN) 2754 ifp->if_collisions++; 2755 dc_newbuf(sc, i, 0); 2756 if (rxstat & DC_RXSTAT_CRCERR) { 2757 DC_INC(i, DC_RX_LIST_CNT); 2758 continue; 2759 } else { 2760 dc_init_locked(sc); 2761 return; 2762 } 2763 } 2764 } 2765 2766 /* No errors; receive the packet. */ 2767 total_len -= ETHER_CRC_LEN; 2768 #ifdef __i386__ 2769 /* 2770 * On the x86 we do not have alignment problems, so try to 2771 * allocate a new buffer for the receive ring, and pass up 2772 * the one where the packet is already, saving the expensive 2773 * copy done in m_devget(). 2774 * If we are on an architecture with alignment problems, or 2775 * if the allocation fails, then use m_devget and leave the 2776 * existing buffer in the receive ring. 2777 */ 2778 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2779 m->m_pkthdr.rcvif = ifp; 2780 m->m_pkthdr.len = m->m_len = total_len; 2781 DC_INC(i, DC_RX_LIST_CNT); 2782 } else 2783 #endif 2784 { 2785 struct mbuf *m0; 2786 2787 m0 = m_devget(mtod(m, char *), total_len, 2788 ETHER_ALIGN, ifp, NULL); 2789 dc_newbuf(sc, i, 0); 2790 DC_INC(i, DC_RX_LIST_CNT); 2791 if (m0 == NULL) { 2792 ifp->if_ierrors++; 2793 continue; 2794 } 2795 m = m0; 2796 } 2797 2798 ifp->if_ipackets++; 2799 DC_UNLOCK(sc); 2800 (*ifp->if_input)(ifp, m); 2801 DC_LOCK(sc); 2802 } 2803 2804 sc->dc_cdata.dc_rx_prod = i; 2805 } 2806 2807 /* 2808 * A frame was downloaded to the chip. It's safe for us to clean up 2809 * the list buffers. 2810 */ 2811 2812 static void 2813 dc_txeof(struct dc_softc *sc) 2814 { 2815 struct dc_desc *cur_tx = NULL; 2816 struct ifnet *ifp; 2817 int idx; 2818 u_int32_t ctl, txstat; 2819 2820 ifp = sc->dc_ifp; 2821 2822 /* 2823 * Go through our tx list and free mbufs for those 2824 * frames that have been transmitted. 2825 */ 2826 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2827 idx = sc->dc_cdata.dc_tx_cons; 2828 while (idx != sc->dc_cdata.dc_tx_prod) { 2829 2830 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2831 txstat = le32toh(cur_tx->dc_status); 2832 ctl = le32toh(cur_tx->dc_ctl); 2833 2834 if (txstat & DC_TXSTAT_OWN) 2835 break; 2836 2837 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2838 if (ctl & DC_TXCTL_SETUP) { 2839 /* 2840 * Yes, the PNIC is so brain damaged 2841 * that it will sometimes generate a TX 2842 * underrun error while DMAing the RX 2843 * filter setup frame. If we detect this, 2844 * we have to send the setup frame again, 2845 * or else the filter won't be programmed 2846 * correctly. 2847 */ 2848 if (DC_IS_PNIC(sc)) { 2849 if (txstat & DC_TXSTAT_ERRSUM) 2850 dc_setfilt(sc); 2851 } 2852 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2853 } 2854 sc->dc_cdata.dc_tx_cnt--; 2855 DC_INC(idx, DC_TX_LIST_CNT); 2856 continue; 2857 } 2858 2859 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2860 /* 2861 * XXX: Why does my Xircom taunt me so? 2862 * For some reason it likes setting the CARRLOST flag 2863 * even when the carrier is there. wtf?!? 2864 * Who knows, but Conexant chips have the 2865 * same problem. Maybe they took lessons 2866 * from Xircom. 2867 */ 2868 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2869 sc->dc_pmode == DC_PMODE_MII && 2870 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2871 DC_TXSTAT_NOCARRIER))) 2872 txstat &= ~DC_TXSTAT_ERRSUM; 2873 } else { 2874 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2875 sc->dc_pmode == DC_PMODE_MII && 2876 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2877 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2878 txstat &= ~DC_TXSTAT_ERRSUM; 2879 } 2880 2881 if (txstat & DC_TXSTAT_ERRSUM) { 2882 ifp->if_oerrors++; 2883 if (txstat & DC_TXSTAT_EXCESSCOLL) 2884 ifp->if_collisions++; 2885 if (txstat & DC_TXSTAT_LATECOLL) 2886 ifp->if_collisions++; 2887 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2888 dc_init_locked(sc); 2889 return; 2890 } 2891 } 2892 2893 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2894 2895 ifp->if_opackets++; 2896 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2897 bus_dmamap_sync(sc->dc_mtag, 2898 sc->dc_cdata.dc_tx_map[idx], 2899 BUS_DMASYNC_POSTWRITE); 2900 bus_dmamap_unload(sc->dc_mtag, 2901 sc->dc_cdata.dc_tx_map[idx]); 2902 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2903 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2904 } 2905 2906 sc->dc_cdata.dc_tx_cnt--; 2907 DC_INC(idx, DC_TX_LIST_CNT); 2908 } 2909 2910 if (idx != sc->dc_cdata.dc_tx_cons) { 2911 /* Some buffers have been freed. */ 2912 sc->dc_cdata.dc_tx_cons = idx; 2913 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2914 } 2915 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2916 } 2917 2918 static void 2919 dc_tick(void *xsc) 2920 { 2921 struct dc_softc *sc; 2922 struct mii_data *mii; 2923 struct ifnet *ifp; 2924 u_int32_t r; 2925 2926 sc = xsc; 2927 DC_LOCK_ASSERT(sc); 2928 ifp = sc->dc_ifp; 2929 mii = device_get_softc(sc->dc_miibus); 2930 2931 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2932 if (sc->dc_flags & DC_21143_NWAY) { 2933 r = CSR_READ_4(sc, DC_10BTSTAT); 2934 if (IFM_SUBTYPE(mii->mii_media_active) == 2935 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2936 sc->dc_link = 0; 2937 mii_mediachg(mii); 2938 } 2939 if (IFM_SUBTYPE(mii->mii_media_active) == 2940 IFM_10_T && (r & DC_TSTAT_LS10)) { 2941 sc->dc_link = 0; 2942 mii_mediachg(mii); 2943 } 2944 if (sc->dc_link == 0) 2945 mii_tick(mii); 2946 } else { 2947 r = CSR_READ_4(sc, DC_ISR); 2948 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2949 sc->dc_cdata.dc_tx_cnt == 0) { 2950 mii_tick(mii); 2951 if (!(mii->mii_media_status & IFM_ACTIVE)) 2952 sc->dc_link = 0; 2953 } 2954 } 2955 } else 2956 mii_tick(mii); 2957 2958 /* 2959 * When the init routine completes, we expect to be able to send 2960 * packets right away, and in fact the network code will send a 2961 * gratuitous ARP the moment the init routine marks the interface 2962 * as running. However, even though the MAC may have been initialized, 2963 * there may be a delay of a few seconds before the PHY completes 2964 * autonegotiation and the link is brought up. Any transmissions 2965 * made during that delay will be lost. Dealing with this is tricky: 2966 * we can't just pause in the init routine while waiting for the 2967 * PHY to come ready since that would bring the whole system to 2968 * a screeching halt for several seconds. 2969 * 2970 * What we do here is prevent the TX start routine from sending 2971 * any packets until a link has been established. After the 2972 * interface has been initialized, the tick routine will poll 2973 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2974 * that time, packets will stay in the send queue, and once the 2975 * link comes up, they will be flushed out to the wire. 2976 */ 2977 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2978 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2979 sc->dc_link++; 2980 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2981 dc_start_locked(ifp); 2982 } 2983 2984 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2985 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2986 else 2987 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2988 } 2989 2990 /* 2991 * A transmit underrun has occurred. Back off the transmit threshold, 2992 * or switch to store and forward mode if we have to. 2993 */ 2994 static void 2995 dc_tx_underrun(struct dc_softc *sc) 2996 { 2997 u_int32_t isr; 2998 int i; 2999 3000 if (DC_IS_DAVICOM(sc)) 3001 dc_init_locked(sc); 3002 3003 if (DC_IS_INTEL(sc)) { 3004 /* 3005 * The real 21143 requires that the transmitter be idle 3006 * in order to change the transmit threshold or store 3007 * and forward state. 3008 */ 3009 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3010 3011 for (i = 0; i < DC_TIMEOUT; i++) { 3012 isr = CSR_READ_4(sc, DC_ISR); 3013 if (isr & DC_ISR_TX_IDLE) 3014 break; 3015 DELAY(10); 3016 } 3017 if (i == DC_TIMEOUT) { 3018 if_printf(sc->dc_ifp, 3019 "failed to force tx to idle state\n"); 3020 dc_init_locked(sc); 3021 } 3022 } 3023 3024 if_printf(sc->dc_ifp, "TX underrun -- "); 3025 sc->dc_txthresh += DC_TXTHRESH_INC; 3026 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3027 printf("using store and forward mode\n"); 3028 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3029 } else { 3030 printf("increasing TX threshold\n"); 3031 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3032 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3033 } 3034 3035 if (DC_IS_INTEL(sc)) 3036 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3037 } 3038 3039 #ifdef DEVICE_POLLING 3040 static poll_handler_t dc_poll; 3041 3042 static void 3043 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3044 { 3045 struct dc_softc *sc = ifp->if_softc; 3046 3047 DC_LOCK(sc); 3048 3049 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3050 DC_UNLOCK(sc); 3051 return; 3052 } 3053 3054 sc->rxcycles = count; 3055 dc_rxeof(sc); 3056 dc_txeof(sc); 3057 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3058 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3059 dc_start_locked(ifp); 3060 3061 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3062 u_int32_t status; 3063 3064 status = CSR_READ_4(sc, DC_ISR); 3065 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3066 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3067 DC_ISR_BUS_ERR); 3068 if (!status) { 3069 DC_UNLOCK(sc); 3070 return; 3071 } 3072 /* ack what we have */ 3073 CSR_WRITE_4(sc, DC_ISR, status); 3074 3075 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3076 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3077 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3078 3079 if (dc_rx_resync(sc)) 3080 dc_rxeof(sc); 3081 } 3082 /* restart transmit unit if necessary */ 3083 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3084 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3085 3086 if (status & DC_ISR_TX_UNDERRUN) 3087 dc_tx_underrun(sc); 3088 3089 if (status & DC_ISR_BUS_ERR) { 3090 if_printf(ifp, "dc_poll: bus error\n"); 3091 dc_reset(sc); 3092 dc_init_locked(sc); 3093 } 3094 } 3095 DC_UNLOCK(sc); 3096 } 3097 #endif /* DEVICE_POLLING */ 3098 3099 static void 3100 dc_intr(void *arg) 3101 { 3102 struct dc_softc *sc; 3103 struct ifnet *ifp; 3104 u_int32_t status; 3105 3106 sc = arg; 3107 3108 if (sc->suspended) 3109 return; 3110 3111 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3112 return; 3113 3114 DC_LOCK(sc); 3115 ifp = sc->dc_ifp; 3116 #ifdef DEVICE_POLLING 3117 if (ifp->if_capenable & IFCAP_POLLING) { 3118 DC_UNLOCK(sc); 3119 return; 3120 } 3121 #endif 3122 3123 /* Suppress unwanted interrupts */ 3124 if (!(ifp->if_flags & IFF_UP)) { 3125 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3126 dc_stop(sc); 3127 DC_UNLOCK(sc); 3128 return; 3129 } 3130 3131 /* Disable interrupts. */ 3132 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3133 3134 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3135 && status != 0xFFFFFFFF) { 3136 3137 CSR_WRITE_4(sc, DC_ISR, status); 3138 3139 if (status & DC_ISR_RX_OK) { 3140 int curpkts; 3141 curpkts = ifp->if_ipackets; 3142 dc_rxeof(sc); 3143 if (curpkts == ifp->if_ipackets) { 3144 while (dc_rx_resync(sc)) 3145 dc_rxeof(sc); 3146 } 3147 } 3148 3149 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3150 dc_txeof(sc); 3151 3152 if (status & DC_ISR_TX_IDLE) { 3153 dc_txeof(sc); 3154 if (sc->dc_cdata.dc_tx_cnt) { 3155 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3156 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3157 } 3158 } 3159 3160 if (status & DC_ISR_TX_UNDERRUN) 3161 dc_tx_underrun(sc); 3162 3163 if ((status & DC_ISR_RX_WATDOGTIMEO) 3164 || (status & DC_ISR_RX_NOBUF)) { 3165 int curpkts; 3166 curpkts = ifp->if_ipackets; 3167 dc_rxeof(sc); 3168 if (curpkts == ifp->if_ipackets) { 3169 while (dc_rx_resync(sc)) 3170 dc_rxeof(sc); 3171 } 3172 } 3173 3174 if (status & DC_ISR_BUS_ERR) { 3175 dc_reset(sc); 3176 dc_init_locked(sc); 3177 } 3178 } 3179 3180 /* Re-enable interrupts. */ 3181 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3182 3183 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3184 dc_start_locked(ifp); 3185 3186 DC_UNLOCK(sc); 3187 } 3188 3189 static void 3190 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3191 void *arg; 3192 bus_dma_segment_t *segs; 3193 int nseg; 3194 bus_size_t mapsize; 3195 int error; 3196 { 3197 struct dc_softc *sc; 3198 struct dc_desc *f; 3199 int cur, first, frag, i; 3200 3201 sc = arg; 3202 if (error) { 3203 sc->dc_cdata.dc_tx_err = error; 3204 return; 3205 } 3206 3207 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3208 for (i = 0; i < nseg; i++) { 3209 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3210 (frag == (DC_TX_LIST_CNT - 1)) && 3211 (first != sc->dc_cdata.dc_tx_first)) { 3212 bus_dmamap_unload(sc->dc_mtag, 3213 sc->dc_cdata.dc_tx_map[first]); 3214 sc->dc_cdata.dc_tx_err = ENOBUFS; 3215 return; 3216 } 3217 3218 f = &sc->dc_ldata->dc_tx_list[frag]; 3219 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3220 if (i == 0) { 3221 f->dc_status = 0; 3222 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3223 } else 3224 f->dc_status = htole32(DC_TXSTAT_OWN); 3225 f->dc_data = htole32(segs[i].ds_addr); 3226 cur = frag; 3227 DC_INC(frag, DC_TX_LIST_CNT); 3228 } 3229 3230 sc->dc_cdata.dc_tx_err = 0; 3231 sc->dc_cdata.dc_tx_prod = frag; 3232 sc->dc_cdata.dc_tx_cnt += nseg; 3233 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3234 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3235 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3236 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3237 htole32(DC_TXCTL_FINT); 3238 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3239 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3240 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3241 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3242 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3243 } 3244 3245 /* 3246 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3247 * pointers to the fragment pointers. 3248 */ 3249 static int 3250 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3251 { 3252 struct mbuf *m; 3253 int error, idx, chainlen = 0; 3254 3255 /* 3256 * If there's no way we can send any packets, return now. 3257 */ 3258 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3259 return (ENOBUFS); 3260 3261 /* 3262 * Count the number of frags in this chain to see if 3263 * we need to m_defrag. Since the descriptor list is shared 3264 * by all packets, we'll m_defrag long chains so that they 3265 * do not use up the entire list, even if they would fit. 3266 */ 3267 for (m = *m_head; m != NULL; m = m->m_next) 3268 chainlen++; 3269 3270 if ((chainlen > DC_TX_LIST_CNT / 4) || 3271 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3272 m = m_defrag(*m_head, M_DONTWAIT); 3273 if (m == NULL) 3274 return (ENOBUFS); 3275 *m_head = m; 3276 } 3277 3278 /* 3279 * Start packing the mbufs in this chain into 3280 * the fragment pointers. Stop when we run out 3281 * of fragments or hit the end of the mbuf chain. 3282 */ 3283 idx = sc->dc_cdata.dc_tx_prod; 3284 sc->dc_cdata.dc_tx_mapping = *m_head; 3285 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3286 *m_head, dc_dma_map_txbuf, sc, 0); 3287 if (error) 3288 return (error); 3289 if (sc->dc_cdata.dc_tx_err != 0) 3290 return (sc->dc_cdata.dc_tx_err); 3291 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3292 BUS_DMASYNC_PREWRITE); 3293 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3294 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3295 return (0); 3296 } 3297 3298 /* 3299 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3300 * to the mbuf data regions directly in the transmit lists. We also save a 3301 * copy of the pointers since the transmit list fragment pointers are 3302 * physical addresses. 3303 */ 3304 3305 static void 3306 dc_start(struct ifnet *ifp) 3307 { 3308 struct dc_softc *sc; 3309 3310 sc = ifp->if_softc; 3311 DC_LOCK(sc); 3312 dc_start_locked(ifp); 3313 DC_UNLOCK(sc); 3314 } 3315 3316 static void 3317 dc_start_locked(struct ifnet *ifp) 3318 { 3319 struct dc_softc *sc; 3320 struct mbuf *m_head = NULL, *m; 3321 unsigned int queued = 0; 3322 int idx; 3323 3324 sc = ifp->if_softc; 3325 3326 DC_LOCK_ASSERT(sc); 3327 3328 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3329 return; 3330 3331 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3332 return; 3333 3334 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3335 3336 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3337 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3338 if (m_head == NULL) 3339 break; 3340 3341 if (sc->dc_flags & DC_TX_COALESCE && 3342 (m_head->m_next != NULL || 3343 sc->dc_flags & DC_TX_ALIGN)) { 3344 m = m_defrag(m_head, M_DONTWAIT); 3345 if (m == NULL) { 3346 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3347 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3348 break; 3349 } else { 3350 m_head = m; 3351 } 3352 } 3353 3354 if (dc_encap(sc, &m_head)) { 3355 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3356 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3357 break; 3358 } 3359 idx = sc->dc_cdata.dc_tx_prod; 3360 3361 queued++; 3362 /* 3363 * If there's a BPF listener, bounce a copy of this frame 3364 * to him. 3365 */ 3366 BPF_MTAP(ifp, m_head); 3367 3368 if (sc->dc_flags & DC_TX_ONE) { 3369 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3370 break; 3371 } 3372 } 3373 3374 if (queued > 0) { 3375 /* Transmit */ 3376 if (!(sc->dc_flags & DC_TX_POLL)) 3377 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3378 3379 /* 3380 * Set a timeout in case the chip goes out to lunch. 3381 */ 3382 ifp->if_timer = 5; 3383 } 3384 } 3385 3386 static void 3387 dc_init(void *xsc) 3388 { 3389 struct dc_softc *sc = xsc; 3390 3391 DC_LOCK(sc); 3392 dc_init_locked(sc); 3393 #ifdef SRM_MEDIA 3394 if(sc->dc_srm_media) { 3395 struct ifreq ifr; 3396 struct mii_data *mii; 3397 3398 ifr.ifr_media = sc->dc_srm_media; 3399 sc->dc_srm_media = 0; 3400 DC_UNLOCK(sc); 3401 mii = device_get_softc(sc->dc_miibus); 3402 ifmedia_ioctl(sc->dc_ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3403 } else 3404 #endif 3405 DC_UNLOCK(sc); 3406 } 3407 3408 static void 3409 dc_init_locked(struct dc_softc *sc) 3410 { 3411 struct ifnet *ifp = sc->dc_ifp; 3412 struct mii_data *mii; 3413 3414 DC_LOCK_ASSERT(sc); 3415 3416 mii = device_get_softc(sc->dc_miibus); 3417 3418 /* 3419 * Cancel pending I/O and free all RX/TX buffers. 3420 */ 3421 dc_stop(sc); 3422 dc_reset(sc); 3423 3424 /* 3425 * Set cache alignment and burst length. 3426 */ 3427 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3428 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3429 else 3430 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3431 /* 3432 * Evenly share the bus between receive and transmit process. 3433 */ 3434 if (DC_IS_INTEL(sc)) 3435 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3436 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3437 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3438 } else { 3439 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3440 } 3441 if (sc->dc_flags & DC_TX_POLL) 3442 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3443 switch(sc->dc_cachesize) { 3444 case 32: 3445 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3446 break; 3447 case 16: 3448 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3449 break; 3450 case 8: 3451 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3452 break; 3453 case 0: 3454 default: 3455 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3456 break; 3457 } 3458 3459 if (sc->dc_flags & DC_TX_STORENFWD) 3460 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3461 else { 3462 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3463 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3464 } else { 3465 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3466 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3467 } 3468 } 3469 3470 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3471 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3472 3473 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3474 /* 3475 * The app notes for the 98713 and 98715A say that 3476 * in order to have the chips operate properly, a magic 3477 * number must be written to CSR16. Macronix does not 3478 * document the meaning of these bits so there's no way 3479 * to know exactly what they do. The 98713 has a magic 3480 * number all its own; the rest all use a different one. 3481 */ 3482 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3483 if (sc->dc_type == DC_TYPE_98713) 3484 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3485 else 3486 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3487 } 3488 3489 if (DC_IS_XIRCOM(sc)) { 3490 /* 3491 * setup General Purpose Port mode and data so the tulip 3492 * can talk to the MII. 3493 */ 3494 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3495 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3496 DELAY(10); 3497 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3498 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3499 DELAY(10); 3500 } 3501 3502 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3503 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3504 3505 /* Init circular RX list. */ 3506 if (dc_list_rx_init(sc) == ENOBUFS) { 3507 if_printf(ifp, 3508 "initialization failed: no memory for rx buffers\n"); 3509 dc_stop(sc); 3510 return; 3511 } 3512 3513 /* 3514 * Init TX descriptors. 3515 */ 3516 dc_list_tx_init(sc); 3517 3518 /* 3519 * Load the address of the RX list. 3520 */ 3521 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3522 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3523 3524 /* 3525 * Enable interrupts. 3526 */ 3527 #ifdef DEVICE_POLLING 3528 /* 3529 * ... but only if we are not polling, and make sure they are off in 3530 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3531 * after a reset. 3532 */ 3533 if (ifp->if_capenable & IFCAP_POLLING) 3534 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3535 else 3536 #endif 3537 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3538 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3539 3540 /* Enable transmitter. */ 3541 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3542 3543 /* 3544 * If this is an Intel 21143 and we're not using the 3545 * MII port, program the LED control pins so we get 3546 * link and activity indications. 3547 */ 3548 if (sc->dc_flags & DC_TULIP_LEDS) { 3549 CSR_WRITE_4(sc, DC_WATCHDOG, 3550 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3551 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3552 } 3553 3554 /* 3555 * Load the RX/multicast filter. We do this sort of late 3556 * because the filter programming scheme on the 21143 and 3557 * some clones requires DMAing a setup frame via the TX 3558 * engine, and we need the transmitter enabled for that. 3559 */ 3560 dc_setfilt(sc); 3561 3562 /* Enable receiver. */ 3563 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3564 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3565 3566 mii_mediachg(mii); 3567 dc_setcfg(sc, sc->dc_if_media); 3568 3569 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3570 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3571 3572 /* Don't start the ticker if this is a homePNA link. */ 3573 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3574 sc->dc_link = 1; 3575 else { 3576 if (sc->dc_flags & DC_21143_NWAY) 3577 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3578 else 3579 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3580 } 3581 } 3582 3583 /* 3584 * Set media options. 3585 */ 3586 static int 3587 dc_ifmedia_upd(struct ifnet *ifp) 3588 { 3589 struct dc_softc *sc; 3590 struct mii_data *mii; 3591 struct ifmedia *ifm; 3592 3593 sc = ifp->if_softc; 3594 mii = device_get_softc(sc->dc_miibus); 3595 DC_LOCK(sc); 3596 mii_mediachg(mii); 3597 ifm = &mii->mii_media; 3598 3599 if (DC_IS_DAVICOM(sc) && 3600 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3601 dc_setcfg(sc, ifm->ifm_media); 3602 else 3603 sc->dc_link = 0; 3604 DC_UNLOCK(sc); 3605 3606 return (0); 3607 } 3608 3609 /* 3610 * Report current media status. 3611 */ 3612 static void 3613 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3614 { 3615 struct dc_softc *sc; 3616 struct mii_data *mii; 3617 struct ifmedia *ifm; 3618 3619 sc = ifp->if_softc; 3620 mii = device_get_softc(sc->dc_miibus); 3621 DC_LOCK(sc); 3622 mii_pollstat(mii); 3623 ifm = &mii->mii_media; 3624 if (DC_IS_DAVICOM(sc)) { 3625 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3626 ifmr->ifm_active = ifm->ifm_media; 3627 ifmr->ifm_status = 0; 3628 return; 3629 } 3630 } 3631 ifmr->ifm_active = mii->mii_media_active; 3632 ifmr->ifm_status = mii->mii_media_status; 3633 DC_UNLOCK(sc); 3634 } 3635 3636 static int 3637 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3638 { 3639 struct dc_softc *sc = ifp->if_softc; 3640 struct ifreq *ifr = (struct ifreq *)data; 3641 struct mii_data *mii; 3642 int error = 0; 3643 3644 switch (command) { 3645 case SIOCSIFFLAGS: 3646 DC_LOCK(sc); 3647 if (ifp->if_flags & IFF_UP) { 3648 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3649 (IFF_PROMISC | IFF_ALLMULTI); 3650 3651 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3652 if (need_setfilt) 3653 dc_setfilt(sc); 3654 } else { 3655 sc->dc_txthresh = 0; 3656 dc_init_locked(sc); 3657 } 3658 } else { 3659 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3660 dc_stop(sc); 3661 } 3662 sc->dc_if_flags = ifp->if_flags; 3663 DC_UNLOCK(sc); 3664 error = 0; 3665 break; 3666 case SIOCADDMULTI: 3667 case SIOCDELMULTI: 3668 DC_LOCK(sc); 3669 dc_setfilt(sc); 3670 DC_UNLOCK(sc); 3671 error = 0; 3672 break; 3673 case SIOCGIFMEDIA: 3674 case SIOCSIFMEDIA: 3675 mii = device_get_softc(sc->dc_miibus); 3676 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3677 #ifdef SRM_MEDIA 3678 DC_LOCK(sc); 3679 if (sc->dc_srm_media) 3680 sc->dc_srm_media = 0; 3681 DC_UNLOCK(sc); 3682 #endif 3683 break; 3684 case SIOCSIFCAP: 3685 #ifdef DEVICE_POLLING 3686 if (ifr->ifr_reqcap & IFCAP_POLLING && 3687 !(ifp->if_capenable & IFCAP_POLLING)) { 3688 error = ether_poll_register(dc_poll, ifp); 3689 if (error) 3690 return(error); 3691 DC_LOCK(sc); 3692 /* Disable interrupts */ 3693 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3694 ifp->if_capenable |= IFCAP_POLLING; 3695 DC_UNLOCK(sc); 3696 return (error); 3697 3698 } 3699 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3700 ifp->if_capenable & IFCAP_POLLING) { 3701 error = ether_poll_deregister(ifp); 3702 /* Enable interrupts. */ 3703 DC_LOCK(sc); 3704 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3705 ifp->if_capenable &= ~IFCAP_POLLING; 3706 DC_UNLOCK(sc); 3707 return (error); 3708 } 3709 #endif /* DEVICE_POLLING */ 3710 break; 3711 default: 3712 error = ether_ioctl(ifp, command, data); 3713 break; 3714 } 3715 3716 return (error); 3717 } 3718 3719 static void 3720 dc_watchdog(struct ifnet *ifp) 3721 { 3722 struct dc_softc *sc; 3723 3724 sc = ifp->if_softc; 3725 3726 DC_LOCK(sc); 3727 3728 ifp->if_oerrors++; 3729 if_printf(ifp, "watchdog timeout\n"); 3730 3731 dc_stop(sc); 3732 dc_reset(sc); 3733 dc_init_locked(sc); 3734 3735 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3736 dc_start_locked(ifp); 3737 3738 DC_UNLOCK(sc); 3739 } 3740 3741 /* 3742 * Stop the adapter and free any mbufs allocated to the 3743 * RX and TX lists. 3744 */ 3745 static void 3746 dc_stop(struct dc_softc *sc) 3747 { 3748 struct ifnet *ifp; 3749 struct dc_list_data *ld; 3750 struct dc_chain_data *cd; 3751 int i; 3752 u_int32_t ctl; 3753 3754 DC_LOCK_ASSERT(sc); 3755 3756 ifp = sc->dc_ifp; 3757 ifp->if_timer = 0; 3758 ld = sc->dc_ldata; 3759 cd = &sc->dc_cdata; 3760 3761 callout_stop(&sc->dc_stat_ch); 3762 3763 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3764 3765 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3766 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3767 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3768 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3769 sc->dc_link = 0; 3770 3771 /* 3772 * Free data in the RX lists. 3773 */ 3774 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3775 if (cd->dc_rx_chain[i] != NULL) { 3776 m_freem(cd->dc_rx_chain[i]); 3777 cd->dc_rx_chain[i] = NULL; 3778 } 3779 } 3780 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3781 3782 /* 3783 * Free the TX list buffers. 3784 */ 3785 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3786 if (cd->dc_tx_chain[i] != NULL) { 3787 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3788 if ((ctl & DC_TXCTL_SETUP) || 3789 !(ctl & DC_TXCTL_LASTFRAG)) { 3790 cd->dc_tx_chain[i] = NULL; 3791 continue; 3792 } 3793 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3794 m_freem(cd->dc_tx_chain[i]); 3795 cd->dc_tx_chain[i] = NULL; 3796 } 3797 } 3798 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3799 } 3800 3801 /* 3802 * Device suspend routine. Stop the interface and save some PCI 3803 * settings in case the BIOS doesn't restore them properly on 3804 * resume. 3805 */ 3806 static int 3807 dc_suspend(device_t dev) 3808 { 3809 struct dc_softc *sc; 3810 3811 sc = device_get_softc(dev); 3812 DC_LOCK(sc); 3813 dc_stop(sc); 3814 sc->suspended = 1; 3815 DC_UNLOCK(sc); 3816 3817 return (0); 3818 } 3819 3820 /* 3821 * Device resume routine. Restore some PCI settings in case the BIOS 3822 * doesn't, re-enable busmastering, and restart the interface if 3823 * appropriate. 3824 */ 3825 static int 3826 dc_resume(device_t dev) 3827 { 3828 struct dc_softc *sc; 3829 struct ifnet *ifp; 3830 3831 sc = device_get_softc(dev); 3832 ifp = sc->dc_ifp; 3833 3834 /* reinitialize interface if necessary */ 3835 DC_LOCK(sc); 3836 if (ifp->if_flags & IFF_UP) 3837 dc_init_locked(sc); 3838 3839 sc->suspended = 0; 3840 DC_UNLOCK(sc); 3841 3842 return (0); 3843 } 3844 3845 /* 3846 * Stop all chip I/O so that the kernel's probe routines don't 3847 * get confused by errant DMAs when rebooting. 3848 */ 3849 static void 3850 dc_shutdown(device_t dev) 3851 { 3852 struct dc_softc *sc; 3853 3854 sc = device_get_softc(dev); 3855 3856 DC_LOCK(sc); 3857 dc_stop(sc); 3858 DC_UNLOCK(sc); 3859 }
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