Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/pci/if_dc.c
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1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/6.1/sys/pci/if_dc.c 156974 2006-03-21 21:10:58Z jhb $"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #ifdef HAVE_KERNEL_OPTION_HEADERS 95 #include "opt_device_polling.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/endian.h> 100 #include <sys/systm.h> 101 #include <sys/sockio.h> 102 #include <sys/mbuf.h> 103 #include <sys/malloc.h> 104 #include <sys/kernel.h> 105 #include <sys/module.h> 106 #include <sys/socket.h> 107 #include <sys/sysctl.h> 108 109 #include <net/if.h> 110 #include <net/if_arp.h> 111 #include <net/ethernet.h> 112 #include <net/if_dl.h> 113 #include <net/if_media.h> 114 #include <net/if_types.h> 115 #include <net/if_vlan_var.h> 116 117 #include <net/bpf.h> 118 119 #include <machine/bus.h> 120 #include <machine/resource.h> 121 #include <sys/bus.h> 122 #include <sys/rman.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 130 #define DC_USEIOSPACE 131 #ifdef __alpha__ 132 #define SRM_MEDIA 133 #endif 134 135 #include <pci/if_dcreg.h> 136 137 #ifdef __sparc64__ 138 #include <dev/ofw/openfirm.h> 139 #include <machine/ofw_machdep.h> 140 #endif 141 142 MODULE_DEPEND(dc, pci, 1, 1, 1); 143 MODULE_DEPEND(dc, ether, 1, 1, 1); 144 MODULE_DEPEND(dc, miibus, 1, 1, 1); 145 146 /* "controller miibus0" required. See GENERIC if you get errors here. */ 147 #include "miibus_if.h" 148 149 /* 150 * Various supported device vendors/types and their names. 151 */ 152 static struct dc_type dc_devs[] = { 153 { DC_VENDORID_DEC, DC_DEVICEID_21143, 154 "Intel 21143 10/100BaseTX" }, 155 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 156 "Davicom DM9009 10/100BaseTX" }, 157 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 158 "Davicom DM9100 10/100BaseTX" }, 159 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 160 "Davicom DM9102 10/100BaseTX" }, 161 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 162 "Davicom DM9102A 10/100BaseTX" }, 163 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 164 "ADMtek AL981 10/100BaseTX" }, 165 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 166 "ADMtek AN985 10/100BaseTX" }, 167 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 168 "ADMtek ADM9511 10/100BaseTX" }, 169 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 170 "ADMtek ADM9513 10/100BaseTX" }, 171 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 172 "Netgear FA511 10/100BaseTX" }, 173 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 174 "ASIX AX88140A 10/100BaseTX" }, 175 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 176 "ASIX AX88141 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98713, 178 "Macronix 98713 10/100BaseTX" }, 179 { DC_VENDORID_MX, DC_DEVICEID_98713, 180 "Macronix 98713A 10/100BaseTX" }, 181 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 182 "Compex RL100-TX 10/100BaseTX" }, 183 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 184 "Compex RL100-TX 10/100BaseTX" }, 185 { DC_VENDORID_MX, DC_DEVICEID_987x5, 186 "Macronix 98715/98715A 10/100BaseTX" }, 187 { DC_VENDORID_MX, DC_DEVICEID_987x5, 188 "Macronix 98715AEC-C 10/100BaseTX" }, 189 { DC_VENDORID_MX, DC_DEVICEID_987x5, 190 "Macronix 98725 10/100BaseTX" }, 191 { DC_VENDORID_MX, DC_DEVICEID_98727, 192 "Macronix 98727/98732 10/100BaseTX" }, 193 { DC_VENDORID_LO, DC_DEVICEID_82C115, 194 "LC82C115 PNIC II 10/100BaseTX" }, 195 { DC_VENDORID_LO, DC_DEVICEID_82C168, 196 "82c168 PNIC 10/100BaseTX" }, 197 { DC_VENDORID_LO, DC_DEVICEID_82C168, 198 "82c169 PNIC 10/100BaseTX" }, 199 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 200 "Accton EN1217 10/100BaseTX" }, 201 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 202 "Accton EN2242 MiniPCI 10/100BaseTX" }, 203 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 204 "Xircom X3201 10/100BaseTX" }, 205 { DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD, 206 "Neteasy DRP-32TXD Cardbus 10/100" }, 207 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 208 "Abocom FE2500 10/100BaseTX" }, 209 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX, 210 "Abocom FE2500MX 10/100BaseTX" }, 211 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 212 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 213 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 214 "Hawking CB102 CardBus 10/100" }, 215 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 216 "PlaneX FNW-3602-T CardBus 10/100" }, 217 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 218 "3Com OfficeConnect 10/100B" }, 219 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 220 "Microsoft MN-120 CardBus 10/100" }, 221 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 222 "Microsoft MN-130 10/100" }, 223 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 224 "Microsoft MN-130 10/100" }, 225 { 0, 0, NULL } 226 }; 227 228 static int dc_probe(device_t); 229 static int dc_attach(device_t); 230 static int dc_detach(device_t); 231 static int dc_suspend(device_t); 232 static int dc_resume(device_t); 233 static struct dc_type *dc_devtype(device_t); 234 static int dc_newbuf(struct dc_softc *, int, int); 235 static int dc_encap(struct dc_softc *, struct mbuf **); 236 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 237 static int dc_rx_resync(struct dc_softc *); 238 static void dc_rxeof(struct dc_softc *); 239 static void dc_txeof(struct dc_softc *); 240 static void dc_tick(void *); 241 static void dc_tx_underrun(struct dc_softc *); 242 static void dc_intr(void *); 243 static void dc_start(struct ifnet *); 244 static void dc_start_locked(struct ifnet *); 245 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 246 static void dc_init(void *); 247 static void dc_init_locked(struct dc_softc *); 248 static void dc_stop(struct dc_softc *); 249 static void dc_watchdog(struct ifnet *); 250 static void dc_shutdown(device_t); 251 static int dc_ifmedia_upd(struct ifnet *); 252 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 253 254 static void dc_delay(struct dc_softc *); 255 static void dc_eeprom_idle(struct dc_softc *); 256 static void dc_eeprom_putbyte(struct dc_softc *, int); 257 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 258 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 259 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 260 static void dc_eeprom_width(struct dc_softc *); 261 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 262 263 static void dc_mii_writebit(struct dc_softc *, int); 264 static int dc_mii_readbit(struct dc_softc *); 265 static void dc_mii_sync(struct dc_softc *); 266 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 267 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 268 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 269 static int dc_miibus_readreg(device_t, int, int); 270 static int dc_miibus_writereg(device_t, int, int, int); 271 static void dc_miibus_statchg(device_t); 272 static void dc_miibus_mediainit(device_t); 273 274 static void dc_setcfg(struct dc_softc *, int); 275 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 276 static uint32_t dc_mchash_be(const uint8_t *); 277 static void dc_setfilt_21143(struct dc_softc *); 278 static void dc_setfilt_asix(struct dc_softc *); 279 static void dc_setfilt_admtek(struct dc_softc *); 280 static void dc_setfilt_xircom(struct dc_softc *); 281 282 static void dc_setfilt(struct dc_softc *); 283 284 static void dc_reset(struct dc_softc *); 285 static int dc_list_rx_init(struct dc_softc *); 286 static int dc_list_tx_init(struct dc_softc *); 287 288 static void dc_read_srom(struct dc_softc *, int); 289 static void dc_parse_21143_srom(struct dc_softc *); 290 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 291 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 292 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 293 static void dc_apply_fixup(struct dc_softc *, int); 294 295 static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 296 static void dc_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 297 298 #ifdef DC_USEIOSPACE 299 #define DC_RES SYS_RES_IOPORT 300 #define DC_RID DC_PCI_CFBIO 301 #else 302 #define DC_RES SYS_RES_MEMORY 303 #define DC_RID DC_PCI_CFBMA 304 #endif 305 306 static device_method_t dc_methods[] = { 307 /* Device interface */ 308 DEVMETHOD(device_probe, dc_probe), 309 DEVMETHOD(device_attach, dc_attach), 310 DEVMETHOD(device_detach, dc_detach), 311 DEVMETHOD(device_suspend, dc_suspend), 312 DEVMETHOD(device_resume, dc_resume), 313 DEVMETHOD(device_shutdown, dc_shutdown), 314 315 /* bus interface */ 316 DEVMETHOD(bus_print_child, bus_generic_print_child), 317 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 318 319 /* MII interface */ 320 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 321 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 322 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 323 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 324 325 { 0, 0 } 326 }; 327 328 static driver_t dc_driver = { 329 "dc", 330 dc_methods, 331 sizeof(struct dc_softc) 332 }; 333 334 static devclass_t dc_devclass; 335 #ifdef __i386__ 336 static int dc_quick = 1; 337 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 338 "do not m_devget() in dc driver"); 339 #endif 340 341 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 342 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 343 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 344 345 #define DC_SETBIT(sc, reg, x) \ 346 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 347 348 #define DC_CLRBIT(sc, reg, x) \ 349 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 350 351 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 352 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 353 354 static void 355 dc_delay(struct dc_softc *sc) 356 { 357 int idx; 358 359 for (idx = (300 / 33) + 1; idx > 0; idx--) 360 CSR_READ_4(sc, DC_BUSCTL); 361 } 362 363 static void 364 dc_eeprom_width(struct dc_softc *sc) 365 { 366 int i; 367 368 /* Force EEPROM to idle state. */ 369 dc_eeprom_idle(sc); 370 371 /* Enter EEPROM access mode. */ 372 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 373 dc_delay(sc); 374 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 375 dc_delay(sc); 376 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 377 dc_delay(sc); 378 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 379 dc_delay(sc); 380 381 for (i = 3; i--;) { 382 if (6 & (1 << i)) 383 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 384 else 385 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 386 dc_delay(sc); 387 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 388 dc_delay(sc); 389 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 390 dc_delay(sc); 391 } 392 393 for (i = 1; i <= 12; i++) { 394 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 395 dc_delay(sc); 396 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 397 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 398 dc_delay(sc); 399 break; 400 } 401 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 402 dc_delay(sc); 403 } 404 405 /* Turn off EEPROM access mode. */ 406 dc_eeprom_idle(sc); 407 408 if (i < 4 || i > 12) 409 sc->dc_romwidth = 6; 410 else 411 sc->dc_romwidth = i; 412 413 /* Enter EEPROM access mode. */ 414 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 415 dc_delay(sc); 416 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 417 dc_delay(sc); 418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 419 dc_delay(sc); 420 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 421 dc_delay(sc); 422 423 /* Turn off EEPROM access mode. */ 424 dc_eeprom_idle(sc); 425 } 426 427 static void 428 dc_eeprom_idle(struct dc_softc *sc) 429 { 430 int i; 431 432 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 433 dc_delay(sc); 434 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 435 dc_delay(sc); 436 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 437 dc_delay(sc); 438 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 439 dc_delay(sc); 440 441 for (i = 0; i < 25; i++) { 442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 443 dc_delay(sc); 444 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 445 dc_delay(sc); 446 } 447 448 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 449 dc_delay(sc); 450 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 451 dc_delay(sc); 452 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 453 } 454 455 /* 456 * Send a read command and address to the EEPROM, check for ACK. 457 */ 458 static void 459 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 460 { 461 int d, i; 462 463 d = DC_EECMD_READ >> 6; 464 for (i = 3; i--; ) { 465 if (d & (1 << i)) 466 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 467 else 468 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 469 dc_delay(sc); 470 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 471 dc_delay(sc); 472 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 473 dc_delay(sc); 474 } 475 476 /* 477 * Feed in each bit and strobe the clock. 478 */ 479 for (i = sc->dc_romwidth; i--;) { 480 if (addr & (1 << i)) { 481 SIO_SET(DC_SIO_EE_DATAIN); 482 } else { 483 SIO_CLR(DC_SIO_EE_DATAIN); 484 } 485 dc_delay(sc); 486 SIO_SET(DC_SIO_EE_CLK); 487 dc_delay(sc); 488 SIO_CLR(DC_SIO_EE_CLK); 489 dc_delay(sc); 490 } 491 } 492 493 /* 494 * Read a word of data stored in the EEPROM at address 'addr.' 495 * The PNIC 82c168/82c169 has its own non-standard way to read 496 * the EEPROM. 497 */ 498 static void 499 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 500 { 501 int i; 502 u_int32_t r; 503 504 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 505 506 for (i = 0; i < DC_TIMEOUT; i++) { 507 DELAY(1); 508 r = CSR_READ_4(sc, DC_SIO); 509 if (!(r & DC_PN_SIOCTL_BUSY)) { 510 *dest = (u_int16_t)(r & 0xFFFF); 511 return; 512 } 513 } 514 } 515 516 /* 517 * Read a word of data stored in the EEPROM at address 'addr.' 518 * The Xircom X3201 has its own non-standard way to read 519 * the EEPROM, too. 520 */ 521 static void 522 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 523 { 524 525 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 526 527 addr *= 2; 528 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 529 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 530 addr += 1; 531 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 532 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 533 534 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 535 } 536 537 /* 538 * Read a word of data stored in the EEPROM at address 'addr.' 539 */ 540 static void 541 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 542 { 543 int i; 544 u_int16_t word = 0; 545 546 /* Force EEPROM to idle state. */ 547 dc_eeprom_idle(sc); 548 549 /* Enter EEPROM access mode. */ 550 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 551 dc_delay(sc); 552 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 553 dc_delay(sc); 554 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 555 dc_delay(sc); 556 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 557 dc_delay(sc); 558 559 /* 560 * Send address of word we want to read. 561 */ 562 dc_eeprom_putbyte(sc, addr); 563 564 /* 565 * Start reading bits from EEPROM. 566 */ 567 for (i = 0x8000; i; i >>= 1) { 568 SIO_SET(DC_SIO_EE_CLK); 569 dc_delay(sc); 570 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 571 word |= i; 572 dc_delay(sc); 573 SIO_CLR(DC_SIO_EE_CLK); 574 dc_delay(sc); 575 } 576 577 /* Turn off EEPROM access mode. */ 578 dc_eeprom_idle(sc); 579 580 *dest = word; 581 } 582 583 /* 584 * Read a sequence of words from the EEPROM. 585 */ 586 static void 587 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 588 { 589 int i; 590 u_int16_t word = 0, *ptr; 591 592 for (i = 0; i < cnt; i++) { 593 if (DC_IS_PNIC(sc)) 594 dc_eeprom_getword_pnic(sc, off + i, &word); 595 else if (DC_IS_XIRCOM(sc)) 596 dc_eeprom_getword_xircom(sc, off + i, &word); 597 else 598 dc_eeprom_getword(sc, off + i, &word); 599 ptr = (u_int16_t *)(dest + (i * 2)); 600 if (be) 601 *ptr = be16toh(word); 602 else 603 *ptr = le16toh(word); 604 } 605 } 606 607 /* 608 * The following two routines are taken from the Macronix 98713 609 * Application Notes pp.19-21. 610 */ 611 /* 612 * Write a bit to the MII bus. 613 */ 614 static void 615 dc_mii_writebit(struct dc_softc *sc, int bit) 616 { 617 618 if (bit) 619 CSR_WRITE_4(sc, DC_SIO, 620 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 621 else 622 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 623 624 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 625 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 626 } 627 628 /* 629 * Read a bit from the MII bus. 630 */ 631 static int 632 dc_mii_readbit(struct dc_softc *sc) 633 { 634 635 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 636 CSR_READ_4(sc, DC_SIO); 637 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 638 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 639 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 640 return (1); 641 642 return (0); 643 } 644 645 /* 646 * Sync the PHYs by setting data bit and strobing the clock 32 times. 647 */ 648 static void 649 dc_mii_sync(struct dc_softc *sc) 650 { 651 int i; 652 653 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 654 655 for (i = 0; i < 32; i++) 656 dc_mii_writebit(sc, 1); 657 } 658 659 /* 660 * Clock a series of bits through the MII. 661 */ 662 static void 663 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 664 { 665 int i; 666 667 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 668 dc_mii_writebit(sc, bits & i); 669 } 670 671 /* 672 * Read an PHY register through the MII. 673 */ 674 static int 675 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 676 { 677 int i, ack; 678 679 /* 680 * Set up frame for RX. 681 */ 682 frame->mii_stdelim = DC_MII_STARTDELIM; 683 frame->mii_opcode = DC_MII_READOP; 684 frame->mii_turnaround = 0; 685 frame->mii_data = 0; 686 687 /* 688 * Sync the PHYs. 689 */ 690 dc_mii_sync(sc); 691 692 /* 693 * Send command/address info. 694 */ 695 dc_mii_send(sc, frame->mii_stdelim, 2); 696 dc_mii_send(sc, frame->mii_opcode, 2); 697 dc_mii_send(sc, frame->mii_phyaddr, 5); 698 dc_mii_send(sc, frame->mii_regaddr, 5); 699 700 #ifdef notdef 701 /* Idle bit */ 702 dc_mii_writebit(sc, 1); 703 dc_mii_writebit(sc, 0); 704 #endif 705 706 /* Check for ack. */ 707 ack = dc_mii_readbit(sc); 708 709 /* 710 * Now try reading data bits. If the ack failed, we still 711 * need to clock through 16 cycles to keep the PHY(s) in sync. 712 */ 713 if (ack) { 714 for (i = 0; i < 16; i++) 715 dc_mii_readbit(sc); 716 goto fail; 717 } 718 719 for (i = 0x8000; i; i >>= 1) { 720 if (!ack) { 721 if (dc_mii_readbit(sc)) 722 frame->mii_data |= i; 723 } 724 } 725 726 fail: 727 728 dc_mii_writebit(sc, 0); 729 dc_mii_writebit(sc, 0); 730 731 if (ack) 732 return (1); 733 return (0); 734 } 735 736 /* 737 * Write to a PHY register through the MII. 738 */ 739 static int 740 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 741 { 742 743 /* 744 * Set up frame for TX. 745 */ 746 747 frame->mii_stdelim = DC_MII_STARTDELIM; 748 frame->mii_opcode = DC_MII_WRITEOP; 749 frame->mii_turnaround = DC_MII_TURNAROUND; 750 751 /* 752 * Sync the PHYs. 753 */ 754 dc_mii_sync(sc); 755 756 dc_mii_send(sc, frame->mii_stdelim, 2); 757 dc_mii_send(sc, frame->mii_opcode, 2); 758 dc_mii_send(sc, frame->mii_phyaddr, 5); 759 dc_mii_send(sc, frame->mii_regaddr, 5); 760 dc_mii_send(sc, frame->mii_turnaround, 2); 761 dc_mii_send(sc, frame->mii_data, 16); 762 763 /* Idle bit. */ 764 dc_mii_writebit(sc, 0); 765 dc_mii_writebit(sc, 0); 766 767 return (0); 768 } 769 770 static int 771 dc_miibus_readreg(device_t dev, int phy, int reg) 772 { 773 struct dc_mii_frame frame; 774 struct dc_softc *sc; 775 int i, rval, phy_reg = 0; 776 777 sc = device_get_softc(dev); 778 bzero(&frame, sizeof(frame)); 779 780 /* 781 * Note: both the AL981 and AN985 have internal PHYs, 782 * however the AL981 provides direct access to the PHY 783 * registers while the AN985 uses a serial MII interface. 784 * The AN985's MII interface is also buggy in that you 785 * can read from any MII address (0 to 31), but only address 1 786 * behaves normally. To deal with both cases, we pretend 787 * that the PHY is at MII address 1. 788 */ 789 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 790 return (0); 791 792 /* 793 * Note: the ukphy probes of the RS7112 report a PHY at 794 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 795 * so we only respond to correct one. 796 */ 797 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 798 return (0); 799 800 if (sc->dc_pmode != DC_PMODE_MII) { 801 if (phy == (MII_NPHY - 1)) { 802 switch (reg) { 803 case MII_BMSR: 804 /* 805 * Fake something to make the probe 806 * code think there's a PHY here. 807 */ 808 return (BMSR_MEDIAMASK); 809 break; 810 case MII_PHYIDR1: 811 if (DC_IS_PNIC(sc)) 812 return (DC_VENDORID_LO); 813 return (DC_VENDORID_DEC); 814 break; 815 case MII_PHYIDR2: 816 if (DC_IS_PNIC(sc)) 817 return (DC_DEVICEID_82C168); 818 return (DC_DEVICEID_21143); 819 break; 820 default: 821 return (0); 822 break; 823 } 824 } else 825 return (0); 826 } 827 828 if (DC_IS_PNIC(sc)) { 829 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 830 (phy << 23) | (reg << 18)); 831 for (i = 0; i < DC_TIMEOUT; i++) { 832 DELAY(1); 833 rval = CSR_READ_4(sc, DC_PN_MII); 834 if (!(rval & DC_PN_MII_BUSY)) { 835 rval &= 0xFFFF; 836 return (rval == 0xFFFF ? 0 : rval); 837 } 838 } 839 return (0); 840 } 841 842 if (DC_IS_COMET(sc)) { 843 switch (reg) { 844 case MII_BMCR: 845 phy_reg = DC_AL_BMCR; 846 break; 847 case MII_BMSR: 848 phy_reg = DC_AL_BMSR; 849 break; 850 case MII_PHYIDR1: 851 phy_reg = DC_AL_VENID; 852 break; 853 case MII_PHYIDR2: 854 phy_reg = DC_AL_DEVID; 855 break; 856 case MII_ANAR: 857 phy_reg = DC_AL_ANAR; 858 break; 859 case MII_ANLPAR: 860 phy_reg = DC_AL_LPAR; 861 break; 862 case MII_ANER: 863 phy_reg = DC_AL_ANER; 864 break; 865 default: 866 device_printf(dev, "phy_read: bad phy register %x\n", 867 reg); 868 return (0); 869 break; 870 } 871 872 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 873 874 if (rval == 0xFFFF) 875 return (0); 876 return (rval); 877 } 878 879 frame.mii_phyaddr = phy; 880 frame.mii_regaddr = reg; 881 if (sc->dc_type == DC_TYPE_98713) { 882 phy_reg = CSR_READ_4(sc, DC_NETCFG); 883 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 884 } 885 dc_mii_readreg(sc, &frame); 886 if (sc->dc_type == DC_TYPE_98713) 887 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 888 889 return (frame.mii_data); 890 } 891 892 static int 893 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 894 { 895 struct dc_softc *sc; 896 struct dc_mii_frame frame; 897 int i, phy_reg = 0; 898 899 sc = device_get_softc(dev); 900 bzero(&frame, sizeof(frame)); 901 902 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 903 return (0); 904 905 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 906 return (0); 907 908 if (DC_IS_PNIC(sc)) { 909 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 910 (phy << 23) | (reg << 10) | data); 911 for (i = 0; i < DC_TIMEOUT; i++) { 912 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 913 break; 914 } 915 return (0); 916 } 917 918 if (DC_IS_COMET(sc)) { 919 switch (reg) { 920 case MII_BMCR: 921 phy_reg = DC_AL_BMCR; 922 break; 923 case MII_BMSR: 924 phy_reg = DC_AL_BMSR; 925 break; 926 case MII_PHYIDR1: 927 phy_reg = DC_AL_VENID; 928 break; 929 case MII_PHYIDR2: 930 phy_reg = DC_AL_DEVID; 931 break; 932 case MII_ANAR: 933 phy_reg = DC_AL_ANAR; 934 break; 935 case MII_ANLPAR: 936 phy_reg = DC_AL_LPAR; 937 break; 938 case MII_ANER: 939 phy_reg = DC_AL_ANER; 940 break; 941 default: 942 device_printf(dev, "phy_write: bad phy register %x\n", 943 reg); 944 return (0); 945 break; 946 } 947 948 CSR_WRITE_4(sc, phy_reg, data); 949 return (0); 950 } 951 952 frame.mii_phyaddr = phy; 953 frame.mii_regaddr = reg; 954 frame.mii_data = data; 955 956 if (sc->dc_type == DC_TYPE_98713) { 957 phy_reg = CSR_READ_4(sc, DC_NETCFG); 958 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 959 } 960 dc_mii_writereg(sc, &frame); 961 if (sc->dc_type == DC_TYPE_98713) 962 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 963 964 return (0); 965 } 966 967 static void 968 dc_miibus_statchg(device_t dev) 969 { 970 struct dc_softc *sc; 971 struct mii_data *mii; 972 struct ifmedia *ifm; 973 974 sc = device_get_softc(dev); 975 if (DC_IS_ADMTEK(sc)) 976 return; 977 978 mii = device_get_softc(sc->dc_miibus); 979 ifm = &mii->mii_media; 980 if (DC_IS_DAVICOM(sc) && 981 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 982 dc_setcfg(sc, ifm->ifm_media); 983 sc->dc_if_media = ifm->ifm_media; 984 } else { 985 dc_setcfg(sc, mii->mii_media_active); 986 sc->dc_if_media = mii->mii_media_active; 987 } 988 } 989 990 /* 991 * Special support for DM9102A cards with HomePNA PHYs. Note: 992 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 993 * to be impossible to talk to the management interface of the DM9801 994 * PHY (its MDIO pin is not connected to anything). Consequently, 995 * the driver has to just 'know' about the additional mode and deal 996 * with it itself. *sigh* 997 */ 998 static void 999 dc_miibus_mediainit(device_t dev) 1000 { 1001 struct dc_softc *sc; 1002 struct mii_data *mii; 1003 struct ifmedia *ifm; 1004 int rev; 1005 1006 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1007 1008 sc = device_get_softc(dev); 1009 mii = device_get_softc(sc->dc_miibus); 1010 ifm = &mii->mii_media; 1011 1012 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1013 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1014 } 1015 1016 #define DC_BITS_512 9 1017 #define DC_BITS_128 7 1018 #define DC_BITS_64 6 1019 1020 static uint32_t 1021 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1022 { 1023 uint32_t crc; 1024 1025 /* Compute CRC for the address value. */ 1026 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1027 1028 /* 1029 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1030 * chips is only 128 bits wide. 1031 */ 1032 if (sc->dc_flags & DC_128BIT_HASH) 1033 return (crc & ((1 << DC_BITS_128) - 1)); 1034 1035 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1036 if (sc->dc_flags & DC_64BIT_HASH) 1037 return (crc & ((1 << DC_BITS_64) - 1)); 1038 1039 /* Xircom's hash filtering table is different (read: weird) */ 1040 /* Xircom uses the LEAST significant bits */ 1041 if (DC_IS_XIRCOM(sc)) { 1042 if ((crc & 0x180) == 0x180) 1043 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1044 else 1045 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1046 (12 << 4)); 1047 } 1048 1049 return (crc & ((1 << DC_BITS_512) - 1)); 1050 } 1051 1052 /* 1053 * Calculate CRC of a multicast group address, return the lower 6 bits. 1054 */ 1055 static uint32_t 1056 dc_mchash_be(const uint8_t *addr) 1057 { 1058 uint32_t crc; 1059 1060 /* Compute CRC for the address value. */ 1061 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1062 1063 /* Return the filter bit position. */ 1064 return ((crc >> 26) & 0x0000003F); 1065 } 1066 1067 /* 1068 * 21143-style RX filter setup routine. Filter programming is done by 1069 * downloading a special setup frame into the TX engine. 21143, Macronix, 1070 * PNIC, PNIC II and Davicom chips are programmed this way. 1071 * 1072 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1073 * address (our node address) and a 512-bit hash filter for multicast 1074 * frames. We also sneak the broadcast address into the hash filter since 1075 * we need that too. 1076 */ 1077 static void 1078 dc_setfilt_21143(struct dc_softc *sc) 1079 { 1080 struct dc_desc *sframe; 1081 u_int32_t h, *sp; 1082 struct ifmultiaddr *ifma; 1083 struct ifnet *ifp; 1084 int i; 1085 1086 ifp = sc->dc_ifp; 1087 1088 i = sc->dc_cdata.dc_tx_prod; 1089 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1090 sc->dc_cdata.dc_tx_cnt++; 1091 sframe = &sc->dc_ldata->dc_tx_list[i]; 1092 sp = sc->dc_cdata.dc_sbuf; 1093 bzero(sp, DC_SFRAME_LEN); 1094 1095 sframe->dc_data = htole32(sc->dc_saddr); 1096 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1097 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1098 1099 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1100 1101 /* If we want promiscuous mode, set the allframes bit. */ 1102 if (ifp->if_flags & IFF_PROMISC) 1103 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1104 else 1105 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1106 1107 if (ifp->if_flags & IFF_ALLMULTI) 1108 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1109 else 1110 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1111 1112 IF_ADDR_LOCK(ifp); 1113 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1114 if (ifma->ifma_addr->sa_family != AF_LINK) 1115 continue; 1116 h = dc_mchash_le(sc, 1117 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1118 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1119 } 1120 IF_ADDR_UNLOCK(ifp); 1121 1122 if (ifp->if_flags & IFF_BROADCAST) { 1123 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1124 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1125 } 1126 1127 /* Set our MAC address */ 1128 sp[39] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]); 1129 sp[40] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]); 1130 sp[41] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]); 1131 1132 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1133 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1134 1135 /* 1136 * The PNIC takes an exceedingly long time to process its 1137 * setup frame; wait 10ms after posting the setup frame 1138 * before proceeding, just so it has time to swallow its 1139 * medicine. 1140 */ 1141 DELAY(10000); 1142 1143 ifp->if_timer = 5; 1144 } 1145 1146 static void 1147 dc_setfilt_admtek(struct dc_softc *sc) 1148 { 1149 struct ifnet *ifp; 1150 struct ifmultiaddr *ifma; 1151 int h = 0; 1152 u_int32_t hashes[2] = { 0, 0 }; 1153 1154 ifp = sc->dc_ifp; 1155 1156 /* Init our MAC address. */ 1157 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[0])); 1158 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[4])); 1159 1160 /* If we want promiscuous mode, set the allframes bit. */ 1161 if (ifp->if_flags & IFF_PROMISC) 1162 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1163 else 1164 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1165 1166 if (ifp->if_flags & IFF_ALLMULTI) 1167 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1168 else 1169 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1170 1171 /* First, zot all the existing hash bits. */ 1172 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1173 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1174 1175 /* 1176 * If we're already in promisc or allmulti mode, we 1177 * don't have to bother programming the multicast filter. 1178 */ 1179 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1180 return; 1181 1182 /* Now program new ones. */ 1183 IF_ADDR_LOCK(ifp); 1184 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1185 if (ifma->ifma_addr->sa_family != AF_LINK) 1186 continue; 1187 if (DC_IS_CENTAUR(sc)) 1188 h = dc_mchash_le(sc, 1189 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1190 else 1191 h = dc_mchash_be( 1192 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1193 if (h < 32) 1194 hashes[0] |= (1 << h); 1195 else 1196 hashes[1] |= (1 << (h - 32)); 1197 } 1198 IF_ADDR_UNLOCK(ifp); 1199 1200 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1201 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1202 } 1203 1204 static void 1205 dc_setfilt_asix(struct dc_softc *sc) 1206 { 1207 struct ifnet *ifp; 1208 struct ifmultiaddr *ifma; 1209 int h = 0; 1210 u_int32_t hashes[2] = { 0, 0 }; 1211 1212 ifp = sc->dc_ifp; 1213 1214 /* Init our MAC address */ 1215 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1216 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1217 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[0])); 1218 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1219 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1220 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[4])); 1221 1222 /* If we want promiscuous mode, set the allframes bit. */ 1223 if (ifp->if_flags & IFF_PROMISC) 1224 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1225 else 1226 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1227 1228 if (ifp->if_flags & IFF_ALLMULTI) 1229 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1230 else 1231 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1232 1233 /* 1234 * The ASIX chip has a special bit to enable reception 1235 * of broadcast frames. 1236 */ 1237 if (ifp->if_flags & IFF_BROADCAST) 1238 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1239 else 1240 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1241 1242 /* first, zot all the existing hash bits */ 1243 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1244 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1245 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1246 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1247 1248 /* 1249 * If we're already in promisc or allmulti mode, we 1250 * don't have to bother programming the multicast filter. 1251 */ 1252 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1253 return; 1254 1255 /* now program new ones */ 1256 IF_ADDR_LOCK(ifp); 1257 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1258 if (ifma->ifma_addr->sa_family != AF_LINK) 1259 continue; 1260 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1261 if (h < 32) 1262 hashes[0] |= (1 << h); 1263 else 1264 hashes[1] |= (1 << (h - 32)); 1265 } 1266 IF_ADDR_UNLOCK(ifp); 1267 1268 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1269 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1270 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1271 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1272 } 1273 1274 static void 1275 dc_setfilt_xircom(struct dc_softc *sc) 1276 { 1277 struct ifnet *ifp; 1278 struct ifmultiaddr *ifma; 1279 struct dc_desc *sframe; 1280 u_int32_t h, *sp; 1281 int i; 1282 1283 ifp = sc->dc_ifp; 1284 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1285 1286 i = sc->dc_cdata.dc_tx_prod; 1287 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1288 sc->dc_cdata.dc_tx_cnt++; 1289 sframe = &sc->dc_ldata->dc_tx_list[i]; 1290 sp = sc->dc_cdata.dc_sbuf; 1291 bzero(sp, DC_SFRAME_LEN); 1292 1293 sframe->dc_data = htole32(sc->dc_saddr); 1294 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1295 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1296 1297 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1298 1299 /* If we want promiscuous mode, set the allframes bit. */ 1300 if (ifp->if_flags & IFF_PROMISC) 1301 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1302 else 1303 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1304 1305 if (ifp->if_flags & IFF_ALLMULTI) 1306 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1307 else 1308 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1309 1310 IF_ADDR_LOCK(ifp); 1311 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1312 if (ifma->ifma_addr->sa_family != AF_LINK) 1313 continue; 1314 h = dc_mchash_le(sc, 1315 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1316 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1317 } 1318 IF_ADDR_UNLOCK(ifp); 1319 1320 if (ifp->if_flags & IFF_BROADCAST) { 1321 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1322 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1323 } 1324 1325 /* Set our MAC address */ 1326 sp[0] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]); 1327 sp[1] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]); 1328 sp[2] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]); 1329 1330 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1331 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1332 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1333 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1334 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1335 1336 /* 1337 * Wait some time... 1338 */ 1339 DELAY(1000); 1340 1341 ifp->if_timer = 5; 1342 } 1343 1344 static void 1345 dc_setfilt(struct dc_softc *sc) 1346 { 1347 1348 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1349 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1350 dc_setfilt_21143(sc); 1351 1352 if (DC_IS_ASIX(sc)) 1353 dc_setfilt_asix(sc); 1354 1355 if (DC_IS_ADMTEK(sc)) 1356 dc_setfilt_admtek(sc); 1357 1358 if (DC_IS_XIRCOM(sc)) 1359 dc_setfilt_xircom(sc); 1360 } 1361 1362 /* 1363 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1364 * the netconfig register, we first have to put the transmit and/or 1365 * receive logic in the idle state. 1366 */ 1367 static void 1368 dc_setcfg(struct dc_softc *sc, int media) 1369 { 1370 int i, restart = 0, watchdogreg; 1371 u_int32_t isr; 1372 1373 if (IFM_SUBTYPE(media) == IFM_NONE) 1374 return; 1375 1376 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1377 restart = 1; 1378 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1379 1380 for (i = 0; i < DC_TIMEOUT; i++) { 1381 isr = CSR_READ_4(sc, DC_ISR); 1382 if (isr & DC_ISR_TX_IDLE && 1383 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1384 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1385 break; 1386 DELAY(10); 1387 } 1388 1389 if (i == DC_TIMEOUT) 1390 if_printf(sc->dc_ifp, 1391 "failed to force tx and rx to idle state\n"); 1392 } 1393 1394 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1395 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1396 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1397 if (sc->dc_pmode == DC_PMODE_MII) { 1398 if (DC_IS_INTEL(sc)) { 1399 /* There's a write enable bit here that reads as 1. */ 1400 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1401 watchdogreg &= ~DC_WDOG_CTLWREN; 1402 watchdogreg |= DC_WDOG_JABBERDIS; 1403 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1404 } else { 1405 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1406 } 1407 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1408 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1409 if (sc->dc_type == DC_TYPE_98713) 1410 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1411 DC_NETCFG_SCRAMBLER)); 1412 if (!DC_IS_DAVICOM(sc)) 1413 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1414 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1415 if (DC_IS_INTEL(sc)) 1416 dc_apply_fixup(sc, IFM_AUTO); 1417 } else { 1418 if (DC_IS_PNIC(sc)) { 1419 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1420 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1421 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1422 } 1423 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1424 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1425 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1426 if (DC_IS_INTEL(sc)) 1427 dc_apply_fixup(sc, 1428 (media & IFM_GMASK) == IFM_FDX ? 1429 IFM_100_TX | IFM_FDX : IFM_100_TX); 1430 } 1431 } 1432 1433 if (IFM_SUBTYPE(media) == IFM_10_T) { 1434 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1435 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1436 if (sc->dc_pmode == DC_PMODE_MII) { 1437 /* There's a write enable bit here that reads as 1. */ 1438 if (DC_IS_INTEL(sc)) { 1439 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1440 watchdogreg &= ~DC_WDOG_CTLWREN; 1441 watchdogreg |= DC_WDOG_JABBERDIS; 1442 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1443 } else { 1444 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1445 } 1446 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1447 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1448 if (sc->dc_type == DC_TYPE_98713) 1449 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1450 if (!DC_IS_DAVICOM(sc)) 1451 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1452 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1453 if (DC_IS_INTEL(sc)) 1454 dc_apply_fixup(sc, IFM_AUTO); 1455 } else { 1456 if (DC_IS_PNIC(sc)) { 1457 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1458 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1459 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1460 } 1461 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1462 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1463 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1464 if (DC_IS_INTEL(sc)) { 1465 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1466 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1467 if ((media & IFM_GMASK) == IFM_FDX) 1468 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1469 else 1470 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1471 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1472 DC_CLRBIT(sc, DC_10BTCTRL, 1473 DC_TCTL_AUTONEGENBL); 1474 dc_apply_fixup(sc, 1475 (media & IFM_GMASK) == IFM_FDX ? 1476 IFM_10_T | IFM_FDX : IFM_10_T); 1477 DELAY(20000); 1478 } 1479 } 1480 } 1481 1482 /* 1483 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1484 * PHY and we want HomePNA mode, set the portsel bit to turn 1485 * on the external MII port. 1486 */ 1487 if (DC_IS_DAVICOM(sc)) { 1488 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1489 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1490 sc->dc_link = 1; 1491 } else { 1492 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1493 } 1494 } 1495 1496 if ((media & IFM_GMASK) == IFM_FDX) { 1497 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1498 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1499 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1500 } else { 1501 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1502 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1503 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1504 } 1505 1506 if (restart) 1507 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1508 } 1509 1510 static void 1511 dc_reset(struct dc_softc *sc) 1512 { 1513 int i; 1514 1515 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1516 1517 for (i = 0; i < DC_TIMEOUT; i++) { 1518 DELAY(10); 1519 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1520 break; 1521 } 1522 1523 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1524 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1525 DELAY(10000); 1526 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1527 i = 0; 1528 } 1529 1530 if (i == DC_TIMEOUT) 1531 if_printf(sc->dc_ifp, "reset never completed!\n"); 1532 1533 /* Wait a little while for the chip to get its brains in order. */ 1534 DELAY(1000); 1535 1536 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1537 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1538 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1539 1540 /* 1541 * Bring the SIA out of reset. In some cases, it looks 1542 * like failing to unreset the SIA soon enough gets it 1543 * into a state where it will never come out of reset 1544 * until we reset the whole chip again. 1545 */ 1546 if (DC_IS_INTEL(sc)) { 1547 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1548 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1549 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1550 } 1551 } 1552 1553 static struct dc_type * 1554 dc_devtype(device_t dev) 1555 { 1556 struct dc_type *t; 1557 u_int32_t rev; 1558 1559 t = dc_devs; 1560 1561 while (t->dc_name != NULL) { 1562 if ((pci_get_vendor(dev) == t->dc_vid) && 1563 (pci_get_device(dev) == t->dc_did)) { 1564 /* Check the PCI revision */ 1565 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1566 if (t->dc_did == DC_DEVICEID_98713 && 1567 rev >= DC_REVISION_98713A) 1568 t++; 1569 if (t->dc_did == DC_DEVICEID_98713_CP && 1570 rev >= DC_REVISION_98713A) 1571 t++; 1572 if (t->dc_did == DC_DEVICEID_987x5 && 1573 rev >= DC_REVISION_98715AEC_C) 1574 t++; 1575 if (t->dc_did == DC_DEVICEID_987x5 && 1576 rev >= DC_REVISION_98725) 1577 t++; 1578 if (t->dc_did == DC_DEVICEID_AX88140A && 1579 rev >= DC_REVISION_88141) 1580 t++; 1581 if (t->dc_did == DC_DEVICEID_82C168 && 1582 rev >= DC_REVISION_82C169) 1583 t++; 1584 if (t->dc_did == DC_DEVICEID_DM9102 && 1585 rev >= DC_REVISION_DM9102A) 1586 t++; 1587 /* 1588 * The Microsoft MN-130 has a device ID of 0x0002, 1589 * which happens to be the same as the PNIC 82c168. 1590 * To keep dc_attach() from getting confused, we 1591 * pretend its ID is something different. 1592 * XXX: ideally, dc_attach() should be checking 1593 * vendorid+deviceid together to avoid such 1594 * collisions. 1595 */ 1596 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1597 t->dc_did == DC_DEVICEID_MSMN130) 1598 t++; 1599 return (t); 1600 } 1601 t++; 1602 } 1603 1604 return (NULL); 1605 } 1606 1607 /* 1608 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1609 * IDs against our list and return a device name if we find a match. 1610 * We do a little bit of extra work to identify the exact type of 1611 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1612 * but different revision IDs. The same is true for 98715/98715A 1613 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1614 * cases, the exact chip revision affects driver behavior. 1615 */ 1616 static int 1617 dc_probe(device_t dev) 1618 { 1619 struct dc_type *t; 1620 1621 t = dc_devtype(dev); 1622 1623 if (t != NULL) { 1624 device_set_desc(dev, t->dc_name); 1625 return (BUS_PROBE_DEFAULT); 1626 } 1627 1628 return (ENXIO); 1629 } 1630 1631 static void 1632 dc_apply_fixup(struct dc_softc *sc, int media) 1633 { 1634 struct dc_mediainfo *m; 1635 u_int8_t *p; 1636 int i; 1637 u_int32_t reg; 1638 1639 m = sc->dc_mi; 1640 1641 while (m != NULL) { 1642 if (m->dc_media == media) 1643 break; 1644 m = m->dc_next; 1645 } 1646 1647 if (m == NULL) 1648 return; 1649 1650 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1651 reg = (p[0] | (p[1] << 8)) << 16; 1652 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1653 } 1654 1655 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1656 reg = (p[0] | (p[1] << 8)) << 16; 1657 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1658 } 1659 } 1660 1661 static void 1662 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1663 { 1664 struct dc_mediainfo *m; 1665 1666 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1667 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1668 case DC_SIA_CODE_10BT: 1669 m->dc_media = IFM_10_T; 1670 break; 1671 case DC_SIA_CODE_10BT_FDX: 1672 m->dc_media = IFM_10_T | IFM_FDX; 1673 break; 1674 case DC_SIA_CODE_10B2: 1675 m->dc_media = IFM_10_2; 1676 break; 1677 case DC_SIA_CODE_10B5: 1678 m->dc_media = IFM_10_5; 1679 break; 1680 default: 1681 break; 1682 } 1683 1684 /* 1685 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1686 * Things apparently already work for cards that do 1687 * supply Media Specific Data. 1688 */ 1689 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1690 m->dc_gp_len = 2; 1691 m->dc_gp_ptr = 1692 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1693 } else { 1694 m->dc_gp_len = 2; 1695 m->dc_gp_ptr = 1696 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1697 } 1698 1699 m->dc_next = sc->dc_mi; 1700 sc->dc_mi = m; 1701 1702 sc->dc_pmode = DC_PMODE_SIA; 1703 } 1704 1705 static void 1706 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1707 { 1708 struct dc_mediainfo *m; 1709 1710 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1711 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1712 m->dc_media = IFM_100_TX; 1713 1714 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1715 m->dc_media = IFM_100_TX | IFM_FDX; 1716 1717 m->dc_gp_len = 2; 1718 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1719 1720 m->dc_next = sc->dc_mi; 1721 sc->dc_mi = m; 1722 1723 sc->dc_pmode = DC_PMODE_SYM; 1724 } 1725 1726 static void 1727 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1728 { 1729 struct dc_mediainfo *m; 1730 u_int8_t *p; 1731 1732 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1733 /* We abuse IFM_AUTO to represent MII. */ 1734 m->dc_media = IFM_AUTO; 1735 m->dc_gp_len = l->dc_gpr_len; 1736 1737 p = (u_int8_t *)l; 1738 p += sizeof(struct dc_eblock_mii); 1739 m->dc_gp_ptr = p; 1740 p += 2 * l->dc_gpr_len; 1741 m->dc_reset_len = *p; 1742 p++; 1743 m->dc_reset_ptr = p; 1744 1745 m->dc_next = sc->dc_mi; 1746 sc->dc_mi = m; 1747 } 1748 1749 static void 1750 dc_read_srom(struct dc_softc *sc, int bits) 1751 { 1752 int size; 1753 1754 size = 2 << bits; 1755 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1756 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1757 } 1758 1759 static void 1760 dc_parse_21143_srom(struct dc_softc *sc) 1761 { 1762 struct dc_leaf_hdr *lhdr; 1763 struct dc_eblock_hdr *hdr; 1764 int have_mii, i, loff; 1765 char *ptr; 1766 1767 have_mii = 0; 1768 loff = sc->dc_srom[27]; 1769 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1770 1771 ptr = (char *)lhdr; 1772 ptr += sizeof(struct dc_leaf_hdr) - 1; 1773 /* 1774 * Look if we got a MII media block. 1775 */ 1776 for (i = 0; i < lhdr->dc_mcnt; i++) { 1777 hdr = (struct dc_eblock_hdr *)ptr; 1778 if (hdr->dc_type == DC_EBLOCK_MII) 1779 have_mii++; 1780 1781 ptr += (hdr->dc_len & 0x7F); 1782 ptr++; 1783 } 1784 1785 /* 1786 * Do the same thing again. Only use SIA and SYM media 1787 * blocks if no MII media block is available. 1788 */ 1789 ptr = (char *)lhdr; 1790 ptr += sizeof(struct dc_leaf_hdr) - 1; 1791 for (i = 0; i < lhdr->dc_mcnt; i++) { 1792 hdr = (struct dc_eblock_hdr *)ptr; 1793 switch (hdr->dc_type) { 1794 case DC_EBLOCK_MII: 1795 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1796 break; 1797 case DC_EBLOCK_SIA: 1798 if (! have_mii) 1799 dc_decode_leaf_sia(sc, 1800 (struct dc_eblock_sia *)hdr); 1801 break; 1802 case DC_EBLOCK_SYM: 1803 if (! have_mii) 1804 dc_decode_leaf_sym(sc, 1805 (struct dc_eblock_sym *)hdr); 1806 break; 1807 default: 1808 /* Don't care. Yet. */ 1809 break; 1810 } 1811 ptr += (hdr->dc_len & 0x7F); 1812 ptr++; 1813 } 1814 } 1815 1816 static void 1817 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1818 { 1819 u_int32_t *paddr; 1820 1821 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1822 paddr = arg; 1823 *paddr = segs->ds_addr; 1824 } 1825 1826 /* 1827 * Attach the interface. Allocate softc structures, do ifmedia 1828 * setup and ethernet/BPF attach. 1829 */ 1830 static int 1831 dc_attach(device_t dev) 1832 { 1833 int tmp = 0; 1834 u_char eaddr[ETHER_ADDR_LEN]; 1835 u_int32_t command; 1836 struct dc_softc *sc; 1837 struct ifnet *ifp; 1838 u_int32_t revision; 1839 int error = 0, rid, mac_offset; 1840 int i; 1841 u_int8_t *mac; 1842 1843 sc = device_get_softc(dev); 1844 1845 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1846 MTX_DEF); 1847 1848 /* 1849 * Map control/status registers. 1850 */ 1851 pci_enable_busmaster(dev); 1852 1853 rid = DC_RID; 1854 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1855 1856 if (sc->dc_res == NULL) { 1857 device_printf(dev, "couldn't map ports/memory\n"); 1858 error = ENXIO; 1859 goto fail; 1860 } 1861 1862 sc->dc_btag = rman_get_bustag(sc->dc_res); 1863 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1864 1865 /* Allocate interrupt. */ 1866 rid = 0; 1867 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1868 RF_SHAREABLE | RF_ACTIVE); 1869 1870 if (sc->dc_irq == NULL) { 1871 device_printf(dev, "couldn't map interrupt\n"); 1872 error = ENXIO; 1873 goto fail; 1874 } 1875 1876 /* Need this info to decide on a chip type. */ 1877 sc->dc_info = dc_devtype(dev); 1878 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1879 1880 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1881 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1882 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1883 dc_eeprom_width(sc); 1884 1885 switch (sc->dc_info->dc_did) { 1886 case DC_DEVICEID_21143: 1887 sc->dc_type = DC_TYPE_21143; 1888 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1889 sc->dc_flags |= DC_REDUCED_MII_POLL; 1890 /* Save EEPROM contents so we can parse them later. */ 1891 dc_read_srom(sc, sc->dc_romwidth); 1892 break; 1893 case DC_DEVICEID_DM9009: 1894 case DC_DEVICEID_DM9100: 1895 case DC_DEVICEID_DM9102: 1896 sc->dc_type = DC_TYPE_DM9102; 1897 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1898 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1899 sc->dc_flags |= DC_TX_ALIGN; 1900 sc->dc_pmode = DC_PMODE_MII; 1901 /* Increase the latency timer value. */ 1902 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1903 command &= 0xFFFF00FF; 1904 command |= 0x00008000; 1905 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1906 break; 1907 case DC_DEVICEID_AL981: 1908 sc->dc_type = DC_TYPE_AL981; 1909 sc->dc_flags |= DC_TX_USE_TX_INTR; 1910 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1911 sc->dc_pmode = DC_PMODE_MII; 1912 dc_read_srom(sc, sc->dc_romwidth); 1913 break; 1914 case DC_DEVICEID_AN985: 1915 case DC_DEVICEID_ADM9511: 1916 case DC_DEVICEID_ADM9513: 1917 case DC_DEVICEID_DRP32TXD: 1918 case DC_DEVICEID_FA511: 1919 case DC_DEVICEID_FE2500: 1920 case DC_DEVICEID_EN2242: 1921 case DC_DEVICEID_HAWKING_PN672TX: 1922 case DC_DEVICEID_3CSOHOB: 1923 case DC_DEVICEID_MSMN120: 1924 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1925 sc->dc_type = DC_TYPE_AN985; 1926 sc->dc_flags |= DC_64BIT_HASH; 1927 sc->dc_flags |= DC_TX_USE_TX_INTR; 1928 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1929 sc->dc_pmode = DC_PMODE_MII; 1930 /* Don't read SROM for - auto-loaded on reset */ 1931 break; 1932 case DC_DEVICEID_98713: 1933 case DC_DEVICEID_98713_CP: 1934 if (revision < DC_REVISION_98713A) { 1935 sc->dc_type = DC_TYPE_98713; 1936 } 1937 if (revision >= DC_REVISION_98713A) { 1938 sc->dc_type = DC_TYPE_98713A; 1939 sc->dc_flags |= DC_21143_NWAY; 1940 } 1941 sc->dc_flags |= DC_REDUCED_MII_POLL; 1942 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1943 break; 1944 case DC_DEVICEID_987x5: 1945 case DC_DEVICEID_EN1217: 1946 /* 1947 * Macronix MX98715AEC-C/D/E parts have only a 1948 * 128-bit hash table. We need to deal with these 1949 * in the same manner as the PNIC II so that we 1950 * get the right number of bits out of the 1951 * CRC routine. 1952 */ 1953 if (revision >= DC_REVISION_98715AEC_C && 1954 revision < DC_REVISION_98725) 1955 sc->dc_flags |= DC_128BIT_HASH; 1956 sc->dc_type = DC_TYPE_987x5; 1957 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1958 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1959 break; 1960 case DC_DEVICEID_98727: 1961 sc->dc_type = DC_TYPE_987x5; 1962 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1963 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1964 break; 1965 case DC_DEVICEID_82C115: 1966 sc->dc_type = DC_TYPE_PNICII; 1967 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1968 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1969 break; 1970 case DC_DEVICEID_82C168: 1971 sc->dc_type = DC_TYPE_PNIC; 1972 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1973 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1974 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1975 if (revision < DC_REVISION_82C169) 1976 sc->dc_pmode = DC_PMODE_SYM; 1977 break; 1978 case DC_DEVICEID_AX88140A: 1979 sc->dc_type = DC_TYPE_ASIX; 1980 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1981 sc->dc_flags |= DC_REDUCED_MII_POLL; 1982 sc->dc_pmode = DC_PMODE_MII; 1983 break; 1984 case DC_DEVICEID_X3201: 1985 sc->dc_type = DC_TYPE_XIRCOM; 1986 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1987 DC_TX_ALIGN; 1988 /* 1989 * We don't actually need to coalesce, but we're doing 1990 * it to obtain a double word aligned buffer. 1991 * The DC_TX_COALESCE flag is required. 1992 */ 1993 sc->dc_pmode = DC_PMODE_MII; 1994 break; 1995 case DC_DEVICEID_RS7112: 1996 sc->dc_type = DC_TYPE_CONEXANT; 1997 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1998 sc->dc_flags |= DC_REDUCED_MII_POLL; 1999 sc->dc_pmode = DC_PMODE_MII; 2000 dc_read_srom(sc, sc->dc_romwidth); 2001 break; 2002 default: 2003 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did); 2004 break; 2005 } 2006 2007 /* Save the cache line size. */ 2008 if (DC_IS_DAVICOM(sc)) 2009 sc->dc_cachesize = 0; 2010 else 2011 sc->dc_cachesize = pci_read_config(dev, 2012 DC_PCI_CFLT, 4) & 0xFF; 2013 2014 /* Reset the adapter. */ 2015 dc_reset(sc); 2016 2017 /* Take 21143 out of snooze mode */ 2018 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2019 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2020 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2021 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2022 } 2023 2024 /* 2025 * Try to learn something about the supported media. 2026 * We know that ASIX and ADMtek and Davicom devices 2027 * will *always* be using MII media, so that's a no-brainer. 2028 * The tricky ones are the Macronix/PNIC II and the 2029 * Intel 21143. 2030 */ 2031 if (DC_IS_INTEL(sc)) 2032 dc_parse_21143_srom(sc); 2033 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2034 if (sc->dc_type == DC_TYPE_98713) 2035 sc->dc_pmode = DC_PMODE_MII; 2036 else 2037 sc->dc_pmode = DC_PMODE_SYM; 2038 } else if (!sc->dc_pmode) 2039 sc->dc_pmode = DC_PMODE_MII; 2040 2041 /* 2042 * Get station address from the EEPROM. 2043 */ 2044 switch(sc->dc_type) { 2045 case DC_TYPE_98713: 2046 case DC_TYPE_98713A: 2047 case DC_TYPE_987x5: 2048 case DC_TYPE_PNICII: 2049 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2050 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2051 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2052 break; 2053 case DC_TYPE_PNIC: 2054 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2055 break; 2056 case DC_TYPE_DM9102: 2057 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2058 #ifdef __sparc64__ 2059 /* 2060 * If this is an onboard dc(4) the station address read from 2061 * the EEPROM is all zero and we have to get it from the fcode. 2062 */ 2063 for (i = 0; i < ETHER_ADDR_LEN; i++) 2064 if (eaddr[i] != 0x00) 2065 break; 2066 if (i >= ETHER_ADDR_LEN) 2067 OF_getetheraddr(dev, eaddr); 2068 #endif 2069 break; 2070 case DC_TYPE_21143: 2071 case DC_TYPE_ASIX: 2072 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2073 break; 2074 case DC_TYPE_AL981: 2075 case DC_TYPE_AN985: 2076 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2077 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2078 break; 2079 case DC_TYPE_CONEXANT: 2080 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2081 ETHER_ADDR_LEN); 2082 break; 2083 case DC_TYPE_XIRCOM: 2084 /* The MAC comes from the CIS. */ 2085 mac = pci_get_ether(dev); 2086 if (!mac) { 2087 device_printf(dev, "No station address in CIS!\n"); 2088 error = ENXIO; 2089 goto fail; 2090 } 2091 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2092 break; 2093 default: 2094 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2095 break; 2096 } 2097 2098 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2099 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2100 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2101 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2102 if (error) { 2103 device_printf(dev, "failed to allocate busdma tag\n"); 2104 error = ENXIO; 2105 goto fail; 2106 } 2107 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2108 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2109 if (error) { 2110 device_printf(dev, "failed to allocate DMA safe memory\n"); 2111 error = ENXIO; 2112 goto fail; 2113 } 2114 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2115 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2116 BUS_DMA_NOWAIT); 2117 if (error) { 2118 device_printf(dev, "cannot get address of the descriptors\n"); 2119 error = ENXIO; 2120 goto fail; 2121 } 2122 2123 /* 2124 * Allocate a busdma tag and DMA safe memory for the multicast 2125 * setup frame. 2126 */ 2127 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2128 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2129 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2130 if (error) { 2131 device_printf(dev, "failed to allocate busdma tag\n"); 2132 error = ENXIO; 2133 goto fail; 2134 } 2135 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2136 BUS_DMA_NOWAIT, &sc->dc_smap); 2137 if (error) { 2138 device_printf(dev, "failed to allocate DMA safe memory\n"); 2139 error = ENXIO; 2140 goto fail; 2141 } 2142 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2143 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2144 if (error) { 2145 device_printf(dev, "cannot get address of the descriptors\n"); 2146 error = ENXIO; 2147 goto fail; 2148 } 2149 2150 /* Allocate a busdma tag for mbufs. */ 2151 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 2152 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, DC_TX_LIST_CNT, MCLBYTES, 2153 0, NULL, NULL, &sc->dc_mtag); 2154 if (error) { 2155 device_printf(dev, "failed to allocate busdma tag\n"); 2156 error = ENXIO; 2157 goto fail; 2158 } 2159 2160 /* Create the TX/RX busdma maps. */ 2161 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2162 error = bus_dmamap_create(sc->dc_mtag, 0, 2163 &sc->dc_cdata.dc_tx_map[i]); 2164 if (error) { 2165 device_printf(dev, "failed to init TX ring\n"); 2166 error = ENXIO; 2167 goto fail; 2168 } 2169 } 2170 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2171 error = bus_dmamap_create(sc->dc_mtag, 0, 2172 &sc->dc_cdata.dc_rx_map[i]); 2173 if (error) { 2174 device_printf(dev, "failed to init RX ring\n"); 2175 error = ENXIO; 2176 goto fail; 2177 } 2178 } 2179 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2180 if (error) { 2181 device_printf(dev, "failed to init RX ring\n"); 2182 error = ENXIO; 2183 goto fail; 2184 } 2185 2186 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2187 if (ifp == NULL) { 2188 device_printf(dev, "can not if_alloc()\n"); 2189 error = ENOSPC; 2190 goto fail; 2191 } 2192 ifp->if_softc = sc; 2193 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2194 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2195 ifp->if_mtu = ETHERMTU; 2196 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2197 ifp->if_ioctl = dc_ioctl; 2198 ifp->if_start = dc_start; 2199 ifp->if_watchdog = dc_watchdog; 2200 ifp->if_init = dc_init; 2201 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2202 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2203 IFQ_SET_READY(&ifp->if_snd); 2204 2205 /* 2206 * Do MII setup. If this is a 21143, check for a PHY on the 2207 * MII bus after applying any necessary fixups to twiddle the 2208 * GPIO bits. If we don't end up finding a PHY, restore the 2209 * old selection (SIA only or SIA/SYM) and attach the dcphy 2210 * driver instead. 2211 */ 2212 if (DC_IS_INTEL(sc)) { 2213 dc_apply_fixup(sc, IFM_AUTO); 2214 tmp = sc->dc_pmode; 2215 sc->dc_pmode = DC_PMODE_MII; 2216 } 2217 2218 /* 2219 * Setup General Purpose port mode and data so the tulip can talk 2220 * to the MII. This needs to be done before mii_phy_probe so that 2221 * we can actually see them. 2222 */ 2223 if (DC_IS_XIRCOM(sc)) { 2224 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2225 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2226 DELAY(10); 2227 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2228 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2229 DELAY(10); 2230 } 2231 2232 error = mii_phy_probe(dev, &sc->dc_miibus, 2233 dc_ifmedia_upd, dc_ifmedia_sts); 2234 2235 if (error && DC_IS_INTEL(sc)) { 2236 sc->dc_pmode = tmp; 2237 if (sc->dc_pmode != DC_PMODE_SIA) 2238 sc->dc_pmode = DC_PMODE_SYM; 2239 sc->dc_flags |= DC_21143_NWAY; 2240 mii_phy_probe(dev, &sc->dc_miibus, 2241 dc_ifmedia_upd, dc_ifmedia_sts); 2242 /* 2243 * For non-MII cards, we need to have the 21143 2244 * drive the LEDs. Except there are some systems 2245 * like the NEC VersaPro NoteBook PC which have no 2246 * LEDs, and twiddling these bits has adverse effects 2247 * on them. (I.e. you suddenly can't get a link.) 2248 */ 2249 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2250 sc->dc_flags |= DC_TULIP_LEDS; 2251 error = 0; 2252 } 2253 2254 if (error) { 2255 device_printf(dev, "MII without any PHY!\n"); 2256 goto fail; 2257 } 2258 2259 if (DC_IS_ADMTEK(sc)) { 2260 /* 2261 * Set automatic TX underrun recovery for the ADMtek chips 2262 */ 2263 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2264 } 2265 2266 /* 2267 * Tell the upper layer(s) we support long frames. 2268 */ 2269 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2270 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2271 ifp->if_capenable = ifp->if_capabilities; 2272 #ifdef DEVICE_POLLING 2273 ifp->if_capabilities |= IFCAP_POLLING; 2274 #endif 2275 2276 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2277 2278 #ifdef SRM_MEDIA 2279 sc->dc_srm_media = 0; 2280 2281 /* Remember the SRM console media setting */ 2282 if (DC_IS_INTEL(sc)) { 2283 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2284 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2285 switch ((command >> 8) & 0xff) { 2286 case 3: 2287 sc->dc_srm_media = IFM_10_T; 2288 break; 2289 case 4: 2290 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2291 break; 2292 case 5: 2293 sc->dc_srm_media = IFM_100_TX; 2294 break; 2295 case 6: 2296 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2297 break; 2298 } 2299 if (sc->dc_srm_media) 2300 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2301 } 2302 #endif 2303 2304 /* 2305 * Call MI attach routine. 2306 */ 2307 ether_ifattach(ifp, eaddr); 2308 2309 /* Hook interrupt last to avoid having to lock softc */ 2310 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2311 dc_intr, sc, &sc->dc_intrhand); 2312 2313 if (error) { 2314 device_printf(dev, "couldn't set up irq\n"); 2315 ether_ifdetach(ifp); 2316 goto fail; 2317 } 2318 2319 fail: 2320 if (error) 2321 dc_detach(dev); 2322 return (error); 2323 } 2324 2325 /* 2326 * Shutdown hardware and free up resources. This can be called any 2327 * time after the mutex has been initialized. It is called in both 2328 * the error case in attach and the normal detach case so it needs 2329 * to be careful about only freeing resources that have actually been 2330 * allocated. 2331 */ 2332 static int 2333 dc_detach(device_t dev) 2334 { 2335 struct dc_softc *sc; 2336 struct ifnet *ifp; 2337 struct dc_mediainfo *m; 2338 int i; 2339 2340 sc = device_get_softc(dev); 2341 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2342 2343 ifp = sc->dc_ifp; 2344 2345 #ifdef DEVICE_POLLING 2346 if (ifp->if_capenable & IFCAP_POLLING) 2347 ether_poll_deregister(ifp); 2348 #endif 2349 2350 /* These should only be active if attach succeeded */ 2351 if (device_is_attached(dev)) { 2352 DC_LOCK(sc); 2353 dc_stop(sc); 2354 DC_UNLOCK(sc); 2355 callout_drain(&sc->dc_stat_ch); 2356 ether_ifdetach(ifp); 2357 } 2358 if (ifp) 2359 if_free(ifp); 2360 if (sc->dc_miibus) 2361 device_delete_child(dev, sc->dc_miibus); 2362 bus_generic_detach(dev); 2363 2364 if (sc->dc_intrhand) 2365 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2366 if (sc->dc_irq) 2367 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2368 if (sc->dc_res) 2369 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2370 2371 if (sc->dc_cdata.dc_sbuf != NULL) 2372 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2373 if (sc->dc_ldata != NULL) 2374 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2375 if (sc->dc_mtag) { 2376 for (i = 0; i < DC_TX_LIST_CNT; i++) 2377 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2378 bus_dmamap_destroy(sc->dc_mtag, 2379 sc->dc_cdata.dc_tx_map[i]); 2380 for (i = 0; i < DC_RX_LIST_CNT; i++) 2381 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2382 bus_dmamap_destroy(sc->dc_mtag, 2383 sc->dc_cdata.dc_rx_map[i]); 2384 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2385 } 2386 if (sc->dc_stag) 2387 bus_dma_tag_destroy(sc->dc_stag); 2388 if (sc->dc_mtag) 2389 bus_dma_tag_destroy(sc->dc_mtag); 2390 if (sc->dc_ltag) 2391 bus_dma_tag_destroy(sc->dc_ltag); 2392 2393 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2394 2395 while (sc->dc_mi != NULL) { 2396 m = sc->dc_mi->dc_next; 2397 free(sc->dc_mi, M_DEVBUF); 2398 sc->dc_mi = m; 2399 } 2400 free(sc->dc_srom, M_DEVBUF); 2401 2402 mtx_destroy(&sc->dc_mtx); 2403 2404 return (0); 2405 } 2406 2407 /* 2408 * Initialize the transmit descriptors. 2409 */ 2410 static int 2411 dc_list_tx_init(struct dc_softc *sc) 2412 { 2413 struct dc_chain_data *cd; 2414 struct dc_list_data *ld; 2415 int i, nexti; 2416 2417 cd = &sc->dc_cdata; 2418 ld = sc->dc_ldata; 2419 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2420 if (i == DC_TX_LIST_CNT - 1) 2421 nexti = 0; 2422 else 2423 nexti = i + 1; 2424 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2425 cd->dc_tx_chain[i] = NULL; 2426 ld->dc_tx_list[i].dc_data = 0; 2427 ld->dc_tx_list[i].dc_ctl = 0; 2428 } 2429 2430 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2431 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2432 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2433 return (0); 2434 } 2435 2436 2437 /* 2438 * Initialize the RX descriptors and allocate mbufs for them. Note that 2439 * we arrange the descriptors in a closed ring, so that the last descriptor 2440 * points back to the first. 2441 */ 2442 static int 2443 dc_list_rx_init(struct dc_softc *sc) 2444 { 2445 struct dc_chain_data *cd; 2446 struct dc_list_data *ld; 2447 int i, nexti; 2448 2449 cd = &sc->dc_cdata; 2450 ld = sc->dc_ldata; 2451 2452 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2453 if (dc_newbuf(sc, i, 1) != 0) 2454 return (ENOBUFS); 2455 if (i == DC_RX_LIST_CNT - 1) 2456 nexti = 0; 2457 else 2458 nexti = i + 1; 2459 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2460 } 2461 2462 cd->dc_rx_prod = 0; 2463 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2464 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2465 return (0); 2466 } 2467 2468 static void 2469 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2470 void *arg; 2471 bus_dma_segment_t *segs; 2472 int nseg; 2473 bus_size_t mapsize; 2474 int error; 2475 { 2476 struct dc_softc *sc; 2477 struct dc_desc *c; 2478 2479 sc = arg; 2480 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2481 if (error) { 2482 sc->dc_cdata.dc_rx_err = error; 2483 return; 2484 } 2485 2486 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2487 sc->dc_cdata.dc_rx_err = 0; 2488 c->dc_data = htole32(segs->ds_addr); 2489 } 2490 2491 /* 2492 * Initialize an RX descriptor and attach an MBUF cluster. 2493 */ 2494 static int 2495 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2496 { 2497 struct mbuf *m_new; 2498 bus_dmamap_t tmp; 2499 int error; 2500 2501 if (alloc) { 2502 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2503 if (m_new == NULL) 2504 return (ENOBUFS); 2505 } else { 2506 m_new = sc->dc_cdata.dc_rx_chain[i]; 2507 m_new->m_data = m_new->m_ext.ext_buf; 2508 } 2509 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2510 m_adj(m_new, sizeof(u_int64_t)); 2511 2512 /* 2513 * If this is a PNIC chip, zero the buffer. This is part 2514 * of the workaround for the receive bug in the 82c168 and 2515 * 82c169 chips. 2516 */ 2517 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2518 bzero(mtod(m_new, char *), m_new->m_len); 2519 2520 /* No need to remap the mbuf if we're reusing it. */ 2521 if (alloc) { 2522 sc->dc_cdata.dc_rx_cur = i; 2523 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2524 m_new, dc_dma_map_rxbuf, sc, 0); 2525 if (error) { 2526 m_freem(m_new); 2527 return (error); 2528 } 2529 if (sc->dc_cdata.dc_rx_err != 0) { 2530 m_freem(m_new); 2531 return (sc->dc_cdata.dc_rx_err); 2532 } 2533 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2534 tmp = sc->dc_cdata.dc_rx_map[i]; 2535 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2536 sc->dc_sparemap = tmp; 2537 sc->dc_cdata.dc_rx_chain[i] = m_new; 2538 } 2539 2540 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2541 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2542 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2543 BUS_DMASYNC_PREREAD); 2544 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2545 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2546 return (0); 2547 } 2548 2549 /* 2550 * Grrrrr. 2551 * The PNIC chip has a terrible bug in it that manifests itself during 2552 * periods of heavy activity. The exact mode of failure if difficult to 2553 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2554 * will happen on slow machines. The bug is that sometimes instead of 2555 * uploading one complete frame during reception, it uploads what looks 2556 * like the entire contents of its FIFO memory. The frame we want is at 2557 * the end of the whole mess, but we never know exactly how much data has 2558 * been uploaded, so salvaging the frame is hard. 2559 * 2560 * There is only one way to do it reliably, and it's disgusting. 2561 * Here's what we know: 2562 * 2563 * - We know there will always be somewhere between one and three extra 2564 * descriptors uploaded. 2565 * 2566 * - We know the desired received frame will always be at the end of the 2567 * total data upload. 2568 * 2569 * - We know the size of the desired received frame because it will be 2570 * provided in the length field of the status word in the last descriptor. 2571 * 2572 * Here's what we do: 2573 * 2574 * - When we allocate buffers for the receive ring, we bzero() them. 2575 * This means that we know that the buffer contents should be all 2576 * zeros, except for data uploaded by the chip. 2577 * 2578 * - We also force the PNIC chip to upload frames that include the 2579 * ethernet CRC at the end. 2580 * 2581 * - We gather all of the bogus frame data into a single buffer. 2582 * 2583 * - We then position a pointer at the end of this buffer and scan 2584 * backwards until we encounter the first non-zero byte of data. 2585 * This is the end of the received frame. We know we will encounter 2586 * some data at the end of the frame because the CRC will always be 2587 * there, so even if the sender transmits a packet of all zeros, 2588 * we won't be fooled. 2589 * 2590 * - We know the size of the actual received frame, so we subtract 2591 * that value from the current pointer location. This brings us 2592 * to the start of the actual received packet. 2593 * 2594 * - We copy this into an mbuf and pass it on, along with the actual 2595 * frame length. 2596 * 2597 * The performance hit is tremendous, but it beats dropping frames all 2598 * the time. 2599 */ 2600 2601 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2602 static void 2603 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2604 { 2605 struct dc_desc *cur_rx; 2606 struct dc_desc *c = NULL; 2607 struct mbuf *m = NULL; 2608 unsigned char *ptr; 2609 int i, total_len; 2610 u_int32_t rxstat = 0; 2611 2612 i = sc->dc_pnic_rx_bug_save; 2613 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2614 ptr = sc->dc_pnic_rx_buf; 2615 bzero(ptr, DC_RXLEN * 5); 2616 2617 /* Copy all the bytes from the bogus buffers. */ 2618 while (1) { 2619 c = &sc->dc_ldata->dc_rx_list[i]; 2620 rxstat = le32toh(c->dc_status); 2621 m = sc->dc_cdata.dc_rx_chain[i]; 2622 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2623 ptr += DC_RXLEN; 2624 /* If this is the last buffer, break out. */ 2625 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2626 break; 2627 dc_newbuf(sc, i, 0); 2628 DC_INC(i, DC_RX_LIST_CNT); 2629 } 2630 2631 /* Find the length of the actual receive frame. */ 2632 total_len = DC_RXBYTES(rxstat); 2633 2634 /* Scan backwards until we hit a non-zero byte. */ 2635 while (*ptr == 0x00) 2636 ptr--; 2637 2638 /* Round off. */ 2639 if ((uintptr_t)(ptr) & 0x3) 2640 ptr -= 1; 2641 2642 /* Now find the start of the frame. */ 2643 ptr -= total_len; 2644 if (ptr < sc->dc_pnic_rx_buf) 2645 ptr = sc->dc_pnic_rx_buf; 2646 2647 /* 2648 * Now copy the salvaged frame to the last mbuf and fake up 2649 * the status word to make it look like a successful 2650 * frame reception. 2651 */ 2652 dc_newbuf(sc, i, 0); 2653 bcopy(ptr, mtod(m, char *), total_len); 2654 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2655 } 2656 2657 /* 2658 * This routine searches the RX ring for dirty descriptors in the 2659 * event that the rxeof routine falls out of sync with the chip's 2660 * current descriptor pointer. This may happen sometimes as a result 2661 * of a "no RX buffer available" condition that happens when the chip 2662 * consumes all of the RX buffers before the driver has a chance to 2663 * process the RX ring. This routine may need to be called more than 2664 * once to bring the driver back in sync with the chip, however we 2665 * should still be getting RX DONE interrupts to drive the search 2666 * for new packets in the RX ring, so we should catch up eventually. 2667 */ 2668 static int 2669 dc_rx_resync(struct dc_softc *sc) 2670 { 2671 struct dc_desc *cur_rx; 2672 int i, pos; 2673 2674 pos = sc->dc_cdata.dc_rx_prod; 2675 2676 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2677 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2678 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2679 break; 2680 DC_INC(pos, DC_RX_LIST_CNT); 2681 } 2682 2683 /* If the ring really is empty, then just return. */ 2684 if (i == DC_RX_LIST_CNT) 2685 return (0); 2686 2687 /* We've fallen behing the chip: catch it. */ 2688 sc->dc_cdata.dc_rx_prod = pos; 2689 2690 return (EAGAIN); 2691 } 2692 2693 /* 2694 * A frame has been uploaded: pass the resulting mbuf chain up to 2695 * the higher level protocols. 2696 */ 2697 static void 2698 dc_rxeof(struct dc_softc *sc) 2699 { 2700 struct mbuf *m; 2701 struct ifnet *ifp; 2702 struct dc_desc *cur_rx; 2703 int i, total_len = 0; 2704 u_int32_t rxstat; 2705 2706 DC_LOCK_ASSERT(sc); 2707 2708 ifp = sc->dc_ifp; 2709 i = sc->dc_cdata.dc_rx_prod; 2710 2711 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2712 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2713 DC_RXSTAT_OWN)) { 2714 #ifdef DEVICE_POLLING 2715 if (ifp->if_capenable & IFCAP_POLLING) { 2716 if (sc->rxcycles <= 0) 2717 break; 2718 sc->rxcycles--; 2719 } 2720 #endif 2721 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2722 rxstat = le32toh(cur_rx->dc_status); 2723 m = sc->dc_cdata.dc_rx_chain[i]; 2724 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2725 BUS_DMASYNC_POSTREAD); 2726 total_len = DC_RXBYTES(rxstat); 2727 2728 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2729 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2730 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2731 sc->dc_pnic_rx_bug_save = i; 2732 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2733 DC_INC(i, DC_RX_LIST_CNT); 2734 continue; 2735 } 2736 dc_pnic_rx_bug_war(sc, i); 2737 rxstat = le32toh(cur_rx->dc_status); 2738 total_len = DC_RXBYTES(rxstat); 2739 } 2740 } 2741 2742 /* 2743 * If an error occurs, update stats, clear the 2744 * status word and leave the mbuf cluster in place: 2745 * it should simply get re-used next time this descriptor 2746 * comes up in the ring. However, don't report long 2747 * frames as errors since they could be vlans. 2748 */ 2749 if ((rxstat & DC_RXSTAT_RXERR)) { 2750 if (!(rxstat & DC_RXSTAT_GIANT) || 2751 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2752 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2753 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2754 ifp->if_ierrors++; 2755 if (rxstat & DC_RXSTAT_COLLSEEN) 2756 ifp->if_collisions++; 2757 dc_newbuf(sc, i, 0); 2758 if (rxstat & DC_RXSTAT_CRCERR) { 2759 DC_INC(i, DC_RX_LIST_CNT); 2760 continue; 2761 } else { 2762 dc_init_locked(sc); 2763 return; 2764 } 2765 } 2766 } 2767 2768 /* No errors; receive the packet. */ 2769 total_len -= ETHER_CRC_LEN; 2770 #ifdef __i386__ 2771 /* 2772 * On the x86 we do not have alignment problems, so try to 2773 * allocate a new buffer for the receive ring, and pass up 2774 * the one where the packet is already, saving the expensive 2775 * copy done in m_devget(). 2776 * If we are on an architecture with alignment problems, or 2777 * if the allocation fails, then use m_devget and leave the 2778 * existing buffer in the receive ring. 2779 */ 2780 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2781 m->m_pkthdr.rcvif = ifp; 2782 m->m_pkthdr.len = m->m_len = total_len; 2783 DC_INC(i, DC_RX_LIST_CNT); 2784 } else 2785 #endif 2786 { 2787 struct mbuf *m0; 2788 2789 m0 = m_devget(mtod(m, char *), total_len, 2790 ETHER_ALIGN, ifp, NULL); 2791 dc_newbuf(sc, i, 0); 2792 DC_INC(i, DC_RX_LIST_CNT); 2793 if (m0 == NULL) { 2794 ifp->if_ierrors++; 2795 continue; 2796 } 2797 m = m0; 2798 } 2799 2800 ifp->if_ipackets++; 2801 DC_UNLOCK(sc); 2802 (*ifp->if_input)(ifp, m); 2803 DC_LOCK(sc); 2804 } 2805 2806 sc->dc_cdata.dc_rx_prod = i; 2807 } 2808 2809 /* 2810 * A frame was downloaded to the chip. It's safe for us to clean up 2811 * the list buffers. 2812 */ 2813 2814 static void 2815 dc_txeof(struct dc_softc *sc) 2816 { 2817 struct dc_desc *cur_tx = NULL; 2818 struct ifnet *ifp; 2819 int idx; 2820 u_int32_t ctl, txstat; 2821 2822 ifp = sc->dc_ifp; 2823 2824 /* 2825 * Go through our tx list and free mbufs for those 2826 * frames that have been transmitted. 2827 */ 2828 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2829 idx = sc->dc_cdata.dc_tx_cons; 2830 while (idx != sc->dc_cdata.dc_tx_prod) { 2831 2832 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2833 txstat = le32toh(cur_tx->dc_status); 2834 ctl = le32toh(cur_tx->dc_ctl); 2835 2836 if (txstat & DC_TXSTAT_OWN) 2837 break; 2838 2839 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2840 if (ctl & DC_TXCTL_SETUP) { 2841 /* 2842 * Yes, the PNIC is so brain damaged 2843 * that it will sometimes generate a TX 2844 * underrun error while DMAing the RX 2845 * filter setup frame. If we detect this, 2846 * we have to send the setup frame again, 2847 * or else the filter won't be programmed 2848 * correctly. 2849 */ 2850 if (DC_IS_PNIC(sc)) { 2851 if (txstat & DC_TXSTAT_ERRSUM) 2852 dc_setfilt(sc); 2853 } 2854 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2855 } 2856 sc->dc_cdata.dc_tx_cnt--; 2857 DC_INC(idx, DC_TX_LIST_CNT); 2858 continue; 2859 } 2860 2861 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2862 /* 2863 * XXX: Why does my Xircom taunt me so? 2864 * For some reason it likes setting the CARRLOST flag 2865 * even when the carrier is there. wtf?!? 2866 * Who knows, but Conexant chips have the 2867 * same problem. Maybe they took lessons 2868 * from Xircom. 2869 */ 2870 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2871 sc->dc_pmode == DC_PMODE_MII && 2872 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2873 DC_TXSTAT_NOCARRIER))) 2874 txstat &= ~DC_TXSTAT_ERRSUM; 2875 } else { 2876 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2877 sc->dc_pmode == DC_PMODE_MII && 2878 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2879 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2880 txstat &= ~DC_TXSTAT_ERRSUM; 2881 } 2882 2883 if (txstat & DC_TXSTAT_ERRSUM) { 2884 ifp->if_oerrors++; 2885 if (txstat & DC_TXSTAT_EXCESSCOLL) 2886 ifp->if_collisions++; 2887 if (txstat & DC_TXSTAT_LATECOLL) 2888 ifp->if_collisions++; 2889 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2890 dc_init_locked(sc); 2891 return; 2892 } 2893 } 2894 2895 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2896 2897 ifp->if_opackets++; 2898 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2899 bus_dmamap_sync(sc->dc_mtag, 2900 sc->dc_cdata.dc_tx_map[idx], 2901 BUS_DMASYNC_POSTWRITE); 2902 bus_dmamap_unload(sc->dc_mtag, 2903 sc->dc_cdata.dc_tx_map[idx]); 2904 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2905 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2906 } 2907 2908 sc->dc_cdata.dc_tx_cnt--; 2909 DC_INC(idx, DC_TX_LIST_CNT); 2910 } 2911 2912 if (idx != sc->dc_cdata.dc_tx_cons) { 2913 /* Some buffers have been freed. */ 2914 sc->dc_cdata.dc_tx_cons = idx; 2915 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2916 } 2917 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2918 } 2919 2920 static void 2921 dc_tick(void *xsc) 2922 { 2923 struct dc_softc *sc; 2924 struct mii_data *mii; 2925 struct ifnet *ifp; 2926 u_int32_t r; 2927 2928 sc = xsc; 2929 DC_LOCK_ASSERT(sc); 2930 ifp = sc->dc_ifp; 2931 mii = device_get_softc(sc->dc_miibus); 2932 2933 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2934 if (sc->dc_flags & DC_21143_NWAY) { 2935 r = CSR_READ_4(sc, DC_10BTSTAT); 2936 if (IFM_SUBTYPE(mii->mii_media_active) == 2937 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2938 sc->dc_link = 0; 2939 mii_mediachg(mii); 2940 } 2941 if (IFM_SUBTYPE(mii->mii_media_active) == 2942 IFM_10_T && (r & DC_TSTAT_LS10)) { 2943 sc->dc_link = 0; 2944 mii_mediachg(mii); 2945 } 2946 if (sc->dc_link == 0) 2947 mii_tick(mii); 2948 } else { 2949 r = CSR_READ_4(sc, DC_ISR); 2950 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2951 sc->dc_cdata.dc_tx_cnt == 0) { 2952 mii_tick(mii); 2953 if (!(mii->mii_media_status & IFM_ACTIVE)) 2954 sc->dc_link = 0; 2955 } 2956 } 2957 } else 2958 mii_tick(mii); 2959 2960 /* 2961 * When the init routine completes, we expect to be able to send 2962 * packets right away, and in fact the network code will send a 2963 * gratuitous ARP the moment the init routine marks the interface 2964 * as running. However, even though the MAC may have been initialized, 2965 * there may be a delay of a few seconds before the PHY completes 2966 * autonegotiation and the link is brought up. Any transmissions 2967 * made during that delay will be lost. Dealing with this is tricky: 2968 * we can't just pause in the init routine while waiting for the 2969 * PHY to come ready since that would bring the whole system to 2970 * a screeching halt for several seconds. 2971 * 2972 * What we do here is prevent the TX start routine from sending 2973 * any packets until a link has been established. After the 2974 * interface has been initialized, the tick routine will poll 2975 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2976 * that time, packets will stay in the send queue, and once the 2977 * link comes up, they will be flushed out to the wire. 2978 */ 2979 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2980 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2981 sc->dc_link++; 2982 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2983 dc_start_locked(ifp); 2984 } 2985 2986 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2987 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2988 else 2989 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2990 } 2991 2992 /* 2993 * A transmit underrun has occurred. Back off the transmit threshold, 2994 * or switch to store and forward mode if we have to. 2995 */ 2996 static void 2997 dc_tx_underrun(struct dc_softc *sc) 2998 { 2999 u_int32_t isr; 3000 int i; 3001 3002 if (DC_IS_DAVICOM(sc)) 3003 dc_init_locked(sc); 3004 3005 if (DC_IS_INTEL(sc)) { 3006 /* 3007 * The real 21143 requires that the transmitter be idle 3008 * in order to change the transmit threshold or store 3009 * and forward state. 3010 */ 3011 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3012 3013 for (i = 0; i < DC_TIMEOUT; i++) { 3014 isr = CSR_READ_4(sc, DC_ISR); 3015 if (isr & DC_ISR_TX_IDLE) 3016 break; 3017 DELAY(10); 3018 } 3019 if (i == DC_TIMEOUT) { 3020 if_printf(sc->dc_ifp, 3021 "failed to force tx to idle state\n"); 3022 dc_init_locked(sc); 3023 } 3024 } 3025 3026 if_printf(sc->dc_ifp, "TX underrun -- "); 3027 sc->dc_txthresh += DC_TXTHRESH_INC; 3028 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3029 printf("using store and forward mode\n"); 3030 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3031 } else { 3032 printf("increasing TX threshold\n"); 3033 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3034 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3035 } 3036 3037 if (DC_IS_INTEL(sc)) 3038 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3039 } 3040 3041 #ifdef DEVICE_POLLING 3042 static poll_handler_t dc_poll; 3043 3044 static void 3045 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3046 { 3047 struct dc_softc *sc = ifp->if_softc; 3048 3049 DC_LOCK(sc); 3050 3051 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3052 DC_UNLOCK(sc); 3053 return; 3054 } 3055 3056 sc->rxcycles = count; 3057 dc_rxeof(sc); 3058 dc_txeof(sc); 3059 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3060 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3061 dc_start_locked(ifp); 3062 3063 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3064 u_int32_t status; 3065 3066 status = CSR_READ_4(sc, DC_ISR); 3067 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3068 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3069 DC_ISR_BUS_ERR); 3070 if (!status) { 3071 DC_UNLOCK(sc); 3072 return; 3073 } 3074 /* ack what we have */ 3075 CSR_WRITE_4(sc, DC_ISR, status); 3076 3077 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3078 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3079 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3080 3081 if (dc_rx_resync(sc)) 3082 dc_rxeof(sc); 3083 } 3084 /* restart transmit unit if necessary */ 3085 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3086 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3087 3088 if (status & DC_ISR_TX_UNDERRUN) 3089 dc_tx_underrun(sc); 3090 3091 if (status & DC_ISR_BUS_ERR) { 3092 if_printf(ifp, "dc_poll: bus error\n"); 3093 dc_reset(sc); 3094 dc_init_locked(sc); 3095 } 3096 } 3097 DC_UNLOCK(sc); 3098 } 3099 #endif /* DEVICE_POLLING */ 3100 3101 static void 3102 dc_intr(void *arg) 3103 { 3104 struct dc_softc *sc; 3105 struct ifnet *ifp; 3106 u_int32_t status; 3107 3108 sc = arg; 3109 3110 if (sc->suspended) 3111 return; 3112 3113 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3114 return; 3115 3116 DC_LOCK(sc); 3117 ifp = sc->dc_ifp; 3118 #ifdef DEVICE_POLLING 3119 if (ifp->if_capenable & IFCAP_POLLING) { 3120 DC_UNLOCK(sc); 3121 return; 3122 } 3123 #endif 3124 3125 /* Suppress unwanted interrupts */ 3126 if (!(ifp->if_flags & IFF_UP)) { 3127 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3128 dc_stop(sc); 3129 DC_UNLOCK(sc); 3130 return; 3131 } 3132 3133 /* Disable interrupts. */ 3134 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3135 3136 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 3137 status != 0xFFFFFFFF && 3138 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3139 3140 CSR_WRITE_4(sc, DC_ISR, status); 3141 3142 if (status & DC_ISR_RX_OK) { 3143 int curpkts; 3144 curpkts = ifp->if_ipackets; 3145 dc_rxeof(sc); 3146 if (curpkts == ifp->if_ipackets) { 3147 while (dc_rx_resync(sc)) 3148 dc_rxeof(sc); 3149 } 3150 } 3151 3152 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3153 dc_txeof(sc); 3154 3155 if (status & DC_ISR_TX_IDLE) { 3156 dc_txeof(sc); 3157 if (sc->dc_cdata.dc_tx_cnt) { 3158 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3159 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3160 } 3161 } 3162 3163 if (status & DC_ISR_TX_UNDERRUN) 3164 dc_tx_underrun(sc); 3165 3166 if ((status & DC_ISR_RX_WATDOGTIMEO) 3167 || (status & DC_ISR_RX_NOBUF)) { 3168 int curpkts; 3169 curpkts = ifp->if_ipackets; 3170 dc_rxeof(sc); 3171 if (curpkts == ifp->if_ipackets) { 3172 while (dc_rx_resync(sc)) 3173 dc_rxeof(sc); 3174 } 3175 } 3176 3177 if (status & DC_ISR_BUS_ERR) { 3178 dc_reset(sc); 3179 dc_init_locked(sc); 3180 } 3181 } 3182 3183 /* Re-enable interrupts. */ 3184 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3185 3186 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3187 dc_start_locked(ifp); 3188 3189 DC_UNLOCK(sc); 3190 } 3191 3192 static void 3193 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3194 void *arg; 3195 bus_dma_segment_t *segs; 3196 int nseg; 3197 bus_size_t mapsize; 3198 int error; 3199 { 3200 struct dc_softc *sc; 3201 struct dc_desc *f; 3202 int cur, first, frag, i; 3203 3204 sc = arg; 3205 if (error) { 3206 sc->dc_cdata.dc_tx_err = error; 3207 return; 3208 } 3209 3210 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3211 for (i = 0; i < nseg; i++) { 3212 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3213 (frag == (DC_TX_LIST_CNT - 1)) && 3214 (first != sc->dc_cdata.dc_tx_first)) { 3215 bus_dmamap_unload(sc->dc_mtag, 3216 sc->dc_cdata.dc_tx_map[first]); 3217 sc->dc_cdata.dc_tx_err = ENOBUFS; 3218 return; 3219 } 3220 3221 f = &sc->dc_ldata->dc_tx_list[frag]; 3222 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3223 if (i == 0) { 3224 f->dc_status = 0; 3225 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3226 } else 3227 f->dc_status = htole32(DC_TXSTAT_OWN); 3228 f->dc_data = htole32(segs[i].ds_addr); 3229 cur = frag; 3230 DC_INC(frag, DC_TX_LIST_CNT); 3231 } 3232 3233 sc->dc_cdata.dc_tx_err = 0; 3234 sc->dc_cdata.dc_tx_prod = frag; 3235 sc->dc_cdata.dc_tx_cnt += nseg; 3236 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3237 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3238 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3239 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3240 htole32(DC_TXCTL_FINT); 3241 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3242 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3243 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3244 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3245 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3246 } 3247 3248 /* 3249 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3250 * pointers to the fragment pointers. 3251 */ 3252 static int 3253 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3254 { 3255 struct mbuf *m; 3256 int error, idx, chainlen = 0; 3257 3258 /* 3259 * If there's no way we can send any packets, return now. 3260 */ 3261 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3262 return (ENOBUFS); 3263 3264 /* 3265 * Count the number of frags in this chain to see if 3266 * we need to m_defrag. Since the descriptor list is shared 3267 * by all packets, we'll m_defrag long chains so that they 3268 * do not use up the entire list, even if they would fit. 3269 */ 3270 for (m = *m_head; m != NULL; m = m->m_next) 3271 chainlen++; 3272 3273 if ((chainlen > DC_TX_LIST_CNT / 4) || 3274 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3275 m = m_defrag(*m_head, M_DONTWAIT); 3276 if (m == NULL) 3277 return (ENOBUFS); 3278 *m_head = m; 3279 } 3280 3281 /* 3282 * Start packing the mbufs in this chain into 3283 * the fragment pointers. Stop when we run out 3284 * of fragments or hit the end of the mbuf chain. 3285 */ 3286 idx = sc->dc_cdata.dc_tx_prod; 3287 sc->dc_cdata.dc_tx_mapping = *m_head; 3288 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3289 *m_head, dc_dma_map_txbuf, sc, 0); 3290 if (error) 3291 return (error); 3292 if (sc->dc_cdata.dc_tx_err != 0) 3293 return (sc->dc_cdata.dc_tx_err); 3294 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3295 BUS_DMASYNC_PREWRITE); 3296 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3297 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3298 return (0); 3299 } 3300 3301 /* 3302 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3303 * to the mbuf data regions directly in the transmit lists. We also save a 3304 * copy of the pointers since the transmit list fragment pointers are 3305 * physical addresses. 3306 */ 3307 3308 static void 3309 dc_start(struct ifnet *ifp) 3310 { 3311 struct dc_softc *sc; 3312 3313 sc = ifp->if_softc; 3314 DC_LOCK(sc); 3315 dc_start_locked(ifp); 3316 DC_UNLOCK(sc); 3317 } 3318 3319 static void 3320 dc_start_locked(struct ifnet *ifp) 3321 { 3322 struct dc_softc *sc; 3323 struct mbuf *m_head = NULL, *m; 3324 unsigned int queued = 0; 3325 int idx; 3326 3327 sc = ifp->if_softc; 3328 3329 DC_LOCK_ASSERT(sc); 3330 3331 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3332 return; 3333 3334 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3335 return; 3336 3337 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3338 3339 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3340 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3341 if (m_head == NULL) 3342 break; 3343 3344 if (sc->dc_flags & DC_TX_COALESCE && 3345 (m_head->m_next != NULL || 3346 sc->dc_flags & DC_TX_ALIGN)) { 3347 m = m_defrag(m_head, M_DONTWAIT); 3348 if (m == NULL) { 3349 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3350 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3351 break; 3352 } else { 3353 m_head = m; 3354 } 3355 } 3356 3357 if (dc_encap(sc, &m_head)) { 3358 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3359 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3360 break; 3361 } 3362 idx = sc->dc_cdata.dc_tx_prod; 3363 3364 queued++; 3365 /* 3366 * If there's a BPF listener, bounce a copy of this frame 3367 * to him. 3368 */ 3369 BPF_MTAP(ifp, m_head); 3370 3371 if (sc->dc_flags & DC_TX_ONE) { 3372 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3373 break; 3374 } 3375 } 3376 3377 if (queued > 0) { 3378 /* Transmit */ 3379 if (!(sc->dc_flags & DC_TX_POLL)) 3380 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3381 3382 /* 3383 * Set a timeout in case the chip goes out to lunch. 3384 */ 3385 ifp->if_timer = 5; 3386 } 3387 } 3388 3389 static void 3390 dc_init(void *xsc) 3391 { 3392 struct dc_softc *sc = xsc; 3393 3394 DC_LOCK(sc); 3395 dc_init_locked(sc); 3396 #ifdef SRM_MEDIA 3397 if(sc->dc_srm_media) { 3398 struct ifreq ifr; 3399 struct mii_data *mii; 3400 3401 ifr.ifr_media = sc->dc_srm_media; 3402 sc->dc_srm_media = 0; 3403 DC_UNLOCK(sc); 3404 mii = device_get_softc(sc->dc_miibus); 3405 ifmedia_ioctl(sc->dc_ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3406 } else 3407 #endif 3408 DC_UNLOCK(sc); 3409 } 3410 3411 static void 3412 dc_init_locked(struct dc_softc *sc) 3413 { 3414 struct ifnet *ifp = sc->dc_ifp; 3415 struct mii_data *mii; 3416 3417 DC_LOCK_ASSERT(sc); 3418 3419 mii = device_get_softc(sc->dc_miibus); 3420 3421 /* 3422 * Cancel pending I/O and free all RX/TX buffers. 3423 */ 3424 dc_stop(sc); 3425 dc_reset(sc); 3426 3427 /* 3428 * Set cache alignment and burst length. 3429 */ 3430 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3431 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3432 else 3433 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3434 /* 3435 * Evenly share the bus between receive and transmit process. 3436 */ 3437 if (DC_IS_INTEL(sc)) 3438 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3439 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3440 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3441 } else { 3442 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3443 } 3444 if (sc->dc_flags & DC_TX_POLL) 3445 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3446 switch(sc->dc_cachesize) { 3447 case 32: 3448 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3449 break; 3450 case 16: 3451 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3452 break; 3453 case 8: 3454 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3455 break; 3456 case 0: 3457 default: 3458 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3459 break; 3460 } 3461 3462 if (sc->dc_flags & DC_TX_STORENFWD) 3463 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3464 else { 3465 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3466 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3467 } else { 3468 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3469 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3470 } 3471 } 3472 3473 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3474 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3475 3476 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3477 /* 3478 * The app notes for the 98713 and 98715A say that 3479 * in order to have the chips operate properly, a magic 3480 * number must be written to CSR16. Macronix does not 3481 * document the meaning of these bits so there's no way 3482 * to know exactly what they do. The 98713 has a magic 3483 * number all its own; the rest all use a different one. 3484 */ 3485 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3486 if (sc->dc_type == DC_TYPE_98713) 3487 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3488 else 3489 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3490 } 3491 3492 if (DC_IS_XIRCOM(sc)) { 3493 /* 3494 * setup General Purpose Port mode and data so the tulip 3495 * can talk to the MII. 3496 */ 3497 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3498 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3499 DELAY(10); 3500 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3501 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3502 DELAY(10); 3503 } 3504 3505 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3506 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3507 3508 /* Init circular RX list. */ 3509 if (dc_list_rx_init(sc) == ENOBUFS) { 3510 if_printf(ifp, 3511 "initialization failed: no memory for rx buffers\n"); 3512 dc_stop(sc); 3513 return; 3514 } 3515 3516 /* 3517 * Init TX descriptors. 3518 */ 3519 dc_list_tx_init(sc); 3520 3521 /* 3522 * Load the address of the RX list. 3523 */ 3524 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3525 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3526 3527 /* 3528 * Enable interrupts. 3529 */ 3530 #ifdef DEVICE_POLLING 3531 /* 3532 * ... but only if we are not polling, and make sure they are off in 3533 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3534 * after a reset. 3535 */ 3536 if (ifp->if_capenable & IFCAP_POLLING) 3537 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3538 else 3539 #endif 3540 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3541 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3542 3543 /* Enable transmitter. */ 3544 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3545 3546 /* 3547 * If this is an Intel 21143 and we're not using the 3548 * MII port, program the LED control pins so we get 3549 * link and activity indications. 3550 */ 3551 if (sc->dc_flags & DC_TULIP_LEDS) { 3552 CSR_WRITE_4(sc, DC_WATCHDOG, 3553 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3554 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3555 } 3556 3557 /* 3558 * Load the RX/multicast filter. We do this sort of late 3559 * because the filter programming scheme on the 21143 and 3560 * some clones requires DMAing a setup frame via the TX 3561 * engine, and we need the transmitter enabled for that. 3562 */ 3563 dc_setfilt(sc); 3564 3565 /* Enable receiver. */ 3566 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3567 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3568 3569 mii_mediachg(mii); 3570 dc_setcfg(sc, sc->dc_if_media); 3571 3572 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3573 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3574 3575 /* Don't start the ticker if this is a homePNA link. */ 3576 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3577 sc->dc_link = 1; 3578 else { 3579 if (sc->dc_flags & DC_21143_NWAY) 3580 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3581 else 3582 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3583 } 3584 } 3585 3586 /* 3587 * Set media options. 3588 */ 3589 static int 3590 dc_ifmedia_upd(struct ifnet *ifp) 3591 { 3592 struct dc_softc *sc; 3593 struct mii_data *mii; 3594 struct ifmedia *ifm; 3595 3596 sc = ifp->if_softc; 3597 mii = device_get_softc(sc->dc_miibus); 3598 DC_LOCK(sc); 3599 mii_mediachg(mii); 3600 ifm = &mii->mii_media; 3601 3602 if (DC_IS_DAVICOM(sc) && 3603 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3604 dc_setcfg(sc, ifm->ifm_media); 3605 else 3606 sc->dc_link = 0; 3607 DC_UNLOCK(sc); 3608 3609 return (0); 3610 } 3611 3612 /* 3613 * Report current media status. 3614 */ 3615 static void 3616 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3617 { 3618 struct dc_softc *sc; 3619 struct mii_data *mii; 3620 struct ifmedia *ifm; 3621 3622 sc = ifp->if_softc; 3623 mii = device_get_softc(sc->dc_miibus); 3624 DC_LOCK(sc); 3625 mii_pollstat(mii); 3626 ifm = &mii->mii_media; 3627 if (DC_IS_DAVICOM(sc)) { 3628 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3629 ifmr->ifm_active = ifm->ifm_media; 3630 ifmr->ifm_status = 0; 3631 return; 3632 } 3633 } 3634 ifmr->ifm_active = mii->mii_media_active; 3635 ifmr->ifm_status = mii->mii_media_status; 3636 DC_UNLOCK(sc); 3637 } 3638 3639 static int 3640 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3641 { 3642 struct dc_softc *sc = ifp->if_softc; 3643 struct ifreq *ifr = (struct ifreq *)data; 3644 struct mii_data *mii; 3645 int error = 0; 3646 3647 switch (command) { 3648 case SIOCSIFFLAGS: 3649 DC_LOCK(sc); 3650 if (ifp->if_flags & IFF_UP) { 3651 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3652 (IFF_PROMISC | IFF_ALLMULTI); 3653 3654 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3655 if (need_setfilt) 3656 dc_setfilt(sc); 3657 } else { 3658 sc->dc_txthresh = 0; 3659 dc_init_locked(sc); 3660 } 3661 } else { 3662 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3663 dc_stop(sc); 3664 } 3665 sc->dc_if_flags = ifp->if_flags; 3666 DC_UNLOCK(sc); 3667 error = 0; 3668 break; 3669 case SIOCADDMULTI: 3670 case SIOCDELMULTI: 3671 DC_LOCK(sc); 3672 dc_setfilt(sc); 3673 DC_UNLOCK(sc); 3674 error = 0; 3675 break; 3676 case SIOCGIFMEDIA: 3677 case SIOCSIFMEDIA: 3678 mii = device_get_softc(sc->dc_miibus); 3679 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3680 #ifdef SRM_MEDIA 3681 DC_LOCK(sc); 3682 if (sc->dc_srm_media) 3683 sc->dc_srm_media = 0; 3684 DC_UNLOCK(sc); 3685 #endif 3686 break; 3687 case SIOCSIFCAP: 3688 #ifdef DEVICE_POLLING 3689 if (ifr->ifr_reqcap & IFCAP_POLLING && 3690 !(ifp->if_capenable & IFCAP_POLLING)) { 3691 error = ether_poll_register(dc_poll, ifp); 3692 if (error) 3693 return(error); 3694 DC_LOCK(sc); 3695 /* Disable interrupts */ 3696 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3697 ifp->if_capenable |= IFCAP_POLLING; 3698 DC_UNLOCK(sc); 3699 return (error); 3700 3701 } 3702 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3703 ifp->if_capenable & IFCAP_POLLING) { 3704 error = ether_poll_deregister(ifp); 3705 /* Enable interrupts. */ 3706 DC_LOCK(sc); 3707 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3708 ifp->if_capenable &= ~IFCAP_POLLING; 3709 DC_UNLOCK(sc); 3710 return (error); 3711 } 3712 #endif /* DEVICE_POLLING */ 3713 break; 3714 default: 3715 error = ether_ioctl(ifp, command, data); 3716 break; 3717 } 3718 3719 return (error); 3720 } 3721 3722 static void 3723 dc_watchdog(struct ifnet *ifp) 3724 { 3725 struct dc_softc *sc; 3726 3727 sc = ifp->if_softc; 3728 3729 DC_LOCK(sc); 3730 3731 ifp->if_oerrors++; 3732 if_printf(ifp, "watchdog timeout\n"); 3733 3734 dc_stop(sc); 3735 dc_reset(sc); 3736 dc_init_locked(sc); 3737 3738 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3739 dc_start_locked(ifp); 3740 3741 DC_UNLOCK(sc); 3742 } 3743 3744 /* 3745 * Stop the adapter and free any mbufs allocated to the 3746 * RX and TX lists. 3747 */ 3748 static void 3749 dc_stop(struct dc_softc *sc) 3750 { 3751 struct ifnet *ifp; 3752 struct dc_list_data *ld; 3753 struct dc_chain_data *cd; 3754 int i; 3755 u_int32_t ctl; 3756 3757 DC_LOCK_ASSERT(sc); 3758 3759 ifp = sc->dc_ifp; 3760 ifp->if_timer = 0; 3761 ld = sc->dc_ldata; 3762 cd = &sc->dc_cdata; 3763 3764 callout_stop(&sc->dc_stat_ch); 3765 3766 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3767 3768 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3769 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3770 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3771 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3772 sc->dc_link = 0; 3773 3774 /* 3775 * Free data in the RX lists. 3776 */ 3777 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3778 if (cd->dc_rx_chain[i] != NULL) { 3779 m_freem(cd->dc_rx_chain[i]); 3780 cd->dc_rx_chain[i] = NULL; 3781 } 3782 } 3783 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3784 3785 /* 3786 * Free the TX list buffers. 3787 */ 3788 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3789 if (cd->dc_tx_chain[i] != NULL) { 3790 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3791 if ((ctl & DC_TXCTL_SETUP) || 3792 !(ctl & DC_TXCTL_LASTFRAG)) { 3793 cd->dc_tx_chain[i] = NULL; 3794 continue; 3795 } 3796 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3797 m_freem(cd->dc_tx_chain[i]); 3798 cd->dc_tx_chain[i] = NULL; 3799 } 3800 } 3801 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3802 } 3803 3804 /* 3805 * Device suspend routine. Stop the interface and save some PCI 3806 * settings in case the BIOS doesn't restore them properly on 3807 * resume. 3808 */ 3809 static int 3810 dc_suspend(device_t dev) 3811 { 3812 struct dc_softc *sc; 3813 3814 sc = device_get_softc(dev); 3815 DC_LOCK(sc); 3816 dc_stop(sc); 3817 sc->suspended = 1; 3818 DC_UNLOCK(sc); 3819 3820 return (0); 3821 } 3822 3823 /* 3824 * Device resume routine. Restore some PCI settings in case the BIOS 3825 * doesn't, re-enable busmastering, and restart the interface if 3826 * appropriate. 3827 */ 3828 static int 3829 dc_resume(device_t dev) 3830 { 3831 struct dc_softc *sc; 3832 struct ifnet *ifp; 3833 3834 sc = device_get_softc(dev); 3835 ifp = sc->dc_ifp; 3836 3837 /* reinitialize interface if necessary */ 3838 DC_LOCK(sc); 3839 if (ifp->if_flags & IFF_UP) 3840 dc_init_locked(sc); 3841 3842 sc->suspended = 0; 3843 DC_UNLOCK(sc); 3844 3845 return (0); 3846 } 3847 3848 /* 3849 * Stop all chip I/O so that the kernel's probe routines don't 3850 * get confused by errant DMAs when rebooting. 3851 */ 3852 static void 3853 dc_shutdown(device_t dev) 3854 { 3855 struct dc_softc *sc; 3856 3857 sc = device_get_softc(dev); 3858 3859 DC_LOCK(sc); 3860 dc_stop(sc); 3861 DC_UNLOCK(sc); 3862 }
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