FreeBSD/Linux Kernel Cross Reference
sys/pci/if_dc.c
1 /*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/6.2/sys/pci/if_dc.c 164257 2006-11-13 17:24:24Z marius $");
35
36 /*
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
39 *
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN985 (www.admtek.com.tw)
47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985
48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
49 * Accton EN1217 (www.accton.com)
50 * Xircom X3201 (www.xircom.com)
51 * Abocom FE2500
52 * Conexant LANfinity (www.conexant.com)
53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com)
54 *
55 * Datasheets for the 21143 are available at developer.intel.com.
56 * Datasheets for the clone parts can be found at their respective sites.
57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
58 * The PNIC II is essentially a Macronix 98715A chip; the only difference
59 * worth noting is that its multicast hash table is only 128 bits wide
60 * instead of 512.
61 *
62 * Written by Bill Paul <wpaul@ee.columbia.edu>
63 * Electrical Engineering Department
64 * Columbia University, New York City
65 */
66 /*
67 * The Intel 21143 is the successor to the DEC 21140. It is basically
68 * the same as the 21140 but with a few new features. The 21143 supports
69 * three kinds of media attachments:
70 *
71 * o MII port, for 10Mbps and 100Mbps support and NWAY
72 * autonegotiation provided by an external PHY.
73 * o SYM port, for symbol mode 100Mbps support.
74 * o 10baseT port.
75 * o AUI/BNC port.
76 *
77 * The 100Mbps SYM port and 10baseT port can be used together in
78 * combination with the internal NWAY support to create a 10/100
79 * autosensing configuration.
80 *
81 * Note that not all tulip workalikes are handled in this driver: we only
82 * deal with those which are relatively well behaved. The Winbond is
83 * handled separately due to its different register offsets and the
84 * special handling needed for its various bugs. The PNIC is handled
85 * here, but I'm not thrilled about it.
86 *
87 * All of the workalike chips use some form of MII transceiver support
88 * with the exception of the Macronix chips, which also have a SYM port.
89 * The ASIX AX88140A is also documented to have a SYM port, but all
90 * the cards I've seen use an MII transceiver, probably because the
91 * AX88140A doesn't support internal NWAY.
92 */
93
94 #ifdef HAVE_KERNEL_OPTION_HEADERS
95 #include "opt_device_polling.h"
96 #endif
97
98 #include <sys/param.h>
99 #include <sys/endian.h>
100 #include <sys/systm.h>
101 #include <sys/sockio.h>
102 #include <sys/mbuf.h>
103 #include <sys/malloc.h>
104 #include <sys/kernel.h>
105 #include <sys/module.h>
106 #include <sys/socket.h>
107 #include <sys/sysctl.h>
108
109 #include <net/if.h>
110 #include <net/if_arp.h>
111 #include <net/ethernet.h>
112 #include <net/if_dl.h>
113 #include <net/if_media.h>
114 #include <net/if_types.h>
115 #include <net/if_vlan_var.h>
116
117 #include <net/bpf.h>
118
119 #include <machine/bus.h>
120 #include <machine/resource.h>
121 #include <sys/bus.h>
122 #include <sys/rman.h>
123
124 #include <dev/mii/mii.h>
125 #include <dev/mii/miivar.h>
126
127 #include <dev/pci/pcireg.h>
128 #include <dev/pci/pcivar.h>
129
130 #define DC_USEIOSPACE
131 #ifdef __alpha__
132 #define SRM_MEDIA
133 #endif
134
135 #include <pci/if_dcreg.h>
136
137 #ifdef __sparc64__
138 #include <dev/ofw/openfirm.h>
139 #include <machine/ofw_machdep.h>
140 #endif
141
142 MODULE_DEPEND(dc, pci, 1, 1, 1);
143 MODULE_DEPEND(dc, ether, 1, 1, 1);
144 MODULE_DEPEND(dc, miibus, 1, 1, 1);
145
146 /* "controller miibus0" required. See GENERIC if you get errors here. */
147 #include "miibus_if.h"
148
149 /*
150 * Various supported device vendors/types and their names.
151 */
152 static struct dc_type dc_devs[] = {
153 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0,
154 "Intel 21143 10/100BaseTX" },
155 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0,
156 "Davicom DM9009 10/100BaseTX" },
157 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0,
158 "Davicom DM9100 10/100BaseTX" },
159 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A,
160 "Davicom DM9102A 10/100BaseTX" },
161 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0,
162 "Davicom DM9102 10/100BaseTX" },
163 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0,
164 "ADMtek AL981 10/100BaseTX" },
165 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0,
166 "ADMtek AN985 10/100BaseTX" },
167 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0,
168 "ADMtek ADM9511 10/100BaseTX" },
169 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0,
170 "ADMtek ADM9513 10/100BaseTX" },
171 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511), 0,
172 "Netgear FA511 10/100BaseTX" },
173 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141,
174 "ASIX AX88141 10/100BaseTX" },
175 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0,
176 "ASIX AX88140A 10/100BaseTX" },
177 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A,
178 "Macronix 98713A 10/100BaseTX" },
179 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0,
180 "Macronix 98713 10/100BaseTX" },
181 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A,
182 "Compex RL100-TX 10/100BaseTX" },
183 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0,
184 "Compex RL100-TX 10/100BaseTX" },
185 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725,
186 "Macronix 98725 10/100BaseTX" },
187 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C,
188 "Macronix 98715AEC-C 10/100BaseTX" },
189 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0,
190 "Macronix 98715/98715A 10/100BaseTX" },
191 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0,
192 "Macronix 98727/98732 10/100BaseTX" },
193 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0,
194 "LC82C115 PNIC II 10/100BaseTX" },
195 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169,
196 "82c169 PNIC 10/100BaseTX" },
197 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0,
198 "82c168 PNIC 10/100BaseTX" },
199 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0,
200 "Accton EN1217 10/100BaseTX" },
201 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0,
202 "Accton EN2242 MiniPCI 10/100BaseTX" },
203 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0,
204 "Xircom X3201 10/100BaseTX" },
205 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0,
206 "Neteasy DRP-32TXD Cardbus 10/100" },
207 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0,
208 "Abocom FE2500 10/100BaseTX" },
209 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0,
210 "Abocom FE2500MX 10/100BaseTX" },
211 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0,
212 "Conexant LANfinity MiniPCI 10/100BaseTX" },
213 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0,
214 "Hawking CB102 CardBus 10/100" },
215 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0,
216 "PlaneX FNW-3602-T CardBus 10/100" },
217 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0,
218 "3Com OfficeConnect 10/100B" },
219 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0,
220 "Microsoft MN-120 CardBus 10/100" },
221 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0,
222 "Microsoft MN-130 10/100" },
223 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0,
224 "Linksys PCMPC200 CardBus 10/100" },
225 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0,
226 "Linksys PCMPC200 CardBus 10/100" },
227 { 0, 0, NULL }
228 };
229
230 static int dc_probe(device_t);
231 static int dc_attach(device_t);
232 static int dc_detach(device_t);
233 static int dc_suspend(device_t);
234 static int dc_resume(device_t);
235 static struct dc_type *dc_devtype(device_t);
236 static int dc_newbuf(struct dc_softc *, int, int);
237 static int dc_encap(struct dc_softc *, struct mbuf **);
238 static void dc_pnic_rx_bug_war(struct dc_softc *, int);
239 static int dc_rx_resync(struct dc_softc *);
240 static void dc_rxeof(struct dc_softc *);
241 static void dc_txeof(struct dc_softc *);
242 static void dc_tick(void *);
243 static void dc_tx_underrun(struct dc_softc *);
244 static void dc_intr(void *);
245 static void dc_start(struct ifnet *);
246 static void dc_start_locked(struct ifnet *);
247 static int dc_ioctl(struct ifnet *, u_long, caddr_t);
248 static void dc_init(void *);
249 static void dc_init_locked(struct dc_softc *);
250 static void dc_stop(struct dc_softc *);
251 static void dc_watchdog(struct ifnet *);
252 static void dc_shutdown(device_t);
253 static int dc_ifmedia_upd(struct ifnet *);
254 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
255
256 static void dc_delay(struct dc_softc *);
257 static void dc_eeprom_idle(struct dc_softc *);
258 static void dc_eeprom_putbyte(struct dc_softc *, int);
259 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *);
260 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *);
261 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *);
262 static void dc_eeprom_width(struct dc_softc *);
263 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
264
265 static void dc_mii_writebit(struct dc_softc *, int);
266 static int dc_mii_readbit(struct dc_softc *);
267 static void dc_mii_sync(struct dc_softc *);
268 static void dc_mii_send(struct dc_softc *, u_int32_t, int);
269 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *);
270 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *);
271 static int dc_miibus_readreg(device_t, int, int);
272 static int dc_miibus_writereg(device_t, int, int, int);
273 static void dc_miibus_statchg(device_t);
274 static void dc_miibus_mediainit(device_t);
275
276 static void dc_setcfg(struct dc_softc *, int);
277 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *);
278 static uint32_t dc_mchash_be(const uint8_t *);
279 static void dc_setfilt_21143(struct dc_softc *);
280 static void dc_setfilt_asix(struct dc_softc *);
281 static void dc_setfilt_admtek(struct dc_softc *);
282 static void dc_setfilt_xircom(struct dc_softc *);
283
284 static void dc_setfilt(struct dc_softc *);
285
286 static void dc_reset(struct dc_softc *);
287 static int dc_list_rx_init(struct dc_softc *);
288 static int dc_list_tx_init(struct dc_softc *);
289
290 static void dc_read_srom(struct dc_softc *, int);
291 static void dc_parse_21143_srom(struct dc_softc *);
292 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
293 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
294 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
295 static void dc_apply_fixup(struct dc_softc *, int);
296
297 static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
298 static void dc_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
299
300 #ifdef DC_USEIOSPACE
301 #define DC_RES SYS_RES_IOPORT
302 #define DC_RID DC_PCI_CFBIO
303 #else
304 #define DC_RES SYS_RES_MEMORY
305 #define DC_RID DC_PCI_CFBMA
306 #endif
307
308 static device_method_t dc_methods[] = {
309 /* Device interface */
310 DEVMETHOD(device_probe, dc_probe),
311 DEVMETHOD(device_attach, dc_attach),
312 DEVMETHOD(device_detach, dc_detach),
313 DEVMETHOD(device_suspend, dc_suspend),
314 DEVMETHOD(device_resume, dc_resume),
315 DEVMETHOD(device_shutdown, dc_shutdown),
316
317 /* bus interface */
318 DEVMETHOD(bus_print_child, bus_generic_print_child),
319 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
320
321 /* MII interface */
322 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
323 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
324 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
325 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
326
327 { 0, 0 }
328 };
329
330 static driver_t dc_driver = {
331 "dc",
332 dc_methods,
333 sizeof(struct dc_softc)
334 };
335
336 static devclass_t dc_devclass;
337 #ifdef __NO_STRICT_ALIGNMENT
338 static int dc_quick = 1;
339 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0,
340 "do not m_devget() in dc driver");
341 #endif
342
343 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0);
344 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0);
345 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
346
347 #define DC_SETBIT(sc, reg, x) \
348 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
349
350 #define DC_CLRBIT(sc, reg, x) \
351 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
352
353 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
354 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
355
356 static void
357 dc_delay(struct dc_softc *sc)
358 {
359 int idx;
360
361 for (idx = (300 / 33) + 1; idx > 0; idx--)
362 CSR_READ_4(sc, DC_BUSCTL);
363 }
364
365 static void
366 dc_eeprom_width(struct dc_softc *sc)
367 {
368 int i;
369
370 /* Force EEPROM to idle state. */
371 dc_eeprom_idle(sc);
372
373 /* Enter EEPROM access mode. */
374 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
375 dc_delay(sc);
376 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
377 dc_delay(sc);
378 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
379 dc_delay(sc);
380 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
381 dc_delay(sc);
382
383 for (i = 3; i--;) {
384 if (6 & (1 << i))
385 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
386 else
387 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
388 dc_delay(sc);
389 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
390 dc_delay(sc);
391 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
392 dc_delay(sc);
393 }
394
395 for (i = 1; i <= 12; i++) {
396 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
397 dc_delay(sc);
398 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
399 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
400 dc_delay(sc);
401 break;
402 }
403 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
404 dc_delay(sc);
405 }
406
407 /* Turn off EEPROM access mode. */
408 dc_eeprom_idle(sc);
409
410 if (i < 4 || i > 12)
411 sc->dc_romwidth = 6;
412 else
413 sc->dc_romwidth = i;
414
415 /* Enter EEPROM access mode. */
416 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
417 dc_delay(sc);
418 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
419 dc_delay(sc);
420 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
421 dc_delay(sc);
422 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
423 dc_delay(sc);
424
425 /* Turn off EEPROM access mode. */
426 dc_eeprom_idle(sc);
427 }
428
429 static void
430 dc_eeprom_idle(struct dc_softc *sc)
431 {
432 int i;
433
434 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
435 dc_delay(sc);
436 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
437 dc_delay(sc);
438 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
439 dc_delay(sc);
440 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
441 dc_delay(sc);
442
443 for (i = 0; i < 25; i++) {
444 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
445 dc_delay(sc);
446 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
447 dc_delay(sc);
448 }
449
450 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
451 dc_delay(sc);
452 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
453 dc_delay(sc);
454 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
455 }
456
457 /*
458 * Send a read command and address to the EEPROM, check for ACK.
459 */
460 static void
461 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
462 {
463 int d, i;
464
465 d = DC_EECMD_READ >> 6;
466 for (i = 3; i--; ) {
467 if (d & (1 << i))
468 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
469 else
470 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
471 dc_delay(sc);
472 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
473 dc_delay(sc);
474 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
475 dc_delay(sc);
476 }
477
478 /*
479 * Feed in each bit and strobe the clock.
480 */
481 for (i = sc->dc_romwidth; i--;) {
482 if (addr & (1 << i)) {
483 SIO_SET(DC_SIO_EE_DATAIN);
484 } else {
485 SIO_CLR(DC_SIO_EE_DATAIN);
486 }
487 dc_delay(sc);
488 SIO_SET(DC_SIO_EE_CLK);
489 dc_delay(sc);
490 SIO_CLR(DC_SIO_EE_CLK);
491 dc_delay(sc);
492 }
493 }
494
495 /*
496 * Read a word of data stored in the EEPROM at address 'addr.'
497 * The PNIC 82c168/82c169 has its own non-standard way to read
498 * the EEPROM.
499 */
500 static void
501 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
502 {
503 int i;
504 u_int32_t r;
505
506 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
507
508 for (i = 0; i < DC_TIMEOUT; i++) {
509 DELAY(1);
510 r = CSR_READ_4(sc, DC_SIO);
511 if (!(r & DC_PN_SIOCTL_BUSY)) {
512 *dest = (u_int16_t)(r & 0xFFFF);
513 return;
514 }
515 }
516 }
517
518 /*
519 * Read a word of data stored in the EEPROM at address 'addr.'
520 * The Xircom X3201 has its own non-standard way to read
521 * the EEPROM, too.
522 */
523 static void
524 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
525 {
526
527 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
528
529 addr *= 2;
530 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
531 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
532 addr += 1;
533 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
534 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
535
536 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
537 }
538
539 /*
540 * Read a word of data stored in the EEPROM at address 'addr.'
541 */
542 static void
543 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
544 {
545 int i;
546 u_int16_t word = 0;
547
548 /* Force EEPROM to idle state. */
549 dc_eeprom_idle(sc);
550
551 /* Enter EEPROM access mode. */
552 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
553 dc_delay(sc);
554 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
555 dc_delay(sc);
556 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
557 dc_delay(sc);
558 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
559 dc_delay(sc);
560
561 /*
562 * Send address of word we want to read.
563 */
564 dc_eeprom_putbyte(sc, addr);
565
566 /*
567 * Start reading bits from EEPROM.
568 */
569 for (i = 0x8000; i; i >>= 1) {
570 SIO_SET(DC_SIO_EE_CLK);
571 dc_delay(sc);
572 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
573 word |= i;
574 dc_delay(sc);
575 SIO_CLR(DC_SIO_EE_CLK);
576 dc_delay(sc);
577 }
578
579 /* Turn off EEPROM access mode. */
580 dc_eeprom_idle(sc);
581
582 *dest = word;
583 }
584
585 /*
586 * Read a sequence of words from the EEPROM.
587 */
588 static void
589 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
590 {
591 int i;
592 u_int16_t word = 0, *ptr;
593
594 for (i = 0; i < cnt; i++) {
595 if (DC_IS_PNIC(sc))
596 dc_eeprom_getword_pnic(sc, off + i, &word);
597 else if (DC_IS_XIRCOM(sc))
598 dc_eeprom_getword_xircom(sc, off + i, &word);
599 else
600 dc_eeprom_getword(sc, off + i, &word);
601 ptr = (u_int16_t *)(dest + (i * 2));
602 if (be)
603 *ptr = be16toh(word);
604 else
605 *ptr = le16toh(word);
606 }
607 }
608
609 /*
610 * The following two routines are taken from the Macronix 98713
611 * Application Notes pp.19-21.
612 */
613 /*
614 * Write a bit to the MII bus.
615 */
616 static void
617 dc_mii_writebit(struct dc_softc *sc, int bit)
618 {
619
620 if (bit)
621 CSR_WRITE_4(sc, DC_SIO,
622 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT);
623 else
624 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
625
626 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
627 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
628 }
629
630 /*
631 * Read a bit from the MII bus.
632 */
633 static int
634 dc_mii_readbit(struct dc_softc *sc)
635 {
636
637 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR);
638 CSR_READ_4(sc, DC_SIO);
639 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
640 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
641 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
642 return (1);
643
644 return (0);
645 }
646
647 /*
648 * Sync the PHYs by setting data bit and strobing the clock 32 times.
649 */
650 static void
651 dc_mii_sync(struct dc_softc *sc)
652 {
653 int i;
654
655 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
656
657 for (i = 0; i < 32; i++)
658 dc_mii_writebit(sc, 1);
659 }
660
661 /*
662 * Clock a series of bits through the MII.
663 */
664 static void
665 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
666 {
667 int i;
668
669 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
670 dc_mii_writebit(sc, bits & i);
671 }
672
673 /*
674 * Read an PHY register through the MII.
675 */
676 static int
677 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
678 {
679 int i, ack;
680
681 /*
682 * Set up frame for RX.
683 */
684 frame->mii_stdelim = DC_MII_STARTDELIM;
685 frame->mii_opcode = DC_MII_READOP;
686 frame->mii_turnaround = 0;
687 frame->mii_data = 0;
688
689 /*
690 * Sync the PHYs.
691 */
692 dc_mii_sync(sc);
693
694 /*
695 * Send command/address info.
696 */
697 dc_mii_send(sc, frame->mii_stdelim, 2);
698 dc_mii_send(sc, frame->mii_opcode, 2);
699 dc_mii_send(sc, frame->mii_phyaddr, 5);
700 dc_mii_send(sc, frame->mii_regaddr, 5);
701
702 #ifdef notdef
703 /* Idle bit */
704 dc_mii_writebit(sc, 1);
705 dc_mii_writebit(sc, 0);
706 #endif
707
708 /* Check for ack. */
709 ack = dc_mii_readbit(sc);
710
711 /*
712 * Now try reading data bits. If the ack failed, we still
713 * need to clock through 16 cycles to keep the PHY(s) in sync.
714 */
715 if (ack) {
716 for (i = 0; i < 16; i++)
717 dc_mii_readbit(sc);
718 goto fail;
719 }
720
721 for (i = 0x8000; i; i >>= 1) {
722 if (!ack) {
723 if (dc_mii_readbit(sc))
724 frame->mii_data |= i;
725 }
726 }
727
728 fail:
729
730 dc_mii_writebit(sc, 0);
731 dc_mii_writebit(sc, 0);
732
733 if (ack)
734 return (1);
735 return (0);
736 }
737
738 /*
739 * Write to a PHY register through the MII.
740 */
741 static int
742 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
743 {
744
745 /*
746 * Set up frame for TX.
747 */
748
749 frame->mii_stdelim = DC_MII_STARTDELIM;
750 frame->mii_opcode = DC_MII_WRITEOP;
751 frame->mii_turnaround = DC_MII_TURNAROUND;
752
753 /*
754 * Sync the PHYs.
755 */
756 dc_mii_sync(sc);
757
758 dc_mii_send(sc, frame->mii_stdelim, 2);
759 dc_mii_send(sc, frame->mii_opcode, 2);
760 dc_mii_send(sc, frame->mii_phyaddr, 5);
761 dc_mii_send(sc, frame->mii_regaddr, 5);
762 dc_mii_send(sc, frame->mii_turnaround, 2);
763 dc_mii_send(sc, frame->mii_data, 16);
764
765 /* Idle bit. */
766 dc_mii_writebit(sc, 0);
767 dc_mii_writebit(sc, 0);
768
769 return (0);
770 }
771
772 static int
773 dc_miibus_readreg(device_t dev, int phy, int reg)
774 {
775 struct dc_mii_frame frame;
776 struct dc_softc *sc;
777 int i, rval, phy_reg = 0;
778
779 sc = device_get_softc(dev);
780 bzero(&frame, sizeof(frame));
781
782 /*
783 * Note: both the AL981 and AN985 have internal PHYs,
784 * however the AL981 provides direct access to the PHY
785 * registers while the AN985 uses a serial MII interface.
786 * The AN985's MII interface is also buggy in that you
787 * can read from any MII address (0 to 31), but only address 1
788 * behaves normally. To deal with both cases, we pretend
789 * that the PHY is at MII address 1.
790 */
791 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
792 return (0);
793
794 /*
795 * Note: the ukphy probes of the RS7112 report a PHY at
796 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
797 * so we only respond to correct one.
798 */
799 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
800 return (0);
801
802 if (sc->dc_pmode != DC_PMODE_MII) {
803 if (phy == (MII_NPHY - 1)) {
804 switch (reg) {
805 case MII_BMSR:
806 /*
807 * Fake something to make the probe
808 * code think there's a PHY here.
809 */
810 return (BMSR_MEDIAMASK);
811 break;
812 case MII_PHYIDR1:
813 if (DC_IS_PNIC(sc))
814 return (DC_VENDORID_LO);
815 return (DC_VENDORID_DEC);
816 break;
817 case MII_PHYIDR2:
818 if (DC_IS_PNIC(sc))
819 return (DC_DEVICEID_82C168);
820 return (DC_DEVICEID_21143);
821 break;
822 default:
823 return (0);
824 break;
825 }
826 } else
827 return (0);
828 }
829
830 if (DC_IS_PNIC(sc)) {
831 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
832 (phy << 23) | (reg << 18));
833 for (i = 0; i < DC_TIMEOUT; i++) {
834 DELAY(1);
835 rval = CSR_READ_4(sc, DC_PN_MII);
836 if (!(rval & DC_PN_MII_BUSY)) {
837 rval &= 0xFFFF;
838 return (rval == 0xFFFF ? 0 : rval);
839 }
840 }
841 return (0);
842 }
843
844 if (DC_IS_COMET(sc)) {
845 switch (reg) {
846 case MII_BMCR:
847 phy_reg = DC_AL_BMCR;
848 break;
849 case MII_BMSR:
850 phy_reg = DC_AL_BMSR;
851 break;
852 case MII_PHYIDR1:
853 phy_reg = DC_AL_VENID;
854 break;
855 case MII_PHYIDR2:
856 phy_reg = DC_AL_DEVID;
857 break;
858 case MII_ANAR:
859 phy_reg = DC_AL_ANAR;
860 break;
861 case MII_ANLPAR:
862 phy_reg = DC_AL_LPAR;
863 break;
864 case MII_ANER:
865 phy_reg = DC_AL_ANER;
866 break;
867 default:
868 device_printf(dev, "phy_read: bad phy register %x\n",
869 reg);
870 return (0);
871 break;
872 }
873
874 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
875
876 if (rval == 0xFFFF)
877 return (0);
878 return (rval);
879 }
880
881 frame.mii_phyaddr = phy;
882 frame.mii_regaddr = reg;
883 if (sc->dc_type == DC_TYPE_98713) {
884 phy_reg = CSR_READ_4(sc, DC_NETCFG);
885 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
886 }
887 dc_mii_readreg(sc, &frame);
888 if (sc->dc_type == DC_TYPE_98713)
889 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
890
891 return (frame.mii_data);
892 }
893
894 static int
895 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
896 {
897 struct dc_softc *sc;
898 struct dc_mii_frame frame;
899 int i, phy_reg = 0;
900
901 sc = device_get_softc(dev);
902 bzero(&frame, sizeof(frame));
903
904 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
905 return (0);
906
907 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
908 return (0);
909
910 if (DC_IS_PNIC(sc)) {
911 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
912 (phy << 23) | (reg << 10) | data);
913 for (i = 0; i < DC_TIMEOUT; i++) {
914 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
915 break;
916 }
917 return (0);
918 }
919
920 if (DC_IS_COMET(sc)) {
921 switch (reg) {
922 case MII_BMCR:
923 phy_reg = DC_AL_BMCR;
924 break;
925 case MII_BMSR:
926 phy_reg = DC_AL_BMSR;
927 break;
928 case MII_PHYIDR1:
929 phy_reg = DC_AL_VENID;
930 break;
931 case MII_PHYIDR2:
932 phy_reg = DC_AL_DEVID;
933 break;
934 case MII_ANAR:
935 phy_reg = DC_AL_ANAR;
936 break;
937 case MII_ANLPAR:
938 phy_reg = DC_AL_LPAR;
939 break;
940 case MII_ANER:
941 phy_reg = DC_AL_ANER;
942 break;
943 default:
944 device_printf(dev, "phy_write: bad phy register %x\n",
945 reg);
946 return (0);
947 break;
948 }
949
950 CSR_WRITE_4(sc, phy_reg, data);
951 return (0);
952 }
953
954 frame.mii_phyaddr = phy;
955 frame.mii_regaddr = reg;
956 frame.mii_data = data;
957
958 if (sc->dc_type == DC_TYPE_98713) {
959 phy_reg = CSR_READ_4(sc, DC_NETCFG);
960 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
961 }
962 dc_mii_writereg(sc, &frame);
963 if (sc->dc_type == DC_TYPE_98713)
964 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
965
966 return (0);
967 }
968
969 static void
970 dc_miibus_statchg(device_t dev)
971 {
972 struct dc_softc *sc;
973 struct mii_data *mii;
974 struct ifmedia *ifm;
975
976 sc = device_get_softc(dev);
977 if (DC_IS_ADMTEK(sc))
978 return;
979
980 mii = device_get_softc(sc->dc_miibus);
981 ifm = &mii->mii_media;
982 if (DC_IS_DAVICOM(sc) &&
983 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
984 dc_setcfg(sc, ifm->ifm_media);
985 sc->dc_if_media = ifm->ifm_media;
986 } else {
987 dc_setcfg(sc, mii->mii_media_active);
988 sc->dc_if_media = mii->mii_media_active;
989 }
990 }
991
992 /*
993 * Special support for DM9102A cards with HomePNA PHYs. Note:
994 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
995 * to be impossible to talk to the management interface of the DM9801
996 * PHY (its MDIO pin is not connected to anything). Consequently,
997 * the driver has to just 'know' about the additional mode and deal
998 * with it itself. *sigh*
999 */
1000 static void
1001 dc_miibus_mediainit(device_t dev)
1002 {
1003 struct dc_softc *sc;
1004 struct mii_data *mii;
1005 struct ifmedia *ifm;
1006 int rev;
1007
1008 rev = pci_get_revid(dev);
1009
1010 sc = device_get_softc(dev);
1011 mii = device_get_softc(sc->dc_miibus);
1012 ifm = &mii->mii_media;
1013
1014 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1015 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
1016 }
1017
1018 #define DC_BITS_512 9
1019 #define DC_BITS_128 7
1020 #define DC_BITS_64 6
1021
1022 static uint32_t
1023 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
1024 {
1025 uint32_t crc;
1026
1027 /* Compute CRC for the address value. */
1028 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
1029
1030 /*
1031 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1032 * chips is only 128 bits wide.
1033 */
1034 if (sc->dc_flags & DC_128BIT_HASH)
1035 return (crc & ((1 << DC_BITS_128) - 1));
1036
1037 /* The hash table on the MX98715BEC is only 64 bits wide. */
1038 if (sc->dc_flags & DC_64BIT_HASH)
1039 return (crc & ((1 << DC_BITS_64) - 1));
1040
1041 /* Xircom's hash filtering table is different (read: weird) */
1042 /* Xircom uses the LEAST significant bits */
1043 if (DC_IS_XIRCOM(sc)) {
1044 if ((crc & 0x180) == 0x180)
1045 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
1046 else
1047 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 +
1048 (12 << 4));
1049 }
1050
1051 return (crc & ((1 << DC_BITS_512) - 1));
1052 }
1053
1054 /*
1055 * Calculate CRC of a multicast group address, return the lower 6 bits.
1056 */
1057 static uint32_t
1058 dc_mchash_be(const uint8_t *addr)
1059 {
1060 uint32_t crc;
1061
1062 /* Compute CRC for the address value. */
1063 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
1064
1065 /* Return the filter bit position. */
1066 return ((crc >> 26) & 0x0000003F);
1067 }
1068
1069 /*
1070 * 21143-style RX filter setup routine. Filter programming is done by
1071 * downloading a special setup frame into the TX engine. 21143, Macronix,
1072 * PNIC, PNIC II and Davicom chips are programmed this way.
1073 *
1074 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1075 * address (our node address) and a 512-bit hash filter for multicast
1076 * frames. We also sneak the broadcast address into the hash filter since
1077 * we need that too.
1078 */
1079 static void
1080 dc_setfilt_21143(struct dc_softc *sc)
1081 {
1082 struct dc_desc *sframe;
1083 u_int32_t h, *sp;
1084 struct ifmultiaddr *ifma;
1085 struct ifnet *ifp;
1086 int i;
1087
1088 ifp = sc->dc_ifp;
1089
1090 i = sc->dc_cdata.dc_tx_prod;
1091 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1092 sc->dc_cdata.dc_tx_cnt++;
1093 sframe = &sc->dc_ldata->dc_tx_list[i];
1094 sp = sc->dc_cdata.dc_sbuf;
1095 bzero(sp, DC_SFRAME_LEN);
1096
1097 sframe->dc_data = htole32(sc->dc_saddr);
1098 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1099 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1100
1101 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1102
1103 /* If we want promiscuous mode, set the allframes bit. */
1104 if (ifp->if_flags & IFF_PROMISC)
1105 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1106 else
1107 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1108
1109 if (ifp->if_flags & IFF_ALLMULTI)
1110 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1111 else
1112 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1113
1114 IF_ADDR_LOCK(ifp);
1115 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1116 if (ifma->ifma_addr->sa_family != AF_LINK)
1117 continue;
1118 h = dc_mchash_le(sc,
1119 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1120 sp[h >> 4] |= htole32(1 << (h & 0xF));
1121 }
1122 IF_ADDR_UNLOCK(ifp);
1123
1124 if (ifp->if_flags & IFF_BROADCAST) {
1125 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1126 sp[h >> 4] |= htole32(1 << (h & 0xF));
1127 }
1128
1129 /* Set our MAC address */
1130 sp[39] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]);
1131 sp[40] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]);
1132 sp[41] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]);
1133
1134 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1135 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1136
1137 /*
1138 * The PNIC takes an exceedingly long time to process its
1139 * setup frame; wait 10ms after posting the setup frame
1140 * before proceeding, just so it has time to swallow its
1141 * medicine.
1142 */
1143 DELAY(10000);
1144
1145 ifp->if_timer = 5;
1146 }
1147
1148 static void
1149 dc_setfilt_admtek(struct dc_softc *sc)
1150 {
1151 struct ifnet *ifp;
1152 struct ifmultiaddr *ifma;
1153 int h = 0;
1154 u_int32_t hashes[2] = { 0, 0 };
1155
1156 ifp = sc->dc_ifp;
1157
1158 /* Init our MAC address. */
1159 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[0]));
1160 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[4]));
1161
1162 /* If we want promiscuous mode, set the allframes bit. */
1163 if (ifp->if_flags & IFF_PROMISC)
1164 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1165 else
1166 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1167
1168 if (ifp->if_flags & IFF_ALLMULTI)
1169 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1170 else
1171 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1172
1173 /* First, zot all the existing hash bits. */
1174 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1175 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1176
1177 /*
1178 * If we're already in promisc or allmulti mode, we
1179 * don't have to bother programming the multicast filter.
1180 */
1181 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1182 return;
1183
1184 /* Now program new ones. */
1185 IF_ADDR_LOCK(ifp);
1186 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1187 if (ifma->ifma_addr->sa_family != AF_LINK)
1188 continue;
1189 if (DC_IS_CENTAUR(sc))
1190 h = dc_mchash_le(sc,
1191 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1192 else
1193 h = dc_mchash_be(
1194 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1195 if (h < 32)
1196 hashes[0] |= (1 << h);
1197 else
1198 hashes[1] |= (1 << (h - 32));
1199 }
1200 IF_ADDR_UNLOCK(ifp);
1201
1202 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1203 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1204 }
1205
1206 static void
1207 dc_setfilt_asix(struct dc_softc *sc)
1208 {
1209 struct ifnet *ifp;
1210 struct ifmultiaddr *ifma;
1211 int h = 0;
1212 u_int32_t hashes[2] = { 0, 0 };
1213
1214 ifp = sc->dc_ifp;
1215
1216 /* Init our MAC address */
1217 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1218 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1219 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[0]));
1220 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1221 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1222 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[4]));
1223
1224 /* If we want promiscuous mode, set the allframes bit. */
1225 if (ifp->if_flags & IFF_PROMISC)
1226 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1227 else
1228 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1229
1230 if (ifp->if_flags & IFF_ALLMULTI)
1231 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1232 else
1233 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1234
1235 /*
1236 * The ASIX chip has a special bit to enable reception
1237 * of broadcast frames.
1238 */
1239 if (ifp->if_flags & IFF_BROADCAST)
1240 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1241 else
1242 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1243
1244 /* first, zot all the existing hash bits */
1245 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1246 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1247 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1248 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1249
1250 /*
1251 * If we're already in promisc or allmulti mode, we
1252 * don't have to bother programming the multicast filter.
1253 */
1254 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1255 return;
1256
1257 /* now program new ones */
1258 IF_ADDR_LOCK(ifp);
1259 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1260 if (ifma->ifma_addr->sa_family != AF_LINK)
1261 continue;
1262 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1263 if (h < 32)
1264 hashes[0] |= (1 << h);
1265 else
1266 hashes[1] |= (1 << (h - 32));
1267 }
1268 IF_ADDR_UNLOCK(ifp);
1269
1270 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1271 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1272 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1273 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1274 }
1275
1276 static void
1277 dc_setfilt_xircom(struct dc_softc *sc)
1278 {
1279 struct ifnet *ifp;
1280 struct ifmultiaddr *ifma;
1281 struct dc_desc *sframe;
1282 u_int32_t h, *sp;
1283 int i;
1284
1285 ifp = sc->dc_ifp;
1286 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1287
1288 i = sc->dc_cdata.dc_tx_prod;
1289 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1290 sc->dc_cdata.dc_tx_cnt++;
1291 sframe = &sc->dc_ldata->dc_tx_list[i];
1292 sp = sc->dc_cdata.dc_sbuf;
1293 bzero(sp, DC_SFRAME_LEN);
1294
1295 sframe->dc_data = htole32(sc->dc_saddr);
1296 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1297 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1298
1299 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1300
1301 /* If we want promiscuous mode, set the allframes bit. */
1302 if (ifp->if_flags & IFF_PROMISC)
1303 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1304 else
1305 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1306
1307 if (ifp->if_flags & IFF_ALLMULTI)
1308 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1309 else
1310 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1311
1312 IF_ADDR_LOCK(ifp);
1313 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1314 if (ifma->ifma_addr->sa_family != AF_LINK)
1315 continue;
1316 h = dc_mchash_le(sc,
1317 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1318 sp[h >> 4] |= htole32(1 << (h & 0xF));
1319 }
1320 IF_ADDR_UNLOCK(ifp);
1321
1322 if (ifp->if_flags & IFF_BROADCAST) {
1323 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1324 sp[h >> 4] |= htole32(1 << (h & 0xF));
1325 }
1326
1327 /* Set our MAC address */
1328 sp[0] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]);
1329 sp[1] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]);
1330 sp[2] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]);
1331
1332 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1333 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1334 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1335 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1336 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1337
1338 /*
1339 * Wait some time...
1340 */
1341 DELAY(1000);
1342
1343 ifp->if_timer = 5;
1344 }
1345
1346 static void
1347 dc_setfilt(struct dc_softc *sc)
1348 {
1349
1350 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1351 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1352 dc_setfilt_21143(sc);
1353
1354 if (DC_IS_ASIX(sc))
1355 dc_setfilt_asix(sc);
1356
1357 if (DC_IS_ADMTEK(sc))
1358 dc_setfilt_admtek(sc);
1359
1360 if (DC_IS_XIRCOM(sc))
1361 dc_setfilt_xircom(sc);
1362 }
1363
1364 /*
1365 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in
1366 * the netconfig register, we first have to put the transmit and/or
1367 * receive logic in the idle state.
1368 */
1369 static void
1370 dc_setcfg(struct dc_softc *sc, int media)
1371 {
1372 int i, restart = 0, watchdogreg;
1373 u_int32_t isr;
1374
1375 if (IFM_SUBTYPE(media) == IFM_NONE)
1376 return;
1377
1378 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {
1379 restart = 1;
1380 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1381
1382 for (i = 0; i < DC_TIMEOUT; i++) {
1383 isr = CSR_READ_4(sc, DC_ISR);
1384 if (isr & DC_ISR_TX_IDLE &&
1385 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1386 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1387 break;
1388 DELAY(10);
1389 }
1390
1391 if (i == DC_TIMEOUT) {
1392 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc))
1393 device_printf(sc->dc_dev,
1394 "%s: failed to force tx to idle state\n",
1395 __func__);
1396 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1397 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
1398 !(DC_IS_CENTAUR(sc) || DC_IS_CONEXANT(sc) ||
1399 (DC_IS_DAVICOM(sc) && pci_get_revid(sc->dc_dev) >=
1400 DC_REVISION_DM9102A)))
1401 device_printf(sc->dc_dev,
1402 "%s: failed to force rx to idle state\n",
1403 __func__);
1404 }
1405 }
1406
1407 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1408 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1409 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1410 if (sc->dc_pmode == DC_PMODE_MII) {
1411 if (DC_IS_INTEL(sc)) {
1412 /* There's a write enable bit here that reads as 1. */
1413 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1414 watchdogreg &= ~DC_WDOG_CTLWREN;
1415 watchdogreg |= DC_WDOG_JABBERDIS;
1416 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1417 } else {
1418 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1419 }
1420 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1421 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1422 if (sc->dc_type == DC_TYPE_98713)
1423 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1424 DC_NETCFG_SCRAMBLER));
1425 if (!DC_IS_DAVICOM(sc))
1426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1427 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1428 if (DC_IS_INTEL(sc))
1429 dc_apply_fixup(sc, IFM_AUTO);
1430 } else {
1431 if (DC_IS_PNIC(sc)) {
1432 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1433 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1434 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1435 }
1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1437 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1438 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1439 if (DC_IS_INTEL(sc))
1440 dc_apply_fixup(sc,
1441 (media & IFM_GMASK) == IFM_FDX ?
1442 IFM_100_TX | IFM_FDX : IFM_100_TX);
1443 }
1444 }
1445
1446 if (IFM_SUBTYPE(media) == IFM_10_T) {
1447 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1448 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1449 if (sc->dc_pmode == DC_PMODE_MII) {
1450 /* There's a write enable bit here that reads as 1. */
1451 if (DC_IS_INTEL(sc)) {
1452 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1453 watchdogreg &= ~DC_WDOG_CTLWREN;
1454 watchdogreg |= DC_WDOG_JABBERDIS;
1455 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1456 } else {
1457 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1458 }
1459 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1460 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1461 if (sc->dc_type == DC_TYPE_98713)
1462 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1463 if (!DC_IS_DAVICOM(sc))
1464 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1465 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1466 if (DC_IS_INTEL(sc))
1467 dc_apply_fixup(sc, IFM_AUTO);
1468 } else {
1469 if (DC_IS_PNIC(sc)) {
1470 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1471 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1472 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1473 }
1474 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1475 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1476 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1477 if (DC_IS_INTEL(sc)) {
1478 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1479 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1480 if ((media & IFM_GMASK) == IFM_FDX)
1481 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1482 else
1483 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1484 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1485 DC_CLRBIT(sc, DC_10BTCTRL,
1486 DC_TCTL_AUTONEGENBL);
1487 dc_apply_fixup(sc,
1488 (media & IFM_GMASK) == IFM_FDX ?
1489 IFM_10_T | IFM_FDX : IFM_10_T);
1490 DELAY(20000);
1491 }
1492 }
1493 }
1494
1495 /*
1496 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1497 * PHY and we want HomePNA mode, set the portsel bit to turn
1498 * on the external MII port.
1499 */
1500 if (DC_IS_DAVICOM(sc)) {
1501 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1502 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1503 sc->dc_link = 1;
1504 } else {
1505 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1506 }
1507 }
1508
1509 if ((media & IFM_GMASK) == IFM_FDX) {
1510 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1511 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1512 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1513 } else {
1514 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1515 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1516 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1517 }
1518
1519 if (restart)
1520 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON);
1521 }
1522
1523 static void
1524 dc_reset(struct dc_softc *sc)
1525 {
1526 int i;
1527
1528 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1529
1530 for (i = 0; i < DC_TIMEOUT; i++) {
1531 DELAY(10);
1532 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1533 break;
1534 }
1535
1536 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) ||
1537 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) {
1538 DELAY(10000);
1539 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1540 i = 0;
1541 }
1542
1543 if (i == DC_TIMEOUT)
1544 device_printf(sc->dc_dev, "reset never completed!\n");
1545
1546 /* Wait a little while for the chip to get its brains in order. */
1547 DELAY(1000);
1548
1549 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1550 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1551 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1552
1553 /*
1554 * Bring the SIA out of reset. In some cases, it looks
1555 * like failing to unreset the SIA soon enough gets it
1556 * into a state where it will never come out of reset
1557 * until we reset the whole chip again.
1558 */
1559 if (DC_IS_INTEL(sc)) {
1560 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1561 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1562 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1563 }
1564 }
1565
1566 static struct dc_type *
1567 dc_devtype(device_t dev)
1568 {
1569 struct dc_type *t;
1570 u_int32_t devid;
1571 u_int8_t rev;
1572
1573 t = dc_devs;
1574 devid = pci_get_devid(dev);
1575 rev = pci_get_revid(dev);
1576
1577 while (t->dc_name != NULL) {
1578 if (devid == t->dc_devid && rev >= t->dc_minrev)
1579 return (t);
1580 t++;
1581 }
1582
1583 return (NULL);
1584 }
1585
1586 /*
1587 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1588 * IDs against our list and return a device name if we find a match.
1589 * We do a little bit of extra work to identify the exact type of
1590 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1591 * but different revision IDs. The same is true for 98715/98715A
1592 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1593 * cases, the exact chip revision affects driver behavior.
1594 */
1595 static int
1596 dc_probe(device_t dev)
1597 {
1598 struct dc_type *t;
1599
1600 t = dc_devtype(dev);
1601
1602 if (t != NULL) {
1603 device_set_desc(dev, t->dc_name);
1604 return (BUS_PROBE_DEFAULT);
1605 }
1606
1607 return (ENXIO);
1608 }
1609
1610 static void
1611 dc_apply_fixup(struct dc_softc *sc, int media)
1612 {
1613 struct dc_mediainfo *m;
1614 u_int8_t *p;
1615 int i;
1616 u_int32_t reg;
1617
1618 m = sc->dc_mi;
1619
1620 while (m != NULL) {
1621 if (m->dc_media == media)
1622 break;
1623 m = m->dc_next;
1624 }
1625
1626 if (m == NULL)
1627 return;
1628
1629 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1630 reg = (p[0] | (p[1] << 8)) << 16;
1631 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1632 }
1633
1634 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1635 reg = (p[0] | (p[1] << 8)) << 16;
1636 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1637 }
1638 }
1639
1640 static void
1641 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1642 {
1643 struct dc_mediainfo *m;
1644
1645 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1646 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) {
1647 case DC_SIA_CODE_10BT:
1648 m->dc_media = IFM_10_T;
1649 break;
1650 case DC_SIA_CODE_10BT_FDX:
1651 m->dc_media = IFM_10_T | IFM_FDX;
1652 break;
1653 case DC_SIA_CODE_10B2:
1654 m->dc_media = IFM_10_2;
1655 break;
1656 case DC_SIA_CODE_10B5:
1657 m->dc_media = IFM_10_5;
1658 break;
1659 default:
1660 break;
1661 }
1662
1663 /*
1664 * We need to ignore CSR13, CSR14, CSR15 for SIA mode.
1665 * Things apparently already work for cards that do
1666 * supply Media Specific Data.
1667 */
1668 if (l->dc_sia_code & DC_SIA_CODE_EXT) {
1669 m->dc_gp_len = 2;
1670 m->dc_gp_ptr =
1671 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1672 } else {
1673 m->dc_gp_len = 2;
1674 m->dc_gp_ptr =
1675 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1676 }
1677
1678 m->dc_next = sc->dc_mi;
1679 sc->dc_mi = m;
1680
1681 sc->dc_pmode = DC_PMODE_SIA;
1682 }
1683
1684 static void
1685 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1686 {
1687 struct dc_mediainfo *m;
1688
1689 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1690 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1691 m->dc_media = IFM_100_TX;
1692
1693 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1694 m->dc_media = IFM_100_TX | IFM_FDX;
1695
1696 m->dc_gp_len = 2;
1697 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1698
1699 m->dc_next = sc->dc_mi;
1700 sc->dc_mi = m;
1701
1702 sc->dc_pmode = DC_PMODE_SYM;
1703 }
1704
1705 static void
1706 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1707 {
1708 struct dc_mediainfo *m;
1709 u_int8_t *p;
1710
1711 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1712 /* We abuse IFM_AUTO to represent MII. */
1713 m->dc_media = IFM_AUTO;
1714 m->dc_gp_len = l->dc_gpr_len;
1715
1716 p = (u_int8_t *)l;
1717 p += sizeof(struct dc_eblock_mii);
1718 m->dc_gp_ptr = p;
1719 p += 2 * l->dc_gpr_len;
1720 m->dc_reset_len = *p;
1721 p++;
1722 m->dc_reset_ptr = p;
1723
1724 m->dc_next = sc->dc_mi;
1725 sc->dc_mi = m;
1726 }
1727
1728 static void
1729 dc_read_srom(struct dc_softc *sc, int bits)
1730 {
1731 int size;
1732
1733 size = 2 << bits;
1734 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1735 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1736 }
1737
1738 static void
1739 dc_parse_21143_srom(struct dc_softc *sc)
1740 {
1741 struct dc_leaf_hdr *lhdr;
1742 struct dc_eblock_hdr *hdr;
1743 int have_mii, i, loff;
1744 char *ptr;
1745
1746 have_mii = 0;
1747 loff = sc->dc_srom[27];
1748 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1749
1750 ptr = (char *)lhdr;
1751 ptr += sizeof(struct dc_leaf_hdr) - 1;
1752 /*
1753 * Look if we got a MII media block.
1754 */
1755 for (i = 0; i < lhdr->dc_mcnt; i++) {
1756 hdr = (struct dc_eblock_hdr *)ptr;
1757 if (hdr->dc_type == DC_EBLOCK_MII)
1758 have_mii++;
1759
1760 ptr += (hdr->dc_len & 0x7F);
1761 ptr++;
1762 }
1763
1764 /*
1765 * Do the same thing again. Only use SIA and SYM media
1766 * blocks if no MII media block is available.
1767 */
1768 ptr = (char *)lhdr;
1769 ptr += sizeof(struct dc_leaf_hdr) - 1;
1770 for (i = 0; i < lhdr->dc_mcnt; i++) {
1771 hdr = (struct dc_eblock_hdr *)ptr;
1772 switch (hdr->dc_type) {
1773 case DC_EBLOCK_MII:
1774 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1775 break;
1776 case DC_EBLOCK_SIA:
1777 if (! have_mii)
1778 dc_decode_leaf_sia(sc,
1779 (struct dc_eblock_sia *)hdr);
1780 break;
1781 case DC_EBLOCK_SYM:
1782 if (! have_mii)
1783 dc_decode_leaf_sym(sc,
1784 (struct dc_eblock_sym *)hdr);
1785 break;
1786 default:
1787 /* Don't care. Yet. */
1788 break;
1789 }
1790 ptr += (hdr->dc_len & 0x7F);
1791 ptr++;
1792 }
1793 }
1794
1795 static void
1796 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1797 {
1798 u_int32_t *paddr;
1799
1800 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1801 paddr = arg;
1802 *paddr = segs->ds_addr;
1803 }
1804
1805 /*
1806 * Attach the interface. Allocate softc structures, do ifmedia
1807 * setup and ethernet/BPF attach.
1808 */
1809 static int
1810 dc_attach(device_t dev)
1811 {
1812 int tmp = 0;
1813 u_char eaddr[ETHER_ADDR_LEN];
1814 u_int32_t command;
1815 struct dc_softc *sc;
1816 struct ifnet *ifp;
1817 u_int32_t revision;
1818 int error = 0, rid, mac_offset;
1819 int i;
1820 u_int8_t *mac;
1821
1822 sc = device_get_softc(dev);
1823 sc->dc_dev = dev;
1824
1825 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1826 MTX_DEF);
1827
1828 /*
1829 * Map control/status registers.
1830 */
1831 pci_enable_busmaster(dev);
1832
1833 rid = DC_RID;
1834 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
1835
1836 if (sc->dc_res == NULL) {
1837 device_printf(dev, "couldn't map ports/memory\n");
1838 error = ENXIO;
1839 goto fail;
1840 }
1841
1842 sc->dc_btag = rman_get_bustag(sc->dc_res);
1843 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1844
1845 /* Allocate interrupt. */
1846 rid = 0;
1847 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1848 RF_SHAREABLE | RF_ACTIVE);
1849
1850 if (sc->dc_irq == NULL) {
1851 device_printf(dev, "couldn't map interrupt\n");
1852 error = ENXIO;
1853 goto fail;
1854 }
1855
1856 /* Need this info to decide on a chip type. */
1857 sc->dc_info = dc_devtype(dev);
1858 revision = pci_get_revid(dev);
1859
1860 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
1861 if (sc->dc_info->dc_devid !=
1862 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) &&
1863 sc->dc_info->dc_devid !=
1864 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201))
1865 dc_eeprom_width(sc);
1866
1867 switch (sc->dc_info->dc_devid) {
1868 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143):
1869 sc->dc_type = DC_TYPE_21143;
1870 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1871 sc->dc_flags |= DC_REDUCED_MII_POLL;
1872 /* Save EEPROM contents so we can parse them later. */
1873 dc_read_srom(sc, sc->dc_romwidth);
1874 break;
1875 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009):
1876 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100):
1877 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102):
1878 sc->dc_type = DC_TYPE_DM9102;
1879 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS;
1880 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD;
1881 sc->dc_flags |= DC_TX_ALIGN;
1882 sc->dc_pmode = DC_PMODE_MII;
1883
1884 /* Increase the latency timer value. */
1885 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1);
1886 break;
1887 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981):
1888 sc->dc_type = DC_TYPE_AL981;
1889 sc->dc_flags |= DC_TX_USE_TX_INTR;
1890 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1891 sc->dc_pmode = DC_PMODE_MII;
1892 dc_read_srom(sc, sc->dc_romwidth);
1893 break;
1894 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985):
1895 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511):
1896 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513):
1897 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD):
1898 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511):
1899 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500):
1900 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX):
1901 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242):
1902 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX):
1903 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T):
1904 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB):
1905 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120):
1906 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130):
1907 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08):
1908 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09):
1909 sc->dc_type = DC_TYPE_AN985;
1910 sc->dc_flags |= DC_64BIT_HASH;
1911 sc->dc_flags |= DC_TX_USE_TX_INTR;
1912 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1913 sc->dc_pmode = DC_PMODE_MII;
1914 /* Don't read SROM for - auto-loaded on reset */
1915 break;
1916 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713):
1917 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP):
1918 if (revision < DC_REVISION_98713A) {
1919 sc->dc_type = DC_TYPE_98713;
1920 }
1921 if (revision >= DC_REVISION_98713A) {
1922 sc->dc_type = DC_TYPE_98713A;
1923 sc->dc_flags |= DC_21143_NWAY;
1924 }
1925 sc->dc_flags |= DC_REDUCED_MII_POLL;
1926 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1927 break;
1928 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5):
1929 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217):
1930 /*
1931 * Macronix MX98715AEC-C/D/E parts have only a
1932 * 128-bit hash table. We need to deal with these
1933 * in the same manner as the PNIC II so that we
1934 * get the right number of bits out of the
1935 * CRC routine.
1936 */
1937 if (revision >= DC_REVISION_98715AEC_C &&
1938 revision < DC_REVISION_98725)
1939 sc->dc_flags |= DC_128BIT_HASH;
1940 sc->dc_type = DC_TYPE_987x5;
1941 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1942 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1943 break;
1944 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727):
1945 sc->dc_type = DC_TYPE_987x5;
1946 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1947 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1948 break;
1949 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115):
1950 sc->dc_type = DC_TYPE_PNICII;
1951 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH;
1952 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1953 break;
1954 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168):
1955 sc->dc_type = DC_TYPE_PNIC;
1956 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS;
1957 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1958 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
1959 if (revision < DC_REVISION_82C169)
1960 sc->dc_pmode = DC_PMODE_SYM;
1961 break;
1962 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A):
1963 sc->dc_type = DC_TYPE_ASIX;
1964 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG;
1965 sc->dc_flags |= DC_REDUCED_MII_POLL;
1966 sc->dc_pmode = DC_PMODE_MII;
1967 break;
1968 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201):
1969 sc->dc_type = DC_TYPE_XIRCOM;
1970 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
1971 DC_TX_ALIGN;
1972 /*
1973 * We don't actually need to coalesce, but we're doing
1974 * it to obtain a double word aligned buffer.
1975 * The DC_TX_COALESCE flag is required.
1976 */
1977 sc->dc_pmode = DC_PMODE_MII;
1978 break;
1979 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112):
1980 sc->dc_type = DC_TYPE_CONEXANT;
1981 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1982 sc->dc_flags |= DC_REDUCED_MII_POLL;
1983 sc->dc_pmode = DC_PMODE_MII;
1984 dc_read_srom(sc, sc->dc_romwidth);
1985 break;
1986 default:
1987 device_printf(dev, "unknown device: %x\n",
1988 sc->dc_info->dc_devid);
1989 break;
1990 }
1991
1992 /* Save the cache line size. */
1993 if (DC_IS_DAVICOM(sc))
1994 sc->dc_cachesize = 0;
1995 else
1996 sc->dc_cachesize = pci_get_cachelnsz(dev);
1997
1998 /* Reset the adapter. */
1999 dc_reset(sc);
2000
2001 /* Take 21143 out of snooze mode */
2002 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2003 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2004 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
2005 pci_write_config(dev, DC_PCI_CFDD, command, 4);
2006 }
2007
2008 /*
2009 * Try to learn something about the supported media.
2010 * We know that ASIX and ADMtek and Davicom devices
2011 * will *always* be using MII media, so that's a no-brainer.
2012 * The tricky ones are the Macronix/PNIC II and the
2013 * Intel 21143.
2014 */
2015 if (DC_IS_INTEL(sc))
2016 dc_parse_21143_srom(sc);
2017 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2018 if (sc->dc_type == DC_TYPE_98713)
2019 sc->dc_pmode = DC_PMODE_MII;
2020 else
2021 sc->dc_pmode = DC_PMODE_SYM;
2022 } else if (!sc->dc_pmode)
2023 sc->dc_pmode = DC_PMODE_MII;
2024
2025 /*
2026 * Get station address from the EEPROM.
2027 */
2028 switch(sc->dc_type) {
2029 case DC_TYPE_98713:
2030 case DC_TYPE_98713A:
2031 case DC_TYPE_987x5:
2032 case DC_TYPE_PNICII:
2033 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2034 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2035 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2036 break;
2037 case DC_TYPE_PNIC:
2038 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2039 break;
2040 case DC_TYPE_DM9102:
2041 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2042 #ifdef __sparc64__
2043 /*
2044 * If this is an onboard dc(4) the station address read from
2045 * the EEPROM is all zero and we have to get it from the fcode.
2046 */
2047 for (i = 0; i < ETHER_ADDR_LEN; i++)
2048 if (eaddr[i] != 0x00)
2049 break;
2050 if (i >= ETHER_ADDR_LEN)
2051 OF_getetheraddr(dev, eaddr);
2052 #endif
2053 break;
2054 case DC_TYPE_21143:
2055 case DC_TYPE_ASIX:
2056 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2057 break;
2058 case DC_TYPE_AL981:
2059 case DC_TYPE_AN985:
2060 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0);
2061 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1);
2062 break;
2063 case DC_TYPE_CONEXANT:
2064 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr,
2065 ETHER_ADDR_LEN);
2066 break;
2067 case DC_TYPE_XIRCOM:
2068 /* The MAC comes from the CIS. */
2069 mac = pci_get_ether(dev);
2070 if (!mac) {
2071 device_printf(dev, "No station address in CIS!\n");
2072 error = ENXIO;
2073 goto fail;
2074 }
2075 bcopy(mac, eaddr, ETHER_ADDR_LEN);
2076 break;
2077 default:
2078 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2079 break;
2080 }
2081
2082 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
2083 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
2084 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1,
2085 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag);
2086 if (error) {
2087 device_printf(dev, "failed to allocate busdma tag\n");
2088 error = ENXIO;
2089 goto fail;
2090 }
2091 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata,
2092 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap);
2093 if (error) {
2094 device_printf(dev, "failed to allocate DMA safe memory\n");
2095 error = ENXIO;
2096 goto fail;
2097 }
2098 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata,
2099 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr,
2100 BUS_DMA_NOWAIT);
2101 if (error) {
2102 device_printf(dev, "cannot get address of the descriptors\n");
2103 error = ENXIO;
2104 goto fail;
2105 }
2106
2107 /*
2108 * Allocate a busdma tag and DMA safe memory for the multicast
2109 * setup frame.
2110 */
2111 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
2112 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1,
2113 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag);
2114 if (error) {
2115 device_printf(dev, "failed to allocate busdma tag\n");
2116 error = ENXIO;
2117 goto fail;
2118 }
2119 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf,
2120 BUS_DMA_NOWAIT, &sc->dc_smap);
2121 if (error) {
2122 device_printf(dev, "failed to allocate DMA safe memory\n");
2123 error = ENXIO;
2124 goto fail;
2125 }
2126 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf,
2127 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT);
2128 if (error) {
2129 device_printf(dev, "cannot get address of the descriptors\n");
2130 error = ENXIO;
2131 goto fail;
2132 }
2133
2134 /* Allocate a busdma tag for mbufs. */
2135 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
2136 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, DC_TX_LIST_CNT, MCLBYTES,
2137 0, NULL, NULL, &sc->dc_mtag);
2138 if (error) {
2139 device_printf(dev, "failed to allocate busdma tag\n");
2140 error = ENXIO;
2141 goto fail;
2142 }
2143
2144 /* Create the TX/RX busdma maps. */
2145 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2146 error = bus_dmamap_create(sc->dc_mtag, 0,
2147 &sc->dc_cdata.dc_tx_map[i]);
2148 if (error) {
2149 device_printf(dev, "failed to init TX ring\n");
2150 error = ENXIO;
2151 goto fail;
2152 }
2153 }
2154 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2155 error = bus_dmamap_create(sc->dc_mtag, 0,
2156 &sc->dc_cdata.dc_rx_map[i]);
2157 if (error) {
2158 device_printf(dev, "failed to init RX ring\n");
2159 error = ENXIO;
2160 goto fail;
2161 }
2162 }
2163 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap);
2164 if (error) {
2165 device_printf(dev, "failed to init RX ring\n");
2166 error = ENXIO;
2167 goto fail;
2168 }
2169
2170 ifp = sc->dc_ifp = if_alloc(IFT_ETHER);
2171 if (ifp == NULL) {
2172 device_printf(dev, "can not if_alloc()\n");
2173 error = ENOSPC;
2174 goto fail;
2175 }
2176 ifp->if_softc = sc;
2177 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2178 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */
2179 ifp->if_mtu = ETHERMTU;
2180 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2181 ifp->if_ioctl = dc_ioctl;
2182 ifp->if_start = dc_start;
2183 ifp->if_watchdog = dc_watchdog;
2184 ifp->if_init = dc_init;
2185 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2186 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1;
2187 IFQ_SET_READY(&ifp->if_snd);
2188
2189 /*
2190 * Do MII setup. If this is a 21143, check for a PHY on the
2191 * MII bus after applying any necessary fixups to twiddle the
2192 * GPIO bits. If we don't end up finding a PHY, restore the
2193 * old selection (SIA only or SIA/SYM) and attach the dcphy
2194 * driver instead.
2195 */
2196 if (DC_IS_INTEL(sc)) {
2197 dc_apply_fixup(sc, IFM_AUTO);
2198 tmp = sc->dc_pmode;
2199 sc->dc_pmode = DC_PMODE_MII;
2200 }
2201
2202 /*
2203 * Setup General Purpose port mode and data so the tulip can talk
2204 * to the MII. This needs to be done before mii_phy_probe so that
2205 * we can actually see them.
2206 */
2207 if (DC_IS_XIRCOM(sc)) {
2208 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2209 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2210 DELAY(10);
2211 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2212 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2213 DELAY(10);
2214 }
2215
2216 error = mii_phy_probe(dev, &sc->dc_miibus,
2217 dc_ifmedia_upd, dc_ifmedia_sts);
2218
2219 if (error && DC_IS_INTEL(sc)) {
2220 sc->dc_pmode = tmp;
2221 if (sc->dc_pmode != DC_PMODE_SIA)
2222 sc->dc_pmode = DC_PMODE_SYM;
2223 sc->dc_flags |= DC_21143_NWAY;
2224 mii_phy_probe(dev, &sc->dc_miibus,
2225 dc_ifmedia_upd, dc_ifmedia_sts);
2226 /*
2227 * For non-MII cards, we need to have the 21143
2228 * drive the LEDs. Except there are some systems
2229 * like the NEC VersaPro NoteBook PC which have no
2230 * LEDs, and twiddling these bits has adverse effects
2231 * on them. (I.e. you suddenly can't get a link.)
2232 */
2233 if (!(pci_get_subvendor(dev) == 0x1033 &&
2234 pci_get_subdevice(dev) == 0x8028))
2235 sc->dc_flags |= DC_TULIP_LEDS;
2236 error = 0;
2237 }
2238
2239 if (error) {
2240 device_printf(dev, "MII without any PHY!\n");
2241 goto fail;
2242 }
2243
2244 if (DC_IS_ADMTEK(sc)) {
2245 /*
2246 * Set automatic TX underrun recovery for the ADMtek chips
2247 */
2248 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2249 }
2250
2251 /*
2252 * Tell the upper layer(s) we support long frames.
2253 */
2254 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2255 ifp->if_capabilities |= IFCAP_VLAN_MTU;
2256 ifp->if_capenable = ifp->if_capabilities;
2257 #ifdef DEVICE_POLLING
2258 ifp->if_capabilities |= IFCAP_POLLING;
2259 #endif
2260
2261 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0);
2262
2263 #ifdef SRM_MEDIA
2264 sc->dc_srm_media = 0;
2265
2266 /* Remember the SRM console media setting */
2267 if (DC_IS_INTEL(sc)) {
2268 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2269 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
2270 switch ((command >> 8) & 0xff) {
2271 case 3:
2272 sc->dc_srm_media = IFM_10_T;
2273 break;
2274 case 4:
2275 sc->dc_srm_media = IFM_10_T | IFM_FDX;
2276 break;
2277 case 5:
2278 sc->dc_srm_media = IFM_100_TX;
2279 break;
2280 case 6:
2281 sc->dc_srm_media = IFM_100_TX | IFM_FDX;
2282 break;
2283 }
2284 if (sc->dc_srm_media)
2285 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER;
2286 }
2287 #endif
2288
2289 /*
2290 * Call MI attach routine.
2291 */
2292 ether_ifattach(ifp, eaddr);
2293
2294 /* Hook interrupt last to avoid having to lock softc */
2295 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE,
2296 dc_intr, sc, &sc->dc_intrhand);
2297
2298 if (error) {
2299 device_printf(dev, "couldn't set up irq\n");
2300 ether_ifdetach(ifp);
2301 goto fail;
2302 }
2303
2304 fail:
2305 if (error)
2306 dc_detach(dev);
2307 return (error);
2308 }
2309
2310 /*
2311 * Shutdown hardware and free up resources. This can be called any
2312 * time after the mutex has been initialized. It is called in both
2313 * the error case in attach and the normal detach case so it needs
2314 * to be careful about only freeing resources that have actually been
2315 * allocated.
2316 */
2317 static int
2318 dc_detach(device_t dev)
2319 {
2320 struct dc_softc *sc;
2321 struct ifnet *ifp;
2322 struct dc_mediainfo *m;
2323 int i;
2324
2325 sc = device_get_softc(dev);
2326 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized"));
2327
2328 ifp = sc->dc_ifp;
2329
2330 #ifdef DEVICE_POLLING
2331 if (ifp->if_capenable & IFCAP_POLLING)
2332 ether_poll_deregister(ifp);
2333 #endif
2334
2335 /* These should only be active if attach succeeded */
2336 if (device_is_attached(dev)) {
2337 DC_LOCK(sc);
2338 dc_stop(sc);
2339 DC_UNLOCK(sc);
2340 callout_drain(&sc->dc_stat_ch);
2341 ether_ifdetach(ifp);
2342 }
2343 if (ifp)
2344 if_free(ifp);
2345 if (sc->dc_miibus)
2346 device_delete_child(dev, sc->dc_miibus);
2347 bus_generic_detach(dev);
2348
2349 if (sc->dc_intrhand)
2350 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2351 if (sc->dc_irq)
2352 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2353 if (sc->dc_res)
2354 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2355
2356 if (sc->dc_cdata.dc_sbuf != NULL)
2357 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap);
2358 if (sc->dc_ldata != NULL)
2359 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap);
2360 if (sc->dc_mtag) {
2361 for (i = 0; i < DC_TX_LIST_CNT; i++)
2362 if (sc->dc_cdata.dc_tx_map[i] != NULL)
2363 bus_dmamap_destroy(sc->dc_mtag,
2364 sc->dc_cdata.dc_tx_map[i]);
2365 for (i = 0; i < DC_RX_LIST_CNT; i++)
2366 if (sc->dc_cdata.dc_rx_map[i] != NULL)
2367 bus_dmamap_destroy(sc->dc_mtag,
2368 sc->dc_cdata.dc_rx_map[i]);
2369 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap);
2370 }
2371 if (sc->dc_stag)
2372 bus_dma_tag_destroy(sc->dc_stag);
2373 if (sc->dc_mtag)
2374 bus_dma_tag_destroy(sc->dc_mtag);
2375 if (sc->dc_ltag)
2376 bus_dma_tag_destroy(sc->dc_ltag);
2377
2378 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2379
2380 while (sc->dc_mi != NULL) {
2381 m = sc->dc_mi->dc_next;
2382 free(sc->dc_mi, M_DEVBUF);
2383 sc->dc_mi = m;
2384 }
2385 free(sc->dc_srom, M_DEVBUF);
2386
2387 mtx_destroy(&sc->dc_mtx);
2388
2389 return (0);
2390 }
2391
2392 /*
2393 * Initialize the transmit descriptors.
2394 */
2395 static int
2396 dc_list_tx_init(struct dc_softc *sc)
2397 {
2398 struct dc_chain_data *cd;
2399 struct dc_list_data *ld;
2400 int i, nexti;
2401
2402 cd = &sc->dc_cdata;
2403 ld = sc->dc_ldata;
2404 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2405 if (i == DC_TX_LIST_CNT - 1)
2406 nexti = 0;
2407 else
2408 nexti = i + 1;
2409 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti));
2410 cd->dc_tx_chain[i] = NULL;
2411 ld->dc_tx_list[i].dc_data = 0;
2412 ld->dc_tx_list[i].dc_ctl = 0;
2413 }
2414
2415 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2416 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2417 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2418 return (0);
2419 }
2420
2421
2422 /*
2423 * Initialize the RX descriptors and allocate mbufs for them. Note that
2424 * we arrange the descriptors in a closed ring, so that the last descriptor
2425 * points back to the first.
2426 */
2427 static int
2428 dc_list_rx_init(struct dc_softc *sc)
2429 {
2430 struct dc_chain_data *cd;
2431 struct dc_list_data *ld;
2432 int i, nexti;
2433
2434 cd = &sc->dc_cdata;
2435 ld = sc->dc_ldata;
2436
2437 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2438 if (dc_newbuf(sc, i, 1) != 0)
2439 return (ENOBUFS);
2440 if (i == DC_RX_LIST_CNT - 1)
2441 nexti = 0;
2442 else
2443 nexti = i + 1;
2444 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti));
2445 }
2446
2447 cd->dc_rx_prod = 0;
2448 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2449 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2450 return (0);
2451 }
2452
2453 static void
2454 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error)
2455 void *arg;
2456 bus_dma_segment_t *segs;
2457 int nseg;
2458 bus_size_t mapsize;
2459 int error;
2460 {
2461 struct dc_softc *sc;
2462 struct dc_desc *c;
2463
2464 sc = arg;
2465 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur];
2466 if (error) {
2467 sc->dc_cdata.dc_rx_err = error;
2468 return;
2469 }
2470
2471 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
2472 sc->dc_cdata.dc_rx_err = 0;
2473 c->dc_data = htole32(segs->ds_addr);
2474 }
2475
2476 /*
2477 * Initialize an RX descriptor and attach an MBUF cluster.
2478 */
2479 static int
2480 dc_newbuf(struct dc_softc *sc, int i, int alloc)
2481 {
2482 struct mbuf *m_new;
2483 bus_dmamap_t tmp;
2484 int error;
2485
2486 if (alloc) {
2487 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2488 if (m_new == NULL)
2489 return (ENOBUFS);
2490 } else {
2491 m_new = sc->dc_cdata.dc_rx_chain[i];
2492 m_new->m_data = m_new->m_ext.ext_buf;
2493 }
2494 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2495 m_adj(m_new, sizeof(u_int64_t));
2496
2497 /*
2498 * If this is a PNIC chip, zero the buffer. This is part
2499 * of the workaround for the receive bug in the 82c168 and
2500 * 82c169 chips.
2501 */
2502 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2503 bzero(mtod(m_new, char *), m_new->m_len);
2504
2505 /* No need to remap the mbuf if we're reusing it. */
2506 if (alloc) {
2507 sc->dc_cdata.dc_rx_cur = i;
2508 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap,
2509 m_new, dc_dma_map_rxbuf, sc, 0);
2510 if (error) {
2511 m_freem(m_new);
2512 return (error);
2513 }
2514 if (sc->dc_cdata.dc_rx_err != 0) {
2515 m_freem(m_new);
2516 return (sc->dc_cdata.dc_rx_err);
2517 }
2518 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]);
2519 tmp = sc->dc_cdata.dc_rx_map[i];
2520 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap;
2521 sc->dc_sparemap = tmp;
2522 sc->dc_cdata.dc_rx_chain[i] = m_new;
2523 }
2524
2525 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2526 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
2527 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
2528 BUS_DMASYNC_PREREAD);
2529 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2531 return (0);
2532 }
2533
2534 /*
2535 * Grrrrr.
2536 * The PNIC chip has a terrible bug in it that manifests itself during
2537 * periods of heavy activity. The exact mode of failure if difficult to
2538 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2539 * will happen on slow machines. The bug is that sometimes instead of
2540 * uploading one complete frame during reception, it uploads what looks
2541 * like the entire contents of its FIFO memory. The frame we want is at
2542 * the end of the whole mess, but we never know exactly how much data has
2543 * been uploaded, so salvaging the frame is hard.
2544 *
2545 * There is only one way to do it reliably, and it's disgusting.
2546 * Here's what we know:
2547 *
2548 * - We know there will always be somewhere between one and three extra
2549 * descriptors uploaded.
2550 *
2551 * - We know the desired received frame will always be at the end of the
2552 * total data upload.
2553 *
2554 * - We know the size of the desired received frame because it will be
2555 * provided in the length field of the status word in the last descriptor.
2556 *
2557 * Here's what we do:
2558 *
2559 * - When we allocate buffers for the receive ring, we bzero() them.
2560 * This means that we know that the buffer contents should be all
2561 * zeros, except for data uploaded by the chip.
2562 *
2563 * - We also force the PNIC chip to upload frames that include the
2564 * ethernet CRC at the end.
2565 *
2566 * - We gather all of the bogus frame data into a single buffer.
2567 *
2568 * - We then position a pointer at the end of this buffer and scan
2569 * backwards until we encounter the first non-zero byte of data.
2570 * This is the end of the received frame. We know we will encounter
2571 * some data at the end of the frame because the CRC will always be
2572 * there, so even if the sender transmits a packet of all zeros,
2573 * we won't be fooled.
2574 *
2575 * - We know the size of the actual received frame, so we subtract
2576 * that value from the current pointer location. This brings us
2577 * to the start of the actual received packet.
2578 *
2579 * - We copy this into an mbuf and pass it on, along with the actual
2580 * frame length.
2581 *
2582 * The performance hit is tremendous, but it beats dropping frames all
2583 * the time.
2584 */
2585
2586 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
2587 static void
2588 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2589 {
2590 struct dc_desc *cur_rx;
2591 struct dc_desc *c = NULL;
2592 struct mbuf *m = NULL;
2593 unsigned char *ptr;
2594 int i, total_len;
2595 u_int32_t rxstat = 0;
2596
2597 i = sc->dc_pnic_rx_bug_save;
2598 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2599 ptr = sc->dc_pnic_rx_buf;
2600 bzero(ptr, DC_RXLEN * 5);
2601
2602 /* Copy all the bytes from the bogus buffers. */
2603 while (1) {
2604 c = &sc->dc_ldata->dc_rx_list[i];
2605 rxstat = le32toh(c->dc_status);
2606 m = sc->dc_cdata.dc_rx_chain[i];
2607 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2608 ptr += DC_RXLEN;
2609 /* If this is the last buffer, break out. */
2610 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2611 break;
2612 dc_newbuf(sc, i, 0);
2613 DC_INC(i, DC_RX_LIST_CNT);
2614 }
2615
2616 /* Find the length of the actual receive frame. */
2617 total_len = DC_RXBYTES(rxstat);
2618
2619 /* Scan backwards until we hit a non-zero byte. */
2620 while (*ptr == 0x00)
2621 ptr--;
2622
2623 /* Round off. */
2624 if ((uintptr_t)(ptr) & 0x3)
2625 ptr -= 1;
2626
2627 /* Now find the start of the frame. */
2628 ptr -= total_len;
2629 if (ptr < sc->dc_pnic_rx_buf)
2630 ptr = sc->dc_pnic_rx_buf;
2631
2632 /*
2633 * Now copy the salvaged frame to the last mbuf and fake up
2634 * the status word to make it look like a successful
2635 * frame reception.
2636 */
2637 dc_newbuf(sc, i, 0);
2638 bcopy(ptr, mtod(m, char *), total_len);
2639 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
2640 }
2641
2642 /*
2643 * This routine searches the RX ring for dirty descriptors in the
2644 * event that the rxeof routine falls out of sync with the chip's
2645 * current descriptor pointer. This may happen sometimes as a result
2646 * of a "no RX buffer available" condition that happens when the chip
2647 * consumes all of the RX buffers before the driver has a chance to
2648 * process the RX ring. This routine may need to be called more than
2649 * once to bring the driver back in sync with the chip, however we
2650 * should still be getting RX DONE interrupts to drive the search
2651 * for new packets in the RX ring, so we should catch up eventually.
2652 */
2653 static int
2654 dc_rx_resync(struct dc_softc *sc)
2655 {
2656 struct dc_desc *cur_rx;
2657 int i, pos;
2658
2659 pos = sc->dc_cdata.dc_rx_prod;
2660
2661 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2662 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2663 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN))
2664 break;
2665 DC_INC(pos, DC_RX_LIST_CNT);
2666 }
2667
2668 /* If the ring really is empty, then just return. */
2669 if (i == DC_RX_LIST_CNT)
2670 return (0);
2671
2672 /* We've fallen behing the chip: catch it. */
2673 sc->dc_cdata.dc_rx_prod = pos;
2674
2675 return (EAGAIN);
2676 }
2677
2678 /*
2679 * A frame has been uploaded: pass the resulting mbuf chain up to
2680 * the higher level protocols.
2681 */
2682 static void
2683 dc_rxeof(struct dc_softc *sc)
2684 {
2685 struct mbuf *m, *m0;
2686 struct ifnet *ifp;
2687 struct dc_desc *cur_rx;
2688 int i, total_len = 0;
2689 u_int32_t rxstat;
2690
2691 DC_LOCK_ASSERT(sc);
2692
2693 ifp = sc->dc_ifp;
2694 i = sc->dc_cdata.dc_rx_prod;
2695
2696 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
2697 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) &
2698 DC_RXSTAT_OWN)) {
2699 #ifdef DEVICE_POLLING
2700 if (ifp->if_capenable & IFCAP_POLLING) {
2701 if (sc->rxcycles <= 0)
2702 break;
2703 sc->rxcycles--;
2704 }
2705 #endif
2706 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2707 rxstat = le32toh(cur_rx->dc_status);
2708 m = sc->dc_cdata.dc_rx_chain[i];
2709 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
2710 BUS_DMASYNC_POSTREAD);
2711 total_len = DC_RXBYTES(rxstat);
2712
2713 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2714 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2715 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2716 sc->dc_pnic_rx_bug_save = i;
2717 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2718 DC_INC(i, DC_RX_LIST_CNT);
2719 continue;
2720 }
2721 dc_pnic_rx_bug_war(sc, i);
2722 rxstat = le32toh(cur_rx->dc_status);
2723 total_len = DC_RXBYTES(rxstat);
2724 }
2725 }
2726
2727 /*
2728 * If an error occurs, update stats, clear the
2729 * status word and leave the mbuf cluster in place:
2730 * it should simply get re-used next time this descriptor
2731 * comes up in the ring. However, don't report long
2732 * frames as errors since they could be vlans.
2733 */
2734 if ((rxstat & DC_RXSTAT_RXERR)) {
2735 if (!(rxstat & DC_RXSTAT_GIANT) ||
2736 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2737 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2738 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2739 ifp->if_ierrors++;
2740 if (rxstat & DC_RXSTAT_COLLSEEN)
2741 ifp->if_collisions++;
2742 dc_newbuf(sc, i, 0);
2743 if (rxstat & DC_RXSTAT_CRCERR) {
2744 DC_INC(i, DC_RX_LIST_CNT);
2745 continue;
2746 } else {
2747 dc_init_locked(sc);
2748 return;
2749 }
2750 }
2751 }
2752
2753 /* No errors; receive the packet. */
2754 total_len -= ETHER_CRC_LEN;
2755 #ifdef __NO_STRICT_ALIGNMENT
2756 /*
2757 * On architectures without alignment problems we try to
2758 * allocate a new buffer for the receive ring, and pass up
2759 * the one where the packet is already, saving the expensive
2760 * copy done in m_devget().
2761 * If we are on an architecture with alignment problems, or
2762 * if the allocation fails, then use m_devget and leave the
2763 * existing buffer in the receive ring.
2764 */
2765 if (dc_newbuf(sc, i, 1) == 0) {
2766 m->m_pkthdr.rcvif = ifp;
2767 m->m_pkthdr.len = m->m_len = total_len;
2768 DC_INC(i, DC_RX_LIST_CNT);
2769 } else
2770 #endif
2771 {
2772 m0 = m_devget(mtod(m, char *), total_len,
2773 ETHER_ALIGN, ifp, NULL);
2774 dc_newbuf(sc, i, 0);
2775 DC_INC(i, DC_RX_LIST_CNT);
2776 if (m0 == NULL) {
2777 ifp->if_ierrors++;
2778 continue;
2779 }
2780 m = m0;
2781 }
2782
2783 ifp->if_ipackets++;
2784 DC_UNLOCK(sc);
2785 (*ifp->if_input)(ifp, m);
2786 DC_LOCK(sc);
2787 }
2788
2789 sc->dc_cdata.dc_rx_prod = i;
2790 }
2791
2792 /*
2793 * A frame was downloaded to the chip. It's safe for us to clean up
2794 * the list buffers.
2795 */
2796
2797 static void
2798 dc_txeof(struct dc_softc *sc)
2799 {
2800 struct dc_desc *cur_tx = NULL;
2801 struct ifnet *ifp;
2802 int idx;
2803 u_int32_t ctl, txstat;
2804
2805 ifp = sc->dc_ifp;
2806
2807 /*
2808 * Go through our tx list and free mbufs for those
2809 * frames that have been transmitted.
2810 */
2811 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
2812 idx = sc->dc_cdata.dc_tx_cons;
2813 while (idx != sc->dc_cdata.dc_tx_prod) {
2814
2815 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2816 txstat = le32toh(cur_tx->dc_status);
2817 ctl = le32toh(cur_tx->dc_ctl);
2818
2819 if (txstat & DC_TXSTAT_OWN)
2820 break;
2821
2822 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) {
2823 if (ctl & DC_TXCTL_SETUP) {
2824 /*
2825 * Yes, the PNIC is so brain damaged
2826 * that it will sometimes generate a TX
2827 * underrun error while DMAing the RX
2828 * filter setup frame. If we detect this,
2829 * we have to send the setup frame again,
2830 * or else the filter won't be programmed
2831 * correctly.
2832 */
2833 if (DC_IS_PNIC(sc)) {
2834 if (txstat & DC_TXSTAT_ERRSUM)
2835 dc_setfilt(sc);
2836 }
2837 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2838 }
2839 sc->dc_cdata.dc_tx_cnt--;
2840 DC_INC(idx, DC_TX_LIST_CNT);
2841 continue;
2842 }
2843
2844 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2845 /*
2846 * XXX: Why does my Xircom taunt me so?
2847 * For some reason it likes setting the CARRLOST flag
2848 * even when the carrier is there. wtf?!?
2849 * Who knows, but Conexant chips have the
2850 * same problem. Maybe they took lessons
2851 * from Xircom.
2852 */
2853 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2854 sc->dc_pmode == DC_PMODE_MII &&
2855 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2856 DC_TXSTAT_NOCARRIER)))
2857 txstat &= ~DC_TXSTAT_ERRSUM;
2858 } else {
2859 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2860 sc->dc_pmode == DC_PMODE_MII &&
2861 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2862 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST)))
2863 txstat &= ~DC_TXSTAT_ERRSUM;
2864 }
2865
2866 if (txstat & DC_TXSTAT_ERRSUM) {
2867 ifp->if_oerrors++;
2868 if (txstat & DC_TXSTAT_EXCESSCOLL)
2869 ifp->if_collisions++;
2870 if (txstat & DC_TXSTAT_LATECOLL)
2871 ifp->if_collisions++;
2872 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2873 dc_init_locked(sc);
2874 return;
2875 }
2876 }
2877
2878 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2879
2880 ifp->if_opackets++;
2881 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2882 bus_dmamap_sync(sc->dc_mtag,
2883 sc->dc_cdata.dc_tx_map[idx],
2884 BUS_DMASYNC_POSTWRITE);
2885 bus_dmamap_unload(sc->dc_mtag,
2886 sc->dc_cdata.dc_tx_map[idx]);
2887 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2888 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2889 }
2890
2891 sc->dc_cdata.dc_tx_cnt--;
2892 DC_INC(idx, DC_TX_LIST_CNT);
2893 }
2894
2895 if (idx != sc->dc_cdata.dc_tx_cons) {
2896 /* Some buffers have been freed. */
2897 sc->dc_cdata.dc_tx_cons = idx;
2898 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2899 }
2900 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2901 }
2902
2903 static void
2904 dc_tick(void *xsc)
2905 {
2906 struct dc_softc *sc;
2907 struct mii_data *mii;
2908 struct ifnet *ifp;
2909 u_int32_t r;
2910
2911 sc = xsc;
2912 DC_LOCK_ASSERT(sc);
2913 ifp = sc->dc_ifp;
2914 mii = device_get_softc(sc->dc_miibus);
2915
2916 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2917 if (sc->dc_flags & DC_21143_NWAY) {
2918 r = CSR_READ_4(sc, DC_10BTSTAT);
2919 if (IFM_SUBTYPE(mii->mii_media_active) ==
2920 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2921 sc->dc_link = 0;
2922 mii_mediachg(mii);
2923 }
2924 if (IFM_SUBTYPE(mii->mii_media_active) ==
2925 IFM_10_T && (r & DC_TSTAT_LS10)) {
2926 sc->dc_link = 0;
2927 mii_mediachg(mii);
2928 }
2929 if (sc->dc_link == 0)
2930 mii_tick(mii);
2931 } else {
2932 r = CSR_READ_4(sc, DC_ISR);
2933 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2934 sc->dc_cdata.dc_tx_cnt == 0) {
2935 mii_tick(mii);
2936 if (!(mii->mii_media_status & IFM_ACTIVE))
2937 sc->dc_link = 0;
2938 }
2939 }
2940 } else
2941 mii_tick(mii);
2942
2943 /*
2944 * When the init routine completes, we expect to be able to send
2945 * packets right away, and in fact the network code will send a
2946 * gratuitous ARP the moment the init routine marks the interface
2947 * as running. However, even though the MAC may have been initialized,
2948 * there may be a delay of a few seconds before the PHY completes
2949 * autonegotiation and the link is brought up. Any transmissions
2950 * made during that delay will be lost. Dealing with this is tricky:
2951 * we can't just pause in the init routine while waiting for the
2952 * PHY to come ready since that would bring the whole system to
2953 * a screeching halt for several seconds.
2954 *
2955 * What we do here is prevent the TX start routine from sending
2956 * any packets until a link has been established. After the
2957 * interface has been initialized, the tick routine will poll
2958 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2959 * that time, packets will stay in the send queue, and once the
2960 * link comes up, they will be flushed out to the wire.
2961 */
2962 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE &&
2963 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2964 sc->dc_link++;
2965 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2966 dc_start_locked(ifp);
2967 }
2968
2969 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2970 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
2971 else
2972 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
2973 }
2974
2975 /*
2976 * A transmit underrun has occurred. Back off the transmit threshold,
2977 * or switch to store and forward mode if we have to.
2978 */
2979 static void
2980 dc_tx_underrun(struct dc_softc *sc)
2981 {
2982 u_int32_t isr;
2983 int i;
2984
2985 if (DC_IS_DAVICOM(sc))
2986 dc_init_locked(sc);
2987
2988 if (DC_IS_INTEL(sc)) {
2989 /*
2990 * The real 21143 requires that the transmitter be idle
2991 * in order to change the transmit threshold or store
2992 * and forward state.
2993 */
2994 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2995
2996 for (i = 0; i < DC_TIMEOUT; i++) {
2997 isr = CSR_READ_4(sc, DC_ISR);
2998 if (isr & DC_ISR_TX_IDLE)
2999 break;
3000 DELAY(10);
3001 }
3002 if (i == DC_TIMEOUT) {
3003 device_printf(sc->dc_dev,
3004 "%s: failed to force tx to idle state\n",
3005 __func__);
3006 dc_init_locked(sc);
3007 }
3008 }
3009
3010 device_printf(sc->dc_dev, "TX underrun -- ");
3011 sc->dc_txthresh += DC_TXTHRESH_INC;
3012 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3013 printf("using store and forward mode\n");
3014 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3015 } else {
3016 printf("increasing TX threshold\n");
3017 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3018 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3019 }
3020
3021 if (DC_IS_INTEL(sc))
3022 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3023 }
3024
3025 #ifdef DEVICE_POLLING
3026 static poll_handler_t dc_poll;
3027
3028 static void
3029 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3030 {
3031 struct dc_softc *sc = ifp->if_softc;
3032
3033 DC_LOCK(sc);
3034
3035 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3036 DC_UNLOCK(sc);
3037 return;
3038 }
3039
3040 sc->rxcycles = count;
3041 dc_rxeof(sc);
3042 dc_txeof(sc);
3043 if (!IFQ_IS_EMPTY(&ifp->if_snd) &&
3044 !(ifp->if_drv_flags & IFF_DRV_OACTIVE))
3045 dc_start_locked(ifp);
3046
3047 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3048 u_int32_t status;
3049
3050 status = CSR_READ_4(sc, DC_ISR);
3051 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF |
3052 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN |
3053 DC_ISR_BUS_ERR);
3054 if (!status) {
3055 DC_UNLOCK(sc);
3056 return;
3057 }
3058 /* ack what we have */
3059 CSR_WRITE_4(sc, DC_ISR, status);
3060
3061 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) {
3062 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3063 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3064
3065 if (dc_rx_resync(sc))
3066 dc_rxeof(sc);
3067 }
3068 /* restart transmit unit if necessary */
3069 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3070 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3071
3072 if (status & DC_ISR_TX_UNDERRUN)
3073 dc_tx_underrun(sc);
3074
3075 if (status & DC_ISR_BUS_ERR) {
3076 if_printf(ifp, "%s: bus error\n", __func__);
3077 dc_reset(sc);
3078 dc_init_locked(sc);
3079 }
3080 }
3081 DC_UNLOCK(sc);
3082 }
3083 #endif /* DEVICE_POLLING */
3084
3085 static void
3086 dc_intr(void *arg)
3087 {
3088 struct dc_softc *sc;
3089 struct ifnet *ifp;
3090 u_int32_t status;
3091
3092 sc = arg;
3093
3094 if (sc->suspended)
3095 return;
3096
3097 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
3098 return;
3099
3100 DC_LOCK(sc);
3101 ifp = sc->dc_ifp;
3102 #ifdef DEVICE_POLLING
3103 if (ifp->if_capenable & IFCAP_POLLING) {
3104 DC_UNLOCK(sc);
3105 return;
3106 }
3107 #endif
3108
3109 /* Suppress unwanted interrupts */
3110 if (!(ifp->if_flags & IFF_UP)) {
3111 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
3112 dc_stop(sc);
3113 DC_UNLOCK(sc);
3114 return;
3115 }
3116
3117 /* Disable interrupts. */
3118 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3119
3120 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) &&
3121 status != 0xFFFFFFFF &&
3122 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3123
3124 CSR_WRITE_4(sc, DC_ISR, status);
3125
3126 if (status & DC_ISR_RX_OK) {
3127 int curpkts;
3128 curpkts = ifp->if_ipackets;
3129 dc_rxeof(sc);
3130 if (curpkts == ifp->if_ipackets) {
3131 while (dc_rx_resync(sc))
3132 dc_rxeof(sc);
3133 }
3134 }
3135
3136 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF))
3137 dc_txeof(sc);
3138
3139 if (status & DC_ISR_TX_IDLE) {
3140 dc_txeof(sc);
3141 if (sc->dc_cdata.dc_tx_cnt) {
3142 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3143 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3144 }
3145 }
3146
3147 if (status & DC_ISR_TX_UNDERRUN)
3148 dc_tx_underrun(sc);
3149
3150 if ((status & DC_ISR_RX_WATDOGTIMEO)
3151 || (status & DC_ISR_RX_NOBUF)) {
3152 int curpkts;
3153 curpkts = ifp->if_ipackets;
3154 dc_rxeof(sc);
3155 if (curpkts == ifp->if_ipackets) {
3156 while (dc_rx_resync(sc))
3157 dc_rxeof(sc);
3158 }
3159 }
3160
3161 if (status & DC_ISR_BUS_ERR) {
3162 dc_reset(sc);
3163 dc_init_locked(sc);
3164 }
3165 }
3166
3167 /* Re-enable interrupts. */
3168 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3169
3170 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3171 dc_start_locked(ifp);
3172
3173 DC_UNLOCK(sc);
3174 }
3175
3176 static void
3177 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error)
3178 void *arg;
3179 bus_dma_segment_t *segs;
3180 int nseg;
3181 bus_size_t mapsize;
3182 int error;
3183 {
3184 struct dc_softc *sc;
3185 struct dc_desc *f;
3186 int cur, first, frag, i;
3187
3188 sc = arg;
3189 if (error) {
3190 sc->dc_cdata.dc_tx_err = error;
3191 return;
3192 }
3193
3194 first = cur = frag = sc->dc_cdata.dc_tx_prod;
3195 for (i = 0; i < nseg; i++) {
3196 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3197 (frag == (DC_TX_LIST_CNT - 1)) &&
3198 (first != sc->dc_cdata.dc_tx_first)) {
3199 bus_dmamap_unload(sc->dc_mtag,
3200 sc->dc_cdata.dc_tx_map[first]);
3201 sc->dc_cdata.dc_tx_err = ENOBUFS;
3202 return;
3203 }
3204
3205 f = &sc->dc_ldata->dc_tx_list[frag];
3206 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len);
3207 if (i == 0) {
3208 f->dc_status = 0;
3209 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG);
3210 } else
3211 f->dc_status = htole32(DC_TXSTAT_OWN);
3212 f->dc_data = htole32(segs[i].ds_addr);
3213 cur = frag;
3214 DC_INC(frag, DC_TX_LIST_CNT);
3215 }
3216
3217 sc->dc_cdata.dc_tx_err = 0;
3218 sc->dc_cdata.dc_tx_prod = frag;
3219 sc->dc_cdata.dc_tx_cnt += nseg;
3220 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
3221 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping;
3222 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3223 sc->dc_ldata->dc_tx_list[first].dc_ctl |=
3224 htole32(DC_TXCTL_FINT);
3225 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3226 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3227 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3228 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3229 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN);
3230 }
3231
3232 /*
3233 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3234 * pointers to the fragment pointers.
3235 */
3236 static int
3237 dc_encap(struct dc_softc *sc, struct mbuf **m_head)
3238 {
3239 struct mbuf *m;
3240 int error, idx, chainlen = 0;
3241
3242 /*
3243 * If there's no way we can send any packets, return now.
3244 */
3245 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6)
3246 return (ENOBUFS);
3247
3248 /*
3249 * Count the number of frags in this chain to see if
3250 * we need to m_defrag. Since the descriptor list is shared
3251 * by all packets, we'll m_defrag long chains so that they
3252 * do not use up the entire list, even if they would fit.
3253 */
3254 for (m = *m_head; m != NULL; m = m->m_next)
3255 chainlen++;
3256
3257 if ((chainlen > DC_TX_LIST_CNT / 4) ||
3258 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) {
3259 m = m_defrag(*m_head, M_DONTWAIT);
3260 if (m == NULL)
3261 return (ENOBUFS);
3262 *m_head = m;
3263 }
3264
3265 /*
3266 * Start packing the mbufs in this chain into
3267 * the fragment pointers. Stop when we run out
3268 * of fragments or hit the end of the mbuf chain.
3269 */
3270 idx = sc->dc_cdata.dc_tx_prod;
3271 sc->dc_cdata.dc_tx_mapping = *m_head;
3272 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx],
3273 *m_head, dc_dma_map_txbuf, sc, 0);
3274 if (error)
3275 return (error);
3276 if (sc->dc_cdata.dc_tx_err != 0)
3277 return (sc->dc_cdata.dc_tx_err);
3278 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx],
3279 BUS_DMASYNC_PREWRITE);
3280 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
3281 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3282 return (0);
3283 }
3284
3285 /*
3286 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3287 * to the mbuf data regions directly in the transmit lists. We also save a
3288 * copy of the pointers since the transmit list fragment pointers are
3289 * physical addresses.
3290 */
3291
3292 static void
3293 dc_start(struct ifnet *ifp)
3294 {
3295 struct dc_softc *sc;
3296
3297 sc = ifp->if_softc;
3298 DC_LOCK(sc);
3299 dc_start_locked(ifp);
3300 DC_UNLOCK(sc);
3301 }
3302
3303 static void
3304 dc_start_locked(struct ifnet *ifp)
3305 {
3306 struct dc_softc *sc;
3307 struct mbuf *m_head = NULL, *m;
3308 unsigned int queued = 0;
3309 int idx;
3310
3311 sc = ifp->if_softc;
3312
3313 DC_LOCK_ASSERT(sc);
3314
3315 if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
3316 return;
3317
3318 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
3319 return;
3320
3321 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod;
3322
3323 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3324 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3325 if (m_head == NULL)
3326 break;
3327
3328 if (sc->dc_flags & DC_TX_COALESCE &&
3329 (m_head->m_next != NULL ||
3330 sc->dc_flags & DC_TX_ALIGN)) {
3331 m = m_defrag(m_head, M_DONTWAIT);
3332 if (m == NULL) {
3333 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3334 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3335 break;
3336 } else {
3337 m_head = m;
3338 }
3339 }
3340
3341 if (dc_encap(sc, &m_head)) {
3342 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3343 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3344 break;
3345 }
3346 idx = sc->dc_cdata.dc_tx_prod;
3347
3348 queued++;
3349 /*
3350 * If there's a BPF listener, bounce a copy of this frame
3351 * to him.
3352 */
3353 BPF_MTAP(ifp, m_head);
3354
3355 if (sc->dc_flags & DC_TX_ONE) {
3356 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3357 break;
3358 }
3359 }
3360
3361 if (queued > 0) {
3362 /* Transmit */
3363 if (!(sc->dc_flags & DC_TX_POLL))
3364 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3365
3366 /*
3367 * Set a timeout in case the chip goes out to lunch.
3368 */
3369 ifp->if_timer = 5;
3370 }
3371 }
3372
3373 static void
3374 dc_init(void *xsc)
3375 {
3376 struct dc_softc *sc = xsc;
3377
3378 DC_LOCK(sc);
3379 dc_init_locked(sc);
3380 #ifdef SRM_MEDIA
3381 if(sc->dc_srm_media) {
3382 struct ifreq ifr;
3383 struct mii_data *mii;
3384
3385 ifr.ifr_media = sc->dc_srm_media;
3386 sc->dc_srm_media = 0;
3387 DC_UNLOCK(sc);
3388 mii = device_get_softc(sc->dc_miibus);
3389 ifmedia_ioctl(sc->dc_ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA);
3390 } else
3391 #endif
3392 DC_UNLOCK(sc);
3393 }
3394
3395 static void
3396 dc_init_locked(struct dc_softc *sc)
3397 {
3398 struct ifnet *ifp = sc->dc_ifp;
3399 struct mii_data *mii;
3400
3401 DC_LOCK_ASSERT(sc);
3402
3403 mii = device_get_softc(sc->dc_miibus);
3404
3405 /*
3406 * Cancel pending I/O and free all RX/TX buffers.
3407 */
3408 dc_stop(sc);
3409 dc_reset(sc);
3410
3411 /*
3412 * Set cache alignment and burst length.
3413 */
3414 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3415 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3416 else
3417 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE);
3418 /*
3419 * Evenly share the bus between receive and transmit process.
3420 */
3421 if (DC_IS_INTEL(sc))
3422 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3423 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3424 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3425 } else {
3426 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3427 }
3428 if (sc->dc_flags & DC_TX_POLL)
3429 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3430 switch(sc->dc_cachesize) {
3431 case 32:
3432 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3433 break;
3434 case 16:
3435 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3436 break;
3437 case 8:
3438 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3439 break;
3440 case 0:
3441 default:
3442 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3443 break;
3444 }
3445
3446 if (sc->dc_flags & DC_TX_STORENFWD)
3447 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3448 else {
3449 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3450 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3451 } else {
3452 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3453 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3454 }
3455 }
3456
3457 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3458 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3459
3460 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3461 /*
3462 * The app notes for the 98713 and 98715A say that
3463 * in order to have the chips operate properly, a magic
3464 * number must be written to CSR16. Macronix does not
3465 * document the meaning of these bits so there's no way
3466 * to know exactly what they do. The 98713 has a magic
3467 * number all its own; the rest all use a different one.
3468 */
3469 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3470 if (sc->dc_type == DC_TYPE_98713)
3471 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3472 else
3473 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3474 }
3475
3476 if (DC_IS_XIRCOM(sc)) {
3477 /*
3478 * setup General Purpose Port mode and data so the tulip
3479 * can talk to the MII.
3480 */
3481 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3482 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3483 DELAY(10);
3484 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3485 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3486 DELAY(10);
3487 }
3488
3489 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3490 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3491
3492 /* Init circular RX list. */
3493 if (dc_list_rx_init(sc) == ENOBUFS) {
3494 device_printf(sc->dc_dev,
3495 "initialization failed: no memory for rx buffers\n");
3496 dc_stop(sc);
3497 return;
3498 }
3499
3500 /*
3501 * Init TX descriptors.
3502 */
3503 dc_list_tx_init(sc);
3504
3505 /*
3506 * Load the address of the RX list.
3507 */
3508 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0));
3509 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0));
3510
3511 /*
3512 * Enable interrupts.
3513 */
3514 #ifdef DEVICE_POLLING
3515 /*
3516 * ... but only if we are not polling, and make sure they are off in
3517 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3518 * after a reset.
3519 */
3520 if (ifp->if_capenable & IFCAP_POLLING)
3521 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3522 else
3523 #endif
3524 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3525 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3526
3527 /* Enable transmitter. */
3528 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3529
3530 /*
3531 * If this is an Intel 21143 and we're not using the
3532 * MII port, program the LED control pins so we get
3533 * link and activity indications.
3534 */
3535 if (sc->dc_flags & DC_TULIP_LEDS) {
3536 CSR_WRITE_4(sc, DC_WATCHDOG,
3537 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY);
3538 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3539 }
3540
3541 /*
3542 * Load the RX/multicast filter. We do this sort of late
3543 * because the filter programming scheme on the 21143 and
3544 * some clones requires DMAing a setup frame via the TX
3545 * engine, and we need the transmitter enabled for that.
3546 */
3547 dc_setfilt(sc);
3548
3549 /* Enable receiver. */
3550 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3551 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3552
3553 mii_mediachg(mii);
3554 dc_setcfg(sc, sc->dc_if_media);
3555
3556 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3557 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3558
3559 /* Don't start the ticker if this is a homePNA link. */
3560 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3561 sc->dc_link = 1;
3562 else {
3563 if (sc->dc_flags & DC_21143_NWAY)
3564 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3565 else
3566 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3567 }
3568 }
3569
3570 /*
3571 * Set media options.
3572 */
3573 static int
3574 dc_ifmedia_upd(struct ifnet *ifp)
3575 {
3576 struct dc_softc *sc;
3577 struct mii_data *mii;
3578 struct ifmedia *ifm;
3579
3580 sc = ifp->if_softc;
3581 mii = device_get_softc(sc->dc_miibus);
3582 DC_LOCK(sc);
3583 mii_mediachg(mii);
3584 ifm = &mii->mii_media;
3585
3586 if (DC_IS_DAVICOM(sc) &&
3587 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3588 dc_setcfg(sc, ifm->ifm_media);
3589 else
3590 sc->dc_link = 0;
3591 DC_UNLOCK(sc);
3592
3593 return (0);
3594 }
3595
3596 /*
3597 * Report current media status.
3598 */
3599 static void
3600 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3601 {
3602 struct dc_softc *sc;
3603 struct mii_data *mii;
3604 struct ifmedia *ifm;
3605
3606 sc = ifp->if_softc;
3607 mii = device_get_softc(sc->dc_miibus);
3608 DC_LOCK(sc);
3609 mii_pollstat(mii);
3610 ifm = &mii->mii_media;
3611 if (DC_IS_DAVICOM(sc)) {
3612 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3613 ifmr->ifm_active = ifm->ifm_media;
3614 ifmr->ifm_status = 0;
3615 DC_UNLOCK(sc);
3616 return;
3617 }
3618 }
3619 ifmr->ifm_active = mii->mii_media_active;
3620 ifmr->ifm_status = mii->mii_media_status;
3621 DC_UNLOCK(sc);
3622 }
3623
3624 static int
3625 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3626 {
3627 struct dc_softc *sc = ifp->if_softc;
3628 struct ifreq *ifr = (struct ifreq *)data;
3629 struct mii_data *mii;
3630 int error = 0;
3631
3632 switch (command) {
3633 case SIOCSIFFLAGS:
3634 DC_LOCK(sc);
3635 if (ifp->if_flags & IFF_UP) {
3636 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3637 (IFF_PROMISC | IFF_ALLMULTI);
3638
3639 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3640 if (need_setfilt)
3641 dc_setfilt(sc);
3642 } else {
3643 sc->dc_txthresh = 0;
3644 dc_init_locked(sc);
3645 }
3646 } else {
3647 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3648 dc_stop(sc);
3649 }
3650 sc->dc_if_flags = ifp->if_flags;
3651 DC_UNLOCK(sc);
3652 error = 0;
3653 break;
3654 case SIOCADDMULTI:
3655 case SIOCDELMULTI:
3656 DC_LOCK(sc);
3657 dc_setfilt(sc);
3658 DC_UNLOCK(sc);
3659 error = 0;
3660 break;
3661 case SIOCGIFMEDIA:
3662 case SIOCSIFMEDIA:
3663 mii = device_get_softc(sc->dc_miibus);
3664 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3665 #ifdef SRM_MEDIA
3666 DC_LOCK(sc);
3667 if (sc->dc_srm_media)
3668 sc->dc_srm_media = 0;
3669 DC_UNLOCK(sc);
3670 #endif
3671 break;
3672 case SIOCSIFCAP:
3673 #ifdef DEVICE_POLLING
3674 if (ifr->ifr_reqcap & IFCAP_POLLING &&
3675 !(ifp->if_capenable & IFCAP_POLLING)) {
3676 error = ether_poll_register(dc_poll, ifp);
3677 if (error)
3678 return(error);
3679 DC_LOCK(sc);
3680 /* Disable interrupts */
3681 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3682 ifp->if_capenable |= IFCAP_POLLING;
3683 DC_UNLOCK(sc);
3684 return (error);
3685
3686 }
3687 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
3688 ifp->if_capenable & IFCAP_POLLING) {
3689 error = ether_poll_deregister(ifp);
3690 /* Enable interrupts. */
3691 DC_LOCK(sc);
3692 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3693 ifp->if_capenable &= ~IFCAP_POLLING;
3694 DC_UNLOCK(sc);
3695 return (error);
3696 }
3697 #endif /* DEVICE_POLLING */
3698 break;
3699 default:
3700 error = ether_ioctl(ifp, command, data);
3701 break;
3702 }
3703
3704 return (error);
3705 }
3706
3707 static void
3708 dc_watchdog(struct ifnet *ifp)
3709 {
3710 struct dc_softc *sc;
3711
3712 sc = ifp->if_softc;
3713
3714 DC_LOCK(sc);
3715
3716 ifp->if_oerrors++;
3717 if_printf(ifp, "watchdog timeout\n");
3718
3719 dc_stop(sc);
3720 dc_reset(sc);
3721 dc_init_locked(sc);
3722
3723 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3724 dc_start_locked(ifp);
3725
3726 DC_UNLOCK(sc);
3727 }
3728
3729 /*
3730 * Stop the adapter and free any mbufs allocated to the
3731 * RX and TX lists.
3732 */
3733 static void
3734 dc_stop(struct dc_softc *sc)
3735 {
3736 struct ifnet *ifp;
3737 struct dc_list_data *ld;
3738 struct dc_chain_data *cd;
3739 int i;
3740 u_int32_t ctl;
3741
3742 DC_LOCK_ASSERT(sc);
3743
3744 ifp = sc->dc_ifp;
3745 ifp->if_timer = 0;
3746 ld = sc->dc_ldata;
3747 cd = &sc->dc_cdata;
3748
3749 callout_stop(&sc->dc_stat_ch);
3750
3751 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3752
3753 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON));
3754 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3755 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3756 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3757 sc->dc_link = 0;
3758
3759 /*
3760 * Free data in the RX lists.
3761 */
3762 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3763 if (cd->dc_rx_chain[i] != NULL) {
3764 m_freem(cd->dc_rx_chain[i]);
3765 cd->dc_rx_chain[i] = NULL;
3766 }
3767 }
3768 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list));
3769
3770 /*
3771 * Free the TX list buffers.
3772 */
3773 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3774 if (cd->dc_tx_chain[i] != NULL) {
3775 ctl = le32toh(ld->dc_tx_list[i].dc_ctl);
3776 if ((ctl & DC_TXCTL_SETUP) ||
3777 !(ctl & DC_TXCTL_LASTFRAG)) {
3778 cd->dc_tx_chain[i] = NULL;
3779 continue;
3780 }
3781 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]);
3782 m_freem(cd->dc_tx_chain[i]);
3783 cd->dc_tx_chain[i] = NULL;
3784 }
3785 }
3786 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list));
3787 }
3788
3789 /*
3790 * Device suspend routine. Stop the interface and save some PCI
3791 * settings in case the BIOS doesn't restore them properly on
3792 * resume.
3793 */
3794 static int
3795 dc_suspend(device_t dev)
3796 {
3797 struct dc_softc *sc;
3798
3799 sc = device_get_softc(dev);
3800 DC_LOCK(sc);
3801 dc_stop(sc);
3802 sc->suspended = 1;
3803 DC_UNLOCK(sc);
3804
3805 return (0);
3806 }
3807
3808 /*
3809 * Device resume routine. Restore some PCI settings in case the BIOS
3810 * doesn't, re-enable busmastering, and restart the interface if
3811 * appropriate.
3812 */
3813 static int
3814 dc_resume(device_t dev)
3815 {
3816 struct dc_softc *sc;
3817 struct ifnet *ifp;
3818
3819 sc = device_get_softc(dev);
3820 ifp = sc->dc_ifp;
3821
3822 /* reinitialize interface if necessary */
3823 DC_LOCK(sc);
3824 if (ifp->if_flags & IFF_UP)
3825 dc_init_locked(sc);
3826
3827 sc->suspended = 0;
3828 DC_UNLOCK(sc);
3829
3830 return (0);
3831 }
3832
3833 /*
3834 * Stop all chip I/O so that the kernel's probe routines don't
3835 * get confused by errant DMAs when rebooting.
3836 */
3837 static void
3838 dc_shutdown(device_t dev)
3839 {
3840 struct dc_softc *sc;
3841
3842 sc = device_get_softc(dev);
3843
3844 DC_LOCK(sc);
3845 dc_stop(sc);
3846 DC_UNLOCK(sc);
3847 }
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