Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/pci/if_dc.c
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1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/6.3/sys/pci/if_dc.c 173886 2007-11-24 19:45:58Z cvs2svn $"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #ifdef HAVE_KERNEL_OPTION_HEADERS 95 #include "opt_device_polling.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/endian.h> 100 #include <sys/systm.h> 101 #include <sys/sockio.h> 102 #include <sys/mbuf.h> 103 #include <sys/malloc.h> 104 #include <sys/kernel.h> 105 #include <sys/module.h> 106 #include <sys/socket.h> 107 #include <sys/sysctl.h> 108 109 #include <net/if.h> 110 #include <net/if_arp.h> 111 #include <net/ethernet.h> 112 #include <net/if_dl.h> 113 #include <net/if_media.h> 114 #include <net/if_types.h> 115 #include <net/if_vlan_var.h> 116 117 #include <net/bpf.h> 118 119 #include <machine/bus.h> 120 #include <machine/resource.h> 121 #include <sys/bus.h> 122 #include <sys/rman.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 130 #define DC_USEIOSPACE 131 #ifdef __alpha__ 132 #define SRM_MEDIA 133 #endif 134 135 #include <pci/if_dcreg.h> 136 137 #ifdef __sparc64__ 138 #include <dev/ofw/openfirm.h> 139 #include <machine/ofw_machdep.h> 140 #endif 141 142 MODULE_DEPEND(dc, pci, 1, 1, 1); 143 MODULE_DEPEND(dc, ether, 1, 1, 1); 144 MODULE_DEPEND(dc, miibus, 1, 1, 1); 145 146 /* 147 * "device miibus" is required in kernel config. See GENERIC if you get 148 * errors here. 149 */ 150 #include "miibus_if.h" 151 152 /* 153 * Various supported device vendors/types and their names. 154 */ 155 static struct dc_type dc_devs[] = { 156 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 157 "Intel 21143 10/100BaseTX" }, 158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 159 "Davicom DM9009 10/100BaseTX" }, 160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 161 "Davicom DM9100 10/100BaseTX" }, 162 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 163 "Davicom DM9102A 10/100BaseTX" }, 164 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 165 "Davicom DM9102 10/100BaseTX" }, 166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 167 "ADMtek AL981 10/100BaseTX" }, 168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 169 "ADMtek AN985 10/100BaseTX" }, 170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 171 "ADMtek ADM9511 10/100BaseTX" }, 172 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 173 "ADMtek ADM9513 10/100BaseTX" }, 174 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511), 0, 175 "Netgear FA511 10/100BaseTX" }, 176 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 177 "ASIX AX88141 10/100BaseTX" }, 178 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 179 "ASIX AX88140A 10/100BaseTX" }, 180 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 181 "Macronix 98713A 10/100BaseTX" }, 182 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 183 "Macronix 98713 10/100BaseTX" }, 184 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 185 "Compex RL100-TX 10/100BaseTX" }, 186 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 187 "Compex RL100-TX 10/100BaseTX" }, 188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 189 "Macronix 98725 10/100BaseTX" }, 190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 191 "Macronix 98715AEC-C 10/100BaseTX" }, 192 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 193 "Macronix 98715/98715A 10/100BaseTX" }, 194 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 195 "Macronix 98727/98732 10/100BaseTX" }, 196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 197 "LC82C115 PNIC II 10/100BaseTX" }, 198 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 199 "82c169 PNIC 10/100BaseTX" }, 200 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 201 "82c168 PNIC 10/100BaseTX" }, 202 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 203 "Accton EN1217 10/100BaseTX" }, 204 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 205 "Accton EN2242 MiniPCI 10/100BaseTX" }, 206 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 207 "Xircom X3201 10/100BaseTX" }, 208 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 209 "Neteasy DRP-32TXD Cardbus 10/100" }, 210 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 211 "Abocom FE2500 10/100BaseTX" }, 212 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 213 "Abocom FE2500MX 10/100BaseTX" }, 214 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 215 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 216 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 217 "Hawking CB102 CardBus 10/100" }, 218 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 219 "PlaneX FNW-3602-T CardBus 10/100" }, 220 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 221 "3Com OfficeConnect 10/100B" }, 222 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 223 "Microsoft MN-120 CardBus 10/100" }, 224 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 225 "Microsoft MN-130 10/100" }, 226 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 227 "Linksys PCMPC200 CardBus 10/100" }, 228 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 229 "Linksys PCMPC200 CardBus 10/100" }, 230 { 0, 0, NULL } 231 }; 232 233 static int dc_probe(device_t); 234 static int dc_attach(device_t); 235 static int dc_detach(device_t); 236 static int dc_suspend(device_t); 237 static int dc_resume(device_t); 238 static struct dc_type *dc_devtype(device_t); 239 static int dc_newbuf(struct dc_softc *, int, int); 240 static int dc_encap(struct dc_softc *, struct mbuf **); 241 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 242 static int dc_rx_resync(struct dc_softc *); 243 static void dc_rxeof(struct dc_softc *); 244 static void dc_txeof(struct dc_softc *); 245 static void dc_tick(void *); 246 static void dc_tx_underrun(struct dc_softc *); 247 static void dc_intr(void *); 248 static void dc_start(struct ifnet *); 249 static void dc_start_locked(struct ifnet *); 250 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 251 static void dc_init(void *); 252 static void dc_init_locked(struct dc_softc *); 253 static void dc_stop(struct dc_softc *); 254 static void dc_watchdog(void *); 255 static void dc_shutdown(device_t); 256 static int dc_ifmedia_upd(struct ifnet *); 257 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 258 259 static void dc_delay(struct dc_softc *); 260 static void dc_eeprom_idle(struct dc_softc *); 261 static void dc_eeprom_putbyte(struct dc_softc *, int); 262 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 263 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 264 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 265 static void dc_eeprom_width(struct dc_softc *); 266 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 267 268 static void dc_mii_writebit(struct dc_softc *, int); 269 static int dc_mii_readbit(struct dc_softc *); 270 static void dc_mii_sync(struct dc_softc *); 271 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 272 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 273 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 274 static int dc_miibus_readreg(device_t, int, int); 275 static int dc_miibus_writereg(device_t, int, int, int); 276 static void dc_miibus_statchg(device_t); 277 static void dc_miibus_mediainit(device_t); 278 279 static void dc_setcfg(struct dc_softc *, int); 280 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 281 static uint32_t dc_mchash_be(const uint8_t *); 282 static void dc_setfilt_21143(struct dc_softc *); 283 static void dc_setfilt_asix(struct dc_softc *); 284 static void dc_setfilt_admtek(struct dc_softc *); 285 static void dc_setfilt_xircom(struct dc_softc *); 286 287 static void dc_setfilt(struct dc_softc *); 288 289 static void dc_reset(struct dc_softc *); 290 static int dc_list_rx_init(struct dc_softc *); 291 static int dc_list_tx_init(struct dc_softc *); 292 293 static void dc_read_srom(struct dc_softc *, int); 294 static void dc_parse_21143_srom(struct dc_softc *); 295 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 296 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 297 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 298 static void dc_apply_fixup(struct dc_softc *, int); 299 300 static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 301 302 #ifdef DC_USEIOSPACE 303 #define DC_RES SYS_RES_IOPORT 304 #define DC_RID DC_PCI_CFBIO 305 #else 306 #define DC_RES SYS_RES_MEMORY 307 #define DC_RID DC_PCI_CFBMA 308 #endif 309 310 static device_method_t dc_methods[] = { 311 /* Device interface */ 312 DEVMETHOD(device_probe, dc_probe), 313 DEVMETHOD(device_attach, dc_attach), 314 DEVMETHOD(device_detach, dc_detach), 315 DEVMETHOD(device_suspend, dc_suspend), 316 DEVMETHOD(device_resume, dc_resume), 317 DEVMETHOD(device_shutdown, dc_shutdown), 318 319 /* bus interface */ 320 DEVMETHOD(bus_print_child, bus_generic_print_child), 321 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 322 323 /* MII interface */ 324 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 325 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 326 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 327 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 328 329 { 0, 0 } 330 }; 331 332 static driver_t dc_driver = { 333 "dc", 334 dc_methods, 335 sizeof(struct dc_softc) 336 }; 337 338 static devclass_t dc_devclass; 339 #ifdef __NO_STRICT_ALIGNMENT 340 static int dc_quick = 1; 341 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 342 "do not m_devget() in dc driver"); 343 #endif 344 345 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 346 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 347 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 348 349 #define DC_SETBIT(sc, reg, x) \ 350 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 351 352 #define DC_CLRBIT(sc, reg, x) \ 353 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 354 355 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 356 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 357 358 static void 359 dc_delay(struct dc_softc *sc) 360 { 361 int idx; 362 363 for (idx = (300 / 33) + 1; idx > 0; idx--) 364 CSR_READ_4(sc, DC_BUSCTL); 365 } 366 367 static void 368 dc_eeprom_width(struct dc_softc *sc) 369 { 370 int i; 371 372 /* Force EEPROM to idle state. */ 373 dc_eeprom_idle(sc); 374 375 /* Enter EEPROM access mode. */ 376 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 377 dc_delay(sc); 378 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 379 dc_delay(sc); 380 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 381 dc_delay(sc); 382 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 383 dc_delay(sc); 384 385 for (i = 3; i--;) { 386 if (6 & (1 << i)) 387 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 388 else 389 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 390 dc_delay(sc); 391 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 392 dc_delay(sc); 393 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 394 dc_delay(sc); 395 } 396 397 for (i = 1; i <= 12; i++) { 398 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 399 dc_delay(sc); 400 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 401 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 402 dc_delay(sc); 403 break; 404 } 405 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 406 dc_delay(sc); 407 } 408 409 /* Turn off EEPROM access mode. */ 410 dc_eeprom_idle(sc); 411 412 if (i < 4 || i > 12) 413 sc->dc_romwidth = 6; 414 else 415 sc->dc_romwidth = i; 416 417 /* Enter EEPROM access mode. */ 418 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 419 dc_delay(sc); 420 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 421 dc_delay(sc); 422 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 423 dc_delay(sc); 424 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 425 dc_delay(sc); 426 427 /* Turn off EEPROM access mode. */ 428 dc_eeprom_idle(sc); 429 } 430 431 static void 432 dc_eeprom_idle(struct dc_softc *sc) 433 { 434 int i; 435 436 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 437 dc_delay(sc); 438 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 439 dc_delay(sc); 440 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 441 dc_delay(sc); 442 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 443 dc_delay(sc); 444 445 for (i = 0; i < 25; i++) { 446 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 447 dc_delay(sc); 448 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 449 dc_delay(sc); 450 } 451 452 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 453 dc_delay(sc); 454 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 455 dc_delay(sc); 456 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 457 } 458 459 /* 460 * Send a read command and address to the EEPROM, check for ACK. 461 */ 462 static void 463 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 464 { 465 int d, i; 466 467 d = DC_EECMD_READ >> 6; 468 for (i = 3; i--; ) { 469 if (d & (1 << i)) 470 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 471 else 472 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 473 dc_delay(sc); 474 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 475 dc_delay(sc); 476 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 477 dc_delay(sc); 478 } 479 480 /* 481 * Feed in each bit and strobe the clock. 482 */ 483 for (i = sc->dc_romwidth; i--;) { 484 if (addr & (1 << i)) { 485 SIO_SET(DC_SIO_EE_DATAIN); 486 } else { 487 SIO_CLR(DC_SIO_EE_DATAIN); 488 } 489 dc_delay(sc); 490 SIO_SET(DC_SIO_EE_CLK); 491 dc_delay(sc); 492 SIO_CLR(DC_SIO_EE_CLK); 493 dc_delay(sc); 494 } 495 } 496 497 /* 498 * Read a word of data stored in the EEPROM at address 'addr.' 499 * The PNIC 82c168/82c169 has its own non-standard way to read 500 * the EEPROM. 501 */ 502 static void 503 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 504 { 505 int i; 506 u_int32_t r; 507 508 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 509 510 for (i = 0; i < DC_TIMEOUT; i++) { 511 DELAY(1); 512 r = CSR_READ_4(sc, DC_SIO); 513 if (!(r & DC_PN_SIOCTL_BUSY)) { 514 *dest = (u_int16_t)(r & 0xFFFF); 515 return; 516 } 517 } 518 } 519 520 /* 521 * Read a word of data stored in the EEPROM at address 'addr.' 522 * The Xircom X3201 has its own non-standard way to read 523 * the EEPROM, too. 524 */ 525 static void 526 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 527 { 528 529 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 530 531 addr *= 2; 532 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 533 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 534 addr += 1; 535 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 536 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 537 538 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 539 } 540 541 /* 542 * Read a word of data stored in the EEPROM at address 'addr.' 543 */ 544 static void 545 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 546 { 547 int i; 548 u_int16_t word = 0; 549 550 /* Force EEPROM to idle state. */ 551 dc_eeprom_idle(sc); 552 553 /* Enter EEPROM access mode. */ 554 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 555 dc_delay(sc); 556 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 557 dc_delay(sc); 558 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 559 dc_delay(sc); 560 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 561 dc_delay(sc); 562 563 /* 564 * Send address of word we want to read. 565 */ 566 dc_eeprom_putbyte(sc, addr); 567 568 /* 569 * Start reading bits from EEPROM. 570 */ 571 for (i = 0x8000; i; i >>= 1) { 572 SIO_SET(DC_SIO_EE_CLK); 573 dc_delay(sc); 574 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 575 word |= i; 576 dc_delay(sc); 577 SIO_CLR(DC_SIO_EE_CLK); 578 dc_delay(sc); 579 } 580 581 /* Turn off EEPROM access mode. */ 582 dc_eeprom_idle(sc); 583 584 *dest = word; 585 } 586 587 /* 588 * Read a sequence of words from the EEPROM. 589 */ 590 static void 591 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 592 { 593 int i; 594 u_int16_t word = 0, *ptr; 595 596 for (i = 0; i < cnt; i++) { 597 if (DC_IS_PNIC(sc)) 598 dc_eeprom_getword_pnic(sc, off + i, &word); 599 else if (DC_IS_XIRCOM(sc)) 600 dc_eeprom_getword_xircom(sc, off + i, &word); 601 else 602 dc_eeprom_getword(sc, off + i, &word); 603 ptr = (u_int16_t *)(dest + (i * 2)); 604 if (be) 605 *ptr = be16toh(word); 606 else 607 *ptr = le16toh(word); 608 } 609 } 610 611 /* 612 * The following two routines are taken from the Macronix 98713 613 * Application Notes pp.19-21. 614 */ 615 /* 616 * Write a bit to the MII bus. 617 */ 618 static void 619 dc_mii_writebit(struct dc_softc *sc, int bit) 620 { 621 622 if (bit) 623 CSR_WRITE_4(sc, DC_SIO, 624 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 625 else 626 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 627 628 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 629 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 630 } 631 632 /* 633 * Read a bit from the MII bus. 634 */ 635 static int 636 dc_mii_readbit(struct dc_softc *sc) 637 { 638 639 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 640 CSR_READ_4(sc, DC_SIO); 641 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 642 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 643 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 644 return (1); 645 646 return (0); 647 } 648 649 /* 650 * Sync the PHYs by setting data bit and strobing the clock 32 times. 651 */ 652 static void 653 dc_mii_sync(struct dc_softc *sc) 654 { 655 int i; 656 657 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 658 659 for (i = 0; i < 32; i++) 660 dc_mii_writebit(sc, 1); 661 } 662 663 /* 664 * Clock a series of bits through the MII. 665 */ 666 static void 667 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 668 { 669 int i; 670 671 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 672 dc_mii_writebit(sc, bits & i); 673 } 674 675 /* 676 * Read an PHY register through the MII. 677 */ 678 static int 679 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 680 { 681 int i, ack; 682 683 /* 684 * Set up frame for RX. 685 */ 686 frame->mii_stdelim = DC_MII_STARTDELIM; 687 frame->mii_opcode = DC_MII_READOP; 688 frame->mii_turnaround = 0; 689 frame->mii_data = 0; 690 691 /* 692 * Sync the PHYs. 693 */ 694 dc_mii_sync(sc); 695 696 /* 697 * Send command/address info. 698 */ 699 dc_mii_send(sc, frame->mii_stdelim, 2); 700 dc_mii_send(sc, frame->mii_opcode, 2); 701 dc_mii_send(sc, frame->mii_phyaddr, 5); 702 dc_mii_send(sc, frame->mii_regaddr, 5); 703 704 #ifdef notdef 705 /* Idle bit */ 706 dc_mii_writebit(sc, 1); 707 dc_mii_writebit(sc, 0); 708 #endif 709 710 /* Check for ack. */ 711 ack = dc_mii_readbit(sc); 712 713 /* 714 * Now try reading data bits. If the ack failed, we still 715 * need to clock through 16 cycles to keep the PHY(s) in sync. 716 */ 717 if (ack) { 718 for (i = 0; i < 16; i++) 719 dc_mii_readbit(sc); 720 goto fail; 721 } 722 723 for (i = 0x8000; i; i >>= 1) { 724 if (!ack) { 725 if (dc_mii_readbit(sc)) 726 frame->mii_data |= i; 727 } 728 } 729 730 fail: 731 732 dc_mii_writebit(sc, 0); 733 dc_mii_writebit(sc, 0); 734 735 if (ack) 736 return (1); 737 return (0); 738 } 739 740 /* 741 * Write to a PHY register through the MII. 742 */ 743 static int 744 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 745 { 746 747 /* 748 * Set up frame for TX. 749 */ 750 751 frame->mii_stdelim = DC_MII_STARTDELIM; 752 frame->mii_opcode = DC_MII_WRITEOP; 753 frame->mii_turnaround = DC_MII_TURNAROUND; 754 755 /* 756 * Sync the PHYs. 757 */ 758 dc_mii_sync(sc); 759 760 dc_mii_send(sc, frame->mii_stdelim, 2); 761 dc_mii_send(sc, frame->mii_opcode, 2); 762 dc_mii_send(sc, frame->mii_phyaddr, 5); 763 dc_mii_send(sc, frame->mii_regaddr, 5); 764 dc_mii_send(sc, frame->mii_turnaround, 2); 765 dc_mii_send(sc, frame->mii_data, 16); 766 767 /* Idle bit. */ 768 dc_mii_writebit(sc, 0); 769 dc_mii_writebit(sc, 0); 770 771 return (0); 772 } 773 774 static int 775 dc_miibus_readreg(device_t dev, int phy, int reg) 776 { 777 struct dc_mii_frame frame; 778 struct dc_softc *sc; 779 int i, rval, phy_reg = 0; 780 781 sc = device_get_softc(dev); 782 bzero(&frame, sizeof(frame)); 783 784 /* 785 * Note: both the AL981 and AN985 have internal PHYs, 786 * however the AL981 provides direct access to the PHY 787 * registers while the AN985 uses a serial MII interface. 788 * The AN985's MII interface is also buggy in that you 789 * can read from any MII address (0 to 31), but only address 1 790 * behaves normally. To deal with both cases, we pretend 791 * that the PHY is at MII address 1. 792 */ 793 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 794 return (0); 795 796 /* 797 * Note: the ukphy probes of the RS7112 report a PHY at 798 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 799 * so we only respond to correct one. 800 */ 801 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 802 return (0); 803 804 if (sc->dc_pmode != DC_PMODE_MII) { 805 if (phy == (MII_NPHY - 1)) { 806 switch (reg) { 807 case MII_BMSR: 808 /* 809 * Fake something to make the probe 810 * code think there's a PHY here. 811 */ 812 return (BMSR_MEDIAMASK); 813 break; 814 case MII_PHYIDR1: 815 if (DC_IS_PNIC(sc)) 816 return (DC_VENDORID_LO); 817 return (DC_VENDORID_DEC); 818 break; 819 case MII_PHYIDR2: 820 if (DC_IS_PNIC(sc)) 821 return (DC_DEVICEID_82C168); 822 return (DC_DEVICEID_21143); 823 break; 824 default: 825 return (0); 826 break; 827 } 828 } else 829 return (0); 830 } 831 832 if (DC_IS_PNIC(sc)) { 833 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 834 (phy << 23) | (reg << 18)); 835 for (i = 0; i < DC_TIMEOUT; i++) { 836 DELAY(1); 837 rval = CSR_READ_4(sc, DC_PN_MII); 838 if (!(rval & DC_PN_MII_BUSY)) { 839 rval &= 0xFFFF; 840 return (rval == 0xFFFF ? 0 : rval); 841 } 842 } 843 return (0); 844 } 845 846 if (DC_IS_COMET(sc)) { 847 switch (reg) { 848 case MII_BMCR: 849 phy_reg = DC_AL_BMCR; 850 break; 851 case MII_BMSR: 852 phy_reg = DC_AL_BMSR; 853 break; 854 case MII_PHYIDR1: 855 phy_reg = DC_AL_VENID; 856 break; 857 case MII_PHYIDR2: 858 phy_reg = DC_AL_DEVID; 859 break; 860 case MII_ANAR: 861 phy_reg = DC_AL_ANAR; 862 break; 863 case MII_ANLPAR: 864 phy_reg = DC_AL_LPAR; 865 break; 866 case MII_ANER: 867 phy_reg = DC_AL_ANER; 868 break; 869 default: 870 device_printf(dev, "phy_read: bad phy register %x\n", 871 reg); 872 return (0); 873 break; 874 } 875 876 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 877 878 if (rval == 0xFFFF) 879 return (0); 880 return (rval); 881 } 882 883 frame.mii_phyaddr = phy; 884 frame.mii_regaddr = reg; 885 if (sc->dc_type == DC_TYPE_98713) { 886 phy_reg = CSR_READ_4(sc, DC_NETCFG); 887 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 888 } 889 dc_mii_readreg(sc, &frame); 890 if (sc->dc_type == DC_TYPE_98713) 891 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 892 893 return (frame.mii_data); 894 } 895 896 static int 897 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 898 { 899 struct dc_softc *sc; 900 struct dc_mii_frame frame; 901 int i, phy_reg = 0; 902 903 sc = device_get_softc(dev); 904 bzero(&frame, sizeof(frame)); 905 906 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 907 return (0); 908 909 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 910 return (0); 911 912 if (DC_IS_PNIC(sc)) { 913 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 914 (phy << 23) | (reg << 10) | data); 915 for (i = 0; i < DC_TIMEOUT; i++) { 916 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 917 break; 918 } 919 return (0); 920 } 921 922 if (DC_IS_COMET(sc)) { 923 switch (reg) { 924 case MII_BMCR: 925 phy_reg = DC_AL_BMCR; 926 break; 927 case MII_BMSR: 928 phy_reg = DC_AL_BMSR; 929 break; 930 case MII_PHYIDR1: 931 phy_reg = DC_AL_VENID; 932 break; 933 case MII_PHYIDR2: 934 phy_reg = DC_AL_DEVID; 935 break; 936 case MII_ANAR: 937 phy_reg = DC_AL_ANAR; 938 break; 939 case MII_ANLPAR: 940 phy_reg = DC_AL_LPAR; 941 break; 942 case MII_ANER: 943 phy_reg = DC_AL_ANER; 944 break; 945 default: 946 device_printf(dev, "phy_write: bad phy register %x\n", 947 reg); 948 return (0); 949 break; 950 } 951 952 CSR_WRITE_4(sc, phy_reg, data); 953 return (0); 954 } 955 956 frame.mii_phyaddr = phy; 957 frame.mii_regaddr = reg; 958 frame.mii_data = data; 959 960 if (sc->dc_type == DC_TYPE_98713) { 961 phy_reg = CSR_READ_4(sc, DC_NETCFG); 962 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 963 } 964 dc_mii_writereg(sc, &frame); 965 if (sc->dc_type == DC_TYPE_98713) 966 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 967 968 return (0); 969 } 970 971 static void 972 dc_miibus_statchg(device_t dev) 973 { 974 struct dc_softc *sc; 975 struct mii_data *mii; 976 struct ifmedia *ifm; 977 978 sc = device_get_softc(dev); 979 if (DC_IS_ADMTEK(sc)) 980 return; 981 982 mii = device_get_softc(sc->dc_miibus); 983 ifm = &mii->mii_media; 984 if (DC_IS_DAVICOM(sc) && 985 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 986 dc_setcfg(sc, ifm->ifm_media); 987 sc->dc_if_media = ifm->ifm_media; 988 } else { 989 dc_setcfg(sc, mii->mii_media_active); 990 sc->dc_if_media = mii->mii_media_active; 991 } 992 } 993 994 /* 995 * Special support for DM9102A cards with HomePNA PHYs. Note: 996 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 997 * to be impossible to talk to the management interface of the DM9801 998 * PHY (its MDIO pin is not connected to anything). Consequently, 999 * the driver has to just 'know' about the additional mode and deal 1000 * with it itself. *sigh* 1001 */ 1002 static void 1003 dc_miibus_mediainit(device_t dev) 1004 { 1005 struct dc_softc *sc; 1006 struct mii_data *mii; 1007 struct ifmedia *ifm; 1008 int rev; 1009 1010 rev = pci_get_revid(dev); 1011 1012 sc = device_get_softc(dev); 1013 mii = device_get_softc(sc->dc_miibus); 1014 ifm = &mii->mii_media; 1015 1016 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1017 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1018 } 1019 1020 #define DC_BITS_512 9 1021 #define DC_BITS_128 7 1022 #define DC_BITS_64 6 1023 1024 static uint32_t 1025 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1026 { 1027 uint32_t crc; 1028 1029 /* Compute CRC for the address value. */ 1030 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1031 1032 /* 1033 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1034 * chips is only 128 bits wide. 1035 */ 1036 if (sc->dc_flags & DC_128BIT_HASH) 1037 return (crc & ((1 << DC_BITS_128) - 1)); 1038 1039 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1040 if (sc->dc_flags & DC_64BIT_HASH) 1041 return (crc & ((1 << DC_BITS_64) - 1)); 1042 1043 /* Xircom's hash filtering table is different (read: weird) */ 1044 /* Xircom uses the LEAST significant bits */ 1045 if (DC_IS_XIRCOM(sc)) { 1046 if ((crc & 0x180) == 0x180) 1047 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1048 else 1049 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1050 (12 << 4)); 1051 } 1052 1053 return (crc & ((1 << DC_BITS_512) - 1)); 1054 } 1055 1056 /* 1057 * Calculate CRC of a multicast group address, return the lower 6 bits. 1058 */ 1059 static uint32_t 1060 dc_mchash_be(const uint8_t *addr) 1061 { 1062 uint32_t crc; 1063 1064 /* Compute CRC for the address value. */ 1065 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1066 1067 /* Return the filter bit position. */ 1068 return ((crc >> 26) & 0x0000003F); 1069 } 1070 1071 /* 1072 * 21143-style RX filter setup routine. Filter programming is done by 1073 * downloading a special setup frame into the TX engine. 21143, Macronix, 1074 * PNIC, PNIC II and Davicom chips are programmed this way. 1075 * 1076 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1077 * address (our node address) and a 512-bit hash filter for multicast 1078 * frames. We also sneak the broadcast address into the hash filter since 1079 * we need that too. 1080 */ 1081 static void 1082 dc_setfilt_21143(struct dc_softc *sc) 1083 { 1084 struct dc_desc *sframe; 1085 u_int32_t h, *sp; 1086 struct ifmultiaddr *ifma; 1087 struct ifnet *ifp; 1088 int i; 1089 1090 ifp = sc->dc_ifp; 1091 1092 i = sc->dc_cdata.dc_tx_prod; 1093 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1094 sc->dc_cdata.dc_tx_cnt++; 1095 sframe = &sc->dc_ldata->dc_tx_list[i]; 1096 sp = sc->dc_cdata.dc_sbuf; 1097 bzero(sp, DC_SFRAME_LEN); 1098 1099 sframe->dc_data = htole32(sc->dc_saddr); 1100 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1101 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1102 1103 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1104 1105 /* If we want promiscuous mode, set the allframes bit. */ 1106 if (ifp->if_flags & IFF_PROMISC) 1107 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1108 else 1109 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1110 1111 if (ifp->if_flags & IFF_ALLMULTI) 1112 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1113 else 1114 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1115 1116 IF_ADDR_LOCK(ifp); 1117 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1118 if (ifma->ifma_addr->sa_family != AF_LINK) 1119 continue; 1120 h = dc_mchash_le(sc, 1121 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1122 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1123 } 1124 IF_ADDR_UNLOCK(ifp); 1125 1126 if (ifp->if_flags & IFF_BROADCAST) { 1127 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1128 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1129 } 1130 1131 /* Set our MAC address */ 1132 sp[39] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]); 1133 sp[40] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]); 1134 sp[41] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]); 1135 1136 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1137 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1138 1139 /* 1140 * The PNIC takes an exceedingly long time to process its 1141 * setup frame; wait 10ms after posting the setup frame 1142 * before proceeding, just so it has time to swallow its 1143 * medicine. 1144 */ 1145 DELAY(10000); 1146 1147 sc->dc_wdog_timer = 5; 1148 } 1149 1150 static void 1151 dc_setfilt_admtek(struct dc_softc *sc) 1152 { 1153 struct ifnet *ifp; 1154 struct ifmultiaddr *ifma; 1155 int h = 0; 1156 u_int32_t hashes[2] = { 0, 0 }; 1157 1158 ifp = sc->dc_ifp; 1159 1160 /* Init our MAC address. */ 1161 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[0])); 1162 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[4])); 1163 1164 /* If we want promiscuous mode, set the allframes bit. */ 1165 if (ifp->if_flags & IFF_PROMISC) 1166 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1167 else 1168 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1169 1170 if (ifp->if_flags & IFF_ALLMULTI) 1171 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1172 else 1173 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1174 1175 /* First, zot all the existing hash bits. */ 1176 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1177 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1178 1179 /* 1180 * If we're already in promisc or allmulti mode, we 1181 * don't have to bother programming the multicast filter. 1182 */ 1183 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1184 return; 1185 1186 /* Now program new ones. */ 1187 IF_ADDR_LOCK(ifp); 1188 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1189 if (ifma->ifma_addr->sa_family != AF_LINK) 1190 continue; 1191 if (DC_IS_CENTAUR(sc)) 1192 h = dc_mchash_le(sc, 1193 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1194 else 1195 h = dc_mchash_be( 1196 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1197 if (h < 32) 1198 hashes[0] |= (1 << h); 1199 else 1200 hashes[1] |= (1 << (h - 32)); 1201 } 1202 IF_ADDR_UNLOCK(ifp); 1203 1204 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1205 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1206 } 1207 1208 static void 1209 dc_setfilt_asix(struct dc_softc *sc) 1210 { 1211 struct ifnet *ifp; 1212 struct ifmultiaddr *ifma; 1213 int h = 0; 1214 u_int32_t hashes[2] = { 0, 0 }; 1215 1216 ifp = sc->dc_ifp; 1217 1218 /* Init our MAC address */ 1219 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1220 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1221 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[0])); 1222 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1223 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1224 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[4])); 1225 1226 /* If we want promiscuous mode, set the allframes bit. */ 1227 if (ifp->if_flags & IFF_PROMISC) 1228 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1229 else 1230 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1231 1232 if (ifp->if_flags & IFF_ALLMULTI) 1233 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1234 else 1235 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1236 1237 /* 1238 * The ASIX chip has a special bit to enable reception 1239 * of broadcast frames. 1240 */ 1241 if (ifp->if_flags & IFF_BROADCAST) 1242 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1243 else 1244 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1245 1246 /* first, zot all the existing hash bits */ 1247 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1248 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1249 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1250 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1251 1252 /* 1253 * If we're already in promisc or allmulti mode, we 1254 * don't have to bother programming the multicast filter. 1255 */ 1256 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1257 return; 1258 1259 /* now program new ones */ 1260 IF_ADDR_LOCK(ifp); 1261 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1262 if (ifma->ifma_addr->sa_family != AF_LINK) 1263 continue; 1264 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1265 if (h < 32) 1266 hashes[0] |= (1 << h); 1267 else 1268 hashes[1] |= (1 << (h - 32)); 1269 } 1270 IF_ADDR_UNLOCK(ifp); 1271 1272 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1273 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1274 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1275 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1276 } 1277 1278 static void 1279 dc_setfilt_xircom(struct dc_softc *sc) 1280 { 1281 struct ifnet *ifp; 1282 struct ifmultiaddr *ifma; 1283 struct dc_desc *sframe; 1284 u_int32_t h, *sp; 1285 int i; 1286 1287 ifp = sc->dc_ifp; 1288 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1289 1290 i = sc->dc_cdata.dc_tx_prod; 1291 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1292 sc->dc_cdata.dc_tx_cnt++; 1293 sframe = &sc->dc_ldata->dc_tx_list[i]; 1294 sp = sc->dc_cdata.dc_sbuf; 1295 bzero(sp, DC_SFRAME_LEN); 1296 1297 sframe->dc_data = htole32(sc->dc_saddr); 1298 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1299 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1300 1301 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1302 1303 /* If we want promiscuous mode, set the allframes bit. */ 1304 if (ifp->if_flags & IFF_PROMISC) 1305 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1306 else 1307 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1308 1309 if (ifp->if_flags & IFF_ALLMULTI) 1310 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1311 else 1312 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1313 1314 IF_ADDR_LOCK(ifp); 1315 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1316 if (ifma->ifma_addr->sa_family != AF_LINK) 1317 continue; 1318 h = dc_mchash_le(sc, 1319 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1320 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1321 } 1322 IF_ADDR_UNLOCK(ifp); 1323 1324 if (ifp->if_flags & IFF_BROADCAST) { 1325 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1326 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1327 } 1328 1329 /* Set our MAC address */ 1330 sp[0] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]); 1331 sp[1] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]); 1332 sp[2] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]); 1333 1334 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1335 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1336 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1337 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1338 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1339 1340 /* 1341 * Wait some time... 1342 */ 1343 DELAY(1000); 1344 1345 sc->dc_wdog_timer = 5; 1346 } 1347 1348 static void 1349 dc_setfilt(struct dc_softc *sc) 1350 { 1351 1352 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1353 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1354 dc_setfilt_21143(sc); 1355 1356 if (DC_IS_ASIX(sc)) 1357 dc_setfilt_asix(sc); 1358 1359 if (DC_IS_ADMTEK(sc)) 1360 dc_setfilt_admtek(sc); 1361 1362 if (DC_IS_XIRCOM(sc)) 1363 dc_setfilt_xircom(sc); 1364 } 1365 1366 /* 1367 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1368 * the netconfig register, we first have to put the transmit and/or 1369 * receive logic in the idle state. 1370 */ 1371 static void 1372 dc_setcfg(struct dc_softc *sc, int media) 1373 { 1374 int i, restart = 0, watchdogreg; 1375 u_int32_t isr; 1376 1377 if (IFM_SUBTYPE(media) == IFM_NONE) 1378 return; 1379 1380 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1381 restart = 1; 1382 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1383 1384 for (i = 0; i < DC_TIMEOUT; i++) { 1385 isr = CSR_READ_4(sc, DC_ISR); 1386 if (isr & DC_ISR_TX_IDLE && 1387 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1388 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1389 break; 1390 DELAY(10); 1391 } 1392 1393 if (i == DC_TIMEOUT) { 1394 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1395 device_printf(sc->dc_dev, 1396 "%s: failed to force tx to idle state\n", 1397 __func__); 1398 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1399 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1400 !(DC_IS_CENTAUR(sc) || DC_IS_CONEXANT(sc) || 1401 (DC_IS_DAVICOM(sc) && pci_get_revid(sc->dc_dev) >= 1402 DC_REVISION_DM9102A))) 1403 device_printf(sc->dc_dev, 1404 "%s: failed to force rx to idle state\n", 1405 __func__); 1406 } 1407 } 1408 1409 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1410 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1411 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1412 if (sc->dc_pmode == DC_PMODE_MII) { 1413 if (DC_IS_INTEL(sc)) { 1414 /* There's a write enable bit here that reads as 1. */ 1415 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1416 watchdogreg &= ~DC_WDOG_CTLWREN; 1417 watchdogreg |= DC_WDOG_JABBERDIS; 1418 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1419 } else { 1420 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1421 } 1422 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1423 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1424 if (sc->dc_type == DC_TYPE_98713) 1425 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1426 DC_NETCFG_SCRAMBLER)); 1427 if (!DC_IS_DAVICOM(sc)) 1428 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1429 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1430 if (DC_IS_INTEL(sc)) 1431 dc_apply_fixup(sc, IFM_AUTO); 1432 } else { 1433 if (DC_IS_PNIC(sc)) { 1434 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1435 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1436 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1437 } 1438 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1439 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1440 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1441 if (DC_IS_INTEL(sc)) 1442 dc_apply_fixup(sc, 1443 (media & IFM_GMASK) == IFM_FDX ? 1444 IFM_100_TX | IFM_FDX : IFM_100_TX); 1445 } 1446 } 1447 1448 if (IFM_SUBTYPE(media) == IFM_10_T) { 1449 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1450 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1451 if (sc->dc_pmode == DC_PMODE_MII) { 1452 /* There's a write enable bit here that reads as 1. */ 1453 if (DC_IS_INTEL(sc)) { 1454 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1455 watchdogreg &= ~DC_WDOG_CTLWREN; 1456 watchdogreg |= DC_WDOG_JABBERDIS; 1457 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1458 } else { 1459 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1460 } 1461 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1462 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1463 if (sc->dc_type == DC_TYPE_98713) 1464 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1465 if (!DC_IS_DAVICOM(sc)) 1466 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1467 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1468 if (DC_IS_INTEL(sc)) 1469 dc_apply_fixup(sc, IFM_AUTO); 1470 } else { 1471 if (DC_IS_PNIC(sc)) { 1472 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1473 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1474 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1475 } 1476 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1477 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1478 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1479 if (DC_IS_INTEL(sc)) { 1480 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1481 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1482 if ((media & IFM_GMASK) == IFM_FDX) 1483 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1484 else 1485 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1486 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1487 DC_CLRBIT(sc, DC_10BTCTRL, 1488 DC_TCTL_AUTONEGENBL); 1489 dc_apply_fixup(sc, 1490 (media & IFM_GMASK) == IFM_FDX ? 1491 IFM_10_T | IFM_FDX : IFM_10_T); 1492 DELAY(20000); 1493 } 1494 } 1495 } 1496 1497 /* 1498 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1499 * PHY and we want HomePNA mode, set the portsel bit to turn 1500 * on the external MII port. 1501 */ 1502 if (DC_IS_DAVICOM(sc)) { 1503 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1504 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1505 sc->dc_link = 1; 1506 } else { 1507 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1508 } 1509 } 1510 1511 if ((media & IFM_GMASK) == IFM_FDX) { 1512 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1513 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1514 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1515 } else { 1516 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1517 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1518 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1519 } 1520 1521 if (restart) 1522 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1523 } 1524 1525 static void 1526 dc_reset(struct dc_softc *sc) 1527 { 1528 int i; 1529 1530 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1531 1532 for (i = 0; i < DC_TIMEOUT; i++) { 1533 DELAY(10); 1534 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1535 break; 1536 } 1537 1538 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1539 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1540 DELAY(10000); 1541 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1542 i = 0; 1543 } 1544 1545 if (i == DC_TIMEOUT) 1546 device_printf(sc->dc_dev, "reset never completed!\n"); 1547 1548 /* Wait a little while for the chip to get its brains in order. */ 1549 DELAY(1000); 1550 1551 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1552 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1553 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1554 1555 /* 1556 * Bring the SIA out of reset. In some cases, it looks 1557 * like failing to unreset the SIA soon enough gets it 1558 * into a state where it will never come out of reset 1559 * until we reset the whole chip again. 1560 */ 1561 if (DC_IS_INTEL(sc)) { 1562 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1563 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1564 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1565 } 1566 } 1567 1568 static struct dc_type * 1569 dc_devtype(device_t dev) 1570 { 1571 struct dc_type *t; 1572 u_int32_t devid; 1573 u_int8_t rev; 1574 1575 t = dc_devs; 1576 devid = pci_get_devid(dev); 1577 rev = pci_get_revid(dev); 1578 1579 while (t->dc_name != NULL) { 1580 if (devid == t->dc_devid && rev >= t->dc_minrev) 1581 return (t); 1582 t++; 1583 } 1584 1585 return (NULL); 1586 } 1587 1588 /* 1589 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1590 * IDs against our list and return a device name if we find a match. 1591 * We do a little bit of extra work to identify the exact type of 1592 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1593 * but different revision IDs. The same is true for 98715/98715A 1594 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1595 * cases, the exact chip revision affects driver behavior. 1596 */ 1597 static int 1598 dc_probe(device_t dev) 1599 { 1600 struct dc_type *t; 1601 1602 t = dc_devtype(dev); 1603 1604 if (t != NULL) { 1605 device_set_desc(dev, t->dc_name); 1606 return (BUS_PROBE_DEFAULT); 1607 } 1608 1609 return (ENXIO); 1610 } 1611 1612 static void 1613 dc_apply_fixup(struct dc_softc *sc, int media) 1614 { 1615 struct dc_mediainfo *m; 1616 u_int8_t *p; 1617 int i; 1618 u_int32_t reg; 1619 1620 m = sc->dc_mi; 1621 1622 while (m != NULL) { 1623 if (m->dc_media == media) 1624 break; 1625 m = m->dc_next; 1626 } 1627 1628 if (m == NULL) 1629 return; 1630 1631 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1632 reg = (p[0] | (p[1] << 8)) << 16; 1633 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1634 } 1635 1636 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1637 reg = (p[0] | (p[1] << 8)) << 16; 1638 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1639 } 1640 } 1641 1642 static void 1643 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1644 { 1645 struct dc_mediainfo *m; 1646 1647 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1648 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1649 case DC_SIA_CODE_10BT: 1650 m->dc_media = IFM_10_T; 1651 break; 1652 case DC_SIA_CODE_10BT_FDX: 1653 m->dc_media = IFM_10_T | IFM_FDX; 1654 break; 1655 case DC_SIA_CODE_10B2: 1656 m->dc_media = IFM_10_2; 1657 break; 1658 case DC_SIA_CODE_10B5: 1659 m->dc_media = IFM_10_5; 1660 break; 1661 default: 1662 break; 1663 } 1664 1665 /* 1666 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1667 * Things apparently already work for cards that do 1668 * supply Media Specific Data. 1669 */ 1670 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1671 m->dc_gp_len = 2; 1672 m->dc_gp_ptr = 1673 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1674 } else { 1675 m->dc_gp_len = 2; 1676 m->dc_gp_ptr = 1677 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1678 } 1679 1680 m->dc_next = sc->dc_mi; 1681 sc->dc_mi = m; 1682 1683 sc->dc_pmode = DC_PMODE_SIA; 1684 } 1685 1686 static void 1687 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1688 { 1689 struct dc_mediainfo *m; 1690 1691 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1692 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1693 m->dc_media = IFM_100_TX; 1694 1695 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1696 m->dc_media = IFM_100_TX | IFM_FDX; 1697 1698 m->dc_gp_len = 2; 1699 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1700 1701 m->dc_next = sc->dc_mi; 1702 sc->dc_mi = m; 1703 1704 sc->dc_pmode = DC_PMODE_SYM; 1705 } 1706 1707 static void 1708 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1709 { 1710 struct dc_mediainfo *m; 1711 u_int8_t *p; 1712 1713 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1714 /* We abuse IFM_AUTO to represent MII. */ 1715 m->dc_media = IFM_AUTO; 1716 m->dc_gp_len = l->dc_gpr_len; 1717 1718 p = (u_int8_t *)l; 1719 p += sizeof(struct dc_eblock_mii); 1720 m->dc_gp_ptr = p; 1721 p += 2 * l->dc_gpr_len; 1722 m->dc_reset_len = *p; 1723 p++; 1724 m->dc_reset_ptr = p; 1725 1726 m->dc_next = sc->dc_mi; 1727 sc->dc_mi = m; 1728 } 1729 1730 static void 1731 dc_read_srom(struct dc_softc *sc, int bits) 1732 { 1733 int size; 1734 1735 size = 2 << bits; 1736 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1737 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1738 } 1739 1740 static void 1741 dc_parse_21143_srom(struct dc_softc *sc) 1742 { 1743 struct dc_leaf_hdr *lhdr; 1744 struct dc_eblock_hdr *hdr; 1745 int have_mii, i, loff; 1746 char *ptr; 1747 1748 have_mii = 0; 1749 loff = sc->dc_srom[27]; 1750 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1751 1752 ptr = (char *)lhdr; 1753 ptr += sizeof(struct dc_leaf_hdr) - 1; 1754 /* 1755 * Look if we got a MII media block. 1756 */ 1757 for (i = 0; i < lhdr->dc_mcnt; i++) { 1758 hdr = (struct dc_eblock_hdr *)ptr; 1759 if (hdr->dc_type == DC_EBLOCK_MII) 1760 have_mii++; 1761 1762 ptr += (hdr->dc_len & 0x7F); 1763 ptr++; 1764 } 1765 1766 /* 1767 * Do the same thing again. Only use SIA and SYM media 1768 * blocks if no MII media block is available. 1769 */ 1770 ptr = (char *)lhdr; 1771 ptr += sizeof(struct dc_leaf_hdr) - 1; 1772 for (i = 0; i < lhdr->dc_mcnt; i++) { 1773 hdr = (struct dc_eblock_hdr *)ptr; 1774 switch (hdr->dc_type) { 1775 case DC_EBLOCK_MII: 1776 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1777 break; 1778 case DC_EBLOCK_SIA: 1779 if (! have_mii) 1780 dc_decode_leaf_sia(sc, 1781 (struct dc_eblock_sia *)hdr); 1782 break; 1783 case DC_EBLOCK_SYM: 1784 if (! have_mii) 1785 dc_decode_leaf_sym(sc, 1786 (struct dc_eblock_sym *)hdr); 1787 break; 1788 default: 1789 /* Don't care. Yet. */ 1790 break; 1791 } 1792 ptr += (hdr->dc_len & 0x7F); 1793 ptr++; 1794 } 1795 } 1796 1797 static void 1798 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1799 { 1800 u_int32_t *paddr; 1801 1802 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1803 paddr = arg; 1804 *paddr = segs->ds_addr; 1805 } 1806 1807 /* 1808 * Attach the interface. Allocate softc structures, do ifmedia 1809 * setup and ethernet/BPF attach. 1810 */ 1811 static int 1812 dc_attach(device_t dev) 1813 { 1814 int tmp = 0; 1815 u_char eaddr[ETHER_ADDR_LEN]; 1816 u_int32_t command; 1817 struct dc_softc *sc; 1818 struct ifnet *ifp; 1819 u_int32_t revision; 1820 int error = 0, rid, mac_offset; 1821 int i; 1822 u_int8_t *mac; 1823 1824 sc = device_get_softc(dev); 1825 sc->dc_dev = dev; 1826 1827 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1828 MTX_DEF); 1829 1830 /* 1831 * Map control/status registers. 1832 */ 1833 pci_enable_busmaster(dev); 1834 1835 rid = DC_RID; 1836 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1837 1838 if (sc->dc_res == NULL) { 1839 device_printf(dev, "couldn't map ports/memory\n"); 1840 error = ENXIO; 1841 goto fail; 1842 } 1843 1844 sc->dc_btag = rman_get_bustag(sc->dc_res); 1845 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1846 1847 /* Allocate interrupt. */ 1848 rid = 0; 1849 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1850 RF_SHAREABLE | RF_ACTIVE); 1851 1852 if (sc->dc_irq == NULL) { 1853 device_printf(dev, "couldn't map interrupt\n"); 1854 error = ENXIO; 1855 goto fail; 1856 } 1857 1858 /* Need this info to decide on a chip type. */ 1859 sc->dc_info = dc_devtype(dev); 1860 revision = pci_get_revid(dev); 1861 1862 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1863 if (sc->dc_info->dc_devid != 1864 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 1865 sc->dc_info->dc_devid != 1866 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 1867 dc_eeprom_width(sc); 1868 1869 switch (sc->dc_info->dc_devid) { 1870 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 1871 sc->dc_type = DC_TYPE_21143; 1872 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1873 sc->dc_flags |= DC_REDUCED_MII_POLL; 1874 /* Save EEPROM contents so we can parse them later. */ 1875 dc_read_srom(sc, sc->dc_romwidth); 1876 break; 1877 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 1878 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 1879 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 1880 sc->dc_type = DC_TYPE_DM9102; 1881 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1882 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1883 sc->dc_flags |= DC_TX_ALIGN; 1884 sc->dc_pmode = DC_PMODE_MII; 1885 1886 /* Increase the latency timer value. */ 1887 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 1888 break; 1889 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 1890 sc->dc_type = DC_TYPE_AL981; 1891 sc->dc_flags |= DC_TX_USE_TX_INTR; 1892 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1893 sc->dc_pmode = DC_PMODE_MII; 1894 dc_read_srom(sc, sc->dc_romwidth); 1895 break; 1896 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 1897 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 1898 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 1899 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 1900 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511): 1901 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 1902 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 1903 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 1904 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 1905 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 1906 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 1907 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 1908 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 1909 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 1910 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 1911 sc->dc_type = DC_TYPE_AN985; 1912 sc->dc_flags |= DC_64BIT_HASH; 1913 sc->dc_flags |= DC_TX_USE_TX_INTR; 1914 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1915 sc->dc_pmode = DC_PMODE_MII; 1916 /* Don't read SROM for - auto-loaded on reset */ 1917 break; 1918 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 1919 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 1920 if (revision < DC_REVISION_98713A) { 1921 sc->dc_type = DC_TYPE_98713; 1922 } 1923 if (revision >= DC_REVISION_98713A) { 1924 sc->dc_type = DC_TYPE_98713A; 1925 sc->dc_flags |= DC_21143_NWAY; 1926 } 1927 sc->dc_flags |= DC_REDUCED_MII_POLL; 1928 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1929 break; 1930 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 1931 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 1932 /* 1933 * Macronix MX98715AEC-C/D/E parts have only a 1934 * 128-bit hash table. We need to deal with these 1935 * in the same manner as the PNIC II so that we 1936 * get the right number of bits out of the 1937 * CRC routine. 1938 */ 1939 if (revision >= DC_REVISION_98715AEC_C && 1940 revision < DC_REVISION_98725) 1941 sc->dc_flags |= DC_128BIT_HASH; 1942 sc->dc_type = DC_TYPE_987x5; 1943 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1944 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1945 break; 1946 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 1947 sc->dc_type = DC_TYPE_987x5; 1948 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1949 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1950 break; 1951 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 1952 sc->dc_type = DC_TYPE_PNICII; 1953 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1954 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1955 break; 1956 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 1957 sc->dc_type = DC_TYPE_PNIC; 1958 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1959 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1960 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1961 if (revision < DC_REVISION_82C169) 1962 sc->dc_pmode = DC_PMODE_SYM; 1963 break; 1964 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 1965 sc->dc_type = DC_TYPE_ASIX; 1966 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1967 sc->dc_flags |= DC_REDUCED_MII_POLL; 1968 sc->dc_pmode = DC_PMODE_MII; 1969 break; 1970 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 1971 sc->dc_type = DC_TYPE_XIRCOM; 1972 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1973 DC_TX_ALIGN; 1974 /* 1975 * We don't actually need to coalesce, but we're doing 1976 * it to obtain a double word aligned buffer. 1977 * The DC_TX_COALESCE flag is required. 1978 */ 1979 sc->dc_pmode = DC_PMODE_MII; 1980 break; 1981 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 1982 sc->dc_type = DC_TYPE_CONEXANT; 1983 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1984 sc->dc_flags |= DC_REDUCED_MII_POLL; 1985 sc->dc_pmode = DC_PMODE_MII; 1986 dc_read_srom(sc, sc->dc_romwidth); 1987 break; 1988 default: 1989 device_printf(dev, "unknown device: %x\n", 1990 sc->dc_info->dc_devid); 1991 break; 1992 } 1993 1994 /* Save the cache line size. */ 1995 if (DC_IS_DAVICOM(sc)) 1996 sc->dc_cachesize = 0; 1997 else 1998 sc->dc_cachesize = pci_get_cachelnsz(dev); 1999 2000 /* Reset the adapter. */ 2001 dc_reset(sc); 2002 2003 /* Take 21143 out of snooze mode */ 2004 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2005 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2006 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2007 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2008 } 2009 2010 /* 2011 * Try to learn something about the supported media. 2012 * We know that ASIX and ADMtek and Davicom devices 2013 * will *always* be using MII media, so that's a no-brainer. 2014 * The tricky ones are the Macronix/PNIC II and the 2015 * Intel 21143. 2016 */ 2017 if (DC_IS_INTEL(sc)) 2018 dc_parse_21143_srom(sc); 2019 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2020 if (sc->dc_type == DC_TYPE_98713) 2021 sc->dc_pmode = DC_PMODE_MII; 2022 else 2023 sc->dc_pmode = DC_PMODE_SYM; 2024 } else if (!sc->dc_pmode) 2025 sc->dc_pmode = DC_PMODE_MII; 2026 2027 /* 2028 * Get station address from the EEPROM. 2029 */ 2030 switch(sc->dc_type) { 2031 case DC_TYPE_98713: 2032 case DC_TYPE_98713A: 2033 case DC_TYPE_987x5: 2034 case DC_TYPE_PNICII: 2035 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2036 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2037 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2038 break; 2039 case DC_TYPE_PNIC: 2040 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2041 break; 2042 case DC_TYPE_DM9102: 2043 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2044 #ifdef __sparc64__ 2045 /* 2046 * If this is an onboard dc(4) the station address read from 2047 * the EEPROM is all zero and we have to get it from the fcode. 2048 */ 2049 for (i = 0; i < ETHER_ADDR_LEN; i++) 2050 if (eaddr[i] != 0x00) 2051 break; 2052 if (i >= ETHER_ADDR_LEN) 2053 OF_getetheraddr(dev, eaddr); 2054 #endif 2055 break; 2056 case DC_TYPE_21143: 2057 case DC_TYPE_ASIX: 2058 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2059 break; 2060 case DC_TYPE_AL981: 2061 case DC_TYPE_AN985: 2062 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2063 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2064 break; 2065 case DC_TYPE_CONEXANT: 2066 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2067 ETHER_ADDR_LEN); 2068 break; 2069 case DC_TYPE_XIRCOM: 2070 /* The MAC comes from the CIS. */ 2071 mac = pci_get_ether(dev); 2072 if (!mac) { 2073 device_printf(dev, "No station address in CIS!\n"); 2074 error = ENXIO; 2075 goto fail; 2076 } 2077 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2078 break; 2079 default: 2080 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2081 break; 2082 } 2083 2084 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2085 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2086 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2087 sizeof(struct dc_list_data), 1, sizeof(struct dc_list_data), 2088 0, NULL, NULL, &sc->dc_ltag); 2089 if (error) { 2090 device_printf(dev, "failed to allocate busdma tag\n"); 2091 error = ENXIO; 2092 goto fail; 2093 } 2094 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2095 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2096 if (error) { 2097 device_printf(dev, "failed to allocate DMA safe memory\n"); 2098 error = ENXIO; 2099 goto fail; 2100 } 2101 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2102 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2103 BUS_DMA_NOWAIT); 2104 if (error) { 2105 device_printf(dev, "cannot get address of the descriptors\n"); 2106 error = ENXIO; 2107 goto fail; 2108 } 2109 2110 /* 2111 * Allocate a busdma tag and DMA safe memory for the multicast 2112 * setup frame. 2113 */ 2114 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2115 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2116 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 2117 0, NULL, NULL, &sc->dc_stag); 2118 if (error) { 2119 device_printf(dev, "failed to allocate busdma tag\n"); 2120 error = ENXIO; 2121 goto fail; 2122 } 2123 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2124 BUS_DMA_NOWAIT, &sc->dc_smap); 2125 if (error) { 2126 device_printf(dev, "failed to allocate DMA safe memory\n"); 2127 error = ENXIO; 2128 goto fail; 2129 } 2130 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2131 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2132 if (error) { 2133 device_printf(dev, "cannot get address of the descriptors\n"); 2134 error = ENXIO; 2135 goto fail; 2136 } 2137 2138 /* Allocate a busdma tag for mbufs. */ 2139 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 2140 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2141 MCLBYTES, DC_TX_LIST_CNT, MCLBYTES, 2142 0, NULL, NULL, &sc->dc_mtag); 2143 if (error) { 2144 device_printf(dev, "failed to allocate busdma tag\n"); 2145 error = ENXIO; 2146 goto fail; 2147 } 2148 2149 /* Create the TX/RX busdma maps. */ 2150 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2151 error = bus_dmamap_create(sc->dc_mtag, 0, 2152 &sc->dc_cdata.dc_tx_map[i]); 2153 if (error) { 2154 device_printf(dev, "failed to init TX ring\n"); 2155 error = ENXIO; 2156 goto fail; 2157 } 2158 } 2159 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2160 error = bus_dmamap_create(sc->dc_mtag, 0, 2161 &sc->dc_cdata.dc_rx_map[i]); 2162 if (error) { 2163 device_printf(dev, "failed to init RX ring\n"); 2164 error = ENXIO; 2165 goto fail; 2166 } 2167 } 2168 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2169 if (error) { 2170 device_printf(dev, "failed to init RX ring\n"); 2171 error = ENXIO; 2172 goto fail; 2173 } 2174 2175 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2176 if (ifp == NULL) { 2177 device_printf(dev, "can not if_alloc()\n"); 2178 error = ENOSPC; 2179 goto fail; 2180 } 2181 ifp->if_softc = sc; 2182 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2183 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2184 ifp->if_ioctl = dc_ioctl; 2185 ifp->if_start = dc_start; 2186 ifp->if_init = dc_init; 2187 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2188 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2189 IFQ_SET_READY(&ifp->if_snd); 2190 2191 /* 2192 * Do MII setup. If this is a 21143, check for a PHY on the 2193 * MII bus after applying any necessary fixups to twiddle the 2194 * GPIO bits. If we don't end up finding a PHY, restore the 2195 * old selection (SIA only or SIA/SYM) and attach the dcphy 2196 * driver instead. 2197 */ 2198 if (DC_IS_INTEL(sc)) { 2199 dc_apply_fixup(sc, IFM_AUTO); 2200 tmp = sc->dc_pmode; 2201 sc->dc_pmode = DC_PMODE_MII; 2202 } 2203 2204 /* 2205 * Setup General Purpose port mode and data so the tulip can talk 2206 * to the MII. This needs to be done before mii_phy_probe so that 2207 * we can actually see them. 2208 */ 2209 if (DC_IS_XIRCOM(sc)) { 2210 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2211 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2212 DELAY(10); 2213 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2214 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2215 DELAY(10); 2216 } 2217 2218 error = mii_phy_probe(dev, &sc->dc_miibus, 2219 dc_ifmedia_upd, dc_ifmedia_sts); 2220 2221 if (error && DC_IS_INTEL(sc)) { 2222 sc->dc_pmode = tmp; 2223 if (sc->dc_pmode != DC_PMODE_SIA) 2224 sc->dc_pmode = DC_PMODE_SYM; 2225 sc->dc_flags |= DC_21143_NWAY; 2226 mii_phy_probe(dev, &sc->dc_miibus, 2227 dc_ifmedia_upd, dc_ifmedia_sts); 2228 /* 2229 * For non-MII cards, we need to have the 21143 2230 * drive the LEDs. Except there are some systems 2231 * like the NEC VersaPro NoteBook PC which have no 2232 * LEDs, and twiddling these bits has adverse effects 2233 * on them. (I.e. you suddenly can't get a link.) 2234 */ 2235 if (!(pci_get_subvendor(dev) == 0x1033 && 2236 pci_get_subdevice(dev) == 0x8028)) 2237 sc->dc_flags |= DC_TULIP_LEDS; 2238 error = 0; 2239 } 2240 2241 if (error) { 2242 device_printf(dev, "MII without any PHY!\n"); 2243 goto fail; 2244 } 2245 2246 if (DC_IS_ADMTEK(sc)) { 2247 /* 2248 * Set automatic TX underrun recovery for the ADMtek chips 2249 */ 2250 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2251 } 2252 2253 /* 2254 * Tell the upper layer(s) we support long frames. 2255 */ 2256 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2257 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2258 ifp->if_capenable = ifp->if_capabilities; 2259 #ifdef DEVICE_POLLING 2260 ifp->if_capabilities |= IFCAP_POLLING; 2261 #endif 2262 2263 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2264 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2265 2266 #ifdef SRM_MEDIA 2267 sc->dc_srm_media = 0; 2268 2269 /* Remember the SRM console media setting */ 2270 if (DC_IS_INTEL(sc)) { 2271 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2272 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2273 switch ((command >> 8) & 0xff) { 2274 case 3: 2275 sc->dc_srm_media = IFM_10_T; 2276 break; 2277 case 4: 2278 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2279 break; 2280 case 5: 2281 sc->dc_srm_media = IFM_100_TX; 2282 break; 2283 case 6: 2284 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2285 break; 2286 } 2287 if (sc->dc_srm_media) 2288 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2289 } 2290 #endif 2291 2292 /* 2293 * Call MI attach routine. 2294 */ 2295 ether_ifattach(ifp, eaddr); 2296 2297 /* Hook interrupt last to avoid having to lock softc */ 2298 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2299 dc_intr, sc, &sc->dc_intrhand); 2300 2301 if (error) { 2302 device_printf(dev, "couldn't set up irq\n"); 2303 ether_ifdetach(ifp); 2304 goto fail; 2305 } 2306 2307 fail: 2308 if (error) 2309 dc_detach(dev); 2310 return (error); 2311 } 2312 2313 /* 2314 * Shutdown hardware and free up resources. This can be called any 2315 * time after the mutex has been initialized. It is called in both 2316 * the error case in attach and the normal detach case so it needs 2317 * to be careful about only freeing resources that have actually been 2318 * allocated. 2319 */ 2320 static int 2321 dc_detach(device_t dev) 2322 { 2323 struct dc_softc *sc; 2324 struct ifnet *ifp; 2325 struct dc_mediainfo *m; 2326 int i; 2327 2328 sc = device_get_softc(dev); 2329 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2330 2331 ifp = sc->dc_ifp; 2332 2333 #ifdef DEVICE_POLLING 2334 if (ifp->if_capenable & IFCAP_POLLING) 2335 ether_poll_deregister(ifp); 2336 #endif 2337 2338 /* These should only be active if attach succeeded */ 2339 if (device_is_attached(dev)) { 2340 DC_LOCK(sc); 2341 dc_stop(sc); 2342 DC_UNLOCK(sc); 2343 callout_drain(&sc->dc_stat_ch); 2344 callout_drain(&sc->dc_wdog_ch); 2345 ether_ifdetach(ifp); 2346 } 2347 if (sc->dc_miibus) 2348 device_delete_child(dev, sc->dc_miibus); 2349 bus_generic_detach(dev); 2350 2351 if (sc->dc_intrhand) 2352 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2353 if (sc->dc_irq) 2354 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2355 if (sc->dc_res) 2356 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2357 2358 if (ifp) 2359 if_free(ifp); 2360 2361 if (sc->dc_cdata.dc_sbuf != NULL) 2362 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2363 if (sc->dc_ldata != NULL) 2364 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2365 if (sc->dc_mtag) { 2366 for (i = 0; i < DC_TX_LIST_CNT; i++) 2367 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2368 bus_dmamap_destroy(sc->dc_mtag, 2369 sc->dc_cdata.dc_tx_map[i]); 2370 for (i = 0; i < DC_RX_LIST_CNT; i++) 2371 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2372 bus_dmamap_destroy(sc->dc_mtag, 2373 sc->dc_cdata.dc_rx_map[i]); 2374 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2375 } 2376 if (sc->dc_stag) 2377 bus_dma_tag_destroy(sc->dc_stag); 2378 if (sc->dc_mtag) 2379 bus_dma_tag_destroy(sc->dc_mtag); 2380 if (sc->dc_ltag) 2381 bus_dma_tag_destroy(sc->dc_ltag); 2382 2383 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2384 2385 while (sc->dc_mi != NULL) { 2386 m = sc->dc_mi->dc_next; 2387 free(sc->dc_mi, M_DEVBUF); 2388 sc->dc_mi = m; 2389 } 2390 free(sc->dc_srom, M_DEVBUF); 2391 2392 mtx_destroy(&sc->dc_mtx); 2393 2394 return (0); 2395 } 2396 2397 /* 2398 * Initialize the transmit descriptors. 2399 */ 2400 static int 2401 dc_list_tx_init(struct dc_softc *sc) 2402 { 2403 struct dc_chain_data *cd; 2404 struct dc_list_data *ld; 2405 int i, nexti; 2406 2407 cd = &sc->dc_cdata; 2408 ld = sc->dc_ldata; 2409 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2410 if (i == DC_TX_LIST_CNT - 1) 2411 nexti = 0; 2412 else 2413 nexti = i + 1; 2414 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2415 cd->dc_tx_chain[i] = NULL; 2416 ld->dc_tx_list[i].dc_data = 0; 2417 ld->dc_tx_list[i].dc_ctl = 0; 2418 } 2419 2420 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2421 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2422 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2423 return (0); 2424 } 2425 2426 2427 /* 2428 * Initialize the RX descriptors and allocate mbufs for them. Note that 2429 * we arrange the descriptors in a closed ring, so that the last descriptor 2430 * points back to the first. 2431 */ 2432 static int 2433 dc_list_rx_init(struct dc_softc *sc) 2434 { 2435 struct dc_chain_data *cd; 2436 struct dc_list_data *ld; 2437 int i, nexti; 2438 2439 cd = &sc->dc_cdata; 2440 ld = sc->dc_ldata; 2441 2442 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2443 if (dc_newbuf(sc, i, 1) != 0) 2444 return (ENOBUFS); 2445 if (i == DC_RX_LIST_CNT - 1) 2446 nexti = 0; 2447 else 2448 nexti = i + 1; 2449 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2450 } 2451 2452 cd->dc_rx_prod = 0; 2453 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2454 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2455 return (0); 2456 } 2457 2458 /* 2459 * Initialize an RX descriptor and attach an MBUF cluster. 2460 */ 2461 static int 2462 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2463 { 2464 struct mbuf *m_new; 2465 bus_dmamap_t tmp; 2466 bus_dma_segment_t segs[1]; 2467 int error, nseg; 2468 2469 if (alloc) { 2470 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2471 if (m_new == NULL) 2472 return (ENOBUFS); 2473 } else { 2474 m_new = sc->dc_cdata.dc_rx_chain[i]; 2475 m_new->m_data = m_new->m_ext.ext_buf; 2476 } 2477 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2478 m_adj(m_new, sizeof(u_int64_t)); 2479 2480 /* 2481 * If this is a PNIC chip, zero the buffer. This is part 2482 * of the workaround for the receive bug in the 82c168 and 2483 * 82c169 chips. 2484 */ 2485 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2486 bzero(mtod(m_new, char *), m_new->m_len); 2487 2488 /* No need to remap the mbuf if we're reusing it. */ 2489 if (alloc) { 2490 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, sc->dc_sparemap, 2491 m_new, segs, &nseg, 0); 2492 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2493 if (error) { 2494 m_freem(m_new); 2495 return (error); 2496 } 2497 sc->dc_ldata->dc_rx_list[i].dc_data = htole32(segs->ds_addr); 2498 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2499 tmp = sc->dc_cdata.dc_rx_map[i]; 2500 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2501 sc->dc_sparemap = tmp; 2502 sc->dc_cdata.dc_rx_chain[i] = m_new; 2503 } 2504 2505 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2506 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2507 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2508 BUS_DMASYNC_PREREAD); 2509 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2510 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2511 return (0); 2512 } 2513 2514 /* 2515 * Grrrrr. 2516 * The PNIC chip has a terrible bug in it that manifests itself during 2517 * periods of heavy activity. The exact mode of failure if difficult to 2518 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2519 * will happen on slow machines. The bug is that sometimes instead of 2520 * uploading one complete frame during reception, it uploads what looks 2521 * like the entire contents of its FIFO memory. The frame we want is at 2522 * the end of the whole mess, but we never know exactly how much data has 2523 * been uploaded, so salvaging the frame is hard. 2524 * 2525 * There is only one way to do it reliably, and it's disgusting. 2526 * Here's what we know: 2527 * 2528 * - We know there will always be somewhere between one and three extra 2529 * descriptors uploaded. 2530 * 2531 * - We know the desired received frame will always be at the end of the 2532 * total data upload. 2533 * 2534 * - We know the size of the desired received frame because it will be 2535 * provided in the length field of the status word in the last descriptor. 2536 * 2537 * Here's what we do: 2538 * 2539 * - When we allocate buffers for the receive ring, we bzero() them. 2540 * This means that we know that the buffer contents should be all 2541 * zeros, except for data uploaded by the chip. 2542 * 2543 * - We also force the PNIC chip to upload frames that include the 2544 * ethernet CRC at the end. 2545 * 2546 * - We gather all of the bogus frame data into a single buffer. 2547 * 2548 * - We then position a pointer at the end of this buffer and scan 2549 * backwards until we encounter the first non-zero byte of data. 2550 * This is the end of the received frame. We know we will encounter 2551 * some data at the end of the frame because the CRC will always be 2552 * there, so even if the sender transmits a packet of all zeros, 2553 * we won't be fooled. 2554 * 2555 * - We know the size of the actual received frame, so we subtract 2556 * that value from the current pointer location. This brings us 2557 * to the start of the actual received packet. 2558 * 2559 * - We copy this into an mbuf and pass it on, along with the actual 2560 * frame length. 2561 * 2562 * The performance hit is tremendous, but it beats dropping frames all 2563 * the time. 2564 */ 2565 2566 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2567 static void 2568 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2569 { 2570 struct dc_desc *cur_rx; 2571 struct dc_desc *c = NULL; 2572 struct mbuf *m = NULL; 2573 unsigned char *ptr; 2574 int i, total_len; 2575 u_int32_t rxstat = 0; 2576 2577 i = sc->dc_pnic_rx_bug_save; 2578 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2579 ptr = sc->dc_pnic_rx_buf; 2580 bzero(ptr, DC_RXLEN * 5); 2581 2582 /* Copy all the bytes from the bogus buffers. */ 2583 while (1) { 2584 c = &sc->dc_ldata->dc_rx_list[i]; 2585 rxstat = le32toh(c->dc_status); 2586 m = sc->dc_cdata.dc_rx_chain[i]; 2587 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2588 ptr += DC_RXLEN; 2589 /* If this is the last buffer, break out. */ 2590 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2591 break; 2592 dc_newbuf(sc, i, 0); 2593 DC_INC(i, DC_RX_LIST_CNT); 2594 } 2595 2596 /* Find the length of the actual receive frame. */ 2597 total_len = DC_RXBYTES(rxstat); 2598 2599 /* Scan backwards until we hit a non-zero byte. */ 2600 while (*ptr == 0x00) 2601 ptr--; 2602 2603 /* Round off. */ 2604 if ((uintptr_t)(ptr) & 0x3) 2605 ptr -= 1; 2606 2607 /* Now find the start of the frame. */ 2608 ptr -= total_len; 2609 if (ptr < sc->dc_pnic_rx_buf) 2610 ptr = sc->dc_pnic_rx_buf; 2611 2612 /* 2613 * Now copy the salvaged frame to the last mbuf and fake up 2614 * the status word to make it look like a successful 2615 * frame reception. 2616 */ 2617 dc_newbuf(sc, i, 0); 2618 bcopy(ptr, mtod(m, char *), total_len); 2619 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2620 } 2621 2622 /* 2623 * This routine searches the RX ring for dirty descriptors in the 2624 * event that the rxeof routine falls out of sync with the chip's 2625 * current descriptor pointer. This may happen sometimes as a result 2626 * of a "no RX buffer available" condition that happens when the chip 2627 * consumes all of the RX buffers before the driver has a chance to 2628 * process the RX ring. This routine may need to be called more than 2629 * once to bring the driver back in sync with the chip, however we 2630 * should still be getting RX DONE interrupts to drive the search 2631 * for new packets in the RX ring, so we should catch up eventually. 2632 */ 2633 static int 2634 dc_rx_resync(struct dc_softc *sc) 2635 { 2636 struct dc_desc *cur_rx; 2637 int i, pos; 2638 2639 pos = sc->dc_cdata.dc_rx_prod; 2640 2641 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2642 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2643 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2644 break; 2645 DC_INC(pos, DC_RX_LIST_CNT); 2646 } 2647 2648 /* If the ring really is empty, then just return. */ 2649 if (i == DC_RX_LIST_CNT) 2650 return (0); 2651 2652 /* We've fallen behing the chip: catch it. */ 2653 sc->dc_cdata.dc_rx_prod = pos; 2654 2655 return (EAGAIN); 2656 } 2657 2658 /* 2659 * A frame has been uploaded: pass the resulting mbuf chain up to 2660 * the higher level protocols. 2661 */ 2662 static void 2663 dc_rxeof(struct dc_softc *sc) 2664 { 2665 struct mbuf *m, *m0; 2666 struct ifnet *ifp; 2667 struct dc_desc *cur_rx; 2668 int i, total_len = 0; 2669 u_int32_t rxstat; 2670 2671 DC_LOCK_ASSERT(sc); 2672 2673 ifp = sc->dc_ifp; 2674 i = sc->dc_cdata.dc_rx_prod; 2675 2676 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2677 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2678 DC_RXSTAT_OWN)) { 2679 #ifdef DEVICE_POLLING 2680 if (ifp->if_capenable & IFCAP_POLLING) { 2681 if (sc->rxcycles <= 0) 2682 break; 2683 sc->rxcycles--; 2684 } 2685 #endif 2686 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2687 rxstat = le32toh(cur_rx->dc_status); 2688 m = sc->dc_cdata.dc_rx_chain[i]; 2689 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2690 BUS_DMASYNC_POSTREAD); 2691 total_len = DC_RXBYTES(rxstat); 2692 2693 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2694 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2695 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2696 sc->dc_pnic_rx_bug_save = i; 2697 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2698 DC_INC(i, DC_RX_LIST_CNT); 2699 continue; 2700 } 2701 dc_pnic_rx_bug_war(sc, i); 2702 rxstat = le32toh(cur_rx->dc_status); 2703 total_len = DC_RXBYTES(rxstat); 2704 } 2705 } 2706 2707 /* 2708 * If an error occurs, update stats, clear the 2709 * status word and leave the mbuf cluster in place: 2710 * it should simply get re-used next time this descriptor 2711 * comes up in the ring. However, don't report long 2712 * frames as errors since they could be vlans. 2713 */ 2714 if ((rxstat & DC_RXSTAT_RXERR)) { 2715 if (!(rxstat & DC_RXSTAT_GIANT) || 2716 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2717 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2718 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2719 ifp->if_ierrors++; 2720 if (rxstat & DC_RXSTAT_COLLSEEN) 2721 ifp->if_collisions++; 2722 dc_newbuf(sc, i, 0); 2723 if (rxstat & DC_RXSTAT_CRCERR) { 2724 DC_INC(i, DC_RX_LIST_CNT); 2725 continue; 2726 } else { 2727 dc_init_locked(sc); 2728 return; 2729 } 2730 } 2731 } 2732 2733 /* No errors; receive the packet. */ 2734 total_len -= ETHER_CRC_LEN; 2735 #ifdef __NO_STRICT_ALIGNMENT 2736 /* 2737 * On architectures without alignment problems we try to 2738 * allocate a new buffer for the receive ring, and pass up 2739 * the one where the packet is already, saving the expensive 2740 * copy done in m_devget(). 2741 * If we are on an architecture with alignment problems, or 2742 * if the allocation fails, then use m_devget and leave the 2743 * existing buffer in the receive ring. 2744 */ 2745 if (dc_newbuf(sc, i, 1) == 0) { 2746 m->m_pkthdr.rcvif = ifp; 2747 m->m_pkthdr.len = m->m_len = total_len; 2748 DC_INC(i, DC_RX_LIST_CNT); 2749 } else 2750 #endif 2751 { 2752 m0 = m_devget(mtod(m, char *), total_len, 2753 ETHER_ALIGN, ifp, NULL); 2754 dc_newbuf(sc, i, 0); 2755 DC_INC(i, DC_RX_LIST_CNT); 2756 if (m0 == NULL) { 2757 ifp->if_ierrors++; 2758 continue; 2759 } 2760 m = m0; 2761 } 2762 2763 ifp->if_ipackets++; 2764 DC_UNLOCK(sc); 2765 (*ifp->if_input)(ifp, m); 2766 DC_LOCK(sc); 2767 } 2768 2769 sc->dc_cdata.dc_rx_prod = i; 2770 } 2771 2772 /* 2773 * A frame was downloaded to the chip. It's safe for us to clean up 2774 * the list buffers. 2775 */ 2776 2777 static void 2778 dc_txeof(struct dc_softc *sc) 2779 { 2780 struct dc_desc *cur_tx = NULL; 2781 struct ifnet *ifp; 2782 int idx; 2783 u_int32_t ctl, txstat; 2784 2785 ifp = sc->dc_ifp; 2786 2787 /* 2788 * Go through our tx list and free mbufs for those 2789 * frames that have been transmitted. 2790 */ 2791 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2792 idx = sc->dc_cdata.dc_tx_cons; 2793 while (idx != sc->dc_cdata.dc_tx_prod) { 2794 2795 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2796 txstat = le32toh(cur_tx->dc_status); 2797 ctl = le32toh(cur_tx->dc_ctl); 2798 2799 if (txstat & DC_TXSTAT_OWN) 2800 break; 2801 2802 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2803 if (ctl & DC_TXCTL_SETUP) { 2804 /* 2805 * Yes, the PNIC is so brain damaged 2806 * that it will sometimes generate a TX 2807 * underrun error while DMAing the RX 2808 * filter setup frame. If we detect this, 2809 * we have to send the setup frame again, 2810 * or else the filter won't be programmed 2811 * correctly. 2812 */ 2813 if (DC_IS_PNIC(sc)) { 2814 if (txstat & DC_TXSTAT_ERRSUM) 2815 dc_setfilt(sc); 2816 } 2817 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2818 } 2819 sc->dc_cdata.dc_tx_cnt--; 2820 DC_INC(idx, DC_TX_LIST_CNT); 2821 continue; 2822 } 2823 2824 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2825 /* 2826 * XXX: Why does my Xircom taunt me so? 2827 * For some reason it likes setting the CARRLOST flag 2828 * even when the carrier is there. wtf?!? 2829 * Who knows, but Conexant chips have the 2830 * same problem. Maybe they took lessons 2831 * from Xircom. 2832 */ 2833 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2834 sc->dc_pmode == DC_PMODE_MII && 2835 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2836 DC_TXSTAT_NOCARRIER))) 2837 txstat &= ~DC_TXSTAT_ERRSUM; 2838 } else { 2839 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2840 sc->dc_pmode == DC_PMODE_MII && 2841 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2842 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2843 txstat &= ~DC_TXSTAT_ERRSUM; 2844 } 2845 2846 if (txstat & DC_TXSTAT_ERRSUM) { 2847 ifp->if_oerrors++; 2848 if (txstat & DC_TXSTAT_EXCESSCOLL) 2849 ifp->if_collisions++; 2850 if (txstat & DC_TXSTAT_LATECOLL) 2851 ifp->if_collisions++; 2852 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2853 dc_init_locked(sc); 2854 return; 2855 } 2856 } 2857 2858 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2859 2860 ifp->if_opackets++; 2861 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2862 bus_dmamap_sync(sc->dc_mtag, 2863 sc->dc_cdata.dc_tx_map[idx], 2864 BUS_DMASYNC_POSTWRITE); 2865 bus_dmamap_unload(sc->dc_mtag, 2866 sc->dc_cdata.dc_tx_map[idx]); 2867 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2868 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2869 } 2870 2871 sc->dc_cdata.dc_tx_cnt--; 2872 DC_INC(idx, DC_TX_LIST_CNT); 2873 } 2874 sc->dc_cdata.dc_tx_cons = idx; 2875 2876 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_RSVD) 2877 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2878 2879 if (sc->dc_cdata.dc_tx_cnt == 0) 2880 sc->dc_wdog_timer = 0; 2881 } 2882 2883 static void 2884 dc_tick(void *xsc) 2885 { 2886 struct dc_softc *sc; 2887 struct mii_data *mii; 2888 struct ifnet *ifp; 2889 u_int32_t r; 2890 2891 sc = xsc; 2892 DC_LOCK_ASSERT(sc); 2893 ifp = sc->dc_ifp; 2894 mii = device_get_softc(sc->dc_miibus); 2895 2896 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2897 if (sc->dc_flags & DC_21143_NWAY) { 2898 r = CSR_READ_4(sc, DC_10BTSTAT); 2899 if (IFM_SUBTYPE(mii->mii_media_active) == 2900 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2901 sc->dc_link = 0; 2902 mii_mediachg(mii); 2903 } 2904 if (IFM_SUBTYPE(mii->mii_media_active) == 2905 IFM_10_T && (r & DC_TSTAT_LS10)) { 2906 sc->dc_link = 0; 2907 mii_mediachg(mii); 2908 } 2909 if (sc->dc_link == 0) 2910 mii_tick(mii); 2911 } else { 2912 r = CSR_READ_4(sc, DC_ISR); 2913 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2914 sc->dc_cdata.dc_tx_cnt == 0) { 2915 mii_tick(mii); 2916 if (!(mii->mii_media_status & IFM_ACTIVE)) 2917 sc->dc_link = 0; 2918 } 2919 } 2920 } else 2921 mii_tick(mii); 2922 2923 /* 2924 * When the init routine completes, we expect to be able to send 2925 * packets right away, and in fact the network code will send a 2926 * gratuitous ARP the moment the init routine marks the interface 2927 * as running. However, even though the MAC may have been initialized, 2928 * there may be a delay of a few seconds before the PHY completes 2929 * autonegotiation and the link is brought up. Any transmissions 2930 * made during that delay will be lost. Dealing with this is tricky: 2931 * we can't just pause in the init routine while waiting for the 2932 * PHY to come ready since that would bring the whole system to 2933 * a screeching halt for several seconds. 2934 * 2935 * What we do here is prevent the TX start routine from sending 2936 * any packets until a link has been established. After the 2937 * interface has been initialized, the tick routine will poll 2938 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2939 * that time, packets will stay in the send queue, and once the 2940 * link comes up, they will be flushed out to the wire. 2941 */ 2942 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2943 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2944 sc->dc_link++; 2945 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2946 dc_start_locked(ifp); 2947 } 2948 2949 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2950 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2951 else 2952 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2953 } 2954 2955 /* 2956 * A transmit underrun has occurred. Back off the transmit threshold, 2957 * or switch to store and forward mode if we have to. 2958 */ 2959 static void 2960 dc_tx_underrun(struct dc_softc *sc) 2961 { 2962 u_int32_t isr; 2963 int i; 2964 2965 if (DC_IS_DAVICOM(sc)) 2966 dc_init_locked(sc); 2967 2968 if (DC_IS_INTEL(sc)) { 2969 /* 2970 * The real 21143 requires that the transmitter be idle 2971 * in order to change the transmit threshold or store 2972 * and forward state. 2973 */ 2974 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2975 2976 for (i = 0; i < DC_TIMEOUT; i++) { 2977 isr = CSR_READ_4(sc, DC_ISR); 2978 if (isr & DC_ISR_TX_IDLE) 2979 break; 2980 DELAY(10); 2981 } 2982 if (i == DC_TIMEOUT) { 2983 device_printf(sc->dc_dev, 2984 "%s: failed to force tx to idle state\n", 2985 __func__); 2986 dc_init_locked(sc); 2987 } 2988 } 2989 2990 device_printf(sc->dc_dev, "TX underrun -- "); 2991 sc->dc_txthresh += DC_TXTHRESH_INC; 2992 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2993 printf("using store and forward mode\n"); 2994 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2995 } else { 2996 printf("increasing TX threshold\n"); 2997 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2998 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2999 } 3000 3001 if (DC_IS_INTEL(sc)) 3002 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3003 } 3004 3005 #ifdef DEVICE_POLLING 3006 static poll_handler_t dc_poll; 3007 3008 static void 3009 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3010 { 3011 struct dc_softc *sc = ifp->if_softc; 3012 3013 DC_LOCK(sc); 3014 3015 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3016 DC_UNLOCK(sc); 3017 return; 3018 } 3019 3020 sc->rxcycles = count; 3021 dc_rxeof(sc); 3022 dc_txeof(sc); 3023 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3024 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3025 dc_start_locked(ifp); 3026 3027 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3028 u_int32_t status; 3029 3030 status = CSR_READ_4(sc, DC_ISR); 3031 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3032 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3033 DC_ISR_BUS_ERR); 3034 if (!status) { 3035 DC_UNLOCK(sc); 3036 return; 3037 } 3038 /* ack what we have */ 3039 CSR_WRITE_4(sc, DC_ISR, status); 3040 3041 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3042 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3043 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3044 3045 if (dc_rx_resync(sc)) 3046 dc_rxeof(sc); 3047 } 3048 /* restart transmit unit if necessary */ 3049 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3050 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3051 3052 if (status & DC_ISR_TX_UNDERRUN) 3053 dc_tx_underrun(sc); 3054 3055 if (status & DC_ISR_BUS_ERR) { 3056 if_printf(ifp, "%s: bus error\n", __func__); 3057 dc_reset(sc); 3058 dc_init_locked(sc); 3059 } 3060 } 3061 DC_UNLOCK(sc); 3062 } 3063 #endif /* DEVICE_POLLING */ 3064 3065 static void 3066 dc_intr(void *arg) 3067 { 3068 struct dc_softc *sc; 3069 struct ifnet *ifp; 3070 u_int32_t status; 3071 3072 sc = arg; 3073 3074 if (sc->suspended) 3075 return; 3076 3077 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3078 return; 3079 3080 DC_LOCK(sc); 3081 ifp = sc->dc_ifp; 3082 #ifdef DEVICE_POLLING 3083 if (ifp->if_capenable & IFCAP_POLLING) { 3084 DC_UNLOCK(sc); 3085 return; 3086 } 3087 #endif 3088 3089 /* Suppress unwanted interrupts */ 3090 if (!(ifp->if_flags & IFF_UP)) { 3091 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3092 dc_stop(sc); 3093 DC_UNLOCK(sc); 3094 return; 3095 } 3096 3097 /* Disable interrupts. */ 3098 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3099 3100 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 3101 status != 0xFFFFFFFF && 3102 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3103 3104 CSR_WRITE_4(sc, DC_ISR, status); 3105 3106 if (status & DC_ISR_RX_OK) { 3107 int curpkts; 3108 curpkts = ifp->if_ipackets; 3109 dc_rxeof(sc); 3110 if (curpkts == ifp->if_ipackets) { 3111 while (dc_rx_resync(sc)) 3112 dc_rxeof(sc); 3113 } 3114 } 3115 3116 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3117 dc_txeof(sc); 3118 3119 if (status & DC_ISR_TX_IDLE) { 3120 dc_txeof(sc); 3121 if (sc->dc_cdata.dc_tx_cnt) { 3122 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3123 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3124 } 3125 } 3126 3127 if (status & DC_ISR_TX_UNDERRUN) 3128 dc_tx_underrun(sc); 3129 3130 if ((status & DC_ISR_RX_WATDOGTIMEO) 3131 || (status & DC_ISR_RX_NOBUF)) { 3132 int curpkts; 3133 curpkts = ifp->if_ipackets; 3134 dc_rxeof(sc); 3135 if (curpkts == ifp->if_ipackets) { 3136 while (dc_rx_resync(sc)) 3137 dc_rxeof(sc); 3138 } 3139 } 3140 3141 if (status & DC_ISR_BUS_ERR) { 3142 dc_reset(sc); 3143 dc_init_locked(sc); 3144 } 3145 } 3146 3147 /* Re-enable interrupts. */ 3148 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3149 3150 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3151 dc_start_locked(ifp); 3152 3153 DC_UNLOCK(sc); 3154 } 3155 3156 static void 3157 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3158 void *arg; 3159 bus_dma_segment_t *segs; 3160 int nseg; 3161 bus_size_t mapsize; 3162 int error; 3163 { 3164 struct dc_softc *sc; 3165 struct dc_desc *f; 3166 int cur, first, frag, i; 3167 3168 sc = arg; 3169 if (error) 3170 return; 3171 3172 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3173 for (i = 0; i < nseg; i++) { 3174 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3175 (frag == (DC_TX_LIST_CNT - 1)) && 3176 (first != sc->dc_cdata.dc_tx_first)) { 3177 bus_dmamap_unload(sc->dc_mtag, 3178 sc->dc_cdata.dc_tx_map[first]); 3179 sc->dc_cdata.dc_tx_err = ENOBUFS; 3180 return; 3181 } 3182 3183 f = &sc->dc_ldata->dc_tx_list[frag]; 3184 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3185 if (i == 0) { 3186 f->dc_status = 0; 3187 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3188 } else 3189 f->dc_status = htole32(DC_TXSTAT_OWN); 3190 f->dc_data = htole32(segs[i].ds_addr); 3191 cur = frag; 3192 DC_INC(frag, DC_TX_LIST_CNT); 3193 } 3194 3195 sc->dc_cdata.dc_tx_err = 0; 3196 sc->dc_cdata.dc_tx_prod = frag; 3197 sc->dc_cdata.dc_tx_cnt += nseg; 3198 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3199 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3200 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3201 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3202 htole32(DC_TXCTL_FINT); 3203 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3204 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3205 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3206 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3207 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3208 } 3209 3210 /* 3211 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3212 * pointers to the fragment pointers. 3213 */ 3214 static int 3215 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3216 { 3217 struct mbuf *m; 3218 int error, idx, chainlen = 0; 3219 3220 /* 3221 * If there's no way we can send any packets, return now. 3222 */ 3223 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD) 3224 return (ENOBUFS); 3225 3226 /* 3227 * Count the number of frags in this chain to see if 3228 * we need to m_defrag. Since the descriptor list is shared 3229 * by all packets, we'll m_defrag long chains so that they 3230 * do not use up the entire list, even if they would fit. 3231 */ 3232 for (m = *m_head; m != NULL; m = m->m_next) 3233 chainlen++; 3234 3235 m = NULL; 3236 if ((sc->dc_flags & DC_TX_COALESCE && ((*m_head)->m_next != NULL || 3237 sc->dc_flags & DC_TX_ALIGN)) || (chainlen > DC_TX_LIST_CNT / 4) || 3238 (DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt) <= 3239 DC_TX_LIST_RSVD)) { 3240 m = m_defrag(*m_head, M_DONTWAIT); 3241 if (m == NULL) { 3242 m_freem(*m_head); 3243 *m_head = NULL; 3244 return (ENOBUFS); 3245 } 3246 *m_head = m; 3247 } 3248 idx = sc->dc_cdata.dc_tx_prod; 3249 sc->dc_cdata.dc_tx_mapping = *m_head; 3250 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3251 *m_head, dc_dma_map_txbuf, sc, 0); 3252 if (error != 0 || sc->dc_cdata.dc_tx_err != 0) { 3253 if (m != NULL) { 3254 m_freem(m); 3255 *m_head = NULL; 3256 } 3257 return (error != 0 ? error : sc->dc_cdata.dc_tx_err); 3258 } 3259 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3260 BUS_DMASYNC_PREWRITE); 3261 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3262 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3263 return (0); 3264 } 3265 3266 /* 3267 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3268 * to the mbuf data regions directly in the transmit lists. We also save a 3269 * copy of the pointers since the transmit list fragment pointers are 3270 * physical addresses. 3271 */ 3272 3273 static void 3274 dc_start(struct ifnet *ifp) 3275 { 3276 struct dc_softc *sc; 3277 3278 sc = ifp->if_softc; 3279 DC_LOCK(sc); 3280 dc_start_locked(ifp); 3281 DC_UNLOCK(sc); 3282 } 3283 3284 static void 3285 dc_start_locked(struct ifnet *ifp) 3286 { 3287 struct dc_softc *sc; 3288 struct mbuf *m_head = NULL; 3289 unsigned int queued = 0; 3290 int idx; 3291 3292 sc = ifp->if_softc; 3293 3294 DC_LOCK_ASSERT(sc); 3295 3296 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3297 return; 3298 3299 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3300 return; 3301 3302 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3303 3304 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3305 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3306 if (m_head == NULL) 3307 break; 3308 3309 if (dc_encap(sc, &m_head)) { 3310 if (m_head == NULL) 3311 break; 3312 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3313 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3314 break; 3315 } 3316 idx = sc->dc_cdata.dc_tx_prod; 3317 3318 queued++; 3319 /* 3320 * If there's a BPF listener, bounce a copy of this frame 3321 * to him. 3322 */ 3323 BPF_MTAP(ifp, m_head); 3324 3325 if (sc->dc_flags & DC_TX_ONE) { 3326 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3327 break; 3328 } 3329 } 3330 3331 if (queued > 0) { 3332 /* Transmit */ 3333 if (!(sc->dc_flags & DC_TX_POLL)) 3334 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3335 3336 /* 3337 * Set a timeout in case the chip goes out to lunch. 3338 */ 3339 sc->dc_wdog_timer = 5; 3340 } 3341 } 3342 3343 static void 3344 dc_init(void *xsc) 3345 { 3346 struct dc_softc *sc = xsc; 3347 3348 DC_LOCK(sc); 3349 dc_init_locked(sc); 3350 #ifdef SRM_MEDIA 3351 if(sc->dc_srm_media) { 3352 struct ifreq ifr; 3353 struct mii_data *mii; 3354 3355 ifr.ifr_media = sc->dc_srm_media; 3356 sc->dc_srm_media = 0; 3357 DC_UNLOCK(sc); 3358 mii = device_get_softc(sc->dc_miibus); 3359 ifmedia_ioctl(sc->dc_ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3360 } else 3361 #endif 3362 DC_UNLOCK(sc); 3363 } 3364 3365 static void 3366 dc_init_locked(struct dc_softc *sc) 3367 { 3368 struct ifnet *ifp = sc->dc_ifp; 3369 struct mii_data *mii; 3370 3371 DC_LOCK_ASSERT(sc); 3372 3373 mii = device_get_softc(sc->dc_miibus); 3374 3375 /* 3376 * Cancel pending I/O and free all RX/TX buffers. 3377 */ 3378 dc_stop(sc); 3379 dc_reset(sc); 3380 3381 /* 3382 * Set cache alignment and burst length. 3383 */ 3384 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3385 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3386 else 3387 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3388 /* 3389 * Evenly share the bus between receive and transmit process. 3390 */ 3391 if (DC_IS_INTEL(sc)) 3392 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3393 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3394 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3395 } else { 3396 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3397 } 3398 if (sc->dc_flags & DC_TX_POLL) 3399 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3400 switch(sc->dc_cachesize) { 3401 case 32: 3402 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3403 break; 3404 case 16: 3405 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3406 break; 3407 case 8: 3408 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3409 break; 3410 case 0: 3411 default: 3412 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3413 break; 3414 } 3415 3416 if (sc->dc_flags & DC_TX_STORENFWD) 3417 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3418 else { 3419 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3420 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3421 } else { 3422 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3423 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3424 } 3425 } 3426 3427 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3428 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3429 3430 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3431 /* 3432 * The app notes for the 98713 and 98715A say that 3433 * in order to have the chips operate properly, a magic 3434 * number must be written to CSR16. Macronix does not 3435 * document the meaning of these bits so there's no way 3436 * to know exactly what they do. The 98713 has a magic 3437 * number all its own; the rest all use a different one. 3438 */ 3439 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3440 if (sc->dc_type == DC_TYPE_98713) 3441 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3442 else 3443 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3444 } 3445 3446 if (DC_IS_XIRCOM(sc)) { 3447 /* 3448 * setup General Purpose Port mode and data so the tulip 3449 * can talk to the MII. 3450 */ 3451 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3452 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3453 DELAY(10); 3454 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3455 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3456 DELAY(10); 3457 } 3458 3459 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3460 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3461 3462 /* Init circular RX list. */ 3463 if (dc_list_rx_init(sc) == ENOBUFS) { 3464 device_printf(sc->dc_dev, 3465 "initialization failed: no memory for rx buffers\n"); 3466 dc_stop(sc); 3467 return; 3468 } 3469 3470 /* 3471 * Init TX descriptors. 3472 */ 3473 dc_list_tx_init(sc); 3474 3475 /* 3476 * Load the address of the RX list. 3477 */ 3478 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3479 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3480 3481 /* 3482 * Enable interrupts. 3483 */ 3484 #ifdef DEVICE_POLLING 3485 /* 3486 * ... but only if we are not polling, and make sure they are off in 3487 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3488 * after a reset. 3489 */ 3490 if (ifp->if_capenable & IFCAP_POLLING) 3491 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3492 else 3493 #endif 3494 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3495 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3496 3497 /* Enable transmitter. */ 3498 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3499 3500 /* 3501 * If this is an Intel 21143 and we're not using the 3502 * MII port, program the LED control pins so we get 3503 * link and activity indications. 3504 */ 3505 if (sc->dc_flags & DC_TULIP_LEDS) { 3506 CSR_WRITE_4(sc, DC_WATCHDOG, 3507 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3508 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3509 } 3510 3511 /* 3512 * Load the RX/multicast filter. We do this sort of late 3513 * because the filter programming scheme on the 21143 and 3514 * some clones requires DMAing a setup frame via the TX 3515 * engine, and we need the transmitter enabled for that. 3516 */ 3517 dc_setfilt(sc); 3518 3519 /* Enable receiver. */ 3520 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3521 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3522 3523 mii_mediachg(mii); 3524 dc_setcfg(sc, sc->dc_if_media); 3525 3526 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3527 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3528 3529 /* Don't start the ticker if this is a homePNA link. */ 3530 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3531 sc->dc_link = 1; 3532 else { 3533 if (sc->dc_flags & DC_21143_NWAY) 3534 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3535 else 3536 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3537 } 3538 3539 sc->dc_wdog_timer = 0; 3540 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3541 } 3542 3543 /* 3544 * Set media options. 3545 */ 3546 static int 3547 dc_ifmedia_upd(struct ifnet *ifp) 3548 { 3549 struct dc_softc *sc; 3550 struct mii_data *mii; 3551 struct ifmedia *ifm; 3552 3553 sc = ifp->if_softc; 3554 mii = device_get_softc(sc->dc_miibus); 3555 DC_LOCK(sc); 3556 mii_mediachg(mii); 3557 ifm = &mii->mii_media; 3558 3559 if (DC_IS_DAVICOM(sc) && 3560 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3561 dc_setcfg(sc, ifm->ifm_media); 3562 else 3563 sc->dc_link = 0; 3564 DC_UNLOCK(sc); 3565 3566 return (0); 3567 } 3568 3569 /* 3570 * Report current media status. 3571 */ 3572 static void 3573 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3574 { 3575 struct dc_softc *sc; 3576 struct mii_data *mii; 3577 struct ifmedia *ifm; 3578 3579 sc = ifp->if_softc; 3580 mii = device_get_softc(sc->dc_miibus); 3581 DC_LOCK(sc); 3582 mii_pollstat(mii); 3583 ifm = &mii->mii_media; 3584 if (DC_IS_DAVICOM(sc)) { 3585 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3586 ifmr->ifm_active = ifm->ifm_media; 3587 ifmr->ifm_status = 0; 3588 DC_UNLOCK(sc); 3589 return; 3590 } 3591 } 3592 ifmr->ifm_active = mii->mii_media_active; 3593 ifmr->ifm_status = mii->mii_media_status; 3594 DC_UNLOCK(sc); 3595 } 3596 3597 static int 3598 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3599 { 3600 struct dc_softc *sc = ifp->if_softc; 3601 struct ifreq *ifr = (struct ifreq *)data; 3602 struct mii_data *mii; 3603 int error = 0; 3604 3605 switch (command) { 3606 case SIOCSIFFLAGS: 3607 DC_LOCK(sc); 3608 if (ifp->if_flags & IFF_UP) { 3609 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3610 (IFF_PROMISC | IFF_ALLMULTI); 3611 3612 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3613 if (need_setfilt) 3614 dc_setfilt(sc); 3615 } else { 3616 sc->dc_txthresh = 0; 3617 dc_init_locked(sc); 3618 } 3619 } else { 3620 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3621 dc_stop(sc); 3622 } 3623 sc->dc_if_flags = ifp->if_flags; 3624 DC_UNLOCK(sc); 3625 error = 0; 3626 break; 3627 case SIOCADDMULTI: 3628 case SIOCDELMULTI: 3629 DC_LOCK(sc); 3630 dc_setfilt(sc); 3631 DC_UNLOCK(sc); 3632 error = 0; 3633 break; 3634 case SIOCGIFMEDIA: 3635 case SIOCSIFMEDIA: 3636 mii = device_get_softc(sc->dc_miibus); 3637 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3638 #ifdef SRM_MEDIA 3639 DC_LOCK(sc); 3640 if (sc->dc_srm_media) 3641 sc->dc_srm_media = 0; 3642 DC_UNLOCK(sc); 3643 #endif 3644 break; 3645 case SIOCSIFCAP: 3646 #ifdef DEVICE_POLLING 3647 if (ifr->ifr_reqcap & IFCAP_POLLING && 3648 !(ifp->if_capenable & IFCAP_POLLING)) { 3649 error = ether_poll_register(dc_poll, ifp); 3650 if (error) 3651 return(error); 3652 DC_LOCK(sc); 3653 /* Disable interrupts */ 3654 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3655 ifp->if_capenable |= IFCAP_POLLING; 3656 DC_UNLOCK(sc); 3657 return (error); 3658 3659 } 3660 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3661 ifp->if_capenable & IFCAP_POLLING) { 3662 error = ether_poll_deregister(ifp); 3663 /* Enable interrupts. */ 3664 DC_LOCK(sc); 3665 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3666 ifp->if_capenable &= ~IFCAP_POLLING; 3667 DC_UNLOCK(sc); 3668 return (error); 3669 } 3670 #endif /* DEVICE_POLLING */ 3671 break; 3672 default: 3673 error = ether_ioctl(ifp, command, data); 3674 break; 3675 } 3676 3677 return (error); 3678 } 3679 3680 static void 3681 dc_watchdog(void *xsc) 3682 { 3683 struct dc_softc *sc = xsc; 3684 struct ifnet *ifp; 3685 3686 DC_LOCK_ASSERT(sc); 3687 3688 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3689 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3690 return; 3691 } 3692 3693 ifp = sc->dc_ifp; 3694 ifp->if_oerrors++; 3695 device_printf(sc->dc_dev, "watchdog timeout\n"); 3696 3697 dc_stop(sc); 3698 dc_reset(sc); 3699 dc_init_locked(sc); 3700 3701 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3702 dc_start_locked(ifp); 3703 } 3704 3705 /* 3706 * Stop the adapter and free any mbufs allocated to the 3707 * RX and TX lists. 3708 */ 3709 static void 3710 dc_stop(struct dc_softc *sc) 3711 { 3712 struct ifnet *ifp; 3713 struct dc_list_data *ld; 3714 struct dc_chain_data *cd; 3715 int i; 3716 u_int32_t ctl; 3717 3718 DC_LOCK_ASSERT(sc); 3719 3720 ifp = sc->dc_ifp; 3721 ld = sc->dc_ldata; 3722 cd = &sc->dc_cdata; 3723 3724 callout_stop(&sc->dc_stat_ch); 3725 callout_stop(&sc->dc_wdog_ch); 3726 sc->dc_wdog_timer = 0; 3727 3728 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3729 3730 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3731 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3732 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3733 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3734 sc->dc_link = 0; 3735 3736 /* 3737 * Free data in the RX lists. 3738 */ 3739 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3740 if (cd->dc_rx_chain[i] != NULL) { 3741 m_freem(cd->dc_rx_chain[i]); 3742 cd->dc_rx_chain[i] = NULL; 3743 } 3744 } 3745 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3746 3747 /* 3748 * Free the TX list buffers. 3749 */ 3750 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3751 if (cd->dc_tx_chain[i] != NULL) { 3752 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3753 if ((ctl & DC_TXCTL_SETUP) || 3754 !(ctl & DC_TXCTL_LASTFRAG)) { 3755 cd->dc_tx_chain[i] = NULL; 3756 continue; 3757 } 3758 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3759 m_freem(cd->dc_tx_chain[i]); 3760 cd->dc_tx_chain[i] = NULL; 3761 } 3762 } 3763 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3764 } 3765 3766 /* 3767 * Device suspend routine. Stop the interface and save some PCI 3768 * settings in case the BIOS doesn't restore them properly on 3769 * resume. 3770 */ 3771 static int 3772 dc_suspend(device_t dev) 3773 { 3774 struct dc_softc *sc; 3775 3776 sc = device_get_softc(dev); 3777 DC_LOCK(sc); 3778 dc_stop(sc); 3779 sc->suspended = 1; 3780 DC_UNLOCK(sc); 3781 3782 return (0); 3783 } 3784 3785 /* 3786 * Device resume routine. Restore some PCI settings in case the BIOS 3787 * doesn't, re-enable busmastering, and restart the interface if 3788 * appropriate. 3789 */ 3790 static int 3791 dc_resume(device_t dev) 3792 { 3793 struct dc_softc *sc; 3794 struct ifnet *ifp; 3795 3796 sc = device_get_softc(dev); 3797 ifp = sc->dc_ifp; 3798 3799 /* reinitialize interface if necessary */ 3800 DC_LOCK(sc); 3801 if (ifp->if_flags & IFF_UP) 3802 dc_init_locked(sc); 3803 3804 sc->suspended = 0; 3805 DC_UNLOCK(sc); 3806 3807 return (0); 3808 } 3809 3810 /* 3811 * Stop all chip I/O so that the kernel's probe routines don't 3812 * get confused by errant DMAs when rebooting. 3813 */ 3814 static void 3815 dc_shutdown(device_t dev) 3816 { 3817 struct dc_softc *sc; 3818 3819 sc = device_get_softc(dev); 3820 3821 DC_LOCK(sc); 3822 dc_stop(sc); 3823 DC_UNLOCK(sc); 3824 }
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