Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/pci/if_dc.c
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1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/6.4/sys/pci/if_dc.c 185264 2008-11-24 21:26:26Z marius $"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #ifdef HAVE_KERNEL_OPTION_HEADERS 95 #include "opt_device_polling.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/endian.h> 100 #include <sys/systm.h> 101 #include <sys/sockio.h> 102 #include <sys/mbuf.h> 103 #include <sys/malloc.h> 104 #include <sys/kernel.h> 105 #include <sys/module.h> 106 #include <sys/socket.h> 107 #include <sys/sysctl.h> 108 109 #include <net/if.h> 110 #include <net/if_arp.h> 111 #include <net/ethernet.h> 112 #include <net/if_dl.h> 113 #include <net/if_media.h> 114 #include <net/if_types.h> 115 #include <net/if_vlan_var.h> 116 117 #include <net/bpf.h> 118 119 #include <machine/bus.h> 120 #include <machine/resource.h> 121 #include <sys/bus.h> 122 #include <sys/rman.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 130 #define DC_USEIOSPACE 131 #ifdef __alpha__ 132 #define SRM_MEDIA 133 #endif 134 135 #include <pci/if_dcreg.h> 136 137 #ifdef __sparc64__ 138 #include <dev/ofw/openfirm.h> 139 #include <machine/ofw_machdep.h> 140 #endif 141 142 MODULE_DEPEND(dc, pci, 1, 1, 1); 143 MODULE_DEPEND(dc, ether, 1, 1, 1); 144 MODULE_DEPEND(dc, miibus, 1, 1, 1); 145 146 /* 147 * "device miibus" is required in kernel config. See GENERIC if you get 148 * errors here. 149 */ 150 #include "miibus_if.h" 151 152 /* 153 * Various supported device vendors/types and their names. 154 */ 155 static const struct dc_type dc_devs[] = { 156 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 157 "Intel 21143 10/100BaseTX" }, 158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 159 "Davicom DM9009 10/100BaseTX" }, 160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 161 "Davicom DM9100 10/100BaseTX" }, 162 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 163 "Davicom DM9102A 10/100BaseTX" }, 164 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 165 "Davicom DM9102 10/100BaseTX" }, 166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 167 "ADMtek AL981 10/100BaseTX" }, 168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 169 "ADMtek AN985 10/100BaseTX" }, 170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 171 "ADMtek ADM9511 10/100BaseTX" }, 172 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 173 "ADMtek ADM9513 10/100BaseTX" }, 174 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511), 0, 175 "Netgear FA511 10/100BaseTX" }, 176 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 177 "ASIX AX88141 10/100BaseTX" }, 178 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 179 "ASIX AX88140A 10/100BaseTX" }, 180 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 181 "Macronix 98713A 10/100BaseTX" }, 182 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 183 "Macronix 98713 10/100BaseTX" }, 184 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 185 "Compex RL100-TX 10/100BaseTX" }, 186 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 187 "Compex RL100-TX 10/100BaseTX" }, 188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 189 "Macronix 98725 10/100BaseTX" }, 190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 191 "Macronix 98715AEC-C 10/100BaseTX" }, 192 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 193 "Macronix 98715/98715A 10/100BaseTX" }, 194 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 195 "Macronix 98727/98732 10/100BaseTX" }, 196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 197 "LC82C115 PNIC II 10/100BaseTX" }, 198 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 199 "82c169 PNIC 10/100BaseTX" }, 200 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 201 "82c168 PNIC 10/100BaseTX" }, 202 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 203 "Accton EN1217 10/100BaseTX" }, 204 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 205 "Accton EN2242 MiniPCI 10/100BaseTX" }, 206 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 207 "Xircom X3201 10/100BaseTX" }, 208 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 209 "Neteasy DRP-32TXD Cardbus 10/100" }, 210 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 211 "Abocom FE2500 10/100BaseTX" }, 212 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 213 "Abocom FE2500MX 10/100BaseTX" }, 214 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 215 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 216 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 217 "Hawking CB102 CardBus 10/100" }, 218 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 219 "PlaneX FNW-3602-T CardBus 10/100" }, 220 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 221 "3Com OfficeConnect 10/100B" }, 222 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 223 "Microsoft MN-120 CardBus 10/100" }, 224 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 225 "Microsoft MN-130 10/100" }, 226 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 227 "Linksys PCMPC200 CardBus 10/100" }, 228 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 229 "Linksys PCMPC200 CardBus 10/100" }, 230 { 0, 0, NULL } 231 }; 232 233 static int dc_probe(device_t); 234 static int dc_attach(device_t); 235 static int dc_detach(device_t); 236 static int dc_suspend(device_t); 237 static int dc_resume(device_t); 238 static const struct dc_type *dc_devtype(device_t); 239 static int dc_newbuf(struct dc_softc *, int, int); 240 static int dc_encap(struct dc_softc *, struct mbuf **); 241 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 242 static int dc_rx_resync(struct dc_softc *); 243 static void dc_rxeof(struct dc_softc *); 244 static void dc_txeof(struct dc_softc *); 245 static void dc_tick(void *); 246 static void dc_tx_underrun(struct dc_softc *); 247 static void dc_intr(void *); 248 static void dc_start(struct ifnet *); 249 static void dc_start_locked(struct ifnet *); 250 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 251 static void dc_init(void *); 252 static void dc_init_locked(struct dc_softc *); 253 static void dc_stop(struct dc_softc *); 254 static void dc_watchdog(void *); 255 static int dc_shutdown(device_t); 256 static int dc_ifmedia_upd(struct ifnet *); 257 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 258 259 static void dc_delay(struct dc_softc *); 260 static void dc_eeprom_idle(struct dc_softc *); 261 static void dc_eeprom_putbyte(struct dc_softc *, int); 262 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 263 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 264 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 265 static void dc_eeprom_width(struct dc_softc *); 266 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 267 268 static void dc_mii_writebit(struct dc_softc *, int); 269 static int dc_mii_readbit(struct dc_softc *); 270 static void dc_mii_sync(struct dc_softc *); 271 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 272 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 273 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 274 static int dc_miibus_readreg(device_t, int, int); 275 static int dc_miibus_writereg(device_t, int, int, int); 276 static void dc_miibus_statchg(device_t); 277 static void dc_miibus_mediainit(device_t); 278 279 static void dc_setcfg(struct dc_softc *, int); 280 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 281 static uint32_t dc_mchash_be(const uint8_t *); 282 static void dc_setfilt_21143(struct dc_softc *); 283 static void dc_setfilt_asix(struct dc_softc *); 284 static void dc_setfilt_admtek(struct dc_softc *); 285 static void dc_setfilt_xircom(struct dc_softc *); 286 287 static void dc_setfilt(struct dc_softc *); 288 289 static void dc_reset(struct dc_softc *); 290 static int dc_list_rx_init(struct dc_softc *); 291 static int dc_list_tx_init(struct dc_softc *); 292 293 static void dc_read_srom(struct dc_softc *, int); 294 static void dc_parse_21143_srom(struct dc_softc *); 295 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 296 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 297 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 298 static void dc_apply_fixup(struct dc_softc *, int); 299 300 #ifdef DC_USEIOSPACE 301 #define DC_RES SYS_RES_IOPORT 302 #define DC_RID DC_PCI_CFBIO 303 #else 304 #define DC_RES SYS_RES_MEMORY 305 #define DC_RID DC_PCI_CFBMA 306 #endif 307 308 static device_method_t dc_methods[] = { 309 /* Device interface */ 310 DEVMETHOD(device_probe, dc_probe), 311 DEVMETHOD(device_attach, dc_attach), 312 DEVMETHOD(device_detach, dc_detach), 313 DEVMETHOD(device_suspend, dc_suspend), 314 DEVMETHOD(device_resume, dc_resume), 315 DEVMETHOD(device_shutdown, dc_shutdown), 316 317 /* bus interface */ 318 DEVMETHOD(bus_print_child, bus_generic_print_child), 319 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 320 321 /* MII interface */ 322 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 323 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 324 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 325 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 326 327 { 0, 0 } 328 }; 329 330 static driver_t dc_driver = { 331 "dc", 332 dc_methods, 333 sizeof(struct dc_softc) 334 }; 335 336 static devclass_t dc_devclass; 337 #ifdef __NO_STRICT_ALIGNMENT 338 static int dc_quick = 1; 339 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 340 "do not m_devget() in dc driver"); 341 #endif 342 343 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 344 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 345 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 346 347 #define DC_SETBIT(sc, reg, x) \ 348 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 349 350 #define DC_CLRBIT(sc, reg, x) \ 351 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 352 353 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 354 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 355 356 static void 357 dc_delay(struct dc_softc *sc) 358 { 359 int idx; 360 361 for (idx = (300 / 33) + 1; idx > 0; idx--) 362 CSR_READ_4(sc, DC_BUSCTL); 363 } 364 365 static void 366 dc_eeprom_width(struct dc_softc *sc) 367 { 368 int i; 369 370 /* Force EEPROM to idle state. */ 371 dc_eeprom_idle(sc); 372 373 /* Enter EEPROM access mode. */ 374 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 375 dc_delay(sc); 376 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 377 dc_delay(sc); 378 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 379 dc_delay(sc); 380 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 381 dc_delay(sc); 382 383 for (i = 3; i--;) { 384 if (6 & (1 << i)) 385 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 386 else 387 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 388 dc_delay(sc); 389 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 390 dc_delay(sc); 391 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 392 dc_delay(sc); 393 } 394 395 for (i = 1; i <= 12; i++) { 396 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 397 dc_delay(sc); 398 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 399 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 400 dc_delay(sc); 401 break; 402 } 403 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 404 dc_delay(sc); 405 } 406 407 /* Turn off EEPROM access mode. */ 408 dc_eeprom_idle(sc); 409 410 if (i < 4 || i > 12) 411 sc->dc_romwidth = 6; 412 else 413 sc->dc_romwidth = i; 414 415 /* Enter EEPROM access mode. */ 416 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 417 dc_delay(sc); 418 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 419 dc_delay(sc); 420 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 421 dc_delay(sc); 422 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 423 dc_delay(sc); 424 425 /* Turn off EEPROM access mode. */ 426 dc_eeprom_idle(sc); 427 } 428 429 static void 430 dc_eeprom_idle(struct dc_softc *sc) 431 { 432 int i; 433 434 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 435 dc_delay(sc); 436 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 437 dc_delay(sc); 438 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 439 dc_delay(sc); 440 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 441 dc_delay(sc); 442 443 for (i = 0; i < 25; i++) { 444 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 445 dc_delay(sc); 446 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 447 dc_delay(sc); 448 } 449 450 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 451 dc_delay(sc); 452 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 453 dc_delay(sc); 454 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 455 } 456 457 /* 458 * Send a read command and address to the EEPROM, check for ACK. 459 */ 460 static void 461 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 462 { 463 int d, i; 464 465 d = DC_EECMD_READ >> 6; 466 for (i = 3; i--; ) { 467 if (d & (1 << i)) 468 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 469 else 470 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 471 dc_delay(sc); 472 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 473 dc_delay(sc); 474 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 475 dc_delay(sc); 476 } 477 478 /* 479 * Feed in each bit and strobe the clock. 480 */ 481 for (i = sc->dc_romwidth; i--;) { 482 if (addr & (1 << i)) { 483 SIO_SET(DC_SIO_EE_DATAIN); 484 } else { 485 SIO_CLR(DC_SIO_EE_DATAIN); 486 } 487 dc_delay(sc); 488 SIO_SET(DC_SIO_EE_CLK); 489 dc_delay(sc); 490 SIO_CLR(DC_SIO_EE_CLK); 491 dc_delay(sc); 492 } 493 } 494 495 /* 496 * Read a word of data stored in the EEPROM at address 'addr.' 497 * The PNIC 82c168/82c169 has its own non-standard way to read 498 * the EEPROM. 499 */ 500 static void 501 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 502 { 503 int i; 504 u_int32_t r; 505 506 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 507 508 for (i = 0; i < DC_TIMEOUT; i++) { 509 DELAY(1); 510 r = CSR_READ_4(sc, DC_SIO); 511 if (!(r & DC_PN_SIOCTL_BUSY)) { 512 *dest = (u_int16_t)(r & 0xFFFF); 513 return; 514 } 515 } 516 } 517 518 /* 519 * Read a word of data stored in the EEPROM at address 'addr.' 520 * The Xircom X3201 has its own non-standard way to read 521 * the EEPROM, too. 522 */ 523 static void 524 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 525 { 526 527 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 528 529 addr *= 2; 530 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 531 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 532 addr += 1; 533 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 534 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 535 536 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 537 } 538 539 /* 540 * Read a word of data stored in the EEPROM at address 'addr.' 541 */ 542 static void 543 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 544 { 545 int i; 546 u_int16_t word = 0; 547 548 /* Force EEPROM to idle state. */ 549 dc_eeprom_idle(sc); 550 551 /* Enter EEPROM access mode. */ 552 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 553 dc_delay(sc); 554 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 555 dc_delay(sc); 556 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 557 dc_delay(sc); 558 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 559 dc_delay(sc); 560 561 /* 562 * Send address of word we want to read. 563 */ 564 dc_eeprom_putbyte(sc, addr); 565 566 /* 567 * Start reading bits from EEPROM. 568 */ 569 for (i = 0x8000; i; i >>= 1) { 570 SIO_SET(DC_SIO_EE_CLK); 571 dc_delay(sc); 572 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 573 word |= i; 574 dc_delay(sc); 575 SIO_CLR(DC_SIO_EE_CLK); 576 dc_delay(sc); 577 } 578 579 /* Turn off EEPROM access mode. */ 580 dc_eeprom_idle(sc); 581 582 *dest = word; 583 } 584 585 /* 586 * Read a sequence of words from the EEPROM. 587 */ 588 static void 589 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 590 { 591 int i; 592 u_int16_t word = 0, *ptr; 593 594 for (i = 0; i < cnt; i++) { 595 if (DC_IS_PNIC(sc)) 596 dc_eeprom_getword_pnic(sc, off + i, &word); 597 else if (DC_IS_XIRCOM(sc)) 598 dc_eeprom_getword_xircom(sc, off + i, &word); 599 else 600 dc_eeprom_getword(sc, off + i, &word); 601 ptr = (u_int16_t *)(dest + (i * 2)); 602 if (be) 603 *ptr = be16toh(word); 604 else 605 *ptr = le16toh(word); 606 } 607 } 608 609 /* 610 * The following two routines are taken from the Macronix 98713 611 * Application Notes pp.19-21. 612 */ 613 /* 614 * Write a bit to the MII bus. 615 */ 616 static void 617 dc_mii_writebit(struct dc_softc *sc, int bit) 618 { 619 620 if (bit) 621 CSR_WRITE_4(sc, DC_SIO, 622 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 623 else 624 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 625 626 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 627 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 628 } 629 630 /* 631 * Read a bit from the MII bus. 632 */ 633 static int 634 dc_mii_readbit(struct dc_softc *sc) 635 { 636 637 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 638 CSR_READ_4(sc, DC_SIO); 639 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 640 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 641 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 642 return (1); 643 644 return (0); 645 } 646 647 /* 648 * Sync the PHYs by setting data bit and strobing the clock 32 times. 649 */ 650 static void 651 dc_mii_sync(struct dc_softc *sc) 652 { 653 int i; 654 655 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 656 657 for (i = 0; i < 32; i++) 658 dc_mii_writebit(sc, 1); 659 } 660 661 /* 662 * Clock a series of bits through the MII. 663 */ 664 static void 665 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 666 { 667 int i; 668 669 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 670 dc_mii_writebit(sc, bits & i); 671 } 672 673 /* 674 * Read an PHY register through the MII. 675 */ 676 static int 677 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 678 { 679 int i, ack; 680 681 /* 682 * Set up frame for RX. 683 */ 684 frame->mii_stdelim = DC_MII_STARTDELIM; 685 frame->mii_opcode = DC_MII_READOP; 686 frame->mii_turnaround = 0; 687 frame->mii_data = 0; 688 689 /* 690 * Sync the PHYs. 691 */ 692 dc_mii_sync(sc); 693 694 /* 695 * Send command/address info. 696 */ 697 dc_mii_send(sc, frame->mii_stdelim, 2); 698 dc_mii_send(sc, frame->mii_opcode, 2); 699 dc_mii_send(sc, frame->mii_phyaddr, 5); 700 dc_mii_send(sc, frame->mii_regaddr, 5); 701 702 #ifdef notdef 703 /* Idle bit */ 704 dc_mii_writebit(sc, 1); 705 dc_mii_writebit(sc, 0); 706 #endif 707 708 /* Check for ack. */ 709 ack = dc_mii_readbit(sc); 710 711 /* 712 * Now try reading data bits. If the ack failed, we still 713 * need to clock through 16 cycles to keep the PHY(s) in sync. 714 */ 715 if (ack) { 716 for (i = 0; i < 16; i++) 717 dc_mii_readbit(sc); 718 goto fail; 719 } 720 721 for (i = 0x8000; i; i >>= 1) { 722 if (!ack) { 723 if (dc_mii_readbit(sc)) 724 frame->mii_data |= i; 725 } 726 } 727 728 fail: 729 730 dc_mii_writebit(sc, 0); 731 dc_mii_writebit(sc, 0); 732 733 if (ack) 734 return (1); 735 return (0); 736 } 737 738 /* 739 * Write to a PHY register through the MII. 740 */ 741 static int 742 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 743 { 744 745 /* 746 * Set up frame for TX. 747 */ 748 749 frame->mii_stdelim = DC_MII_STARTDELIM; 750 frame->mii_opcode = DC_MII_WRITEOP; 751 frame->mii_turnaround = DC_MII_TURNAROUND; 752 753 /* 754 * Sync the PHYs. 755 */ 756 dc_mii_sync(sc); 757 758 dc_mii_send(sc, frame->mii_stdelim, 2); 759 dc_mii_send(sc, frame->mii_opcode, 2); 760 dc_mii_send(sc, frame->mii_phyaddr, 5); 761 dc_mii_send(sc, frame->mii_regaddr, 5); 762 dc_mii_send(sc, frame->mii_turnaround, 2); 763 dc_mii_send(sc, frame->mii_data, 16); 764 765 /* Idle bit. */ 766 dc_mii_writebit(sc, 0); 767 dc_mii_writebit(sc, 0); 768 769 return (0); 770 } 771 772 static int 773 dc_miibus_readreg(device_t dev, int phy, int reg) 774 { 775 struct dc_mii_frame frame; 776 struct dc_softc *sc; 777 int i, rval, phy_reg = 0; 778 779 sc = device_get_softc(dev); 780 bzero(&frame, sizeof(frame)); 781 782 /* 783 * Note: both the AL981 and AN985 have internal PHYs, 784 * however the AL981 provides direct access to the PHY 785 * registers while the AN985 uses a serial MII interface. 786 * The AN985's MII interface is also buggy in that you 787 * can read from any MII address (0 to 31), but only address 1 788 * behaves normally. To deal with both cases, we pretend 789 * that the PHY is at MII address 1. 790 */ 791 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 792 return (0); 793 794 /* 795 * Note: the ukphy probes of the RS7112 report a PHY at 796 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 797 * so we only respond to correct one. 798 */ 799 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 800 return (0); 801 802 if (sc->dc_pmode != DC_PMODE_MII) { 803 if (phy == (MII_NPHY - 1)) { 804 switch (reg) { 805 case MII_BMSR: 806 /* 807 * Fake something to make the probe 808 * code think there's a PHY here. 809 */ 810 return (BMSR_MEDIAMASK); 811 break; 812 case MII_PHYIDR1: 813 if (DC_IS_PNIC(sc)) 814 return (DC_VENDORID_LO); 815 return (DC_VENDORID_DEC); 816 break; 817 case MII_PHYIDR2: 818 if (DC_IS_PNIC(sc)) 819 return (DC_DEVICEID_82C168); 820 return (DC_DEVICEID_21143); 821 break; 822 default: 823 return (0); 824 break; 825 } 826 } else 827 return (0); 828 } 829 830 if (DC_IS_PNIC(sc)) { 831 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 832 (phy << 23) | (reg << 18)); 833 for (i = 0; i < DC_TIMEOUT; i++) { 834 DELAY(1); 835 rval = CSR_READ_4(sc, DC_PN_MII); 836 if (!(rval & DC_PN_MII_BUSY)) { 837 rval &= 0xFFFF; 838 return (rval == 0xFFFF ? 0 : rval); 839 } 840 } 841 return (0); 842 } 843 844 if (DC_IS_COMET(sc)) { 845 switch (reg) { 846 case MII_BMCR: 847 phy_reg = DC_AL_BMCR; 848 break; 849 case MII_BMSR: 850 phy_reg = DC_AL_BMSR; 851 break; 852 case MII_PHYIDR1: 853 phy_reg = DC_AL_VENID; 854 break; 855 case MII_PHYIDR2: 856 phy_reg = DC_AL_DEVID; 857 break; 858 case MII_ANAR: 859 phy_reg = DC_AL_ANAR; 860 break; 861 case MII_ANLPAR: 862 phy_reg = DC_AL_LPAR; 863 break; 864 case MII_ANER: 865 phy_reg = DC_AL_ANER; 866 break; 867 default: 868 device_printf(dev, "phy_read: bad phy register %x\n", 869 reg); 870 return (0); 871 break; 872 } 873 874 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 875 876 if (rval == 0xFFFF) 877 return (0); 878 return (rval); 879 } 880 881 frame.mii_phyaddr = phy; 882 frame.mii_regaddr = reg; 883 if (sc->dc_type == DC_TYPE_98713) { 884 phy_reg = CSR_READ_4(sc, DC_NETCFG); 885 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 886 } 887 dc_mii_readreg(sc, &frame); 888 if (sc->dc_type == DC_TYPE_98713) 889 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 890 891 return (frame.mii_data); 892 } 893 894 static int 895 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 896 { 897 struct dc_softc *sc; 898 struct dc_mii_frame frame; 899 int i, phy_reg = 0; 900 901 sc = device_get_softc(dev); 902 bzero(&frame, sizeof(frame)); 903 904 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 905 return (0); 906 907 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 908 return (0); 909 910 if (DC_IS_PNIC(sc)) { 911 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 912 (phy << 23) | (reg << 10) | data); 913 for (i = 0; i < DC_TIMEOUT; i++) { 914 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 915 break; 916 } 917 return (0); 918 } 919 920 if (DC_IS_COMET(sc)) { 921 switch (reg) { 922 case MII_BMCR: 923 phy_reg = DC_AL_BMCR; 924 break; 925 case MII_BMSR: 926 phy_reg = DC_AL_BMSR; 927 break; 928 case MII_PHYIDR1: 929 phy_reg = DC_AL_VENID; 930 break; 931 case MII_PHYIDR2: 932 phy_reg = DC_AL_DEVID; 933 break; 934 case MII_ANAR: 935 phy_reg = DC_AL_ANAR; 936 break; 937 case MII_ANLPAR: 938 phy_reg = DC_AL_LPAR; 939 break; 940 case MII_ANER: 941 phy_reg = DC_AL_ANER; 942 break; 943 default: 944 device_printf(dev, "phy_write: bad phy register %x\n", 945 reg); 946 return (0); 947 break; 948 } 949 950 CSR_WRITE_4(sc, phy_reg, data); 951 return (0); 952 } 953 954 frame.mii_phyaddr = phy; 955 frame.mii_regaddr = reg; 956 frame.mii_data = data; 957 958 if (sc->dc_type == DC_TYPE_98713) { 959 phy_reg = CSR_READ_4(sc, DC_NETCFG); 960 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 961 } 962 dc_mii_writereg(sc, &frame); 963 if (sc->dc_type == DC_TYPE_98713) 964 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 965 966 return (0); 967 } 968 969 static void 970 dc_miibus_statchg(device_t dev) 971 { 972 struct dc_softc *sc; 973 struct mii_data *mii; 974 struct ifmedia *ifm; 975 976 sc = device_get_softc(dev); 977 if (DC_IS_ADMTEK(sc)) 978 return; 979 980 mii = device_get_softc(sc->dc_miibus); 981 ifm = &mii->mii_media; 982 if (DC_IS_DAVICOM(sc) && 983 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 984 dc_setcfg(sc, ifm->ifm_media); 985 sc->dc_if_media = ifm->ifm_media; 986 } else { 987 dc_setcfg(sc, mii->mii_media_active); 988 sc->dc_if_media = mii->mii_media_active; 989 } 990 } 991 992 /* 993 * Special support for DM9102A cards with HomePNA PHYs. Note: 994 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 995 * to be impossible to talk to the management interface of the DM9801 996 * PHY (its MDIO pin is not connected to anything). Consequently, 997 * the driver has to just 'know' about the additional mode and deal 998 * with it itself. *sigh* 999 */ 1000 static void 1001 dc_miibus_mediainit(device_t dev) 1002 { 1003 struct dc_softc *sc; 1004 struct mii_data *mii; 1005 struct ifmedia *ifm; 1006 int rev; 1007 1008 rev = pci_get_revid(dev); 1009 1010 sc = device_get_softc(dev); 1011 mii = device_get_softc(sc->dc_miibus); 1012 ifm = &mii->mii_media; 1013 1014 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1015 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1016 } 1017 1018 #define DC_BITS_512 9 1019 #define DC_BITS_128 7 1020 #define DC_BITS_64 6 1021 1022 static uint32_t 1023 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1024 { 1025 uint32_t crc; 1026 1027 /* Compute CRC for the address value. */ 1028 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1029 1030 /* 1031 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1032 * chips is only 128 bits wide. 1033 */ 1034 if (sc->dc_flags & DC_128BIT_HASH) 1035 return (crc & ((1 << DC_BITS_128) - 1)); 1036 1037 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1038 if (sc->dc_flags & DC_64BIT_HASH) 1039 return (crc & ((1 << DC_BITS_64) - 1)); 1040 1041 /* Xircom's hash filtering table is different (read: weird) */ 1042 /* Xircom uses the LEAST significant bits */ 1043 if (DC_IS_XIRCOM(sc)) { 1044 if ((crc & 0x180) == 0x180) 1045 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1046 else 1047 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1048 (12 << 4)); 1049 } 1050 1051 return (crc & ((1 << DC_BITS_512) - 1)); 1052 } 1053 1054 /* 1055 * Calculate CRC of a multicast group address, return the lower 6 bits. 1056 */ 1057 static uint32_t 1058 dc_mchash_be(const uint8_t *addr) 1059 { 1060 uint32_t crc; 1061 1062 /* Compute CRC for the address value. */ 1063 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1064 1065 /* Return the filter bit position. */ 1066 return ((crc >> 26) & 0x0000003F); 1067 } 1068 1069 /* 1070 * 21143-style RX filter setup routine. Filter programming is done by 1071 * downloading a special setup frame into the TX engine. 21143, Macronix, 1072 * PNIC, PNIC II and Davicom chips are programmed this way. 1073 * 1074 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1075 * address (our node address) and a 512-bit hash filter for multicast 1076 * frames. We also sneak the broadcast address into the hash filter since 1077 * we need that too. 1078 */ 1079 static void 1080 dc_setfilt_21143(struct dc_softc *sc) 1081 { 1082 struct dc_desc *sframe; 1083 u_int32_t h, *sp; 1084 struct ifmultiaddr *ifma; 1085 struct ifnet *ifp; 1086 int i; 1087 1088 ifp = sc->dc_ifp; 1089 1090 i = sc->dc_cdata.dc_tx_prod; 1091 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1092 sc->dc_cdata.dc_tx_cnt++; 1093 sframe = &sc->dc_ldata->dc_tx_list[i]; 1094 sp = sc->dc_cdata.dc_sbuf; 1095 bzero(sp, DC_SFRAME_LEN); 1096 1097 sframe->dc_data = htole32(sc->dc_saddr); 1098 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1099 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1100 1101 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1102 1103 /* If we want promiscuous mode, set the allframes bit. */ 1104 if (ifp->if_flags & IFF_PROMISC) 1105 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1106 else 1107 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1108 1109 if (ifp->if_flags & IFF_ALLMULTI) 1110 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1111 else 1112 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1113 1114 IF_ADDR_LOCK(ifp); 1115 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1116 if (ifma->ifma_addr->sa_family != AF_LINK) 1117 continue; 1118 h = dc_mchash_le(sc, 1119 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1120 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1121 } 1122 IF_ADDR_UNLOCK(ifp); 1123 1124 if (ifp->if_flags & IFF_BROADCAST) { 1125 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1126 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1127 } 1128 1129 /* Set our MAC address */ 1130 sp[39] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]); 1131 sp[40] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]); 1132 sp[41] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]); 1133 1134 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1135 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1136 1137 /* 1138 * The PNIC takes an exceedingly long time to process its 1139 * setup frame; wait 10ms after posting the setup frame 1140 * before proceeding, just so it has time to swallow its 1141 * medicine. 1142 */ 1143 DELAY(10000); 1144 1145 sc->dc_wdog_timer = 5; 1146 } 1147 1148 static void 1149 dc_setfilt_admtek(struct dc_softc *sc) 1150 { 1151 uint8_t eaddr[ETHER_ADDR_LEN]; 1152 struct ifnet *ifp; 1153 struct ifmultiaddr *ifma; 1154 int h = 0; 1155 u_int32_t hashes[2] = { 0, 0 }; 1156 1157 ifp = sc->dc_ifp; 1158 1159 /* Init our MAC address. */ 1160 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1161 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1162 eaddr[1] << 8 | eaddr[0]); 1163 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1164 1165 /* If we want promiscuous mode, set the allframes bit. */ 1166 if (ifp->if_flags & IFF_PROMISC) 1167 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1168 else 1169 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1170 1171 if (ifp->if_flags & IFF_ALLMULTI) 1172 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1173 else 1174 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1175 1176 /* First, zot all the existing hash bits. */ 1177 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1178 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1179 1180 /* 1181 * If we're already in promisc or allmulti mode, we 1182 * don't have to bother programming the multicast filter. 1183 */ 1184 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1185 return; 1186 1187 /* Now program new ones. */ 1188 IF_ADDR_LOCK(ifp); 1189 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1190 if (ifma->ifma_addr->sa_family != AF_LINK) 1191 continue; 1192 if (DC_IS_CENTAUR(sc)) 1193 h = dc_mchash_le(sc, 1194 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1195 else 1196 h = dc_mchash_be( 1197 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1198 if (h < 32) 1199 hashes[0] |= (1 << h); 1200 else 1201 hashes[1] |= (1 << (h - 32)); 1202 } 1203 IF_ADDR_UNLOCK(ifp); 1204 1205 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1206 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1207 } 1208 1209 static void 1210 dc_setfilt_asix(struct dc_softc *sc) 1211 { 1212 struct ifnet *ifp; 1213 struct ifmultiaddr *ifma; 1214 int h = 0; 1215 u_int32_t hashes[2] = { 0, 0 }; 1216 1217 ifp = sc->dc_ifp; 1218 1219 /* Init our MAC address */ 1220 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1221 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1222 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[0])); 1223 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1224 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1225 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[4])); 1226 1227 /* If we want promiscuous mode, set the allframes bit. */ 1228 if (ifp->if_flags & IFF_PROMISC) 1229 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1230 else 1231 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1232 1233 if (ifp->if_flags & IFF_ALLMULTI) 1234 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1235 else 1236 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1237 1238 /* 1239 * The ASIX chip has a special bit to enable reception 1240 * of broadcast frames. 1241 */ 1242 if (ifp->if_flags & IFF_BROADCAST) 1243 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1244 else 1245 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1246 1247 /* first, zot all the existing hash bits */ 1248 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1249 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1250 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1251 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1252 1253 /* 1254 * If we're already in promisc or allmulti mode, we 1255 * don't have to bother programming the multicast filter. 1256 */ 1257 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1258 return; 1259 1260 /* now program new ones */ 1261 IF_ADDR_LOCK(ifp); 1262 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1263 if (ifma->ifma_addr->sa_family != AF_LINK) 1264 continue; 1265 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1266 if (h < 32) 1267 hashes[0] |= (1 << h); 1268 else 1269 hashes[1] |= (1 << (h - 32)); 1270 } 1271 IF_ADDR_UNLOCK(ifp); 1272 1273 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1274 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1275 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1276 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1277 } 1278 1279 static void 1280 dc_setfilt_xircom(struct dc_softc *sc) 1281 { 1282 struct ifnet *ifp; 1283 struct ifmultiaddr *ifma; 1284 struct dc_desc *sframe; 1285 u_int32_t h, *sp; 1286 int i; 1287 1288 ifp = sc->dc_ifp; 1289 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1290 1291 i = sc->dc_cdata.dc_tx_prod; 1292 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1293 sc->dc_cdata.dc_tx_cnt++; 1294 sframe = &sc->dc_ldata->dc_tx_list[i]; 1295 sp = sc->dc_cdata.dc_sbuf; 1296 bzero(sp, DC_SFRAME_LEN); 1297 1298 sframe->dc_data = htole32(sc->dc_saddr); 1299 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1300 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1301 1302 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1303 1304 /* If we want promiscuous mode, set the allframes bit. */ 1305 if (ifp->if_flags & IFF_PROMISC) 1306 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1307 else 1308 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1309 1310 if (ifp->if_flags & IFF_ALLMULTI) 1311 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1312 else 1313 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1314 1315 IF_ADDR_LOCK(ifp); 1316 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1317 if (ifma->ifma_addr->sa_family != AF_LINK) 1318 continue; 1319 h = dc_mchash_le(sc, 1320 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1321 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1322 } 1323 IF_ADDR_UNLOCK(ifp); 1324 1325 if (ifp->if_flags & IFF_BROADCAST) { 1326 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1327 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1328 } 1329 1330 /* Set our MAC address */ 1331 sp[0] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]); 1332 sp[1] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]); 1333 sp[2] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]); 1334 1335 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1336 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1337 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1338 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1339 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1340 1341 /* 1342 * Wait some time... 1343 */ 1344 DELAY(1000); 1345 1346 sc->dc_wdog_timer = 5; 1347 } 1348 1349 static void 1350 dc_setfilt(struct dc_softc *sc) 1351 { 1352 1353 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1354 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1355 dc_setfilt_21143(sc); 1356 1357 if (DC_IS_ASIX(sc)) 1358 dc_setfilt_asix(sc); 1359 1360 if (DC_IS_ADMTEK(sc)) 1361 dc_setfilt_admtek(sc); 1362 1363 if (DC_IS_XIRCOM(sc)) 1364 dc_setfilt_xircom(sc); 1365 } 1366 1367 /* 1368 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1369 * the netconfig register, we first have to put the transmit and/or 1370 * receive logic in the idle state. 1371 */ 1372 static void 1373 dc_setcfg(struct dc_softc *sc, int media) 1374 { 1375 int i, restart = 0, watchdogreg; 1376 u_int32_t isr; 1377 1378 if (IFM_SUBTYPE(media) == IFM_NONE) 1379 return; 1380 1381 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1382 restart = 1; 1383 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1384 1385 for (i = 0; i < DC_TIMEOUT; i++) { 1386 isr = CSR_READ_4(sc, DC_ISR); 1387 if (isr & DC_ISR_TX_IDLE && 1388 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1389 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1390 break; 1391 DELAY(10); 1392 } 1393 1394 if (i == DC_TIMEOUT) { 1395 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1396 device_printf(sc->dc_dev, 1397 "%s: failed to force tx to idle state\n", 1398 __func__); 1399 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1400 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1401 !DC_HAS_BROKEN_RXSTATE(sc)) 1402 device_printf(sc->dc_dev, 1403 "%s: failed to force rx to idle state\n", 1404 __func__); 1405 } 1406 } 1407 1408 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1409 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1410 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1411 if (sc->dc_pmode == DC_PMODE_MII) { 1412 if (DC_IS_INTEL(sc)) { 1413 /* There's a write enable bit here that reads as 1. */ 1414 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1415 watchdogreg &= ~DC_WDOG_CTLWREN; 1416 watchdogreg |= DC_WDOG_JABBERDIS; 1417 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1418 } else { 1419 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1420 } 1421 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1422 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1423 if (sc->dc_type == DC_TYPE_98713) 1424 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1425 DC_NETCFG_SCRAMBLER)); 1426 if (!DC_IS_DAVICOM(sc)) 1427 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1428 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1429 if (DC_IS_INTEL(sc)) 1430 dc_apply_fixup(sc, IFM_AUTO); 1431 } else { 1432 if (DC_IS_PNIC(sc)) { 1433 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1434 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1435 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1436 } 1437 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1438 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1439 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1440 if (DC_IS_INTEL(sc)) 1441 dc_apply_fixup(sc, 1442 (media & IFM_GMASK) == IFM_FDX ? 1443 IFM_100_TX | IFM_FDX : IFM_100_TX); 1444 } 1445 } 1446 1447 if (IFM_SUBTYPE(media) == IFM_10_T) { 1448 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1449 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1450 if (sc->dc_pmode == DC_PMODE_MII) { 1451 /* There's a write enable bit here that reads as 1. */ 1452 if (DC_IS_INTEL(sc)) { 1453 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1454 watchdogreg &= ~DC_WDOG_CTLWREN; 1455 watchdogreg |= DC_WDOG_JABBERDIS; 1456 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1457 } else { 1458 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1459 } 1460 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1461 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1462 if (sc->dc_type == DC_TYPE_98713) 1463 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1464 if (!DC_IS_DAVICOM(sc)) 1465 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1466 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1467 if (DC_IS_INTEL(sc)) 1468 dc_apply_fixup(sc, IFM_AUTO); 1469 } else { 1470 if (DC_IS_PNIC(sc)) { 1471 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1472 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1473 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1474 } 1475 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1476 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1477 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1478 if (DC_IS_INTEL(sc)) { 1479 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1480 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1481 if ((media & IFM_GMASK) == IFM_FDX) 1482 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1483 else 1484 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1485 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1486 DC_CLRBIT(sc, DC_10BTCTRL, 1487 DC_TCTL_AUTONEGENBL); 1488 dc_apply_fixup(sc, 1489 (media & IFM_GMASK) == IFM_FDX ? 1490 IFM_10_T | IFM_FDX : IFM_10_T); 1491 DELAY(20000); 1492 } 1493 } 1494 } 1495 1496 /* 1497 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1498 * PHY and we want HomePNA mode, set the portsel bit to turn 1499 * on the external MII port. 1500 */ 1501 if (DC_IS_DAVICOM(sc)) { 1502 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1503 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1504 sc->dc_link = 1; 1505 } else { 1506 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1507 } 1508 } 1509 1510 if ((media & IFM_GMASK) == IFM_FDX) { 1511 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1512 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1513 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1514 } else { 1515 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1516 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1517 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1518 } 1519 1520 if (restart) 1521 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1522 } 1523 1524 static void 1525 dc_reset(struct dc_softc *sc) 1526 { 1527 int i; 1528 1529 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1530 1531 for (i = 0; i < DC_TIMEOUT; i++) { 1532 DELAY(10); 1533 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1534 break; 1535 } 1536 1537 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1538 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1539 DELAY(10000); 1540 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1541 i = 0; 1542 } 1543 1544 if (i == DC_TIMEOUT) 1545 device_printf(sc->dc_dev, "reset never completed!\n"); 1546 1547 /* Wait a little while for the chip to get its brains in order. */ 1548 DELAY(1000); 1549 1550 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1551 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1552 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1553 1554 /* 1555 * Bring the SIA out of reset. In some cases, it looks 1556 * like failing to unreset the SIA soon enough gets it 1557 * into a state where it will never come out of reset 1558 * until we reset the whole chip again. 1559 */ 1560 if (DC_IS_INTEL(sc)) { 1561 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1562 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1563 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1564 } 1565 } 1566 1567 static const struct dc_type * 1568 dc_devtype(device_t dev) 1569 { 1570 const struct dc_type *t; 1571 u_int32_t devid; 1572 u_int8_t rev; 1573 1574 t = dc_devs; 1575 devid = pci_get_devid(dev); 1576 rev = pci_get_revid(dev); 1577 1578 while (t->dc_name != NULL) { 1579 if (devid == t->dc_devid && rev >= t->dc_minrev) 1580 return (t); 1581 t++; 1582 } 1583 1584 return (NULL); 1585 } 1586 1587 /* 1588 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1589 * IDs against our list and return a device name if we find a match. 1590 * We do a little bit of extra work to identify the exact type of 1591 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1592 * but different revision IDs. The same is true for 98715/98715A 1593 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1594 * cases, the exact chip revision affects driver behavior. 1595 */ 1596 static int 1597 dc_probe(device_t dev) 1598 { 1599 const struct dc_type *t; 1600 1601 t = dc_devtype(dev); 1602 1603 if (t != NULL) { 1604 device_set_desc(dev, t->dc_name); 1605 return (BUS_PROBE_DEFAULT); 1606 } 1607 1608 return (ENXIO); 1609 } 1610 1611 static void 1612 dc_apply_fixup(struct dc_softc *sc, int media) 1613 { 1614 struct dc_mediainfo *m; 1615 u_int8_t *p; 1616 int i; 1617 u_int32_t reg; 1618 1619 m = sc->dc_mi; 1620 1621 while (m != NULL) { 1622 if (m->dc_media == media) 1623 break; 1624 m = m->dc_next; 1625 } 1626 1627 if (m == NULL) 1628 return; 1629 1630 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1631 reg = (p[0] | (p[1] << 8)) << 16; 1632 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1633 } 1634 1635 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1636 reg = (p[0] | (p[1] << 8)) << 16; 1637 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1638 } 1639 } 1640 1641 static void 1642 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1643 { 1644 struct dc_mediainfo *m; 1645 1646 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1647 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1648 case DC_SIA_CODE_10BT: 1649 m->dc_media = IFM_10_T; 1650 break; 1651 case DC_SIA_CODE_10BT_FDX: 1652 m->dc_media = IFM_10_T | IFM_FDX; 1653 break; 1654 case DC_SIA_CODE_10B2: 1655 m->dc_media = IFM_10_2; 1656 break; 1657 case DC_SIA_CODE_10B5: 1658 m->dc_media = IFM_10_5; 1659 break; 1660 default: 1661 break; 1662 } 1663 1664 /* 1665 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1666 * Things apparently already work for cards that do 1667 * supply Media Specific Data. 1668 */ 1669 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1670 m->dc_gp_len = 2; 1671 m->dc_gp_ptr = 1672 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1673 } else { 1674 m->dc_gp_len = 2; 1675 m->dc_gp_ptr = 1676 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1677 } 1678 1679 m->dc_next = sc->dc_mi; 1680 sc->dc_mi = m; 1681 1682 sc->dc_pmode = DC_PMODE_SIA; 1683 } 1684 1685 static void 1686 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1687 { 1688 struct dc_mediainfo *m; 1689 1690 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1691 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1692 m->dc_media = IFM_100_TX; 1693 1694 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1695 m->dc_media = IFM_100_TX | IFM_FDX; 1696 1697 m->dc_gp_len = 2; 1698 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1699 1700 m->dc_next = sc->dc_mi; 1701 sc->dc_mi = m; 1702 1703 sc->dc_pmode = DC_PMODE_SYM; 1704 } 1705 1706 static void 1707 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1708 { 1709 struct dc_mediainfo *m; 1710 u_int8_t *p; 1711 1712 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1713 /* We abuse IFM_AUTO to represent MII. */ 1714 m->dc_media = IFM_AUTO; 1715 m->dc_gp_len = l->dc_gpr_len; 1716 1717 p = (u_int8_t *)l; 1718 p += sizeof(struct dc_eblock_mii); 1719 m->dc_gp_ptr = p; 1720 p += 2 * l->dc_gpr_len; 1721 m->dc_reset_len = *p; 1722 p++; 1723 m->dc_reset_ptr = p; 1724 1725 m->dc_next = sc->dc_mi; 1726 sc->dc_mi = m; 1727 } 1728 1729 static void 1730 dc_read_srom(struct dc_softc *sc, int bits) 1731 { 1732 int size; 1733 1734 size = 2 << bits; 1735 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1736 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1737 } 1738 1739 static void 1740 dc_parse_21143_srom(struct dc_softc *sc) 1741 { 1742 struct dc_leaf_hdr *lhdr; 1743 struct dc_eblock_hdr *hdr; 1744 int have_mii, i, loff; 1745 char *ptr; 1746 1747 have_mii = 0; 1748 loff = sc->dc_srom[27]; 1749 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1750 1751 ptr = (char *)lhdr; 1752 ptr += sizeof(struct dc_leaf_hdr) - 1; 1753 /* 1754 * Look if we got a MII media block. 1755 */ 1756 for (i = 0; i < lhdr->dc_mcnt; i++) { 1757 hdr = (struct dc_eblock_hdr *)ptr; 1758 if (hdr->dc_type == DC_EBLOCK_MII) 1759 have_mii++; 1760 1761 ptr += (hdr->dc_len & 0x7F); 1762 ptr++; 1763 } 1764 1765 /* 1766 * Do the same thing again. Only use SIA and SYM media 1767 * blocks if no MII media block is available. 1768 */ 1769 ptr = (char *)lhdr; 1770 ptr += sizeof(struct dc_leaf_hdr) - 1; 1771 for (i = 0; i < lhdr->dc_mcnt; i++) { 1772 hdr = (struct dc_eblock_hdr *)ptr; 1773 switch (hdr->dc_type) { 1774 case DC_EBLOCK_MII: 1775 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1776 break; 1777 case DC_EBLOCK_SIA: 1778 if (! have_mii) 1779 dc_decode_leaf_sia(sc, 1780 (struct dc_eblock_sia *)hdr); 1781 break; 1782 case DC_EBLOCK_SYM: 1783 if (! have_mii) 1784 dc_decode_leaf_sym(sc, 1785 (struct dc_eblock_sym *)hdr); 1786 break; 1787 default: 1788 /* Don't care. Yet. */ 1789 break; 1790 } 1791 ptr += (hdr->dc_len & 0x7F); 1792 ptr++; 1793 } 1794 } 1795 1796 static void 1797 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1798 { 1799 u_int32_t *paddr; 1800 1801 KASSERT(nseg == 1, 1802 ("%s: wrong number of segments (%d)", __func__, nseg)); 1803 paddr = arg; 1804 *paddr = segs->ds_addr; 1805 } 1806 1807 /* 1808 * Attach the interface. Allocate softc structures, do ifmedia 1809 * setup and ethernet/BPF attach. 1810 */ 1811 static int 1812 dc_attach(device_t dev) 1813 { 1814 int tmp = 0; 1815 u_char eaddr[ETHER_ADDR_LEN]; 1816 u_int32_t command; 1817 struct dc_softc *sc; 1818 struct ifnet *ifp; 1819 u_int32_t reg, revision; 1820 int error = 0, rid, mac_offset; 1821 int i; 1822 u_int8_t *mac; 1823 1824 sc = device_get_softc(dev); 1825 sc->dc_dev = dev; 1826 1827 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1828 MTX_DEF); 1829 1830 /* 1831 * Map control/status registers. 1832 */ 1833 pci_enable_busmaster(dev); 1834 1835 rid = DC_RID; 1836 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1837 1838 if (sc->dc_res == NULL) { 1839 device_printf(dev, "couldn't map ports/memory\n"); 1840 error = ENXIO; 1841 goto fail; 1842 } 1843 1844 sc->dc_btag = rman_get_bustag(sc->dc_res); 1845 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1846 1847 /* Allocate interrupt. */ 1848 rid = 0; 1849 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1850 RF_SHAREABLE | RF_ACTIVE); 1851 1852 if (sc->dc_irq == NULL) { 1853 device_printf(dev, "couldn't map interrupt\n"); 1854 error = ENXIO; 1855 goto fail; 1856 } 1857 1858 /* Need this info to decide on a chip type. */ 1859 sc->dc_info = dc_devtype(dev); 1860 revision = pci_get_revid(dev); 1861 1862 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1863 if (sc->dc_info->dc_devid != 1864 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 1865 sc->dc_info->dc_devid != 1866 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 1867 dc_eeprom_width(sc); 1868 1869 switch (sc->dc_info->dc_devid) { 1870 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 1871 sc->dc_type = DC_TYPE_21143; 1872 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1873 sc->dc_flags |= DC_REDUCED_MII_POLL; 1874 /* Save EEPROM contents so we can parse them later. */ 1875 dc_read_srom(sc, sc->dc_romwidth); 1876 break; 1877 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 1878 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 1879 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 1880 sc->dc_type = DC_TYPE_DM9102; 1881 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1882 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1883 sc->dc_flags |= DC_TX_ALIGN; 1884 sc->dc_pmode = DC_PMODE_MII; 1885 1886 /* Increase the latency timer value. */ 1887 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 1888 break; 1889 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 1890 sc->dc_type = DC_TYPE_AL981; 1891 sc->dc_flags |= DC_TX_USE_TX_INTR; 1892 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1893 sc->dc_pmode = DC_PMODE_MII; 1894 dc_read_srom(sc, sc->dc_romwidth); 1895 break; 1896 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 1897 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 1898 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 1899 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 1900 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511): 1901 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 1902 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 1903 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 1904 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 1905 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 1906 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 1907 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 1908 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 1909 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 1910 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 1911 sc->dc_type = DC_TYPE_AN985; 1912 sc->dc_flags |= DC_64BIT_HASH; 1913 sc->dc_flags |= DC_TX_USE_TX_INTR; 1914 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1915 sc->dc_pmode = DC_PMODE_MII; 1916 /* Don't read SROM for - auto-loaded on reset */ 1917 break; 1918 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 1919 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 1920 if (revision < DC_REVISION_98713A) { 1921 sc->dc_type = DC_TYPE_98713; 1922 } 1923 if (revision >= DC_REVISION_98713A) { 1924 sc->dc_type = DC_TYPE_98713A; 1925 sc->dc_flags |= DC_21143_NWAY; 1926 } 1927 sc->dc_flags |= DC_REDUCED_MII_POLL; 1928 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1929 break; 1930 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 1931 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 1932 /* 1933 * Macronix MX98715AEC-C/D/E parts have only a 1934 * 128-bit hash table. We need to deal with these 1935 * in the same manner as the PNIC II so that we 1936 * get the right number of bits out of the 1937 * CRC routine. 1938 */ 1939 if (revision >= DC_REVISION_98715AEC_C && 1940 revision < DC_REVISION_98725) 1941 sc->dc_flags |= DC_128BIT_HASH; 1942 sc->dc_type = DC_TYPE_987x5; 1943 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1944 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1945 break; 1946 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 1947 sc->dc_type = DC_TYPE_987x5; 1948 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1949 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1950 break; 1951 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 1952 sc->dc_type = DC_TYPE_PNICII; 1953 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1954 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1955 break; 1956 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 1957 sc->dc_type = DC_TYPE_PNIC; 1958 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1959 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1960 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1961 if (revision < DC_REVISION_82C169) 1962 sc->dc_pmode = DC_PMODE_SYM; 1963 break; 1964 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 1965 sc->dc_type = DC_TYPE_ASIX; 1966 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1967 sc->dc_flags |= DC_REDUCED_MII_POLL; 1968 sc->dc_pmode = DC_PMODE_MII; 1969 break; 1970 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 1971 sc->dc_type = DC_TYPE_XIRCOM; 1972 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1973 DC_TX_ALIGN; 1974 /* 1975 * We don't actually need to coalesce, but we're doing 1976 * it to obtain a double word aligned buffer. 1977 * The DC_TX_COALESCE flag is required. 1978 */ 1979 sc->dc_pmode = DC_PMODE_MII; 1980 break; 1981 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 1982 sc->dc_type = DC_TYPE_CONEXANT; 1983 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1984 sc->dc_flags |= DC_REDUCED_MII_POLL; 1985 sc->dc_pmode = DC_PMODE_MII; 1986 dc_read_srom(sc, sc->dc_romwidth); 1987 break; 1988 default: 1989 device_printf(dev, "unknown device: %x\n", 1990 sc->dc_info->dc_devid); 1991 break; 1992 } 1993 1994 /* Save the cache line size. */ 1995 if (DC_IS_DAVICOM(sc)) 1996 sc->dc_cachesize = 0; 1997 else 1998 sc->dc_cachesize = pci_get_cachelnsz(dev); 1999 2000 /* Reset the adapter. */ 2001 dc_reset(sc); 2002 2003 /* Take 21143 out of snooze mode */ 2004 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2005 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2006 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2007 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2008 } 2009 2010 /* 2011 * Try to learn something about the supported media. 2012 * We know that ASIX and ADMtek and Davicom devices 2013 * will *always* be using MII media, so that's a no-brainer. 2014 * The tricky ones are the Macronix/PNIC II and the 2015 * Intel 21143. 2016 */ 2017 if (DC_IS_INTEL(sc)) 2018 dc_parse_21143_srom(sc); 2019 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2020 if (sc->dc_type == DC_TYPE_98713) 2021 sc->dc_pmode = DC_PMODE_MII; 2022 else 2023 sc->dc_pmode = DC_PMODE_SYM; 2024 } else if (!sc->dc_pmode) 2025 sc->dc_pmode = DC_PMODE_MII; 2026 2027 /* 2028 * Get station address from the EEPROM. 2029 */ 2030 switch(sc->dc_type) { 2031 case DC_TYPE_98713: 2032 case DC_TYPE_98713A: 2033 case DC_TYPE_987x5: 2034 case DC_TYPE_PNICII: 2035 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2036 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2037 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2038 break; 2039 case DC_TYPE_PNIC: 2040 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2041 break; 2042 case DC_TYPE_DM9102: 2043 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2044 #ifdef __sparc64__ 2045 /* 2046 * If this is an onboard dc(4) the station address read from 2047 * the EEPROM is all zero and we have to get it from the fcode. 2048 */ 2049 for (i = 0; i < ETHER_ADDR_LEN; i++) 2050 if (eaddr[i] != 0x00) 2051 break; 2052 if (i >= ETHER_ADDR_LEN) 2053 OF_getetheraddr(dev, eaddr); 2054 #endif 2055 break; 2056 case DC_TYPE_21143: 2057 case DC_TYPE_ASIX: 2058 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2059 break; 2060 case DC_TYPE_AL981: 2061 case DC_TYPE_AN985: 2062 reg = CSR_READ_4(sc, DC_AL_PAR0); 2063 mac = (uint8_t *)&eaddr[0]; 2064 mac[0] = (reg >> 0) & 0xff; 2065 mac[1] = (reg >> 8) & 0xff; 2066 mac[2] = (reg >> 16) & 0xff; 2067 mac[3] = (reg >> 24) & 0xff; 2068 reg = CSR_READ_4(sc, DC_AL_PAR1); 2069 mac[4] = (reg >> 0) & 0xff; 2070 mac[5] = (reg >> 8) & 0xff; 2071 break; 2072 case DC_TYPE_CONEXANT: 2073 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2074 ETHER_ADDR_LEN); 2075 break; 2076 case DC_TYPE_XIRCOM: 2077 /* The MAC comes from the CIS. */ 2078 mac = pci_get_ether(dev); 2079 if (!mac) { 2080 device_printf(dev, "No station address in CIS!\n"); 2081 error = ENXIO; 2082 goto fail; 2083 } 2084 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2085 break; 2086 default: 2087 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2088 break; 2089 } 2090 2091 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2092 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2093 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2094 sizeof(struct dc_list_data), 1, sizeof(struct dc_list_data), 2095 0, NULL, NULL, &sc->dc_ltag); 2096 if (error) { 2097 device_printf(dev, "failed to allocate busdma tag\n"); 2098 error = ENXIO; 2099 goto fail; 2100 } 2101 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2102 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2103 if (error) { 2104 device_printf(dev, "failed to allocate DMA safe memory\n"); 2105 error = ENXIO; 2106 goto fail; 2107 } 2108 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2109 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2110 BUS_DMA_NOWAIT); 2111 if (error) { 2112 device_printf(dev, "cannot get address of the descriptors\n"); 2113 error = ENXIO; 2114 goto fail; 2115 } 2116 2117 /* 2118 * Allocate a busdma tag and DMA safe memory for the multicast 2119 * setup frame. 2120 */ 2121 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2122 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2123 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 2124 0, NULL, NULL, &sc->dc_stag); 2125 if (error) { 2126 device_printf(dev, "failed to allocate busdma tag\n"); 2127 error = ENXIO; 2128 goto fail; 2129 } 2130 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2131 BUS_DMA_NOWAIT, &sc->dc_smap); 2132 if (error) { 2133 device_printf(dev, "failed to allocate DMA safe memory\n"); 2134 error = ENXIO; 2135 goto fail; 2136 } 2137 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2138 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2139 if (error) { 2140 device_printf(dev, "cannot get address of the descriptors\n"); 2141 error = ENXIO; 2142 goto fail; 2143 } 2144 2145 /* Allocate a busdma tag for mbufs. */ 2146 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 2147 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2148 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 2149 0, NULL, NULL, &sc->dc_mtag); 2150 if (error) { 2151 device_printf(dev, "failed to allocate busdma tag\n"); 2152 error = ENXIO; 2153 goto fail; 2154 } 2155 2156 /* Create the TX/RX busdma maps. */ 2157 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2158 error = bus_dmamap_create(sc->dc_mtag, 0, 2159 &sc->dc_cdata.dc_tx_map[i]); 2160 if (error) { 2161 device_printf(dev, "failed to init TX ring\n"); 2162 error = ENXIO; 2163 goto fail; 2164 } 2165 } 2166 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2167 error = bus_dmamap_create(sc->dc_mtag, 0, 2168 &sc->dc_cdata.dc_rx_map[i]); 2169 if (error) { 2170 device_printf(dev, "failed to init RX ring\n"); 2171 error = ENXIO; 2172 goto fail; 2173 } 2174 } 2175 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2176 if (error) { 2177 device_printf(dev, "failed to init RX ring\n"); 2178 error = ENXIO; 2179 goto fail; 2180 } 2181 2182 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2183 if (ifp == NULL) { 2184 device_printf(dev, "can not if_alloc()\n"); 2185 error = ENOSPC; 2186 goto fail; 2187 } 2188 ifp->if_softc = sc; 2189 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2190 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2191 ifp->if_ioctl = dc_ioctl; 2192 ifp->if_start = dc_start; 2193 ifp->if_init = dc_init; 2194 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2195 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2196 IFQ_SET_READY(&ifp->if_snd); 2197 2198 /* 2199 * Do MII setup. If this is a 21143, check for a PHY on the 2200 * MII bus after applying any necessary fixups to twiddle the 2201 * GPIO bits. If we don't end up finding a PHY, restore the 2202 * old selection (SIA only or SIA/SYM) and attach the dcphy 2203 * driver instead. 2204 */ 2205 if (DC_IS_INTEL(sc)) { 2206 dc_apply_fixup(sc, IFM_AUTO); 2207 tmp = sc->dc_pmode; 2208 sc->dc_pmode = DC_PMODE_MII; 2209 } 2210 2211 /* 2212 * Setup General Purpose port mode and data so the tulip can talk 2213 * to the MII. This needs to be done before mii_phy_probe so that 2214 * we can actually see them. 2215 */ 2216 if (DC_IS_XIRCOM(sc)) { 2217 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2218 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2219 DELAY(10); 2220 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2221 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2222 DELAY(10); 2223 } 2224 2225 error = mii_phy_probe(dev, &sc->dc_miibus, 2226 dc_ifmedia_upd, dc_ifmedia_sts); 2227 2228 if (error && DC_IS_INTEL(sc)) { 2229 sc->dc_pmode = tmp; 2230 if (sc->dc_pmode != DC_PMODE_SIA) 2231 sc->dc_pmode = DC_PMODE_SYM; 2232 sc->dc_flags |= DC_21143_NWAY; 2233 mii_phy_probe(dev, &sc->dc_miibus, 2234 dc_ifmedia_upd, dc_ifmedia_sts); 2235 /* 2236 * For non-MII cards, we need to have the 21143 2237 * drive the LEDs. Except there are some systems 2238 * like the NEC VersaPro NoteBook PC which have no 2239 * LEDs, and twiddling these bits has adverse effects 2240 * on them. (I.e. you suddenly can't get a link.) 2241 */ 2242 if (!(pci_get_subvendor(dev) == 0x1033 && 2243 pci_get_subdevice(dev) == 0x8028)) 2244 sc->dc_flags |= DC_TULIP_LEDS; 2245 error = 0; 2246 } 2247 2248 if (error) { 2249 device_printf(dev, "MII without any PHY!\n"); 2250 goto fail; 2251 } 2252 2253 if (DC_IS_ADMTEK(sc)) { 2254 /* 2255 * Set automatic TX underrun recovery for the ADMtek chips 2256 */ 2257 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2258 } 2259 2260 /* 2261 * Tell the upper layer(s) we support long frames. 2262 */ 2263 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2264 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2265 ifp->if_capenable = ifp->if_capabilities; 2266 #ifdef DEVICE_POLLING 2267 ifp->if_capabilities |= IFCAP_POLLING; 2268 #endif 2269 2270 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2271 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2272 2273 #ifdef SRM_MEDIA 2274 sc->dc_srm_media = 0; 2275 2276 /* Remember the SRM console media setting */ 2277 if (DC_IS_INTEL(sc)) { 2278 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2279 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2280 switch ((command >> 8) & 0xff) { 2281 case 3: 2282 sc->dc_srm_media = IFM_10_T; 2283 break; 2284 case 4: 2285 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2286 break; 2287 case 5: 2288 sc->dc_srm_media = IFM_100_TX; 2289 break; 2290 case 6: 2291 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2292 break; 2293 } 2294 if (sc->dc_srm_media) 2295 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2296 } 2297 #endif 2298 2299 /* 2300 * Call MI attach routine. 2301 */ 2302 ether_ifattach(ifp, eaddr); 2303 2304 /* Hook interrupt last to avoid having to lock softc */ 2305 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2306 dc_intr, sc, &sc->dc_intrhand); 2307 2308 if (error) { 2309 device_printf(dev, "couldn't set up irq\n"); 2310 ether_ifdetach(ifp); 2311 goto fail; 2312 } 2313 2314 fail: 2315 if (error) 2316 dc_detach(dev); 2317 return (error); 2318 } 2319 2320 /* 2321 * Shutdown hardware and free up resources. This can be called any 2322 * time after the mutex has been initialized. It is called in both 2323 * the error case in attach and the normal detach case so it needs 2324 * to be careful about only freeing resources that have actually been 2325 * allocated. 2326 */ 2327 static int 2328 dc_detach(device_t dev) 2329 { 2330 struct dc_softc *sc; 2331 struct ifnet *ifp; 2332 struct dc_mediainfo *m; 2333 int i; 2334 2335 sc = device_get_softc(dev); 2336 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2337 2338 ifp = sc->dc_ifp; 2339 2340 #ifdef DEVICE_POLLING 2341 if (ifp->if_capenable & IFCAP_POLLING) 2342 ether_poll_deregister(ifp); 2343 #endif 2344 2345 /* These should only be active if attach succeeded */ 2346 if (device_is_attached(dev)) { 2347 DC_LOCK(sc); 2348 dc_stop(sc); 2349 DC_UNLOCK(sc); 2350 callout_drain(&sc->dc_stat_ch); 2351 callout_drain(&sc->dc_wdog_ch); 2352 ether_ifdetach(ifp); 2353 } 2354 if (sc->dc_miibus) 2355 device_delete_child(dev, sc->dc_miibus); 2356 bus_generic_detach(dev); 2357 2358 if (sc->dc_intrhand) 2359 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2360 if (sc->dc_irq) 2361 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2362 if (sc->dc_res) 2363 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2364 2365 if (ifp) 2366 if_free(ifp); 2367 2368 if (sc->dc_cdata.dc_sbuf != NULL) 2369 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2370 if (sc->dc_ldata != NULL) 2371 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2372 if (sc->dc_mtag) { 2373 for (i = 0; i < DC_TX_LIST_CNT; i++) 2374 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2375 bus_dmamap_destroy(sc->dc_mtag, 2376 sc->dc_cdata.dc_tx_map[i]); 2377 for (i = 0; i < DC_RX_LIST_CNT; i++) 2378 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2379 bus_dmamap_destroy(sc->dc_mtag, 2380 sc->dc_cdata.dc_rx_map[i]); 2381 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2382 } 2383 if (sc->dc_stag) 2384 bus_dma_tag_destroy(sc->dc_stag); 2385 if (sc->dc_mtag) 2386 bus_dma_tag_destroy(sc->dc_mtag); 2387 if (sc->dc_ltag) 2388 bus_dma_tag_destroy(sc->dc_ltag); 2389 2390 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2391 2392 while (sc->dc_mi != NULL) { 2393 m = sc->dc_mi->dc_next; 2394 free(sc->dc_mi, M_DEVBUF); 2395 sc->dc_mi = m; 2396 } 2397 free(sc->dc_srom, M_DEVBUF); 2398 2399 mtx_destroy(&sc->dc_mtx); 2400 2401 return (0); 2402 } 2403 2404 /* 2405 * Initialize the transmit descriptors. 2406 */ 2407 static int 2408 dc_list_tx_init(struct dc_softc *sc) 2409 { 2410 struct dc_chain_data *cd; 2411 struct dc_list_data *ld; 2412 int i, nexti; 2413 2414 cd = &sc->dc_cdata; 2415 ld = sc->dc_ldata; 2416 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2417 if (i == DC_TX_LIST_CNT - 1) 2418 nexti = 0; 2419 else 2420 nexti = i + 1; 2421 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2422 cd->dc_tx_chain[i] = NULL; 2423 ld->dc_tx_list[i].dc_data = 0; 2424 ld->dc_tx_list[i].dc_ctl = 0; 2425 } 2426 2427 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2428 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2429 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2430 return (0); 2431 } 2432 2433 2434 /* 2435 * Initialize the RX descriptors and allocate mbufs for them. Note that 2436 * we arrange the descriptors in a closed ring, so that the last descriptor 2437 * points back to the first. 2438 */ 2439 static int 2440 dc_list_rx_init(struct dc_softc *sc) 2441 { 2442 struct dc_chain_data *cd; 2443 struct dc_list_data *ld; 2444 int i, nexti; 2445 2446 cd = &sc->dc_cdata; 2447 ld = sc->dc_ldata; 2448 2449 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2450 if (dc_newbuf(sc, i, 1) != 0) 2451 return (ENOBUFS); 2452 if (i == DC_RX_LIST_CNT - 1) 2453 nexti = 0; 2454 else 2455 nexti = i + 1; 2456 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2457 } 2458 2459 cd->dc_rx_prod = 0; 2460 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2461 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2462 return (0); 2463 } 2464 2465 /* 2466 * Initialize an RX descriptor and attach an MBUF cluster. 2467 */ 2468 static int 2469 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2470 { 2471 struct mbuf *m_new; 2472 bus_dmamap_t tmp; 2473 bus_dma_segment_t segs[1]; 2474 int error, nseg; 2475 2476 if (alloc) { 2477 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2478 if (m_new == NULL) 2479 return (ENOBUFS); 2480 } else { 2481 m_new = sc->dc_cdata.dc_rx_chain[i]; 2482 m_new->m_data = m_new->m_ext.ext_buf; 2483 } 2484 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2485 m_adj(m_new, sizeof(u_int64_t)); 2486 2487 /* 2488 * If this is a PNIC chip, zero the buffer. This is part 2489 * of the workaround for the receive bug in the 82c168 and 2490 * 82c169 chips. 2491 */ 2492 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2493 bzero(mtod(m_new, char *), m_new->m_len); 2494 2495 /* No need to remap the mbuf if we're reusing it. */ 2496 if (alloc) { 2497 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, sc->dc_sparemap, 2498 m_new, segs, &nseg, 0); 2499 if (error) { 2500 m_freem(m_new); 2501 return (error); 2502 } 2503 KASSERT(nseg == 1, 2504 ("%s: wrong number of segments (%d)", __func__, nseg)); 2505 sc->dc_ldata->dc_rx_list[i].dc_data = htole32(segs->ds_addr); 2506 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2507 tmp = sc->dc_cdata.dc_rx_map[i]; 2508 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2509 sc->dc_sparemap = tmp; 2510 sc->dc_cdata.dc_rx_chain[i] = m_new; 2511 } 2512 2513 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2514 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2515 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2516 BUS_DMASYNC_PREREAD); 2517 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2518 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2519 return (0); 2520 } 2521 2522 /* 2523 * Grrrrr. 2524 * The PNIC chip has a terrible bug in it that manifests itself during 2525 * periods of heavy activity. The exact mode of failure if difficult to 2526 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2527 * will happen on slow machines. The bug is that sometimes instead of 2528 * uploading one complete frame during reception, it uploads what looks 2529 * like the entire contents of its FIFO memory. The frame we want is at 2530 * the end of the whole mess, but we never know exactly how much data has 2531 * been uploaded, so salvaging the frame is hard. 2532 * 2533 * There is only one way to do it reliably, and it's disgusting. 2534 * Here's what we know: 2535 * 2536 * - We know there will always be somewhere between one and three extra 2537 * descriptors uploaded. 2538 * 2539 * - We know the desired received frame will always be at the end of the 2540 * total data upload. 2541 * 2542 * - We know the size of the desired received frame because it will be 2543 * provided in the length field of the status word in the last descriptor. 2544 * 2545 * Here's what we do: 2546 * 2547 * - When we allocate buffers for the receive ring, we bzero() them. 2548 * This means that we know that the buffer contents should be all 2549 * zeros, except for data uploaded by the chip. 2550 * 2551 * - We also force the PNIC chip to upload frames that include the 2552 * ethernet CRC at the end. 2553 * 2554 * - We gather all of the bogus frame data into a single buffer. 2555 * 2556 * - We then position a pointer at the end of this buffer and scan 2557 * backwards until we encounter the first non-zero byte of data. 2558 * This is the end of the received frame. We know we will encounter 2559 * some data at the end of the frame because the CRC will always be 2560 * there, so even if the sender transmits a packet of all zeros, 2561 * we won't be fooled. 2562 * 2563 * - We know the size of the actual received frame, so we subtract 2564 * that value from the current pointer location. This brings us 2565 * to the start of the actual received packet. 2566 * 2567 * - We copy this into an mbuf and pass it on, along with the actual 2568 * frame length. 2569 * 2570 * The performance hit is tremendous, but it beats dropping frames all 2571 * the time. 2572 */ 2573 2574 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2575 static void 2576 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2577 { 2578 struct dc_desc *cur_rx; 2579 struct dc_desc *c = NULL; 2580 struct mbuf *m = NULL; 2581 unsigned char *ptr; 2582 int i, total_len; 2583 u_int32_t rxstat = 0; 2584 2585 i = sc->dc_pnic_rx_bug_save; 2586 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2587 ptr = sc->dc_pnic_rx_buf; 2588 bzero(ptr, DC_RXLEN * 5); 2589 2590 /* Copy all the bytes from the bogus buffers. */ 2591 while (1) { 2592 c = &sc->dc_ldata->dc_rx_list[i]; 2593 rxstat = le32toh(c->dc_status); 2594 m = sc->dc_cdata.dc_rx_chain[i]; 2595 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2596 ptr += DC_RXLEN; 2597 /* If this is the last buffer, break out. */ 2598 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2599 break; 2600 dc_newbuf(sc, i, 0); 2601 DC_INC(i, DC_RX_LIST_CNT); 2602 } 2603 2604 /* Find the length of the actual receive frame. */ 2605 total_len = DC_RXBYTES(rxstat); 2606 2607 /* Scan backwards until we hit a non-zero byte. */ 2608 while (*ptr == 0x00) 2609 ptr--; 2610 2611 /* Round off. */ 2612 if ((uintptr_t)(ptr) & 0x3) 2613 ptr -= 1; 2614 2615 /* Now find the start of the frame. */ 2616 ptr -= total_len; 2617 if (ptr < sc->dc_pnic_rx_buf) 2618 ptr = sc->dc_pnic_rx_buf; 2619 2620 /* 2621 * Now copy the salvaged frame to the last mbuf and fake up 2622 * the status word to make it look like a successful 2623 * frame reception. 2624 */ 2625 dc_newbuf(sc, i, 0); 2626 bcopy(ptr, mtod(m, char *), total_len); 2627 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2628 } 2629 2630 /* 2631 * This routine searches the RX ring for dirty descriptors in the 2632 * event that the rxeof routine falls out of sync with the chip's 2633 * current descriptor pointer. This may happen sometimes as a result 2634 * of a "no RX buffer available" condition that happens when the chip 2635 * consumes all of the RX buffers before the driver has a chance to 2636 * process the RX ring. This routine may need to be called more than 2637 * once to bring the driver back in sync with the chip, however we 2638 * should still be getting RX DONE interrupts to drive the search 2639 * for new packets in the RX ring, so we should catch up eventually. 2640 */ 2641 static int 2642 dc_rx_resync(struct dc_softc *sc) 2643 { 2644 struct dc_desc *cur_rx; 2645 int i, pos; 2646 2647 pos = sc->dc_cdata.dc_rx_prod; 2648 2649 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2650 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2651 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2652 break; 2653 DC_INC(pos, DC_RX_LIST_CNT); 2654 } 2655 2656 /* If the ring really is empty, then just return. */ 2657 if (i == DC_RX_LIST_CNT) 2658 return (0); 2659 2660 /* We've fallen behing the chip: catch it. */ 2661 sc->dc_cdata.dc_rx_prod = pos; 2662 2663 return (EAGAIN); 2664 } 2665 2666 /* 2667 * A frame has been uploaded: pass the resulting mbuf chain up to 2668 * the higher level protocols. 2669 */ 2670 static void 2671 dc_rxeof(struct dc_softc *sc) 2672 { 2673 struct mbuf *m, *m0; 2674 struct ifnet *ifp; 2675 struct dc_desc *cur_rx; 2676 int i, total_len = 0; 2677 u_int32_t rxstat; 2678 2679 DC_LOCK_ASSERT(sc); 2680 2681 ifp = sc->dc_ifp; 2682 i = sc->dc_cdata.dc_rx_prod; 2683 2684 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2685 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2686 DC_RXSTAT_OWN)) { 2687 #ifdef DEVICE_POLLING 2688 if (ifp->if_capenable & IFCAP_POLLING) { 2689 if (sc->rxcycles <= 0) 2690 break; 2691 sc->rxcycles--; 2692 } 2693 #endif 2694 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2695 rxstat = le32toh(cur_rx->dc_status); 2696 m = sc->dc_cdata.dc_rx_chain[i]; 2697 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2698 BUS_DMASYNC_POSTREAD); 2699 total_len = DC_RXBYTES(rxstat); 2700 2701 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2702 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2703 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2704 sc->dc_pnic_rx_bug_save = i; 2705 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2706 DC_INC(i, DC_RX_LIST_CNT); 2707 continue; 2708 } 2709 dc_pnic_rx_bug_war(sc, i); 2710 rxstat = le32toh(cur_rx->dc_status); 2711 total_len = DC_RXBYTES(rxstat); 2712 } 2713 } 2714 2715 /* 2716 * If an error occurs, update stats, clear the 2717 * status word and leave the mbuf cluster in place: 2718 * it should simply get re-used next time this descriptor 2719 * comes up in the ring. However, don't report long 2720 * frames as errors since they could be vlans. 2721 */ 2722 if ((rxstat & DC_RXSTAT_RXERR)) { 2723 if (!(rxstat & DC_RXSTAT_GIANT) || 2724 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2725 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2726 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2727 ifp->if_ierrors++; 2728 if (rxstat & DC_RXSTAT_COLLSEEN) 2729 ifp->if_collisions++; 2730 dc_newbuf(sc, i, 0); 2731 if (rxstat & DC_RXSTAT_CRCERR) { 2732 DC_INC(i, DC_RX_LIST_CNT); 2733 continue; 2734 } else { 2735 dc_init_locked(sc); 2736 return; 2737 } 2738 } 2739 } 2740 2741 /* No errors; receive the packet. */ 2742 total_len -= ETHER_CRC_LEN; 2743 #ifdef __NO_STRICT_ALIGNMENT 2744 /* 2745 * On architectures without alignment problems we try to 2746 * allocate a new buffer for the receive ring, and pass up 2747 * the one where the packet is already, saving the expensive 2748 * copy done in m_devget(). 2749 * If we are on an architecture with alignment problems, or 2750 * if the allocation fails, then use m_devget and leave the 2751 * existing buffer in the receive ring. 2752 */ 2753 if (dc_newbuf(sc, i, 1) == 0) { 2754 m->m_pkthdr.rcvif = ifp; 2755 m->m_pkthdr.len = m->m_len = total_len; 2756 DC_INC(i, DC_RX_LIST_CNT); 2757 } else 2758 #endif 2759 { 2760 m0 = m_devget(mtod(m, char *), total_len, 2761 ETHER_ALIGN, ifp, NULL); 2762 dc_newbuf(sc, i, 0); 2763 DC_INC(i, DC_RX_LIST_CNT); 2764 if (m0 == NULL) { 2765 ifp->if_ierrors++; 2766 continue; 2767 } 2768 m = m0; 2769 } 2770 2771 ifp->if_ipackets++; 2772 DC_UNLOCK(sc); 2773 (*ifp->if_input)(ifp, m); 2774 DC_LOCK(sc); 2775 } 2776 2777 sc->dc_cdata.dc_rx_prod = i; 2778 } 2779 2780 /* 2781 * A frame was downloaded to the chip. It's safe for us to clean up 2782 * the list buffers. 2783 */ 2784 static void 2785 dc_txeof(struct dc_softc *sc) 2786 { 2787 struct dc_desc *cur_tx = NULL; 2788 struct ifnet *ifp; 2789 int idx; 2790 u_int32_t ctl, txstat; 2791 2792 ifp = sc->dc_ifp; 2793 2794 /* 2795 * Go through our tx list and free mbufs for those 2796 * frames that have been transmitted. 2797 */ 2798 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2799 idx = sc->dc_cdata.dc_tx_cons; 2800 while (idx != sc->dc_cdata.dc_tx_prod) { 2801 2802 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2803 txstat = le32toh(cur_tx->dc_status); 2804 ctl = le32toh(cur_tx->dc_ctl); 2805 2806 if (txstat & DC_TXSTAT_OWN) 2807 break; 2808 2809 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2810 if (ctl & DC_TXCTL_SETUP) { 2811 /* 2812 * Yes, the PNIC is so brain damaged 2813 * that it will sometimes generate a TX 2814 * underrun error while DMAing the RX 2815 * filter setup frame. If we detect this, 2816 * we have to send the setup frame again, 2817 * or else the filter won't be programmed 2818 * correctly. 2819 */ 2820 if (DC_IS_PNIC(sc)) { 2821 if (txstat & DC_TXSTAT_ERRSUM) 2822 dc_setfilt(sc); 2823 } 2824 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2825 } 2826 sc->dc_cdata.dc_tx_cnt--; 2827 DC_INC(idx, DC_TX_LIST_CNT); 2828 continue; 2829 } 2830 2831 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2832 /* 2833 * XXX: Why does my Xircom taunt me so? 2834 * For some reason it likes setting the CARRLOST flag 2835 * even when the carrier is there. wtf?!? 2836 * Who knows, but Conexant chips have the 2837 * same problem. Maybe they took lessons 2838 * from Xircom. 2839 */ 2840 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2841 sc->dc_pmode == DC_PMODE_MII && 2842 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2843 DC_TXSTAT_NOCARRIER))) 2844 txstat &= ~DC_TXSTAT_ERRSUM; 2845 } else { 2846 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2847 sc->dc_pmode == DC_PMODE_MII && 2848 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2849 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2850 txstat &= ~DC_TXSTAT_ERRSUM; 2851 } 2852 2853 if (txstat & DC_TXSTAT_ERRSUM) { 2854 ifp->if_oerrors++; 2855 if (txstat & DC_TXSTAT_EXCESSCOLL) 2856 ifp->if_collisions++; 2857 if (txstat & DC_TXSTAT_LATECOLL) 2858 ifp->if_collisions++; 2859 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2860 dc_init_locked(sc); 2861 return; 2862 } 2863 } 2864 2865 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2866 2867 ifp->if_opackets++; 2868 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2869 bus_dmamap_sync(sc->dc_mtag, 2870 sc->dc_cdata.dc_tx_map[idx], 2871 BUS_DMASYNC_POSTWRITE); 2872 bus_dmamap_unload(sc->dc_mtag, 2873 sc->dc_cdata.dc_tx_map[idx]); 2874 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2875 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2876 } 2877 2878 sc->dc_cdata.dc_tx_cnt--; 2879 DC_INC(idx, DC_TX_LIST_CNT); 2880 } 2881 sc->dc_cdata.dc_tx_cons = idx; 2882 2883 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_RSVD) 2884 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2885 2886 if (sc->dc_cdata.dc_tx_cnt == 0) 2887 sc->dc_wdog_timer = 0; 2888 } 2889 2890 static void 2891 dc_tick(void *xsc) 2892 { 2893 struct dc_softc *sc; 2894 struct mii_data *mii; 2895 struct ifnet *ifp; 2896 u_int32_t r; 2897 2898 sc = xsc; 2899 DC_LOCK_ASSERT(sc); 2900 ifp = sc->dc_ifp; 2901 mii = device_get_softc(sc->dc_miibus); 2902 2903 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2904 if (sc->dc_flags & DC_21143_NWAY) { 2905 r = CSR_READ_4(sc, DC_10BTSTAT); 2906 if (IFM_SUBTYPE(mii->mii_media_active) == 2907 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2908 sc->dc_link = 0; 2909 mii_mediachg(mii); 2910 } 2911 if (IFM_SUBTYPE(mii->mii_media_active) == 2912 IFM_10_T && (r & DC_TSTAT_LS10)) { 2913 sc->dc_link = 0; 2914 mii_mediachg(mii); 2915 } 2916 if (sc->dc_link == 0) 2917 mii_tick(mii); 2918 } else { 2919 r = CSR_READ_4(sc, DC_ISR); 2920 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2921 sc->dc_cdata.dc_tx_cnt == 0) { 2922 mii_tick(mii); 2923 if (!(mii->mii_media_status & IFM_ACTIVE)) 2924 sc->dc_link = 0; 2925 } 2926 } 2927 } else 2928 mii_tick(mii); 2929 2930 /* 2931 * When the init routine completes, we expect to be able to send 2932 * packets right away, and in fact the network code will send a 2933 * gratuitous ARP the moment the init routine marks the interface 2934 * as running. However, even though the MAC may have been initialized, 2935 * there may be a delay of a few seconds before the PHY completes 2936 * autonegotiation and the link is brought up. Any transmissions 2937 * made during that delay will be lost. Dealing with this is tricky: 2938 * we can't just pause in the init routine while waiting for the 2939 * PHY to come ready since that would bring the whole system to 2940 * a screeching halt for several seconds. 2941 * 2942 * What we do here is prevent the TX start routine from sending 2943 * any packets until a link has been established. After the 2944 * interface has been initialized, the tick routine will poll 2945 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2946 * that time, packets will stay in the send queue, and once the 2947 * link comes up, they will be flushed out to the wire. 2948 */ 2949 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2950 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2951 sc->dc_link++; 2952 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2953 dc_start_locked(ifp); 2954 } 2955 2956 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2957 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2958 else 2959 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2960 } 2961 2962 /* 2963 * A transmit underrun has occurred. Back off the transmit threshold, 2964 * or switch to store and forward mode if we have to. 2965 */ 2966 static void 2967 dc_tx_underrun(struct dc_softc *sc) 2968 { 2969 u_int32_t isr; 2970 int i; 2971 2972 if (DC_IS_DAVICOM(sc)) 2973 dc_init_locked(sc); 2974 2975 if (DC_IS_INTEL(sc)) { 2976 /* 2977 * The real 21143 requires that the transmitter be idle 2978 * in order to change the transmit threshold or store 2979 * and forward state. 2980 */ 2981 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2982 2983 for (i = 0; i < DC_TIMEOUT; i++) { 2984 isr = CSR_READ_4(sc, DC_ISR); 2985 if (isr & DC_ISR_TX_IDLE) 2986 break; 2987 DELAY(10); 2988 } 2989 if (i == DC_TIMEOUT) { 2990 device_printf(sc->dc_dev, 2991 "%s: failed to force tx to idle state\n", 2992 __func__); 2993 dc_init_locked(sc); 2994 } 2995 } 2996 2997 device_printf(sc->dc_dev, "TX underrun -- "); 2998 sc->dc_txthresh += DC_TXTHRESH_INC; 2999 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3000 printf("using store and forward mode\n"); 3001 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3002 } else { 3003 printf("increasing TX threshold\n"); 3004 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3005 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3006 } 3007 3008 if (DC_IS_INTEL(sc)) 3009 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3010 } 3011 3012 #ifdef DEVICE_POLLING 3013 static poll_handler_t dc_poll; 3014 3015 static void 3016 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3017 { 3018 struct dc_softc *sc = ifp->if_softc; 3019 3020 DC_LOCK(sc); 3021 3022 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3023 DC_UNLOCK(sc); 3024 return; 3025 } 3026 3027 sc->rxcycles = count; 3028 dc_rxeof(sc); 3029 dc_txeof(sc); 3030 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3031 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3032 dc_start_locked(ifp); 3033 3034 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3035 u_int32_t status; 3036 3037 status = CSR_READ_4(sc, DC_ISR); 3038 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3039 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3040 DC_ISR_BUS_ERR); 3041 if (!status) { 3042 DC_UNLOCK(sc); 3043 return; 3044 } 3045 /* ack what we have */ 3046 CSR_WRITE_4(sc, DC_ISR, status); 3047 3048 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3049 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3050 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3051 3052 if (dc_rx_resync(sc)) 3053 dc_rxeof(sc); 3054 } 3055 /* restart transmit unit if necessary */ 3056 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3057 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3058 3059 if (status & DC_ISR_TX_UNDERRUN) 3060 dc_tx_underrun(sc); 3061 3062 if (status & DC_ISR_BUS_ERR) { 3063 if_printf(ifp, "%s: bus error\n", __func__); 3064 dc_reset(sc); 3065 dc_init_locked(sc); 3066 } 3067 } 3068 DC_UNLOCK(sc); 3069 } 3070 #endif /* DEVICE_POLLING */ 3071 3072 static void 3073 dc_intr(void *arg) 3074 { 3075 struct dc_softc *sc; 3076 struct ifnet *ifp; 3077 u_int32_t status; 3078 3079 sc = arg; 3080 3081 if (sc->suspended) 3082 return; 3083 3084 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3085 return; 3086 3087 DC_LOCK(sc); 3088 ifp = sc->dc_ifp; 3089 #ifdef DEVICE_POLLING 3090 if (ifp->if_capenable & IFCAP_POLLING) { 3091 DC_UNLOCK(sc); 3092 return; 3093 } 3094 #endif 3095 3096 /* Suppress unwanted interrupts */ 3097 if (!(ifp->if_flags & IFF_UP)) { 3098 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3099 dc_stop(sc); 3100 DC_UNLOCK(sc); 3101 return; 3102 } 3103 3104 /* Disable interrupts. */ 3105 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3106 3107 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 3108 status != 0xFFFFFFFF && 3109 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3110 3111 CSR_WRITE_4(sc, DC_ISR, status); 3112 3113 if (status & DC_ISR_RX_OK) { 3114 int curpkts; 3115 curpkts = ifp->if_ipackets; 3116 dc_rxeof(sc); 3117 if (curpkts == ifp->if_ipackets) { 3118 while (dc_rx_resync(sc)) 3119 dc_rxeof(sc); 3120 } 3121 } 3122 3123 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3124 dc_txeof(sc); 3125 3126 if (status & DC_ISR_TX_IDLE) { 3127 dc_txeof(sc); 3128 if (sc->dc_cdata.dc_tx_cnt) { 3129 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3130 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3131 } 3132 } 3133 3134 if (status & DC_ISR_TX_UNDERRUN) 3135 dc_tx_underrun(sc); 3136 3137 if ((status & DC_ISR_RX_WATDOGTIMEO) 3138 || (status & DC_ISR_RX_NOBUF)) { 3139 int curpkts; 3140 curpkts = ifp->if_ipackets; 3141 dc_rxeof(sc); 3142 if (curpkts == ifp->if_ipackets) { 3143 while (dc_rx_resync(sc)) 3144 dc_rxeof(sc); 3145 } 3146 } 3147 3148 if (status & DC_ISR_BUS_ERR) { 3149 dc_reset(sc); 3150 dc_init_locked(sc); 3151 } 3152 } 3153 3154 /* Re-enable interrupts. */ 3155 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3156 3157 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3158 dc_start_locked(ifp); 3159 3160 DC_UNLOCK(sc); 3161 } 3162 3163 /* 3164 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3165 * pointers to the fragment pointers. 3166 */ 3167 static int 3168 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3169 { 3170 bus_dma_segment_t segs[DC_MAXFRAGS]; 3171 struct dc_desc *f; 3172 struct mbuf *m; 3173 int chainlen, cur, error, first, frag, i, idx, nseg; 3174 3175 /* 3176 * If there's no way we can send any packets, return now. 3177 */ 3178 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD) 3179 return (ENOBUFS); 3180 3181 /* 3182 * Count the number of frags in this chain to see if 3183 * we need to m_defrag. Since the descriptor list is shared 3184 * by all packets, we'll m_defrag long chains so that they 3185 * do not use up the entire list, even if they would fit. 3186 */ 3187 chainlen = 0; 3188 for (m = *m_head; m != NULL; m = m->m_next) 3189 chainlen++; 3190 3191 m = NULL; 3192 if ((sc->dc_flags & DC_TX_COALESCE && ((*m_head)->m_next != NULL || 3193 sc->dc_flags & DC_TX_ALIGN)) || (chainlen > DC_TX_LIST_CNT / 4) || 3194 (DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt) <= 3195 DC_TX_LIST_RSVD)) { 3196 m = m_defrag(*m_head, M_DONTWAIT); 3197 if (m == NULL) { 3198 m_freem(*m_head); 3199 *m_head = NULL; 3200 return (ENOBUFS); 3201 } 3202 *m_head = m; 3203 } 3204 idx = sc->dc_cdata.dc_tx_prod; 3205 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3206 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3207 if (error == EFBIG) { 3208 m = m_defrag(*m_head, M_DONTWAIT); 3209 if (m == NULL) { 3210 m_freem(*m_head); 3211 *m_head = NULL; 3212 return (ENOBUFS); 3213 } 3214 *m_head = m; 3215 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3216 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3217 if (error != 0) { 3218 m_freem(*m_head); 3219 *m_head = NULL; 3220 return (error); 3221 } 3222 } else if (error != 0) 3223 return (error); 3224 KASSERT(nseg <= DC_MAXFRAGS, 3225 ("%s: wrong number of segments (%d)", __func__, nseg)); 3226 if (nseg == 0) { 3227 m_freem(*m_head); 3228 *m_head = NULL; 3229 return (EIO); 3230 } 3231 3232 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3233 for (i = 0; i < nseg; i++) { 3234 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3235 (frag == (DC_TX_LIST_CNT - 1)) && 3236 (first != sc->dc_cdata.dc_tx_first)) { 3237 bus_dmamap_unload(sc->dc_mtag, 3238 sc->dc_cdata.dc_tx_map[first]); 3239 m_freem(*m_head); 3240 *m_head = NULL; 3241 return (ENOBUFS); 3242 } 3243 3244 f = &sc->dc_ldata->dc_tx_list[frag]; 3245 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3246 if (i == 0) { 3247 f->dc_status = 0; 3248 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3249 } else 3250 f->dc_status = htole32(DC_TXSTAT_OWN); 3251 f->dc_data = htole32(segs[i].ds_addr); 3252 cur = frag; 3253 DC_INC(frag, DC_TX_LIST_CNT); 3254 } 3255 3256 sc->dc_cdata.dc_tx_prod = frag; 3257 sc->dc_cdata.dc_tx_cnt += nseg; 3258 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3259 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3260 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3261 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3262 htole32(DC_TXCTL_FINT); 3263 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3264 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3265 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3266 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3267 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3268 3269 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3270 BUS_DMASYNC_PREWRITE); 3271 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3272 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3273 return (0); 3274 } 3275 3276 static void 3277 dc_start(struct ifnet *ifp) 3278 { 3279 struct dc_softc *sc; 3280 3281 sc = ifp->if_softc; 3282 DC_LOCK(sc); 3283 dc_start_locked(ifp); 3284 DC_UNLOCK(sc); 3285 } 3286 3287 /* 3288 * Main transmit routine 3289 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3290 * regions directly in the transmit lists. We also save a copy of the 3291 * pointers since the transmit list fragment pointers are physical 3292 * addresses. 3293 */ 3294 static void 3295 dc_start_locked(struct ifnet *ifp) 3296 { 3297 struct dc_softc *sc; 3298 struct mbuf *m_head = NULL; 3299 unsigned int queued = 0; 3300 int idx; 3301 3302 sc = ifp->if_softc; 3303 3304 DC_LOCK_ASSERT(sc); 3305 3306 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3307 return; 3308 3309 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3310 return; 3311 3312 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3313 3314 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3315 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3316 if (m_head == NULL) 3317 break; 3318 3319 if (dc_encap(sc, &m_head)) { 3320 if (m_head == NULL) 3321 break; 3322 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3323 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3324 break; 3325 } 3326 idx = sc->dc_cdata.dc_tx_prod; 3327 3328 queued++; 3329 /* 3330 * If there's a BPF listener, bounce a copy of this frame 3331 * to him. 3332 */ 3333 BPF_MTAP(ifp, m_head); 3334 3335 if (sc->dc_flags & DC_TX_ONE) { 3336 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3337 break; 3338 } 3339 } 3340 3341 if (queued > 0) { 3342 /* Transmit */ 3343 if (!(sc->dc_flags & DC_TX_POLL)) 3344 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3345 3346 /* 3347 * Set a timeout in case the chip goes out to lunch. 3348 */ 3349 sc->dc_wdog_timer = 5; 3350 } 3351 } 3352 3353 static void 3354 dc_init(void *xsc) 3355 { 3356 struct dc_softc *sc = xsc; 3357 3358 DC_LOCK(sc); 3359 dc_init_locked(sc); 3360 #ifdef SRM_MEDIA 3361 if(sc->dc_srm_media) { 3362 struct ifreq ifr; 3363 struct mii_data *mii; 3364 3365 ifr.ifr_media = sc->dc_srm_media; 3366 sc->dc_srm_media = 0; 3367 DC_UNLOCK(sc); 3368 mii = device_get_softc(sc->dc_miibus); 3369 ifmedia_ioctl(sc->dc_ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3370 } else 3371 #endif 3372 DC_UNLOCK(sc); 3373 } 3374 3375 static void 3376 dc_init_locked(struct dc_softc *sc) 3377 { 3378 struct ifnet *ifp = sc->dc_ifp; 3379 struct mii_data *mii; 3380 3381 DC_LOCK_ASSERT(sc); 3382 3383 mii = device_get_softc(sc->dc_miibus); 3384 3385 /* 3386 * Cancel pending I/O and free all RX/TX buffers. 3387 */ 3388 dc_stop(sc); 3389 dc_reset(sc); 3390 3391 /* 3392 * Set cache alignment and burst length. 3393 */ 3394 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3395 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3396 else 3397 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3398 /* 3399 * Evenly share the bus between receive and transmit process. 3400 */ 3401 if (DC_IS_INTEL(sc)) 3402 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3403 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3404 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3405 } else { 3406 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3407 } 3408 if (sc->dc_flags & DC_TX_POLL) 3409 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3410 switch(sc->dc_cachesize) { 3411 case 32: 3412 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3413 break; 3414 case 16: 3415 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3416 break; 3417 case 8: 3418 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3419 break; 3420 case 0: 3421 default: 3422 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3423 break; 3424 } 3425 3426 if (sc->dc_flags & DC_TX_STORENFWD) 3427 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3428 else { 3429 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3430 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3431 } else { 3432 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3433 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3434 } 3435 } 3436 3437 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3438 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3439 3440 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3441 /* 3442 * The app notes for the 98713 and 98715A say that 3443 * in order to have the chips operate properly, a magic 3444 * number must be written to CSR16. Macronix does not 3445 * document the meaning of these bits so there's no way 3446 * to know exactly what they do. The 98713 has a magic 3447 * number all its own; the rest all use a different one. 3448 */ 3449 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3450 if (sc->dc_type == DC_TYPE_98713) 3451 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3452 else 3453 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3454 } 3455 3456 if (DC_IS_XIRCOM(sc)) { 3457 /* 3458 * setup General Purpose Port mode and data so the tulip 3459 * can talk to the MII. 3460 */ 3461 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3462 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3463 DELAY(10); 3464 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3465 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3466 DELAY(10); 3467 } 3468 3469 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3470 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3471 3472 /* Init circular RX list. */ 3473 if (dc_list_rx_init(sc) == ENOBUFS) { 3474 device_printf(sc->dc_dev, 3475 "initialization failed: no memory for rx buffers\n"); 3476 dc_stop(sc); 3477 return; 3478 } 3479 3480 /* 3481 * Init TX descriptors. 3482 */ 3483 dc_list_tx_init(sc); 3484 3485 /* 3486 * Load the address of the RX list. 3487 */ 3488 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3489 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3490 3491 /* 3492 * Enable interrupts. 3493 */ 3494 #ifdef DEVICE_POLLING 3495 /* 3496 * ... but only if we are not polling, and make sure they are off in 3497 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3498 * after a reset. 3499 */ 3500 if (ifp->if_capenable & IFCAP_POLLING) 3501 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3502 else 3503 #endif 3504 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3505 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3506 3507 /* Enable transmitter. */ 3508 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3509 3510 /* 3511 * If this is an Intel 21143 and we're not using the 3512 * MII port, program the LED control pins so we get 3513 * link and activity indications. 3514 */ 3515 if (sc->dc_flags & DC_TULIP_LEDS) { 3516 CSR_WRITE_4(sc, DC_WATCHDOG, 3517 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3518 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3519 } 3520 3521 /* 3522 * Load the RX/multicast filter. We do this sort of late 3523 * because the filter programming scheme on the 21143 and 3524 * some clones requires DMAing a setup frame via the TX 3525 * engine, and we need the transmitter enabled for that. 3526 */ 3527 dc_setfilt(sc); 3528 3529 /* Enable receiver. */ 3530 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3531 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3532 3533 mii_mediachg(mii); 3534 dc_setcfg(sc, sc->dc_if_media); 3535 3536 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3537 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3538 3539 /* Don't start the ticker if this is a homePNA link. */ 3540 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3541 sc->dc_link = 1; 3542 else { 3543 if (sc->dc_flags & DC_21143_NWAY) 3544 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3545 else 3546 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3547 } 3548 3549 sc->dc_wdog_timer = 0; 3550 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3551 } 3552 3553 /* 3554 * Set media options. 3555 */ 3556 static int 3557 dc_ifmedia_upd(struct ifnet *ifp) 3558 { 3559 struct dc_softc *sc; 3560 struct mii_data *mii; 3561 struct ifmedia *ifm; 3562 3563 sc = ifp->if_softc; 3564 mii = device_get_softc(sc->dc_miibus); 3565 DC_LOCK(sc); 3566 mii_mediachg(mii); 3567 ifm = &mii->mii_media; 3568 3569 if (DC_IS_DAVICOM(sc) && 3570 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3571 dc_setcfg(sc, ifm->ifm_media); 3572 else 3573 sc->dc_link = 0; 3574 DC_UNLOCK(sc); 3575 3576 return (0); 3577 } 3578 3579 /* 3580 * Report current media status. 3581 */ 3582 static void 3583 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3584 { 3585 struct dc_softc *sc; 3586 struct mii_data *mii; 3587 struct ifmedia *ifm; 3588 3589 sc = ifp->if_softc; 3590 mii = device_get_softc(sc->dc_miibus); 3591 DC_LOCK(sc); 3592 mii_pollstat(mii); 3593 ifm = &mii->mii_media; 3594 if (DC_IS_DAVICOM(sc)) { 3595 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3596 ifmr->ifm_active = ifm->ifm_media; 3597 ifmr->ifm_status = 0; 3598 DC_UNLOCK(sc); 3599 return; 3600 } 3601 } 3602 ifmr->ifm_active = mii->mii_media_active; 3603 ifmr->ifm_status = mii->mii_media_status; 3604 DC_UNLOCK(sc); 3605 } 3606 3607 static int 3608 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3609 { 3610 struct dc_softc *sc = ifp->if_softc; 3611 struct ifreq *ifr = (struct ifreq *)data; 3612 struct mii_data *mii; 3613 int error = 0; 3614 3615 switch (command) { 3616 case SIOCSIFFLAGS: 3617 DC_LOCK(sc); 3618 if (ifp->if_flags & IFF_UP) { 3619 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3620 (IFF_PROMISC | IFF_ALLMULTI); 3621 3622 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3623 if (need_setfilt) 3624 dc_setfilt(sc); 3625 } else { 3626 sc->dc_txthresh = 0; 3627 dc_init_locked(sc); 3628 } 3629 } else { 3630 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3631 dc_stop(sc); 3632 } 3633 sc->dc_if_flags = ifp->if_flags; 3634 DC_UNLOCK(sc); 3635 error = 0; 3636 break; 3637 case SIOCADDMULTI: 3638 case SIOCDELMULTI: 3639 DC_LOCK(sc); 3640 dc_setfilt(sc); 3641 DC_UNLOCK(sc); 3642 error = 0; 3643 break; 3644 case SIOCGIFMEDIA: 3645 case SIOCSIFMEDIA: 3646 mii = device_get_softc(sc->dc_miibus); 3647 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3648 #ifdef SRM_MEDIA 3649 DC_LOCK(sc); 3650 if (sc->dc_srm_media) 3651 sc->dc_srm_media = 0; 3652 DC_UNLOCK(sc); 3653 #endif 3654 break; 3655 case SIOCSIFCAP: 3656 #ifdef DEVICE_POLLING 3657 if (ifr->ifr_reqcap & IFCAP_POLLING && 3658 !(ifp->if_capenable & IFCAP_POLLING)) { 3659 error = ether_poll_register(dc_poll, ifp); 3660 if (error) 3661 return(error); 3662 DC_LOCK(sc); 3663 /* Disable interrupts */ 3664 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3665 ifp->if_capenable |= IFCAP_POLLING; 3666 DC_UNLOCK(sc); 3667 return (error); 3668 } 3669 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3670 ifp->if_capenable & IFCAP_POLLING) { 3671 error = ether_poll_deregister(ifp); 3672 /* Enable interrupts. */ 3673 DC_LOCK(sc); 3674 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3675 ifp->if_capenable &= ~IFCAP_POLLING; 3676 DC_UNLOCK(sc); 3677 return (error); 3678 } 3679 #endif /* DEVICE_POLLING */ 3680 break; 3681 default: 3682 error = ether_ioctl(ifp, command, data); 3683 break; 3684 } 3685 3686 return (error); 3687 } 3688 3689 static void 3690 dc_watchdog(void *xsc) 3691 { 3692 struct dc_softc *sc = xsc; 3693 struct ifnet *ifp; 3694 3695 DC_LOCK_ASSERT(sc); 3696 3697 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3698 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3699 return; 3700 } 3701 3702 ifp = sc->dc_ifp; 3703 ifp->if_oerrors++; 3704 device_printf(sc->dc_dev, "watchdog timeout\n"); 3705 3706 dc_stop(sc); 3707 dc_reset(sc); 3708 dc_init_locked(sc); 3709 3710 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3711 dc_start_locked(ifp); 3712 } 3713 3714 /* 3715 * Stop the adapter and free any mbufs allocated to the 3716 * RX and TX lists. 3717 */ 3718 static void 3719 dc_stop(struct dc_softc *sc) 3720 { 3721 struct ifnet *ifp; 3722 struct dc_list_data *ld; 3723 struct dc_chain_data *cd; 3724 int i; 3725 u_int32_t ctl; 3726 3727 DC_LOCK_ASSERT(sc); 3728 3729 ifp = sc->dc_ifp; 3730 ld = sc->dc_ldata; 3731 cd = &sc->dc_cdata; 3732 3733 callout_stop(&sc->dc_stat_ch); 3734 callout_stop(&sc->dc_wdog_ch); 3735 sc->dc_wdog_timer = 0; 3736 3737 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3738 3739 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3740 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3741 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3742 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3743 sc->dc_link = 0; 3744 3745 /* 3746 * Free data in the RX lists. 3747 */ 3748 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3749 if (cd->dc_rx_chain[i] != NULL) { 3750 m_freem(cd->dc_rx_chain[i]); 3751 cd->dc_rx_chain[i] = NULL; 3752 } 3753 } 3754 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3755 3756 /* 3757 * Free the TX list buffers. 3758 */ 3759 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3760 if (cd->dc_tx_chain[i] != NULL) { 3761 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3762 if ((ctl & DC_TXCTL_SETUP) || 3763 !(ctl & DC_TXCTL_LASTFRAG)) { 3764 cd->dc_tx_chain[i] = NULL; 3765 continue; 3766 } 3767 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3768 m_freem(cd->dc_tx_chain[i]); 3769 cd->dc_tx_chain[i] = NULL; 3770 } 3771 } 3772 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3773 } 3774 3775 /* 3776 * Device suspend routine. Stop the interface and save some PCI 3777 * settings in case the BIOS doesn't restore them properly on 3778 * resume. 3779 */ 3780 static int 3781 dc_suspend(device_t dev) 3782 { 3783 struct dc_softc *sc; 3784 3785 sc = device_get_softc(dev); 3786 DC_LOCK(sc); 3787 dc_stop(sc); 3788 sc->suspended = 1; 3789 DC_UNLOCK(sc); 3790 3791 return (0); 3792 } 3793 3794 /* 3795 * Device resume routine. Restore some PCI settings in case the BIOS 3796 * doesn't, re-enable busmastering, and restart the interface if 3797 * appropriate. 3798 */ 3799 static int 3800 dc_resume(device_t dev) 3801 { 3802 struct dc_softc *sc; 3803 struct ifnet *ifp; 3804 3805 sc = device_get_softc(dev); 3806 ifp = sc->dc_ifp; 3807 3808 /* reinitialize interface if necessary */ 3809 DC_LOCK(sc); 3810 if (ifp->if_flags & IFF_UP) 3811 dc_init_locked(sc); 3812 3813 sc->suspended = 0; 3814 DC_UNLOCK(sc); 3815 3816 return (0); 3817 } 3818 3819 /* 3820 * Stop all chip I/O so that the kernel's probe routines don't 3821 * get confused by errant DMAs when rebooting. 3822 */ 3823 static int 3824 dc_shutdown(device_t dev) 3825 { 3826 struct dc_softc *sc; 3827 3828 sc = device_get_softc(dev); 3829 3830 DC_LOCK(sc); 3831 dc_stop(sc); 3832 DC_UNLOCK(sc); 3833 3834 return (0); 3835 }
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