The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_dcreg.h

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    1 /*
    2  * Copyright (c) 1997, 1998, 1999
    3  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD$
   33  */
   34 
   35 /*
   36  * 21143 and clone common register definitions.
   37  */
   38 
   39 #define DC_BUSCTL               0x00    /* bus control */
   40 #define DC_TXSTART              0x08    /* tx start demand */
   41 #define DC_RXSTART              0x10    /* rx start demand */
   42 #define DC_RXADDR               0x18    /* rx descriptor list start addr */
   43 #define DC_TXADDR               0x20    /* tx descriptor list start addr */
   44 #define DC_ISR                  0x28    /* interrupt status register */
   45 #define DC_NETCFG               0x30    /* network config register */
   46 #define DC_IMR                  0x38    /* interrupt mask */
   47 #define DC_FRAMESDISCARDED      0x40    /* # of discarded frames */
   48 #define DC_SIO                  0x48    /* MII and ROM/EEPROM access */
   49 #define DC_ROM                  0x50    /* ROM programming address */
   50 #define DC_TIMER                0x58    /* general timer */
   51 #define DC_10BTSTAT             0x60    /* SIA status */
   52 #define DC_SIARESET             0x68    /* SIA connectivity */
   53 #define DC_10BTCTRL             0x70    /* SIA transmit and receive */
   54 #define DC_WATCHDOG             0x78    /* SIA and general purpose port */
   55 
   56 /*
   57  * There are two general 'types' of MX chips that we need to be
   58  * concerned with. One is the original 98713, which has its internal
   59  * NWAY support controlled via the MDIO bits in the serial I/O
   60  * register. The other is everything else (from the 98713A on up),
   61  * which has its internal NWAY controlled via CSR13, CSR14 and CSR15,
   62  * just like the 21143. This type setting also governs which of the
   63  * 'magic' numbers we write to CSR16. The PNIC II falls into the
   64  * 98713A/98715/98715A/98725 category.
   65  */
   66 #define DC_TYPE_98713           0x1
   67 #define DC_TYPE_98713A          0x2
   68 #define DC_TYPE_987x5           0x3
   69 
   70 /* Other type of supported chips. */
   71 #define DC_TYPE_21143           0x4     /* Intel 21143 */
   72 #define DC_TYPE_ASIX            0x5     /* ASIX AX88140A/AX88141 */
   73 #define DC_TYPE_AL981           0x6     /* ADMtek AL981 Comet */
   74 #define DC_TYPE_AN985           0x7     /* ADMtek AN985 Centaur */
   75 #define DC_TYPE_DM9102          0x8     /* Davicom DM9102 */
   76 #define DC_TYPE_PNICII          0x9     /* 82c115 PNIC II */
   77 #define DC_TYPE_PNIC            0xA     /* 82c168/82c169 PNIC I */
   78 #define DC_TYPE_CONEXANT        0xC     /* Conexant LANfinity RS7112 */
   79 
   80 #define DC_IS_MACRONIX(x)                       \
   81         (x->dc_type == DC_TYPE_98713 ||         \
   82          x->dc_type == DC_TYPE_98713A ||        \
   83          x->dc_type == DC_TYPE_987x5)
   84 
   85 #define DC_IS_ADMTEK(x)                         \
   86         (x->dc_type == DC_TYPE_AL981 ||         \
   87          x->dc_type == DC_TYPE_AN985)
   88 
   89 #define DC_IS_INTEL(x)          (x->dc_type == DC_TYPE_21143)
   90 #define DC_IS_ASIX(x)           (x->dc_type == DC_TYPE_ASIX)
   91 #define DC_IS_COMET(x)          (x->dc_type == DC_TYPE_AL981)
   92 #define DC_IS_CENTAUR(x)        (x->dc_type == DC_TYPE_AN985)
   93 #define DC_IS_DAVICOM(x)        (x->dc_type == DC_TYPE_DM9102)
   94 #define DC_IS_PNICII(x)         (x->dc_type == DC_TYPE_PNICII)
   95 #define DC_IS_PNIC(x)           (x->dc_type == DC_TYPE_PNIC)
   96 #define DC_IS_CONEXANT(x)       (x->dc_type == DC_TYPE_CONEXANT)
   97 
   98 /* MII/symbol mode port types */
   99 #define DC_PMODE_MII            0x1
  100 #define DC_PMODE_SYM            0x2
  101 #define DC_PMODE_SIA            0x3
  102 
  103 /*
  104  * Bus control bits.
  105  */
  106 #define DC_BUSCTL_RESET         0x00000001
  107 #define DC_BUSCTL_ARBITRATION   0x00000002
  108 #define DC_BUSCTL_SKIPLEN       0x0000007C
  109 #define DC_BUSCTL_BUF_BIGENDIAN 0x00000080
  110 #define DC_BUSCTL_BURSTLEN      0x00003F00
  111 #define DC_BUSCTL_CACHEALIGN    0x0000C000
  112 #define DC_BUSCTL_TXPOLL        0x000E0000
  113 #define DC_BUSCTL_DBO           0x00100000
  114 #define DC_BUSCTL_MRME          0x00200000
  115 #define DC_BUSCTL_MRLE          0x00800000
  116 #define DC_BUSCTL_MWIE          0x01000000
  117 #define DC_BUSCTL_ONNOW_ENB     0x04000000
  118 
  119 #define DC_SKIPLEN_1LONG        0x00000004
  120 #define DC_SKIPLEN_2LONG        0x00000008
  121 #define DC_SKIPLEN_3LONG        0x00000010
  122 #define DC_SKIPLEN_4LONG        0x00000020
  123 #define DC_SKIPLEN_5LONG        0x00000040
  124 
  125 #define DC_CACHEALIGN_NONE      0x00000000
  126 #define DC_CACHEALIGN_8LONG     0x00004000
  127 #define DC_CACHEALIGN_16LONG    0x00008000
  128 #define DC_CACHEALIGN_32LONG    0x0000C000
  129 
  130 #define DC_BURSTLEN_USECA       0x00000000
  131 #define DC_BURSTLEN_1LONG       0x00000100
  132 #define DC_BURSTLEN_2LONG       0x00000200
  133 #define DC_BURSTLEN_4LONG       0x00000400
  134 #define DC_BURSTLEN_8LONG       0x00000800
  135 #define DC_BURSTLEN_16LONG      0x00001000
  136 #define DC_BURSTLEN_32LONG      0x00002000
  137 
  138 #define DC_TXPOLL_OFF           0x00000000
  139 #define DC_TXPOLL_1             0x00020000
  140 #define DC_TXPOLL_2             0x00040000
  141 #define DC_TXPOLL_3             0x00060000
  142 #define DC_TXPOLL_4             0x00080000
  143 #define DC_TXPOLL_5             0x000A0000
  144 #define DC_TXPOLL_6             0x000C0000
  145 #define DC_TXPOLL_7             0x000E0000
  146 
  147 /*
  148  * Interrupt status bits.
  149  */
  150 #define DC_ISR_TX_OK            0x00000001
  151 #define DC_ISR_TX_IDLE          0x00000002
  152 #define DC_ISR_TX_NOBUF         0x00000004
  153 #define DC_ISR_TX_JABBERTIMEO   0x00000008
  154 #define DC_ISR_LINKGOOD         0x00000010
  155 #define DC_ISR_TX_UNDERRUN      0x00000020
  156 #define DC_ISR_RX_OK            0x00000040
  157 #define DC_ISR_RX_NOBUF         0x00000080
  158 #define DC_ISR_RX_READ          0x00000100
  159 #define DC_ISR_RX_WATDOGTIMEO   0x00000200
  160 #define DC_ISR_TX_EARLY         0x00000400
  161 #define DC_ISR_TIMER_EXPIRED    0x00000800
  162 #define DC_ISR_LINKFAIL         0x00001000
  163 #define DC_ISR_BUS_ERR          0x00002000
  164 #define DC_ISR_RX_EARLY         0x00004000
  165 #define DC_ISR_ABNORMAL         0x00008000
  166 #define DC_ISR_NORMAL           0x00010000
  167 #define DC_ISR_RX_STATE         0x000E0000
  168 #define DC_ISR_TX_STATE         0x00700000
  169 #define DC_ISR_BUSERRTYPE       0x03800000
  170 #define DC_ISR_100MBPSLINK      0x08000000
  171 #define DC_ISR_MAGICKPACK       0x10000000
  172 
  173 #define DC_RXSTATE_STOPPED      0x00000000      /* 000 - Stopped */
  174 #define DC_RXSTATE_FETCH        0x00020000      /* 001 - Fetching descriptor */
  175 #define DC_RXSTATE_ENDCHECK     0x00040000      /* 010 - check for rx end */
  176 #define DC_RXSTATE_WAIT         0x00060000      /* 011 - waiting for packet */
  177 #define DC_RXSTATE_SUSPEND      0x00080000      /* 100 - suspend rx */
  178 #define DC_RXSTATE_CLOSE        0x000A0000      /* 101 - close tx desc */
  179 #define DC_RXSTATE_FLUSH        0x000C0000      /* 110 - flush from FIFO */
  180 #define DC_RXSTATE_DEQUEUE      0x000E0000      /* 111 - dequeue from FIFO */
  181 
  182 #define DC_TXSTATE_RESET        0x00000000      /* 000 - reset */
  183 #define DC_TXSTATE_FETCH        0x00100000      /* 001 - fetching descriptor */
  184 #define DC_TXSTATE_WAITEND      0x00200000      /* 010 - wait for tx end */
  185 #define DC_TXSTATE_READING      0x00300000      /* 011 - read and enqueue */
  186 #define DC_TXSTATE_RSVD         0x00400000      /* 100 - reserved */
  187 #define DC_TXSTATE_SETUP        0x00500000      /* 101 - setup packet */
  188 #define DC_TXSTATE_SUSPEND      0x00600000      /* 110 - suspend tx */
  189 #define DC_TXSTATE_CLOSE        0x00700000      /* 111 - close tx desc */
  190 
  191 /*
  192  * Network config bits.
  193  */
  194 #define DC_NETCFG_RX_HASHPERF   0x00000001
  195 #define DC_NETCFG_RX_ON         0x00000002
  196 #define DC_NETCFG_RX_HASHONLY   0x00000004
  197 #define DC_NETCFG_RX_BADFRAMES  0x00000008
  198 #define DC_NETCFG_RX_INVFILT    0x00000010
  199 #define DC_NETCFG_BACKOFFCNT    0x00000020
  200 #define DC_NETCFG_RX_PROMISC    0x00000040
  201 #define DC_NETCFG_RX_ALLMULTI   0x00000080
  202 #define DC_NETCFG_FULLDUPLEX    0x00000200
  203 #define DC_NETCFG_LOOPBACK      0x00000C00
  204 #define DC_NETCFG_FORCECOLL     0x00001000
  205 #define DC_NETCFG_TX_ON         0x00002000
  206 #define DC_NETCFG_TX_THRESH     0x0000C000
  207 #define DC_NETCFG_TX_BACKOFF    0x00020000
  208 #define DC_NETCFG_PORTSEL       0x00040000      /* 0 == 10, 1 == 100 */
  209 #define DC_NETCFG_HEARTBEAT     0x00080000
  210 #define DC_NETCFG_STORENFWD     0x00200000
  211 #define DC_NETCFG_SPEEDSEL      0x00400000      /* 1 == 10, 0 == 100 */
  212 #define DC_NETCFG_PCS           0x00800000
  213 #define DC_NETCFG_SCRAMBLER     0x01000000
  214 #define DC_NETCFG_NO_RXCRC      0x02000000
  215 #define DC_NETCFG_RX_ALL        0x40000000
  216 #define DC_NETCFG_CAPEFFECT     0x80000000
  217 
  218 #define DC_OPMODE_NORM          0x00000000
  219 #define DC_OPMODE_INTLOOP       0x00000400
  220 #define DC_OPMODE_EXTLOOP       0x00000800
  221 
  222 #if 0
  223 #define DC_TXTHRESH_72BYTES     0x00000000
  224 #define DC_TXTHRESH_96BYTES     0x00004000
  225 #define DC_TXTHRESH_128BYTES    0x00008000
  226 #define DC_TXTHRESH_160BYTES    0x0000C000
  227 #endif
  228 
  229 #define DC_TXTHRESH_MIN         0x00000000
  230 #define DC_TXTHRESH_INC         0x00004000
  231 #define DC_TXTHRESH_MAX         0x0000C000
  232 
  233 
  234 /*
  235  * Interrupt mask bits.
  236  */
  237 #define DC_IMR_TX_OK            0x00000001
  238 #define DC_IMR_TX_IDLE          0x00000002
  239 #define DC_IMR_TX_NOBUF         0x00000004
  240 #define DC_IMR_TX_JABBERTIMEO   0x00000008
  241 #define DC_IMR_LINKGOOD         0x00000010
  242 #define DC_IMR_TX_UNDERRUN      0x00000020
  243 #define DC_IMR_RX_OK            0x00000040
  244 #define DC_IMR_RX_NOBUF         0x00000080
  245 #define DC_IMR_RX_READ          0x00000100
  246 #define DC_IMR_RX_WATDOGTIMEO   0x00000200
  247 #define DC_IMR_TX_EARLY         0x00000400
  248 #define DC_IMR_TIMER_EXPIRED    0x00000800
  249 #define DC_IMR_LINKFAIL         0x00001000
  250 #define DC_IMR_BUS_ERR          0x00002000
  251 #define DC_IMR_RX_EARLY         0x00004000
  252 #define DC_IMR_ABNORMAL         0x00008000
  253 #define DC_IMR_NORMAL           0x00010000
  254 #define DC_IMR_100MBPSLINK      0x08000000
  255 #define DC_IMR_MAGICKPACK       0x10000000
  256 
  257 #define DC_INTRS        \
  258         (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\
  259         DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR|              \
  260         DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/)
  261 /*
  262  * Serial I/O (EEPROM/ROM) bits.
  263  */
  264 #define DC_SIO_EE_CS            0x00000001      /* EEPROM chip select */
  265 #define DC_SIO_EE_CLK           0x00000002      /* EEPROM clock */
  266 #define DC_SIO_EE_DATAIN        0x00000004      /* EEPROM data output */
  267 #define DC_SIO_EE_DATAOUT       0x00000008      /* EEPROM data input */
  268 #define DC_SIO_ROMDATA4         0x00000010
  269 #define DC_SIO_ROMDATA5         0x00000020
  270 #define DC_SIO_ROMDATA6         0x00000040
  271 #define DC_SIO_ROMDATA7         0x00000080
  272 #define DC_SIO_EESEL            0x00000800
  273 #define DC_SIO_ROMSEL           0x00001000
  274 #define DC_SIO_ROMCTL_WRITE     0x00002000
  275 #define DC_SIO_ROMCTL_READ      0x00004000
  276 #define DC_SIO_MII_CLK          0x00010000      /* MDIO clock */
  277 #define DC_SIO_MII_DATAOUT      0x00020000      /* MDIO data out */
  278 #define DC_SIO_MII_DIR          0x00040000      /* MDIO dir */
  279 #define DC_SIO_MII_DATAIN       0x00080000      /* MDIO data in */
  280 
  281 #define DC_EECMD_WRITE          0x140
  282 #define DC_EECMD_READ           0x180
  283 #define DC_EECMD_ERASE          0x1c0
  284 
  285 #define DC_EE_NODEADDR_OFFSET   0x70
  286 #define DC_EE_NODEADDR          10
  287 
  288 /*
  289  * General purpose timer register
  290  */
  291 #define DC_TIMER_VALUE          0x0000FFFF
  292 #define DC_TIMER_CONTINUOUS     0x00010000
  293 
  294 /*
  295  * 10baseT status register
  296  */
  297 #define DC_TSTAT_MIIACT         0x00000001 /* MII port activity */
  298 #define DC_TSTAT_LS100          0x00000002 /* link status of 100baseTX */
  299 #define DC_TSTAT_LS10           0x00000004 /* link status of 10baseT */
  300 #define DC_TSTAT_AUTOPOLARITY   0x00000008
  301 #define DC_TSTAT_AUIACT         0x00000100 /* AUI activity */
  302 #define DC_TSTAT_10BTACT        0x00000200 /* 10baseT activity */
  303 #define DC_TSTAT_NSN            0x00000400 /* non-stable FLPs detected */
  304 #define DC_TSTAT_REMFAULT       0x00000800
  305 #define DC_TSTAT_ANEGSTAT       0x00007000
  306 #define DC_TSTAT_LP_CAN_NWAY    0x00008000 /* link partner supports NWAY */
  307 #define DC_TSTAT_LPCODEWORD     0xFFFF0000 /* link partner's code word */
  308 
  309 #define DC_ASTAT_DISABLE        0x00000000
  310 #define DC_ASTAT_TXDISABLE      0x00001000
  311 #define DC_ASTAT_ABDETECT       0x00002000
  312 #define DC_ASTAT_ACKDETECT      0x00003000
  313 #define DC_ASTAT_CMPACKDETECT   0x00004000
  314 #define DC_ASTAT_AUTONEGCMP     0x00005000
  315 #define DC_ASTAT_LINKCHECK      0x00006000
  316 
  317 /*
  318  * PHY reset register
  319  */
  320 #define DC_SIA_RESET            0x00000001
  321 #define DC_SIA_AUI              0x00000008 /* AUI or 10baseT */
  322 
  323 /*
  324  * 10baseT control register
  325  */
  326 #define DC_TCTL_ENCODER_ENB     0x00000001
  327 #define DC_TCTL_LOOPBACK        0x00000002
  328 #define DC_TCTL_DRIVER_ENB      0x00000004
  329 #define DC_TCTL_LNKPULSE_ENB    0x00000008
  330 #define DC_TCTL_HALFDUPLEX      0x00000040
  331 #define DC_TCTL_AUTONEGENBL     0x00000080
  332 #define DC_TCTL_RX_SQUELCH      0x00000100
  333 #define DC_TCTL_COLL_SQUELCH    0x00000200
  334 #define DC_TCTL_COLL_DETECT     0x00000400
  335 #define DC_TCTL_SQE_ENB         0x00000800
  336 #define DC_TCTL_LINKTEST        0x00001000
  337 #define DC_TCTL_AUTOPOLARITY    0x00002000
  338 #define DC_TCTL_SET_POL_PLUS    0x00004000
  339 #define DC_TCTL_AUTOSENSE       0x00008000      /* 10bt/AUI autosense */
  340 #define DC_TCTL_100BTXHALF      0x00010000
  341 #define DC_TCTL_100BTXFULL      0x00020000
  342 #define DC_TCTL_100BT4          0x00040000
  343 
  344 /*
  345  * Watchdog timer register
  346  */
  347 #define DC_WDOG_JABBERDIS       0x00000001
  348 #define DC_WDOG_HOSTUNJAB       0x00000002
  349 #define DC_WDOG_JABBERCLK       0x00000004
  350 #define DC_WDOG_RXWDOGDIS       0x00000010
  351 #define DC_WDOG_RXWDOGCLK       0x00000020
  352 #define DC_WDOG_MUSTBEZERO      0x00000100
  353 #define DC_WDOG_AUIBNC          0x00100000
  354 #define DC_WDOG_ACTIVITY        0x00200000
  355 #define DC_WDOG_RX_MATCH        0x00400000
  356 #define DC_WDOG_LINK            0x00800000
  357 #define DC_WDOG_CTLWREN         0x08000000
  358 
  359 /*
  360  * Size of a setup frame.
  361  */
  362 #define DC_SFRAME_LEN           192
  363 
  364 /*
  365  * 21x4x TX/RX list structure.
  366  */
  367 
  368 struct dc_desc {
  369         u_int32_t               dc_status;
  370         u_int32_t               dc_ctl;
  371         u_int32_t               dc_ptr1;
  372         u_int32_t               dc_ptr2;
  373 };
  374 
  375 #define dc_data         dc_ptr1
  376 #define dc_next         dc_ptr2
  377 
  378 #define DC_RXSTAT_FIFOOFLOW     0x00000001
  379 #define DC_RXSTAT_CRCERR        0x00000002
  380 #define DC_RXSTAT_DRIBBLE       0x00000004
  381 #define DC_RXSTAT_MIIERE        0x00000008
  382 #define DC_RXSTAT_WATCHDOG      0x00000010
  383 #define DC_RXSTAT_FRAMETYPE     0x00000020      /* 0 == IEEE 802.3 */
  384 #define DC_RXSTAT_COLLSEEN      0x00000040
  385 #define DC_RXSTAT_GIANT         0x00000080
  386 #define DC_RXSTAT_LASTFRAG      0x00000100
  387 #define DC_RXSTAT_FIRSTFRAG     0x00000200
  388 #define DC_RXSTAT_MULTICAST     0x00000400
  389 #define DC_RXSTAT_RUNT          0x00000800
  390 #define DC_RXSTAT_RXTYPE        0x00003000
  391 #define DC_RXSTAT_DE            0x00004000
  392 #define DC_RXSTAT_RXERR         0x00008000
  393 #define DC_RXSTAT_RXLEN         0x3FFF0000
  394 #define DC_RXSTAT_OWN           0x80000000
  395 
  396 #define DC_RXBYTES(x)           ((x & DC_RXSTAT_RXLEN) >> 16)
  397 #define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN)
  398 
  399 #define DC_RXCTL_BUFLEN1        0x00000FFF
  400 #define DC_RXCTL_BUFLEN2        0x00FFF000
  401 #define DC_RXCTL_RLINK          0x01000000
  402 #define DC_RXCTL_RLAST          0x02000000
  403 
  404 #define DC_TXSTAT_DEFER         0x00000001
  405 #define DC_TXSTAT_UNDERRUN      0x00000002
  406 #define DC_TXSTAT_LINKFAIL      0x00000003
  407 #define DC_TXSTAT_COLLCNT       0x00000078
  408 #define DC_TXSTAT_SQE           0x00000080
  409 #define DC_TXSTAT_EXCESSCOLL    0x00000100
  410 #define DC_TXSTAT_LATECOLL      0x00000200
  411 #define DC_TXSTAT_NOCARRIER     0x00000400
  412 #define DC_TXSTAT_CARRLOST      0x00000800
  413 #define DC_TXSTAT_JABTIMEO      0x00004000
  414 #define DC_TXSTAT_ERRSUM        0x00008000
  415 #define DC_TXSTAT_OWN           0x80000000
  416 
  417 #define DC_TXCTL_BUFLEN1        0x000007FF
  418 #define DC_TXCTL_BUFLEN2        0x003FF800
  419 #define DC_TXCTL_FILTTYPE0      0x00400000
  420 #define DC_TXCTL_PAD            0x00800000
  421 #define DC_TXCTL_TLINK          0x01000000
  422 #define DC_TXCTL_TLAST          0x02000000
  423 #define DC_TXCTL_NOCRC          0x04000000
  424 #define DC_TXCTL_SETUP          0x08000000
  425 #define DC_TXCTL_FILTTYPE1      0x10000000
  426 #define DC_TXCTL_FIRSTFRAG      0x20000000
  427 #define DC_TXCTL_LASTFRAG       0x40000000
  428 #define DC_TXCTL_FINT           0x80000000
  429 
  430 #define DC_FILTER_PERFECT       0x00000000
  431 #define DC_FILTER_HASHPERF      0x00400000
  432 #define DC_FILTER_INVERSE       0x10000000
  433 #define DC_FILTER_HASHONLY      0x10400000
  434 
  435 #define DC_MAXFRAGS             16
  436 #ifdef DEVICE_POLLING
  437 #define DC_RX_LIST_CNT          192
  438 #else
  439 #define DC_RX_LIST_CNT          64
  440 #endif
  441 #define DC_TX_LIST_CNT          256
  442 #define DC_MIN_FRAMELEN         60
  443 #define DC_RXLEN                1536
  444 
  445 #define DC_INC(x, y)    (x) = (x + 1) % y
  446 
  447 struct dc_list_data {
  448         struct dc_desc          dc_rx_list[DC_RX_LIST_CNT];
  449         struct dc_desc          dc_tx_list[DC_TX_LIST_CNT];
  450 };
  451 
  452 struct dc_chain_data {
  453         struct mbuf             *dc_rx_chain[DC_RX_LIST_CNT];
  454         struct mbuf             *dc_tx_chain[DC_TX_LIST_CNT];
  455         u_int32_t               dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)];
  456         u_int8_t                dc_pad[DC_MIN_FRAMELEN];
  457         int                     dc_tx_prod;
  458         int                     dc_tx_cons;
  459         int                     dc_tx_cnt;
  460         int                     dc_rx_prod;
  461 };
  462 
  463 struct dc_mediainfo {
  464         int                     dc_media;
  465         u_int8_t                *dc_gp_ptr;
  466         u_int8_t                dc_gp_len;
  467         u_int8_t                *dc_reset_ptr;
  468         u_int8_t                dc_reset_len;
  469         struct dc_mediainfo     *dc_next;
  470 };
  471 
  472 
  473 struct dc_type {
  474         u_int16_t               dc_vid;
  475         u_int16_t               dc_did;
  476         char                    *dc_name;
  477 };
  478 
  479 struct dc_mii_frame {
  480         u_int8_t                mii_stdelim;
  481         u_int8_t                mii_opcode;
  482         u_int8_t                mii_phyaddr;
  483         u_int8_t                mii_regaddr;
  484         u_int8_t                mii_turnaround;
  485         u_int16_t               mii_data;
  486 };
  487 
  488 /*
  489  * MII constants
  490  */
  491 #define DC_MII_STARTDELIM       0x01
  492 #define DC_MII_READOP           0x02
  493 #define DC_MII_WRITEOP          0x01
  494 #define DC_MII_TURNAROUND       0x02
  495 
  496 
  497 /*
  498  * Registers specific to clone devices.
  499  * This mainly relates to RX filter programming: not all 21x4x clones
  500  * use the standard DEC filter programming mechanism.
  501  */
  502 
  503 /*
  504  * ADMtek specific registers and constants for the AL981 and AN985.
  505  * The AN985 doesn't use the magic PHY registers.
  506  */
  507 #define DC_AL_CR                0x88    /* command register */
  508 #define DC_AL_PAR0              0xA4    /* station address */
  509 #define DC_AL_PAR1              0xA8    /* station address */
  510 #define DC_AL_MAR0              0xAC    /* multicast hash filter */
  511 #define DC_AL_MAR1              0xB0    /* multicast hash filter */
  512 #define DC_AL_BMCR              0xB4    /* built in PHY control */
  513 #define DC_AL_BMSR              0xB8    /* built in PHY status */
  514 #define DC_AL_VENID             0xBC    /* built in PHY ID0 */
  515 #define DC_AL_DEVID             0xC0    /* built in PHY ID1 */
  516 #define DC_AL_ANAR              0xC4    /* built in PHY autoneg advert */
  517 #define DC_AL_LPAR              0xC8    /* bnilt in PHY link part. ability */
  518 #define DC_AL_ANER              0xCC    /* built in PHY autoneg expansion */
  519 
  520 #define DC_AL_CR_ATUR           0x00000001 /* automatic TX underrun recovery */
  521 #define DC_ADMTEK_PHYADDR       0x1
  522 #define DC_AL_EE_NODEADDR       4
  523 /* End of ADMtek specific registers */
  524 
  525 /*
  526  * ASIX specific registers.
  527  */
  528 #define DC_AX_FILTIDX           0x68    /* RX filter index */
  529 #define DC_AX_FILTDATA          0x70    /* RX filter data */
  530 
  531 /*
  532  * Special ASIX-specific bits in the ASIX NETCFG register (CSR6).
  533  */
  534 #define DC_AX_NETCFG_RX_BROAD   0x00000100 
  535 
  536 /*
  537  * RX Filter Index Register values
  538  */
  539 #define DC_AX_FILTIDX_PAR0      0x00000000
  540 #define DC_AX_FILTIDX_PAR1      0x00000001
  541 #define DC_AX_FILTIDX_MAR0      0x00000002
  542 #define DC_AX_FILTIDX_MAR1      0x00000003
  543 /* End of ASIX specific registers */
  544 
  545 /*
  546  * Macronix specific registers. The Macronix chips have a special
  547  * register for reading the NWAY status, which we don't use, plus
  548  * a magic packet register, which we need to tweak a bit per the
  549  * Macronix application notes.
  550  */
  551 #define DC_MX_MAGICPACKET       0x80
  552 #define DC_MX_NWAYSTAT          0xA0
  553 
  554 /*
  555  * Magic packet register
  556  */
  557 #define DC_MX_MPACK_DISABLE     0x00400000
  558 
  559 /*
  560  * NWAY status register.
  561  */
  562 #define DC_MX_NWAY_10BTHALF     0x08000000
  563 #define DC_MX_NWAY_10BTFULL     0x10000000
  564 #define DC_MX_NWAY_100BTHALF    0x20000000
  565 #define DC_MX_NWAY_100BTFULL    0x40000000
  566 #define DC_MX_NWAY_100BT4       0x80000000
  567 
  568 /*
  569  * These are magic values that must be written into CSR16
  570  * (DC_MX_MAGICPACKET) in order to put the chip into proper
  571  * operating mode. The magic numbers are documented in the
  572  * Macronix 98715 application notes.
  573  */
  574 #define DC_MX_MAGIC_98713       0x0F370000
  575 #define DC_MX_MAGIC_98713A      0x0B3C0000
  576 #define DC_MX_MAGIC_98715       0x0B3C0000
  577 #define DC_MX_MAGIC_98725       0x0B3C0000
  578 /* End of Macronix specific registers */
  579 
  580 /*
  581  * PNIC 82c168/82c169 specific registers.
  582  * The PNIC has its own special NWAY support, which doesn't work,
  583  * and shortcut ways of reading the EEPROM and MII bus.
  584  */
  585 #define DC_PN_GPIO              0x60    /* general purpose pins control */
  586 #define DC_PN_PWRUP_CFG         0x90    /* config register, set by EEPROM */
  587 #define DC_PN_SIOCTL            0x98    /* serial EEPROM control register */
  588 #define DC_PN_MII               0xA0    /* MII access register */
  589 #define DC_PN_NWAY              0xB8    /* Internal NWAY register */
  590 
  591 /* Serial I/O EEPROM register */
  592 #define DC_PN_SIOCTL_DATA       0x0000003F
  593 #define DC_PN_SIOCTL_OPCODE     0x00000300
  594 #define DC_PN_SIOCTL_BUSY       0x80000000
  595 
  596 #define DC_PN_EEOPCODE_ERASE    0x00000300
  597 #define DC_PN_EEOPCODE_READ     0x00000600
  598 #define DC_PN_EEOPCODE_WRITE    0x00000100
  599 
  600 /*
  601  * The first two general purpose pins control speed selection and
  602  * 100Mbps loopback on the 82c168 chip. The control bits should always
  603  * be set (to make the data pins outputs) and the speed selction and
  604  * loopback bits set accordingly when changing media. Physically, this
  605  * will set the state of a relay mounted on the card.
  606  */
  607 #define DC_PN_GPIO_DATA0        0x000000001
  608 #define DC_PN_GPIO_DATA1        0x000000002
  609 #define DC_PN_GPIO_DATA2        0x000000004
  610 #define DC_PN_GPIO_DATA3        0x000000008
  611 #define DC_PN_GPIO_CTL0         0x000000010
  612 #define DC_PN_GPIO_CTL1         0x000000020
  613 #define DC_PN_GPIO_CTL2         0x000000040
  614 #define DC_PN_GPIO_CTL3         0x000000080
  615 #define DC_PN_GPIO_SPEEDSEL     DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */
  616 #define DC_PN_GPIO_100TX_LOOP   DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */
  617 #define DC_PN_GPIO_BNC_ENB      DC_PN_GPIO_DATA2
  618 #define DC_PN_GPIO_100TX_LNK    DC_PN_GPIO_DATA3
  619 #define DC_PN_GPIO_SETBIT(sc, r)                        \
  620         DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4)))
  621 #define DC_PN_GPIO_CLRBIT(sc, r)                        \
  622         {                                               \
  623                 DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4));  \
  624                 DC_CLRBIT(sc, DC_PN_GPIO, (r));         \
  625         }
  626         
  627 /* shortcut MII access register */
  628 #define DC_PN_MII_DATA          0x0000FFFF
  629 #define DC_PN_MII_RESERVER      0x00020000
  630 #define DC_PN_MII_REGADDR       0x007C0000
  631 #define DC_PN_MII_PHYADDR       0x0F800000
  632 #define DC_PN_MII_OPCODE        0x30000000
  633 #define DC_PN_MII_BUSY          0x80000000
  634 
  635 #define DC_PN_MIIOPCODE_READ    0x60020000
  636 #define DC_PN_MIIOPCODE_WRITE   0x50020000
  637 
  638 /* Internal NWAY bits */
  639 #define DC_PN_NWAY_RESET        0x00000001      /* reset */
  640 #define DC_PN_NWAY_PDOWN        0x00000002      /* power down */
  641 #define DC_PN_NWAY_BYPASS       0x00000004      /* bypass */
  642 #define DC_PN_NWAY_AUILOWCUR    0x00000008      /* AUI low current */
  643 #define DC_PN_NWAY_TPEXTEND     0x00000010      /* low squelch voltage */
  644 #define DC_PN_NWAY_POLARITY     0x00000020      /* 0 == on, 1 == off */
  645 #define DC_PN_NWAY_TP           0x00000040      /* 1 == tp, 0 == AUI */
  646 #define DC_PN_NWAY_AUIVOLT      0x00000080      /* 1 == full, 0 == half */
  647 #define DC_PN_NWAY_DUPLEX       0x00000100      /* LED, 1 == full, 0 == half */
  648 #define DC_PN_NWAY_LINKTEST     0x00000200      /* 0 == on, 1 == off */
  649 #define DC_PN_NWAY_AUTODETECT   0x00000400      /* 1 == off, 0 == on */
  650 #define DC_PN_NWAY_SPEEDSEL     0x00000800      /* LED, 0 = 10, 1 == 100 */
  651 #define DC_PN_NWAY_NWAY_ENB     0x00001000      /* 0 == off, 1 == on */
  652 #define DC_PN_NWAY_CAP10HDX     0x00002000
  653 #define DC_PN_NWAY_CAP10FDX     0x00004000
  654 #define DC_PN_NWAY_CAP100FDX    0x00008000
  655 #define DC_PN_NWAY_CAP100HDX    0x00010000
  656 #define DC_PN_NWAY_CAP100T4     0x00020000
  657 #define DC_PN_NWAY_ANEGRESTART  0x02000000      /* resets when aneg done */
  658 #define DC_PN_NWAY_REMFAULT     0x04000000
  659 #define DC_PN_NWAY_LPAR10HDX    0x08000000
  660 #define DC_PN_NWAY_LPAR10FDX    0x10000000
  661 #define DC_PN_NWAY_LPAR100FDX   0x20000000
  662 #define DC_PN_NWAY_LPAR100HDX   0x40000000
  663 #define DC_PN_NWAY_LPAR100T4    0x80000000
  664 
  665 /* End of PNIC specific registers */
  666 
  667 /*
  668  * CONEXANT specific registers.
  669  */
  670 
  671 #define DC_CONEXANT_PHYADDR     0x1
  672 #define DC_CONEXANT_EE_NODEADDR 0x19A
  673 
  674 /* End of CONEXANT specific registers */
  675 
  676 
  677 struct dc_softc {
  678         struct arpcom           arpcom;         /* interface info */
  679         bus_space_handle_t      dc_bhandle;     /* bus space handle */
  680         bus_space_tag_t         dc_btag;        /* bus space tag */
  681         void                    *dc_intrhand;
  682         struct resource         *dc_irq;
  683         struct resource         *dc_res;
  684         struct dc_type          *dc_info;       /* adapter info */
  685         device_t                dc_miibus;
  686         u_int8_t                dc_unit;        /* interface number */
  687         u_int8_t                dc_type;
  688         u_int8_t                dc_pmode;
  689         u_int8_t                dc_link;
  690         u_int8_t                dc_cachesize;
  691         int                     dc_romwidth;
  692         int                     dc_pnic_rx_bug_save;
  693         unsigned char           *dc_pnic_rx_buf;
  694         int                     dc_if_flags;
  695         int                     dc_if_media;
  696         u_int32_t               dc_flags;
  697         u_int32_t               dc_txthresh;
  698         u_int8_t                *dc_srom;
  699         struct dc_mediainfo     *dc_mi;
  700         struct dc_list_data     *dc_ldata;
  701         struct dc_chain_data    dc_cdata;
  702         struct callout_handle   dc_stat_ch;
  703 #ifdef __alpha__
  704         int                     dc_srm_media;
  705 #endif
  706 #ifdef  DEVICE_POLLING
  707         int                     rxcycles;       /* ... when polling */
  708 #endif
  709         int                     suspended;      /* 0 = normal  1 = suspended */
  710 
  711         u_int32_t               saved_maps[5];  /* pci data */
  712         u_int32_t               saved_biosaddr;
  713         u_int8_t                saved_intline;
  714         u_int8_t                saved_cachelnsz;
  715         u_int8_t                saved_lattimer;
  716 };
  717 
  718 #define DC_TX_POLL              0x00000001
  719 #define DC_TX_COALESCE          0x00000002
  720 #define DC_TX_ADMTEK_WAR        0x00000004
  721 #define DC_TX_USE_TX_INTR       0x00000008
  722 #define DC_RX_FILTER_TULIP      0x00000010
  723 #define DC_TX_INTR_FIRSTFRAG    0x00000020
  724 #define DC_PNIC_RX_BUG_WAR      0x00000040
  725 #define DC_TX_FIXED_RING        0x00000080
  726 #define DC_TX_STORENFWD         0x00000100
  727 #define DC_REDUCED_MII_POLL     0x00000200
  728 #define DC_TX_INTR_ALWAYS       0x00000400
  729 #define DC_21143_NWAY           0x00000800
  730 #define DC_128BIT_HASH          0x00001000
  731 #define DC_64BIT_HASH           0x00002000
  732 #define DC_TULIP_LEDS           0x00004000
  733 #define DC_TX_ONE               0x00008000
  734 #define DC_TX_ALIGN             0x00010000      /* align mbuf on tx */
  735 
  736 /*
  737  * register space access macros
  738  */
  739 #define CSR_WRITE_4(sc, reg, val)       \
  740         bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val)
  741 
  742 #define CSR_READ_4(sc, reg)             \
  743         bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg)
  744 
  745 #define DC_TIMEOUT              1000
  746 #define ETHER_ALIGN             2
  747 
  748 /*
  749  * General constants that are fun to know.
  750  */
  751 
  752 /*
  753  * DEC PCI vendor ID
  754  */
  755 #define DC_VENDORID_DEC         0x1011
  756 
  757 /*
  758  * DEC/Intel 21143 PCI device ID
  759  */
  760 #define DC_DEVICEID_21143       0x0019
  761 
  762 /*
  763  * Macronix PCI vendor ID
  764  */
  765 #define DC_VENDORID_MX          0x10D9
  766 
  767 /*
  768  * Macronix PMAC device IDs.
  769  */
  770 #define DC_DEVICEID_98713       0x0512
  771 #define DC_DEVICEID_987x5       0x0531
  772 #define DC_DEVICEID_98727       0x0532
  773 #define DC_DEVICEID_98732       0x0532
  774 
  775 /* Macronix PCI revision codes. */
  776 #define DC_REVISION_98713       0x00
  777 #define DC_REVISION_98713A      0x10
  778 #define DC_REVISION_98715       0x20
  779 #define DC_REVISION_98715AEC_C  0x25
  780 #define DC_REVISION_98725       0x30
  781 
  782 /*
  783  * Compex PCI vendor ID.
  784  */
  785 #define DC_VENDORID_CP          0x11F6
  786 
  787 /*
  788  * Compex PMAC PCI device IDs.
  789  */
  790 #define DC_DEVICEID_98713_CP    0x9881
  791 
  792 /*
  793  * Lite-On PNIC PCI vendor ID
  794  */
  795 #define DC_VENDORID_LO          0x11AD
  796 
  797 /*
  798  * 82c168/82c169 PNIC device IDs. Both chips have the same device
  799  * ID but different revisions. Revision 0x10 is the 82c168, and
  800  * 0x20 is the 82c169.
  801  */
  802 #define DC_DEVICEID_82C168      0x0002
  803 
  804 #define DC_REVISION_82C168      0x10
  805 #define DC_REVISION_82C169      0x20
  806 
  807 /* 
  808  * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A
  809  * with wake on lan/magic packet support.
  810  */
  811 #define DC_DEVICEID_82C115      0xc115
  812 
  813 /*
  814  * Davicom vendor ID.
  815  */
  816 #define DC_VENDORID_DAVICOM     0x1282
  817 
  818 /*
  819  * Davicom device IDs.
  820  */
  821 #define DC_DEVICEID_DM9009      0x9009
  822 #define DC_DEVICEID_DM9100      0x9100
  823 #define DC_DEVICEID_DM9102      0x9102
  824 
  825 /*
  826  * The DM9102A has the same PCI device ID as the DM9102,
  827  * but a higher revision code.
  828  */
  829 #define DC_REVISION_DM9102      0x10
  830 #define DC_REVISION_DM9102A     0x30
  831 
  832 /*
  833  * ADMtek vendor ID.
  834  */
  835 #define DC_VENDORID_ADMTEK      0x1317
  836 
  837 /*
  838  * ADMtek device IDs.
  839  */
  840 #define DC_DEVICEID_AL981       0x0981
  841 #define DC_DEVICEID_AN985       0x0985
  842 #define DC_DEVICEID_ADM9511     0x9511 
  843 #define DC_DEVICEID_ADM9513     0x9513 
  844 
  845 
  846 /*
  847  * 3COM PCI vendor ID
  848  */
  849 #define DC_VENDORID_3COM        0x10b7
  850 
  851 /*
  852  * 3COM OfficeConnect 10/100B (3CSOHO100B-TX)
  853  */
  854 #define DC_DEVICEID_3CSOHOB     0x9300
  855 
  856 /*
  857  * ASIX vendor ID.
  858  */
  859 #define DC_VENDORID_ASIX        0x125B
  860 
  861 /*
  862  * ASIX device IDs.
  863  */
  864 #define DC_DEVICEID_AX88140A    0x1400
  865 
  866 /*
  867  * The ASIX AX88140 and ASIX AX88141 have the same vendor and
  868  * device IDs but different revision values.
  869  */
  870 #define DC_REVISION_88140       0x00
  871 #define DC_REVISION_88141       0x10
  872 
  873 /*
  874  * Accton vendor ID.
  875  */
  876 #define DC_VENDORID_ACCTON      0x1113
  877 
  878 /*
  879  * Accton device IDs.
  880  */
  881 #define DC_DEVICEID_EN1217      0x1217
  882 #define DC_DEVICEID_EN2242      0x1216
  883 
  884 /*
  885  * Conexant vendor ID.
  886  */
  887 #define DC_VENDORID_CONEXANT    0x14f1
  888 
  889 /*
  890  * Conexant device IDs.
  891  */
  892 #define DC_DEVICEID_RS7112      0x1803
  893 
  894 /*
  895  * PCI low memory base and low I/O base register, and
  896  * other PCI registers.
  897  */
  898 
  899 #define DC_PCI_CFID             0x00    /* Id */
  900 #define DC_PCI_CFCS             0x04    /* Command and status */
  901 #define DC_PCI_CFRV             0x08    /* Revision */
  902 #define DC_PCI_CFLT             0x0C    /* Latency timer */
  903 #define DC_PCI_CFBIO            0x10    /* Base I/O address */
  904 #define DC_PCI_CFBMA            0x14    /* Base memory address */
  905 #define DC_PCI_CCIS             0x28    /* Card info struct */
  906 #define DC_PCI_CSID             0x2C    /* Subsystem ID */
  907 #define DC_PCI_CBER             0x30    /* Expansion ROM base address */
  908 #define DC_PCI_CCAP             0x34    /* Caps pointer - PD/TD chip only */
  909 #define DC_PCI_CFIT             0x3C    /* Interrupt */
  910 #define DC_PCI_CFDD             0x40    /* Device and driver area */
  911 #define DC_PCI_CWUA0            0x44    /* Wake-Up LAN addr 0 */
  912 #define DC_PCI_CWUA1            0x48    /* Wake-Up LAN addr 1 */
  913 #define DC_PCI_SOP0             0x4C    /* SecureON passwd 0 */
  914 #define DC_PCI_SOP1             0x50    /* SecureON passwd 1 */
  915 #define DC_PCI_CWUC             0x54    /* Configuration Wake-Up cmd */
  916 #define DC_PCI_CCID             0xDC    /* Capability ID - PD/TD only */
  917 #define DC_PCI_CPMC             0xE0    /* Pwrmgmt ctl & sts - PD/TD only */
  918 
  919 /* PCI ID register */
  920 #define DC_CFID_VENDOR          0x0000FFFF
  921 #define DC_CFID_DEVICE          0xFFFF0000
  922 
  923 /* PCI command/status register */
  924 #define DC_CFCS_IOSPACE         0x00000001 /* I/O space enable */
  925 #define DC_CFCS_MEMSPACE        0x00000002 /* memory space enable */
  926 #define DC_CFCS_BUSMASTER       0x00000004 /* bus master enable */
  927 #define DC_CFCS_MWI_ENB         0x00000010 /* mem write and inval enable */
  928 #define DC_CFCS_PARITYERR_ENB   0x00000040 /* parity error enable */
  929 #define DC_CFCS_SYSERR_ENB      0x00000100 /* system error enable */
  930 #define DC_CFCS_NEWCAPS         0x00100000 /* new capabilities */
  931 #define DC_CFCS_FAST_B2B        0x00800000 /* fast back-to-back capable */
  932 #define DC_CFCS_DATAPARITY      0x01000000 /* Parity error report */
  933 #define DC_CFCS_DEVSELTIM       0x06000000 /* devsel timing */
  934 #define DC_CFCS_TGTABRT         0x10000000 /* received target abort */
  935 #define DC_CFCS_MASTERABRT      0x20000000 /* received master abort */
  936 #define DC_CFCS_SYSERR          0x40000000 /* asserted system error */
  937 #define DC_CFCS_PARITYERR       0x80000000 /* asserted parity error */
  938 
  939 /* PCI revision register */
  940 #define DC_CFRV_STEPPING        0x0000000F
  941 #define DC_CFRV_REVISION        0x000000F0
  942 #define DC_CFRV_SUBCLASS        0x00FF0000
  943 #define DC_CFRV_BASECLASS       0xFF000000
  944 
  945 #define DC_21143_PB_REV         0x00000030
  946 #define DC_21143_TB_REV         0x00000030
  947 #define DC_21143_PC_REV         0x00000030
  948 #define DC_21143_TC_REV         0x00000030
  949 #define DC_21143_PD_REV         0x00000041
  950 #define DC_21143_TD_REV         0x00000041
  951 
  952 /* PCI latency timer register */
  953 #define DC_CFLT_CACHELINESIZE   0x000000FF
  954 #define DC_CFLT_LATENCYTIMER    0x0000FF00
  955 
  956 /* PCI subsystem ID register */
  957 #define DC_CSID_VENDOR          0x0000FFFF
  958 #define DC_CSID_DEVICE          0xFFFF0000
  959 
  960 /* PCI cababilities pointer */
  961 #define DC_CCAP_OFFSET          0x000000FF
  962 
  963 /* PCI interrupt config register */
  964 #define DC_CFIT_INTLINE         0x000000FF
  965 #define DC_CFIT_INTPIN          0x0000FF00
  966 #define DC_CFIT_MIN_GNT         0x00FF0000
  967 #define DC_CFIT_MAX_LAT         0xFF000000
  968 
  969 /* PCI capability register */
  970 #define DC_CCID_CAPID           0x000000FF
  971 #define DC_CCID_NEXTPTR         0x0000FF00
  972 #define DC_CCID_PM_VERS         0x00070000
  973 #define DC_CCID_PME_CLK         0x00080000
  974 #define DC_CCID_DVSPEC_INT      0x00200000
  975 #define DC_CCID_STATE_D1        0x02000000
  976 #define DC_CCID_STATE_D2        0x04000000
  977 #define DC_CCID_PME_D0          0x08000000
  978 #define DC_CCID_PME_D1          0x10000000
  979 #define DC_CCID_PME_D2          0x20000000
  980 #define DC_CCID_PME_D3HOT       0x40000000
  981 #define DC_CCID_PME_D3COLD      0x80000000
  982 
  983 /* PCI power management control/status register */
  984 #define DC_CPMC_STATE           0x00000003
  985 #define DC_CPMC_PME_ENB         0x00000100
  986 #define DC_CPMC_PME_STS         0x00008000
  987 
  988 #define DC_PSTATE_D0            0x0
  989 #define DC_PSTATE_D1            0x1
  990 #define DC_PSTATE_D2            0x2
  991 #define DC_PSTATE_D3            0x3
  992 
  993 /* Device specific region */
  994 /* Configuration and driver area */
  995 #define DC_CFDD_DRVUSE          0x0000FFFF
  996 #define DC_CFDD_SNOOZE_MODE     0x40000000
  997 #define DC_CFDD_SLEEP_MODE      0x80000000
  998 
  999 /* Configuration wake-up command register */
 1000 #define DC_CWUC_MUST_BE_ZERO    0x00000001
 1001 #define DC_CWUC_SECUREON_ENB    0x00000002
 1002 #define DC_CWUC_FORCE_WUL       0x00000004
 1003 #define DC_CWUC_BNC_ABILITY     0x00000008
 1004 #define DC_CWUC_AUI_ABILITY     0x00000010
 1005 #define DC_CWUC_TP10_ABILITY    0x00000020
 1006 #define DC_CWUC_MII_ABILITY     0x00000040
 1007 #define DC_CWUC_SYM_ABILITY     0x00000080
 1008 #define DC_CWUC_LOCK            0x00000100
 1009 
 1010 /*
 1011  * SROM nonsense.
 1012  */
 1013 
 1014 #define DC_IB_CTLRCNT           0x13
 1015 #define DC_IB_LEAF0_CNUM        0x1A
 1016 #define DC_IB_LEAF0_OFFSET      0x1B
 1017 
 1018 struct dc_info_leaf {
 1019         u_int16_t               dc_conntype;
 1020         u_int8_t                dc_blkcnt;
 1021         u_int8_t                dc_rsvd;
 1022         u_int16_t               dc_infoblk;
 1023 };
 1024 
 1025 #define DC_CTYPE_10BT                   0x0000
 1026 #define DC_CTYPE_10BT_NWAY              0x0100
 1027 #define DC_CTYPE_10BT_FDX               0x0204
 1028 #define DC_CTYPE_10B2                   0x0001
 1029 #define DC_CTYPE_10B5                   0x0002
 1030 #define DC_CTYPE_100BT                  0x0003
 1031 #define DC_CTYPE_100BT_FDX              0x0205
 1032 #define DC_CTYPE_100T4                  0x0006
 1033 #define DC_CTYPE_100FX                  0x0007
 1034 #define DC_CTYPE_100FX_FDX              0x0208
 1035 #define DC_CTYPE_MII_10BT               0x0009
 1036 #define DC_CTYPE_MII_10BT_FDX           0x020A
 1037 #define DC_CTYPE_MII_100BT              0x000D
 1038 #define DC_CTYPE_MII_100BT_FDX          0x020E
 1039 #define DC_CTYPE_MII_100T4              0x000F
 1040 #define DC_CTYPE_MII_100FX              0x0010
 1041 #define DC_CTYPE_MII_100FX_FDX          0x0211
 1042 #define DC_CTYPE_DYN_PUP_AUTOSENSE      0x0800
 1043 #define DC_CTYPE_PUP_AUTOSENSE          0x8800
 1044 #define DC_CTYPE_NOMEDIA                0xFFFF
 1045 
 1046 #define DC_EBLOCK_SIA                   0x0002
 1047 #define DC_EBLOCK_MII                   0x0003
 1048 #define DC_EBLOCK_SYM                   0x0004
 1049 #define DC_EBLOCK_RESET                 0x0005
 1050 #define DC_EBLOCK_PHY_SHUTDOWN          0x0006
 1051 
 1052 struct dc_leaf_hdr {
 1053         u_int16_t               dc_mtype;
 1054         u_int8_t                dc_mcnt;
 1055         u_int8_t                dc_rsvd;
 1056 };
 1057 
 1058 struct dc_eblock_hdr {
 1059         u_int8_t                dc_len;
 1060         u_int8_t                dc_type;
 1061 };
 1062 
 1063 struct dc_eblock_sia {
 1064         struct dc_eblock_hdr    dc_sia_hdr;
 1065         u_int8_t                dc_sia_code;
 1066         union {
 1067                 struct dc_sia_ext { /* if (dc_sia_code & DC_SIA_CODE_EXT) */
 1068                         u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */
 1069                         u_int8_t dc_sia_gpio_ctl[2];
 1070                         u_int8_t dc_sia_gpio_dat[2];
 1071                 } dc_sia_ext;
 1072                 struct dc_sia_noext { 
 1073                         u_int8_t dc_sia_gpio_ctl[2];
 1074                         u_int8_t dc_sia_gpio_dat[2];
 1075                 } dc_sia_noext;
 1076         } dc_un;
 1077 };
 1078 
 1079 #define DC_SIA_CODE_10BT        0x00
 1080 #define DC_SIA_CODE_10B2        0x01
 1081 #define DC_SIA_CODE_10B5        0x02
 1082 #define DC_SIA_CODE_10BT_FDX    0x04
 1083 #define DC_SIA_CODE_EXT         0x40
 1084 
 1085 /*
 1086  * Note that the first word in the gpr and reset
 1087  * sequences is always a control word.
 1088  */
 1089 struct dc_eblock_mii {
 1090         struct dc_eblock_hdr    dc_mii_hdr;
 1091         u_int8_t                dc_mii_phynum;
 1092         u_int8_t                dc_gpr_len;
 1093 /*      u_int16_t               dc_gpr_dat[n]; */
 1094 /*      u_int8_t                dc_reset_len; */
 1095 /*      u_int16_t               dc_reset_dat[n]; */
 1096 /* There are other fields after these, but we don't
 1097  * care about them since they can be determined by looking
 1098  * at the PHY.
 1099  */
 1100 };
 1101 
 1102 struct dc_eblock_sym {
 1103         struct dc_eblock_hdr    dc_sym_hdr;
 1104         u_int8_t                dc_sym_code;
 1105         u_int8_t                dc_sym_gpio_ctl[2];
 1106         u_int8_t                dc_sym_gpio_dat[2];
 1107         u_int8_t                dc_sym_cmd[2];
 1108 };
 1109 
 1110 #define DC_SYM_CODE_100BT       0x03
 1111 #define DC_SYM_CODE_100BT_FDX   0x05
 1112 #define DC_SYM_CODE_100T4       0x06
 1113 #define DC_SYM_CODE_100FX       0x07
 1114 #define DC_SYM_CODE_100FX_FDX   0x08
 1115 
 1116 struct dc_eblock_reset {
 1117         struct dc_eblock_hdr    dc_reset_hdr;
 1118         u_int8_t                dc_reset_len;
 1119 /*      u_int16_t               dc_reset_dat[n]; */
 1120 };
 1121 
 1122 #ifdef __alpha__
 1123 #undef vtophys
 1124 #define vtophys(va)             alpha_XXX_dmamap((vm_offset_t)va)
 1125 #endif

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