FreeBSD/Linux Kernel Cross Reference
sys/pci/if_dcreg.h
1 /*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: releng/5.2/sys/pci/if_dcreg.h 124315 2004-01-09 21:13:56Z truckman $
33 */
34
35 /*
36 * 21143 and clone common register definitions.
37 */
38
39 #define DC_BUSCTL 0x00 /* bus control */
40 #define DC_TXSTART 0x08 /* tx start demand */
41 #define DC_RXSTART 0x10 /* rx start demand */
42 #define DC_RXADDR 0x18 /* rx descriptor list start addr */
43 #define DC_TXADDR 0x20 /* tx descriptor list start addr */
44 #define DC_ISR 0x28 /* interrupt status register */
45 #define DC_NETCFG 0x30 /* network config register */
46 #define DC_IMR 0x38 /* interrupt mask */
47 #define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */
48 #define DC_SIO 0x48 /* MII and ROM/EEPROM access */
49 #define DC_ROM 0x50 /* ROM programming address */
50 #define DC_TIMER 0x58 /* general timer */
51 #define DC_10BTSTAT 0x60 /* SIA status */
52 #define DC_SIARESET 0x68 /* SIA connectivity */
53 #define DC_10BTCTRL 0x70 /* SIA transmit and receive */
54 #define DC_WATCHDOG 0x78 /* SIA and general purpose port */
55 #define DC_SIAGP 0x78 /* SIA and general purpose port (X3201) */
56
57 /*
58 * There are two general 'types' of MX chips that we need to be
59 * concerned with. One is the original 98713, which has its internal
60 * NWAY support controlled via the MDIO bits in the serial I/O
61 * register. The other is everything else (from the 98713A on up),
62 * which has its internal NWAY controlled via CSR13, CSR14 and CSR15,
63 * just like the 21143. This type setting also governs which of the
64 * 'magic' numbers we write to CSR16. The PNIC II falls into the
65 * 98713A/98715/98715A/98725 category.
66 */
67 #define DC_TYPE_98713 0x1
68 #define DC_TYPE_98713A 0x2
69 #define DC_TYPE_987x5 0x3
70
71 /* Other type of supported chips. */
72 #define DC_TYPE_21143 0x4 /* Intel 21143 */
73 #define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */
74 #define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */
75 #define DC_TYPE_AN985 0x7 /* ADMtek AN985 Centaur */
76 #define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */
77 #define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */
78 #define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */
79 #define DC_TYPE_XIRCOM 0xB /* Xircom X3201 */
80 #define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */
81
82 #define DC_IS_MACRONIX(x) \
83 (x->dc_type == DC_TYPE_98713 || \
84 x->dc_type == DC_TYPE_98713A || \
85 x->dc_type == DC_TYPE_987x5)
86
87 #define DC_IS_ADMTEK(x) \
88 (x->dc_type == DC_TYPE_AL981 || \
89 x->dc_type == DC_TYPE_AN985)
90
91 #define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143)
92 #define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX)
93 #define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981)
94 #define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN985)
95 #define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102)
96 #define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII)
97 #define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC)
98 #define DC_IS_XIRCOM(x) (x->dc_type == DC_TYPE_XIRCOM)
99 #define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT)
100
101 /* MII/symbol mode port types */
102 #define DC_PMODE_MII 0x1
103 #define DC_PMODE_SYM 0x2
104 #define DC_PMODE_SIA 0x3
105
106 /*
107 * Bus control bits.
108 */
109 #define DC_BUSCTL_RESET 0x00000001
110 #define DC_BUSCTL_ARBITRATION 0x00000002
111 #define DC_BUSCTL_SKIPLEN 0x0000007C
112 #define DC_BUSCTL_BUF_BIGENDIAN 0x00000080
113 #define DC_BUSCTL_BURSTLEN 0x00003F00
114 #define DC_BUSCTL_CACHEALIGN 0x0000C000
115 #define DC_BUSCTL_TXPOLL 0x000E0000
116 #define DC_BUSCTL_DBO 0x00100000
117 #define DC_BUSCTL_MRME 0x00200000
118 #define DC_BUSCTL_MRLE 0x00800000
119 #define DC_BUSCTL_MWIE 0x01000000
120 #define DC_BUSCTL_ONNOW_ENB 0x04000000
121
122 #define DC_SKIPLEN_1LONG 0x00000004
123 #define DC_SKIPLEN_2LONG 0x00000008
124 #define DC_SKIPLEN_3LONG 0x00000010
125 #define DC_SKIPLEN_4LONG 0x00000020
126 #define DC_SKIPLEN_5LONG 0x00000040
127
128 #define DC_CACHEALIGN_NONE 0x00000000
129 #define DC_CACHEALIGN_8LONG 0x00004000
130 #define DC_CACHEALIGN_16LONG 0x00008000
131 #define DC_CACHEALIGN_32LONG 0x0000C000
132
133 #define DC_BURSTLEN_USECA 0x00000000
134 #define DC_BURSTLEN_1LONG 0x00000100
135 #define DC_BURSTLEN_2LONG 0x00000200
136 #define DC_BURSTLEN_4LONG 0x00000400
137 #define DC_BURSTLEN_8LONG 0x00000800
138 #define DC_BURSTLEN_16LONG 0x00001000
139 #define DC_BURSTLEN_32LONG 0x00002000
140
141 #define DC_TXPOLL_OFF 0x00000000
142 #define DC_TXPOLL_1 0x00020000
143 #define DC_TXPOLL_2 0x00040000
144 #define DC_TXPOLL_3 0x00060000
145 #define DC_TXPOLL_4 0x00080000
146 #define DC_TXPOLL_5 0x000A0000
147 #define DC_TXPOLL_6 0x000C0000
148 #define DC_TXPOLL_7 0x000E0000
149
150 /*
151 * Interrupt status bits.
152 */
153 #define DC_ISR_TX_OK 0x00000001
154 #define DC_ISR_TX_IDLE 0x00000002
155 #define DC_ISR_TX_NOBUF 0x00000004
156 #define DC_ISR_TX_JABBERTIMEO 0x00000008
157 #define DC_ISR_LINKGOOD 0x00000010
158 #define DC_ISR_TX_UNDERRUN 0x00000020
159 #define DC_ISR_RX_OK 0x00000040
160 #define DC_ISR_RX_NOBUF 0x00000080
161 #define DC_ISR_RX_READ 0x00000100
162 #define DC_ISR_RX_WATDOGTIMEO 0x00000200
163 #define DC_ISR_TX_EARLY 0x00000400
164 #define DC_ISR_TIMER_EXPIRED 0x00000800
165 #define DC_ISR_LINKFAIL 0x00001000
166 #define DC_ISR_BUS_ERR 0x00002000
167 #define DC_ISR_RX_EARLY 0x00004000
168 #define DC_ISR_ABNORMAL 0x00008000
169 #define DC_ISR_NORMAL 0x00010000
170 #define DC_ISR_RX_STATE 0x000E0000
171 #define DC_ISR_TX_STATE 0x00700000
172 #define DC_ISR_BUSERRTYPE 0x03800000
173 #define DC_ISR_100MBPSLINK 0x08000000
174 #define DC_ISR_MAGICKPACK 0x10000000
175
176 #define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
177 #define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
178 #define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
179 #define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
180 #define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
181 #define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
182 #define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
183 #define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
184
185 #define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */
186 #define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
187 #define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
188 #define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
189 #define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
190 #define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
191 #define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
192 #define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
193
194 /*
195 * Network config bits.
196 */
197 #define DC_NETCFG_RX_HASHPERF 0x00000001
198 #define DC_NETCFG_RX_ON 0x00000002
199 #define DC_NETCFG_RX_HASHONLY 0x00000004
200 #define DC_NETCFG_RX_BADFRAMES 0x00000008
201 #define DC_NETCFG_RX_INVFILT 0x00000010
202 #define DC_NETCFG_BACKOFFCNT 0x00000020
203 #define DC_NETCFG_RX_PROMISC 0x00000040
204 #define DC_NETCFG_RX_ALLMULTI 0x00000080
205 #define DC_NETCFG_FULLDUPLEX 0x00000200
206 #define DC_NETCFG_LOOPBACK 0x00000C00
207 #define DC_NETCFG_FORCECOLL 0x00001000
208 #define DC_NETCFG_TX_ON 0x00002000
209 #define DC_NETCFG_TX_THRESH 0x0000C000
210 #define DC_NETCFG_TX_BACKOFF 0x00020000
211 #define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */
212 #define DC_NETCFG_HEARTBEAT 0x00080000
213 #define DC_NETCFG_STORENFWD 0x00200000
214 #define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
215 #define DC_NETCFG_PCS 0x00800000
216 #define DC_NETCFG_SCRAMBLER 0x01000000
217 #define DC_NETCFG_NO_RXCRC 0x02000000
218 #define DC_NETCFG_RX_ALL 0x40000000
219 #define DC_NETCFG_CAPEFFECT 0x80000000
220
221 #define DC_OPMODE_NORM 0x00000000
222 #define DC_OPMODE_INTLOOP 0x00000400
223 #define DC_OPMODE_EXTLOOP 0x00000800
224
225 #if 0
226 #define DC_TXTHRESH_72BYTES 0x00000000
227 #define DC_TXTHRESH_96BYTES 0x00004000
228 #define DC_TXTHRESH_128BYTES 0x00008000
229 #define DC_TXTHRESH_160BYTES 0x0000C000
230 #endif
231
232 #define DC_TXTHRESH_MIN 0x00000000
233 #define DC_TXTHRESH_INC 0x00004000
234 #define DC_TXTHRESH_MAX 0x0000C000
235
236
237 /*
238 * Interrupt mask bits.
239 */
240 #define DC_IMR_TX_OK 0x00000001
241 #define DC_IMR_TX_IDLE 0x00000002
242 #define DC_IMR_TX_NOBUF 0x00000004
243 #define DC_IMR_TX_JABBERTIMEO 0x00000008
244 #define DC_IMR_LINKGOOD 0x00000010
245 #define DC_IMR_TX_UNDERRUN 0x00000020
246 #define DC_IMR_RX_OK 0x00000040
247 #define DC_IMR_RX_NOBUF 0x00000080
248 #define DC_IMR_RX_READ 0x00000100
249 #define DC_IMR_RX_WATDOGTIMEO 0x00000200
250 #define DC_IMR_TX_EARLY 0x00000400
251 #define DC_IMR_TIMER_EXPIRED 0x00000800
252 #define DC_IMR_LINKFAIL 0x00001000
253 #define DC_IMR_BUS_ERR 0x00002000
254 #define DC_IMR_RX_EARLY 0x00004000
255 #define DC_IMR_ABNORMAL 0x00008000
256 #define DC_IMR_NORMAL 0x00010000
257 #define DC_IMR_100MBPSLINK 0x08000000
258 #define DC_IMR_MAGICKPACK 0x10000000
259
260 #define DC_INTRS \
261 (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\
262 DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \
263 DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/)
264 /*
265 * Serial I/O (EEPROM/ROM) bits.
266 */
267 #define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */
268 #define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */
269 #define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
270 #define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
271 #define DC_SIO_ROMDATA4 0x00000010
272 #define DC_SIO_ROMDATA5 0x00000020
273 #define DC_SIO_ROMDATA6 0x00000040
274 #define DC_SIO_ROMDATA7 0x00000080
275 #define DC_SIO_EESEL 0x00000800
276 #define DC_SIO_ROMSEL 0x00001000
277 #define DC_SIO_ROMCTL_WRITE 0x00002000
278 #define DC_SIO_ROMCTL_READ 0x00004000
279 #define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */
280 #define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
281 #define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */
282 #define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
283
284 #define DC_EECMD_WRITE 0x140
285 #define DC_EECMD_READ 0x180
286 #define DC_EECMD_ERASE 0x1c0
287
288 #define DC_EE_NODEADDR_OFFSET 0x70
289 #define DC_EE_NODEADDR 10
290
291 /*
292 * General purpose timer register
293 */
294 #define DC_TIMER_VALUE 0x0000FFFF
295 #define DC_TIMER_CONTINUOUS 0x00010000
296
297 /*
298 * 10baseT status register
299 */
300 #define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */
301 #define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */
302 #define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */
303 #define DC_TSTAT_AUTOPOLARITY 0x00000008
304 #define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */
305 #define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */
306 #define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */
307 #define DC_TSTAT_REMFAULT 0x00000800
308 #define DC_TSTAT_ANEGSTAT 0x00007000
309 #define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */
310 #define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */
311
312 #define DC_ASTAT_DISABLE 0x00000000
313 #define DC_ASTAT_TXDISABLE 0x00001000
314 #define DC_ASTAT_ABDETECT 0x00002000
315 #define DC_ASTAT_ACKDETECT 0x00003000
316 #define DC_ASTAT_CMPACKDETECT 0x00004000
317 #define DC_ASTAT_AUTONEGCMP 0x00005000
318 #define DC_ASTAT_LINKCHECK 0x00006000
319
320 /*
321 * PHY reset register
322 */
323 #define DC_SIA_RESET 0x00000001
324 #define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */
325
326 /*
327 * 10baseT control register
328 */
329 #define DC_TCTL_ENCODER_ENB 0x00000001
330 #define DC_TCTL_LOOPBACK 0x00000002
331 #define DC_TCTL_DRIVER_ENB 0x00000004
332 #define DC_TCTL_LNKPULSE_ENB 0x00000008
333 #define DC_TCTL_HALFDUPLEX 0x00000040
334 #define DC_TCTL_AUTONEGENBL 0x00000080
335 #define DC_TCTL_RX_SQUELCH 0x00000100
336 #define DC_TCTL_COLL_SQUELCH 0x00000200
337 #define DC_TCTL_COLL_DETECT 0x00000400
338 #define DC_TCTL_SQE_ENB 0x00000800
339 #define DC_TCTL_LINKTEST 0x00001000
340 #define DC_TCTL_AUTOPOLARITY 0x00002000
341 #define DC_TCTL_SET_POL_PLUS 0x00004000
342 #define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */
343 #define DC_TCTL_100BTXHALF 0x00010000
344 #define DC_TCTL_100BTXFULL 0x00020000
345 #define DC_TCTL_100BT4 0x00040000
346
347 /*
348 * Watchdog timer register
349 */
350 #define DC_WDOG_JABBERDIS 0x00000001
351 #define DC_WDOG_HOSTUNJAB 0x00000002
352 #define DC_WDOG_JABBERCLK 0x00000004
353 #define DC_WDOG_RXWDOGDIS 0x00000010
354 #define DC_WDOG_RXWDOGCLK 0x00000020
355 #define DC_WDOG_MUSTBEZERO 0x00000100
356 #define DC_WDOG_AUIBNC 0x00100000
357 #define DC_WDOG_ACTIVITY 0x00200000
358 #define DC_WDOG_RX_MATCH 0x00400000
359 #define DC_WDOG_LINK 0x00800000
360 #define DC_WDOG_CTLWREN 0x08000000
361
362 /*
363 * SIA and General Purpose Port register (X3201)
364 */
365 #define DC_SIAGP_RXMATCH 0x40000000
366 #define DC_SIAGP_INT1 0x20000000
367 #define DC_SIAGP_INT0 0x10000000
368 #define DC_SIAGP_WRITE_EN 0x08000000
369 #define DC_SIAGP_RXMATCH_EN 0x04000000
370 #define DC_SIAGP_INT1_EN 0x02000000
371 #define DC_SIAGP_INT0_EN 0x01000000
372 #define DC_SIAGP_LED3 0x00800000
373 #define DC_SIAGP_LED2 0x00400000
374 #define DC_SIAGP_LED1 0x00200000
375 #define DC_SIAGP_LED0 0x00100000
376 #define DC_SIAGP_MD_GP3_OUTPUT 0x00080000
377 #define DC_SIAGP_MD_GP2_OUTPUT 0x00040000
378 #define DC_SIAGP_MD_GP1_OUTPUT 0x00020000
379 #define DC_SIAGP_MD_GP0_OUTPUT 0x00010000
380
381 /*
382 * Size of a setup frame.
383 */
384 #define DC_SFRAME_LEN 192
385
386 /*
387 * 21x4x TX/RX list structure.
388 */
389
390 struct dc_desc {
391 u_int32_t dc_status;
392 u_int32_t dc_ctl;
393 u_int32_t dc_ptr1;
394 u_int32_t dc_ptr2;
395 };
396
397 #define dc_data dc_ptr1
398 #define dc_next dc_ptr2
399
400 #define DC_RXSTAT_FIFOOFLOW 0x00000001
401 #define DC_RXSTAT_CRCERR 0x00000002
402 #define DC_RXSTAT_DRIBBLE 0x00000004
403 #define DC_RXSTAT_MIIERE 0x00000008
404 #define DC_RXSTAT_WATCHDOG 0x00000010
405 #define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
406 #define DC_RXSTAT_COLLSEEN 0x00000040
407 #define DC_RXSTAT_GIANT 0x00000080
408 #define DC_RXSTAT_LASTFRAG 0x00000100
409 #define DC_RXSTAT_FIRSTFRAG 0x00000200
410 #define DC_RXSTAT_MULTICAST 0x00000400
411 #define DC_RXSTAT_RUNT 0x00000800
412 #define DC_RXSTAT_RXTYPE 0x00003000
413 #define DC_RXSTAT_DE 0x00004000
414 #define DC_RXSTAT_RXERR 0x00008000
415 #define DC_RXSTAT_RXLEN 0x3FFF0000
416 #define DC_RXSTAT_OWN 0x80000000
417
418 #define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16)
419 #define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN)
420
421 #define DC_RXCTL_BUFLEN1 0x00000FFF
422 #define DC_RXCTL_BUFLEN2 0x00FFF000
423 #define DC_RXCTL_RLINK 0x01000000
424 #define DC_RXCTL_RLAST 0x02000000
425
426 #define DC_TXSTAT_DEFER 0x00000001
427 #define DC_TXSTAT_UNDERRUN 0x00000002
428 #define DC_TXSTAT_LINKFAIL 0x00000003
429 #define DC_TXSTAT_COLLCNT 0x00000078
430 #define DC_TXSTAT_SQE 0x00000080
431 #define DC_TXSTAT_EXCESSCOLL 0x00000100
432 #define DC_TXSTAT_LATECOLL 0x00000200
433 #define DC_TXSTAT_NOCARRIER 0x00000400
434 #define DC_TXSTAT_CARRLOST 0x00000800
435 #define DC_TXSTAT_JABTIMEO 0x00004000
436 #define DC_TXSTAT_ERRSUM 0x00008000
437 #define DC_TXSTAT_OWN 0x80000000
438
439 #define DC_TXCTL_BUFLEN1 0x000007FF
440 #define DC_TXCTL_BUFLEN2 0x003FF800
441 #define DC_TXCTL_FILTTYPE0 0x00400000
442 #define DC_TXCTL_PAD 0x00800000
443 #define DC_TXCTL_TLINK 0x01000000
444 #define DC_TXCTL_TLAST 0x02000000
445 #define DC_TXCTL_NOCRC 0x04000000
446 #define DC_TXCTL_SETUP 0x08000000
447 #define DC_TXCTL_FILTTYPE1 0x10000000
448 #define DC_TXCTL_FIRSTFRAG 0x20000000
449 #define DC_TXCTL_LASTFRAG 0x40000000
450 #define DC_TXCTL_FINT 0x80000000
451
452 #define DC_FILTER_PERFECT 0x00000000
453 #define DC_FILTER_HASHPERF 0x00400000
454 #define DC_FILTER_INVERSE 0x10000000
455 #define DC_FILTER_HASHONLY 0x10400000
456
457 #define DC_MAXFRAGS 16
458 #ifdef DEVICE_POLLING
459 #define DC_RX_LIST_CNT 192
460 #else
461 #define DC_RX_LIST_CNT 64
462 #endif
463 #define DC_TX_LIST_CNT 256
464 #define DC_MIN_FRAMELEN 60
465 #define DC_RXLEN 1536
466
467 #define DC_INC(x, y) (x) = (x + 1) % y
468
469 /* Macros to easily get the DMA address of a descriptor. */
470 #define DC_RXDESC(sc, i) (sc->dc_laddr + \
471 (uintptr_t)(sc->dc_ldata->dc_rx_list + i) - (uintptr_t)sc->dc_ldata)
472 #define DC_TXDESC(sc, i) (sc->dc_laddr + \
473 (uintptr_t)(sc->dc_ldata->dc_tx_list + i) - (uintptr_t)sc->dc_ldata)
474
475 #if BYTE_ORDER == BIG_ENDIAN
476 #define DC_SP_MAC(x) ((x) << 16)
477 #else
478 #define DC_SP_MAC(x) (x)
479 #endif
480
481 struct dc_list_data {
482 struct dc_desc dc_rx_list[DC_RX_LIST_CNT];
483 struct dc_desc dc_tx_list[DC_TX_LIST_CNT];
484 };
485
486 struct dc_chain_data {
487 struct mbuf *dc_rx_chain[DC_RX_LIST_CNT];
488 struct mbuf *dc_tx_chain[DC_TX_LIST_CNT];
489 struct mbuf *dc_tx_mapping;
490 bus_dmamap_t dc_rx_map[DC_RX_LIST_CNT];
491 bus_dmamap_t dc_tx_map[DC_TX_LIST_CNT];
492 u_int32_t *dc_sbuf;
493 u_int8_t dc_pad[DC_MIN_FRAMELEN];
494 int dc_tx_err;
495 int dc_tx_first;
496 int dc_tx_prod;
497 int dc_tx_cons;
498 int dc_tx_cnt;
499 int dc_rx_err;
500 int dc_rx_cur;
501 int dc_rx_prod;
502 };
503
504 struct dc_mediainfo {
505 int dc_media;
506 u_int8_t *dc_gp_ptr;
507 u_int8_t dc_gp_len;
508 u_int8_t *dc_reset_ptr;
509 u_int8_t dc_reset_len;
510 struct dc_mediainfo *dc_next;
511 };
512
513
514 struct dc_type {
515 u_int16_t dc_vid;
516 u_int16_t dc_did;
517 char *dc_name;
518 };
519
520 struct dc_mii_frame {
521 u_int8_t mii_stdelim;
522 u_int8_t mii_opcode;
523 u_int8_t mii_phyaddr;
524 u_int8_t mii_regaddr;
525 u_int8_t mii_turnaround;
526 u_int16_t mii_data;
527 };
528
529 /*
530 * MII constants
531 */
532 #define DC_MII_STARTDELIM 0x01
533 #define DC_MII_READOP 0x02
534 #define DC_MII_WRITEOP 0x01
535 #define DC_MII_TURNAROUND 0x02
536
537
538 /*
539 * Registers specific to clone devices.
540 * This mainly relates to RX filter programming: not all 21x4x clones
541 * use the standard DEC filter programming mechanism.
542 */
543
544 /*
545 * ADMtek specific registers and constants for the AL981 and AN985.
546 * The AN985 doesn't use the magic PHY registers.
547 */
548 #define DC_AL_CR 0x88 /* command register */
549 #define DC_AL_PAR0 0xA4 /* station address */
550 #define DC_AL_PAR1 0xA8 /* station address */
551 #define DC_AL_MAR0 0xAC /* multicast hash filter */
552 #define DC_AL_MAR1 0xB0 /* multicast hash filter */
553 #define DC_AL_BMCR 0xB4 /* built in PHY control */
554 #define DC_AL_BMSR 0xB8 /* built in PHY status */
555 #define DC_AL_VENID 0xBC /* built in PHY ID0 */
556 #define DC_AL_DEVID 0xC0 /* built in PHY ID1 */
557 #define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */
558 #define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */
559 #define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */
560
561 #define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */
562 #define DC_ADMTEK_PHYADDR 0x1
563 #define DC_AL_EE_NODEADDR 4
564 /* End of ADMtek specific registers */
565
566 /*
567 * ASIX specific registers.
568 */
569 #define DC_AX_FILTIDX 0x68 /* RX filter index */
570 #define DC_AX_FILTDATA 0x70 /* RX filter data */
571
572 /*
573 * Special ASIX-specific bits in the ASIX NETCFG register (CSR6).
574 */
575 #define DC_AX_NETCFG_RX_BROAD 0x00000100
576
577 /*
578 * RX Filter Index Register values
579 */
580 #define DC_AX_FILTIDX_PAR0 0x00000000
581 #define DC_AX_FILTIDX_PAR1 0x00000001
582 #define DC_AX_FILTIDX_MAR0 0x00000002
583 #define DC_AX_FILTIDX_MAR1 0x00000003
584 /* End of ASIX specific registers */
585
586 /*
587 * Macronix specific registers. The Macronix chips have a special
588 * register for reading the NWAY status, which we don't use, plus
589 * a magic packet register, which we need to tweak a bit per the
590 * Macronix application notes.
591 */
592 #define DC_MX_MAGICPACKET 0x80
593 #define DC_MX_NWAYSTAT 0xA0
594
595 /*
596 * Magic packet register
597 */
598 #define DC_MX_MPACK_DISABLE 0x00400000
599
600 /*
601 * NWAY status register.
602 */
603 #define DC_MX_NWAY_10BTHALF 0x08000000
604 #define DC_MX_NWAY_10BTFULL 0x10000000
605 #define DC_MX_NWAY_100BTHALF 0x20000000
606 #define DC_MX_NWAY_100BTFULL 0x40000000
607 #define DC_MX_NWAY_100BT4 0x80000000
608
609 /*
610 * These are magic values that must be written into CSR16
611 * (DC_MX_MAGICPACKET) in order to put the chip into proper
612 * operating mode. The magic numbers are documented in the
613 * Macronix 98715 application notes.
614 */
615 #define DC_MX_MAGIC_98713 0x0F370000
616 #define DC_MX_MAGIC_98713A 0x0B3C0000
617 #define DC_MX_MAGIC_98715 0x0B3C0000
618 #define DC_MX_MAGIC_98725 0x0B3C0000
619 /* End of Macronix specific registers */
620
621 /*
622 * PNIC 82c168/82c169 specific registers.
623 * The PNIC has its own special NWAY support, which doesn't work,
624 * and shortcut ways of reading the EEPROM and MII bus.
625 */
626 #define DC_PN_GPIO 0x60 /* general purpose pins control */
627 #define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */
628 #define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */
629 #define DC_PN_MII 0xA0 /* MII access register */
630 #define DC_PN_NWAY 0xB8 /* Internal NWAY register */
631
632 /* Serial I/O EEPROM register */
633 #define DC_PN_SIOCTL_DATA 0x0000003F
634 #define DC_PN_SIOCTL_OPCODE 0x00000300
635 #define DC_PN_SIOCTL_BUSY 0x80000000
636
637 #define DC_PN_EEOPCODE_ERASE 0x00000300
638 #define DC_PN_EEOPCODE_READ 0x00000600
639 #define DC_PN_EEOPCODE_WRITE 0x00000100
640
641 /*
642 * The first two general purpose pins control speed selection and
643 * 100Mbps loopback on the 82c168 chip. The control bits should always
644 * be set (to make the data pins outputs) and the speed selction and
645 * loopback bits set accordingly when changing media. Physically, this
646 * will set the state of a relay mounted on the card.
647 */
648 #define DC_PN_GPIO_DATA0 0x000000001
649 #define DC_PN_GPIO_DATA1 0x000000002
650 #define DC_PN_GPIO_DATA2 0x000000004
651 #define DC_PN_GPIO_DATA3 0x000000008
652 #define DC_PN_GPIO_CTL0 0x000000010
653 #define DC_PN_GPIO_CTL1 0x000000020
654 #define DC_PN_GPIO_CTL2 0x000000040
655 #define DC_PN_GPIO_CTL3 0x000000080
656 #define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */
657 #define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */
658 #define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2
659 #define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3
660 #define DC_PN_GPIO_SETBIT(sc, r) \
661 DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4)))
662 #define DC_PN_GPIO_CLRBIT(sc, r) \
663 { \
664 DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \
665 DC_CLRBIT(sc, DC_PN_GPIO, (r)); \
666 }
667
668 /* shortcut MII access register */
669 #define DC_PN_MII_DATA 0x0000FFFF
670 #define DC_PN_MII_RESERVER 0x00020000
671 #define DC_PN_MII_REGADDR 0x007C0000
672 #define DC_PN_MII_PHYADDR 0x0F800000
673 #define DC_PN_MII_OPCODE 0x30000000
674 #define DC_PN_MII_BUSY 0x80000000
675
676 #define DC_PN_MIIOPCODE_READ 0x60020000
677 #define DC_PN_MIIOPCODE_WRITE 0x50020000
678
679 /* Internal NWAY bits */
680 #define DC_PN_NWAY_RESET 0x00000001 /* reset */
681 #define DC_PN_NWAY_PDOWN 0x00000002 /* power down */
682 #define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */
683 #define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */
684 #define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */
685 #define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */
686 #define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */
687 #define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */
688 #define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */
689 #define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */
690 #define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */
691 #define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */
692 #define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */
693 #define DC_PN_NWAY_CAP10HDX 0x00002000
694 #define DC_PN_NWAY_CAP10FDX 0x00004000
695 #define DC_PN_NWAY_CAP100FDX 0x00008000
696 #define DC_PN_NWAY_CAP100HDX 0x00010000
697 #define DC_PN_NWAY_CAP100T4 0x00020000
698 #define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */
699 #define DC_PN_NWAY_REMFAULT 0x04000000
700 #define DC_PN_NWAY_LPAR10HDX 0x08000000
701 #define DC_PN_NWAY_LPAR10FDX 0x10000000
702 #define DC_PN_NWAY_LPAR100FDX 0x20000000
703 #define DC_PN_NWAY_LPAR100HDX 0x40000000
704 #define DC_PN_NWAY_LPAR100T4 0x80000000
705
706 /* End of PNIC specific registers */
707
708 /*
709 * CONEXANT specific registers.
710 */
711
712 #define DC_CONEXANT_PHYADDR 0x1
713 #define DC_CONEXANT_EE_NODEADDR 0x19A
714
715 /* End of CONEXANT specific registers */
716
717
718 struct dc_softc {
719 struct arpcom arpcom; /* interface info */
720 bus_space_handle_t dc_bhandle; /* bus space handle */
721 bus_space_tag_t dc_btag; /* bus space tag */
722 bus_dma_tag_t dc_ltag; /* tag for descriptor ring */
723 bus_dmamap_t dc_lmap; /* map for descriptor ring */
724 u_int32_t dc_laddr; /* DMA address of dc_ldata */
725 bus_dma_tag_t dc_mtag; /* tag for mbufs */
726 bus_dmamap_t dc_sparemap;
727 bus_dma_tag_t dc_stag; /* tag for the setup frame */
728 bus_dmamap_t dc_smap; /* map for the setup frame */
729 u_int32_t dc_saddr; /* DMA address of setup frame */
730 void *dc_intrhand;
731 struct resource *dc_irq;
732 struct resource *dc_res;
733 struct dc_type *dc_info; /* adapter info */
734 device_t dc_miibus;
735 u_int8_t dc_unit; /* interface number */
736 u_int8_t dc_type;
737 u_int8_t dc_pmode;
738 u_int8_t dc_link;
739 u_int8_t dc_cachesize;
740 int dc_romwidth;
741 int dc_pnic_rx_bug_save;
742 unsigned char *dc_pnic_rx_buf;
743 int dc_if_flags;
744 int dc_if_media;
745 u_int32_t dc_flags;
746 u_int32_t dc_txthresh;
747 u_int8_t *dc_srom;
748 struct dc_mediainfo *dc_mi;
749 struct dc_list_data *dc_ldata;
750 struct dc_chain_data dc_cdata;
751 struct callout dc_stat_ch;
752 #ifdef SRM_MEDIA
753 int dc_srm_media;
754 #endif
755 struct mtx dc_mtx;
756 #ifdef DEVICE_POLLING
757 int rxcycles; /* ... when polling */
758 #endif
759 int suspended; /* 0 = normal 1 = suspended */
760 u_int32_t saved_maps[5]; /* pci data */
761 u_int32_t saved_biosaddr;
762 u_int8_t saved_intline;
763 u_int8_t saved_cachelnsz;
764 u_int8_t saved_lattimer;
765 };
766
767
768 #define DC_LOCK(_sc) mtx_lock(&(_sc)->dc_mtx)
769 #define DC_UNLOCK(_sc) mtx_unlock(&(_sc)->dc_mtx)
770 #define DC_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->dc_mtx, MA_OWNED)
771
772 #define DC_TX_POLL 0x00000001
773 #define DC_TX_COALESCE 0x00000002
774 #define DC_TX_ADMTEK_WAR 0x00000004
775 #define DC_TX_USE_TX_INTR 0x00000008
776 #define DC_RX_FILTER_TULIP 0x00000010
777 #define DC_TX_INTR_FIRSTFRAG 0x00000020
778 #define DC_PNIC_RX_BUG_WAR 0x00000040
779 #define DC_TX_FIXED_RING 0x00000080
780 #define DC_TX_STORENFWD 0x00000100
781 #define DC_REDUCED_MII_POLL 0x00000200
782 #define DC_TX_INTR_ALWAYS 0x00000400
783 #define DC_21143_NWAY 0x00000800
784 #define DC_128BIT_HASH 0x00001000
785 #define DC_64BIT_HASH 0x00002000
786 #define DC_TULIP_LEDS 0x00004000
787 #define DC_TX_ONE 0x00008000
788 #define DC_TX_ALIGN 0x00010000 /* align mbuf on tx */
789
790 /*
791 * register space access macros
792 */
793 #define CSR_WRITE_4(sc, reg, val) \
794 bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val)
795
796 #define CSR_READ_4(sc, reg) \
797 bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg)
798
799 #define DC_TIMEOUT 1000
800 #define ETHER_ALIGN 2
801
802 /*
803 * General constants that are fun to know.
804 */
805
806 /*
807 * DEC PCI vendor ID
808 */
809 #define DC_VENDORID_DEC 0x1011
810
811 /*
812 * DEC/Intel 21143 PCI device ID
813 */
814 #define DC_DEVICEID_21143 0x0019
815
816 /*
817 * Macronix PCI vendor ID
818 */
819 #define DC_VENDORID_MX 0x10D9
820
821 /*
822 * Macronix PMAC device IDs.
823 */
824 #define DC_DEVICEID_98713 0x0512
825 #define DC_DEVICEID_987x5 0x0531
826 #define DC_DEVICEID_98727 0x0532
827 #define DC_DEVICEID_98732 0x0532
828
829 /* Macronix PCI revision codes. */
830 #define DC_REVISION_98713 0x00
831 #define DC_REVISION_98713A 0x10
832 #define DC_REVISION_98715 0x20
833 #define DC_REVISION_98715AEC_C 0x25
834 #define DC_REVISION_98725 0x30
835
836 /*
837 * Compex PCI vendor ID.
838 */
839 #define DC_VENDORID_CP 0x11F6
840
841 /*
842 * Compex PMAC PCI device IDs.
843 */
844 #define DC_DEVICEID_98713_CP 0x9881
845
846 /*
847 * Lite-On PNIC PCI vendor ID
848 */
849 #define DC_VENDORID_LO 0x11AD
850
851 /*
852 * 82c168/82c169 PNIC device IDs. Both chips have the same device
853 * ID but different revisions. Revision 0x10 is the 82c168, and
854 * 0x20 is the 82c169.
855 */
856 #define DC_DEVICEID_82C168 0x0002
857
858 #define DC_REVISION_82C168 0x10
859 #define DC_REVISION_82C169 0x20
860
861 /*
862 * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A
863 * with wake on lan/magic packet support.
864 */
865 #define DC_DEVICEID_82C115 0xc115
866
867 /*
868 * Davicom vendor ID.
869 */
870 #define DC_VENDORID_DAVICOM 0x1282
871
872 /*
873 * Davicom device IDs.
874 */
875 #define DC_DEVICEID_DM9009 0x9009
876 #define DC_DEVICEID_DM9100 0x9100
877 #define DC_DEVICEID_DM9102 0x9102
878
879 /*
880 * The DM9102A has the same PCI device ID as the DM9102,
881 * but a higher revision code.
882 */
883 #define DC_REVISION_DM9102 0x10
884 #define DC_REVISION_DM9102A 0x30
885
886 /*
887 * ADMtek vendor ID.
888 */
889 #define DC_VENDORID_ADMTEK 0x1317
890
891 /*
892 * ADMtek device IDs.
893 */
894 #define DC_DEVICEID_AL981 0x0981
895 #define DC_DEVICEID_AN985 0x0985
896 #define DC_DEVICEID_FA511 0x1985
897 #define DC_DEVICEID_ADM9511 0x9511
898 #define DC_DEVICEID_ADM9513 0x9513
899
900 /*
901 * 3COM PCI vendor ID
902 */
903 #define DC_VENDORID_3COM 0x10b7
904
905 /*
906 * 3COM OfficeConnect 10/100B (3CSOHO100B-TX)
907 */
908 #define DC_DEVICEID_3CSOHOB 0x9300
909
910 /*
911 * ASIX vendor ID.
912 */
913 #define DC_VENDORID_ASIX 0x125B
914
915 /*
916 * ASIX device IDs.
917 */
918 #define DC_DEVICEID_AX88140A 0x1400
919
920 /*
921 * The ASIX AX88140 and ASIX AX88141 have the same vendor and
922 * device IDs but different revision values.
923 */
924 #define DC_REVISION_88140 0x00
925 #define DC_REVISION_88141 0x10
926
927 /*
928 * Accton vendor ID.
929 */
930 #define DC_VENDORID_ACCTON 0x1113
931
932 /*
933 * Accton device IDs.
934 */
935 #define DC_DEVICEID_EN1217 0x1217
936 #define DC_DEVICEID_EN2242 0x1216
937
938 /*
939 * Xircom vendor ID
940 */
941 #define DC_VENDORID_XIRCOM 0x115d
942
943 /*
944 * Xircom device IDs.
945 */
946 #define DC_DEVICEID_X3201 0x0003
947
948 /*
949 * Abocom vendor ID
950 */
951 #define DC_VENDORID_ABOCOM 0x13d1
952
953 /*
954 * Abocom device IDs.
955 */
956 #define DC_DEVICEID_FE2500 0xAB02
957 #define DC_DEVICEID_FE2500MX 0xab08
958
959 /*
960 * Conexant vendor ID.
961 */
962 #define DC_VENDORID_CONEXANT 0x14f1
963
964 /*
965 * Conexant device IDs.
966 */
967 #define DC_DEVICEID_RS7112 0x1803
968
969 /*
970 * Planex vendor ID
971 */
972 #define DC_VENDORID_PLANEX 0x14ea
973
974 /*
975 * Planex device IDs.
976 */
977 #define DC_DEVICEID_FNW3602T 0xab08
978
979 /*
980 * Not sure who this vendor should be, so we'll go with HAWKING until
981 * I can locate the right one.
982 */
983 #define DC_VENDORID_HAWKING 0x17b3
984
985 /*
986 * Sure looks like an abocom device ID, but it found on my hawking PN672TX
987 * card. Use that for now, and upgrade later.
988 */
989 #define DC_DEVICEID_HAWKING_PN672TX 0xab08
990
991 /*
992 * Microsoft device ID.
993 */
994 #define DC_VENDORID_MICROSOFT 0x1414
995
996 /*
997 * Supported Microsoft PCI and cardbus NICs. These are really
998 * ADMtek parts in disguise.
999 */
1000
1001 #define DC_DEVICEID_MSMN120 0x0001
1002 #define DC_DEVICEID_MSMN130 0x0002
1003 #define DC_DEVICEID_MSMN130_FAKE 0xFFF2
1004
1005 /*
1006 * PCI low memory base and low I/O base register, and
1007 * other PCI registers.
1008 */
1009
1010 #define DC_PCI_CFID 0x00 /* Id */
1011 #define DC_PCI_CFCS 0x04 /* Command and status */
1012 #define DC_PCI_CFRV 0x08 /* Revision */
1013 #define DC_PCI_CFLT 0x0C /* Latency timer */
1014 #define DC_PCI_CFBIO 0x10 /* Base I/O address */
1015 #define DC_PCI_CFBMA 0x14 /* Base memory address */
1016 #define DC_PCI_CCIS 0x28 /* Card info struct */
1017 #define DC_PCI_CSID 0x2C /* Subsystem ID */
1018 #define DC_PCI_CBER 0x30 /* Expansion ROM base address */
1019 #define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */
1020 #define DC_PCI_CFIT 0x3C /* Interrupt */
1021 #define DC_PCI_CFDD 0x40 /* Device and driver area */
1022 #define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */
1023 #define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */
1024 #define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */
1025 #define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */
1026 #define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */
1027 #define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */
1028 #define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */
1029
1030 /* PCI ID register */
1031 #define DC_CFID_VENDOR 0x0000FFFF
1032 #define DC_CFID_DEVICE 0xFFFF0000
1033
1034 /* PCI command/status register */
1035 #define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */
1036 #define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */
1037 #define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */
1038 #define DC_CFCS_MWI_ENB 0x00000010 /* mem write and inval enable */
1039 #define DC_CFCS_PARITYERR_ENB 0x00000040 /* parity error enable */
1040 #define DC_CFCS_SYSERR_ENB 0x00000100 /* system error enable */
1041 #define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */
1042 #define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */
1043 #define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */
1044 #define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */
1045 #define DC_CFCS_TGTABRT 0x10000000 /* received target abort */
1046 #define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */
1047 #define DC_CFCS_SYSERR 0x40000000 /* asserted system error */
1048 #define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */
1049
1050 /* PCI revision register */
1051 #define DC_CFRV_STEPPING 0x0000000F
1052 #define DC_CFRV_REVISION 0x000000F0
1053 #define DC_CFRV_SUBCLASS 0x00FF0000
1054 #define DC_CFRV_BASECLASS 0xFF000000
1055
1056 #define DC_21143_PB_REV 0x00000030
1057 #define DC_21143_TB_REV 0x00000030
1058 #define DC_21143_PC_REV 0x00000030
1059 #define DC_21143_TC_REV 0x00000030
1060 #define DC_21143_PD_REV 0x00000041
1061 #define DC_21143_TD_REV 0x00000041
1062
1063 /* PCI latency timer register */
1064 #define DC_CFLT_CACHELINESIZE 0x000000FF
1065 #define DC_CFLT_LATENCYTIMER 0x0000FF00
1066
1067 /* PCI subsystem ID register */
1068 #define DC_CSID_VENDOR 0x0000FFFF
1069 #define DC_CSID_DEVICE 0xFFFF0000
1070
1071 /* PCI cababilities pointer */
1072 #define DC_CCAP_OFFSET 0x000000FF
1073
1074 /* PCI interrupt config register */
1075 #define DC_CFIT_INTLINE 0x000000FF
1076 #define DC_CFIT_INTPIN 0x0000FF00
1077 #define DC_CFIT_MIN_GNT 0x00FF0000
1078 #define DC_CFIT_MAX_LAT 0xFF000000
1079
1080 /* PCI capability register */
1081 #define DC_CCID_CAPID 0x000000FF
1082 #define DC_CCID_NEXTPTR 0x0000FF00
1083 #define DC_CCID_PM_VERS 0x00070000
1084 #define DC_CCID_PME_CLK 0x00080000
1085 #define DC_CCID_DVSPEC_INT 0x00200000
1086 #define DC_CCID_STATE_D1 0x02000000
1087 #define DC_CCID_STATE_D2 0x04000000
1088 #define DC_CCID_PME_D0 0x08000000
1089 #define DC_CCID_PME_D1 0x10000000
1090 #define DC_CCID_PME_D2 0x20000000
1091 #define DC_CCID_PME_D3HOT 0x40000000
1092 #define DC_CCID_PME_D3COLD 0x80000000
1093
1094 /* PCI power management control/status register */
1095 #define DC_CPMC_STATE 0x00000003
1096 #define DC_CPMC_PME_ENB 0x00000100
1097 #define DC_CPMC_PME_STS 0x00008000
1098
1099 #define DC_PSTATE_D0 0x0
1100 #define DC_PSTATE_D1 0x1
1101 #define DC_PSTATE_D2 0x2
1102 #define DC_PSTATE_D3 0x3
1103
1104 /* Device specific region */
1105 /* Configuration and driver area */
1106 #define DC_CFDD_DRVUSE 0x0000FFFF
1107 #define DC_CFDD_SNOOZE_MODE 0x40000000
1108 #define DC_CFDD_SLEEP_MODE 0x80000000
1109
1110 /* Configuration wake-up command register */
1111 #define DC_CWUC_MUST_BE_ZERO 0x00000001
1112 #define DC_CWUC_SECUREON_ENB 0x00000002
1113 #define DC_CWUC_FORCE_WUL 0x00000004
1114 #define DC_CWUC_BNC_ABILITY 0x00000008
1115 #define DC_CWUC_AUI_ABILITY 0x00000010
1116 #define DC_CWUC_TP10_ABILITY 0x00000020
1117 #define DC_CWUC_MII_ABILITY 0x00000040
1118 #define DC_CWUC_SYM_ABILITY 0x00000080
1119 #define DC_CWUC_LOCK 0x00000100
1120
1121 /*
1122 * SROM nonsense.
1123 */
1124
1125 #define DC_IB_CTLRCNT 0x13
1126 #define DC_IB_LEAF0_CNUM 0x1A
1127 #define DC_IB_LEAF0_OFFSET 0x1B
1128
1129 struct dc_info_leaf {
1130 u_int16_t dc_conntype;
1131 u_int8_t dc_blkcnt;
1132 u_int8_t dc_rsvd;
1133 u_int16_t dc_infoblk;
1134 };
1135
1136 #define DC_CTYPE_10BT 0x0000
1137 #define DC_CTYPE_10BT_NWAY 0x0100
1138 #define DC_CTYPE_10BT_FDX 0x0204
1139 #define DC_CTYPE_10B2 0x0001
1140 #define DC_CTYPE_10B5 0x0002
1141 #define DC_CTYPE_100BT 0x0003
1142 #define DC_CTYPE_100BT_FDX 0x0205
1143 #define DC_CTYPE_100T4 0x0006
1144 #define DC_CTYPE_100FX 0x0007
1145 #define DC_CTYPE_100FX_FDX 0x0208
1146 #define DC_CTYPE_MII_10BT 0x0009
1147 #define DC_CTYPE_MII_10BT_FDX 0x020A
1148 #define DC_CTYPE_MII_100BT 0x000D
1149 #define DC_CTYPE_MII_100BT_FDX 0x020E
1150 #define DC_CTYPE_MII_100T4 0x000F
1151 #define DC_CTYPE_MII_100FX 0x0010
1152 #define DC_CTYPE_MII_100FX_FDX 0x0211
1153 #define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800
1154 #define DC_CTYPE_PUP_AUTOSENSE 0x8800
1155 #define DC_CTYPE_NOMEDIA 0xFFFF
1156
1157 #define DC_EBLOCK_SIA 0x0002
1158 #define DC_EBLOCK_MII 0x0003
1159 #define DC_EBLOCK_SYM 0x0004
1160 #define DC_EBLOCK_RESET 0x0005
1161 #define DC_EBLOCK_PHY_SHUTDOWN 0x0006
1162
1163 struct dc_leaf_hdr {
1164 u_int16_t dc_mtype;
1165 u_int8_t dc_mcnt;
1166 u_int8_t dc_rsvd;
1167 };
1168
1169 struct dc_eblock_hdr {
1170 u_int8_t dc_len;
1171 u_int8_t dc_type;
1172 };
1173
1174 struct dc_eblock_sia {
1175 struct dc_eblock_hdr dc_sia_hdr;
1176 u_int8_t dc_sia_code;
1177 union {
1178 struct dc_sia_ext { /* if (dc_sia_code & DC_SIA_CODE_EXT) */
1179 u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */
1180 u_int8_t dc_sia_gpio_ctl[2];
1181 u_int8_t dc_sia_gpio_dat[2];
1182 } dc_sia_ext;
1183 struct dc_sia_noext {
1184 u_int8_t dc_sia_gpio_ctl[2];
1185 u_int8_t dc_sia_gpio_dat[2];
1186 } dc_sia_noext;
1187 } dc_un;
1188 };
1189
1190 #define DC_SIA_CODE_10BT 0x00
1191 #define DC_SIA_CODE_10B2 0x01
1192 #define DC_SIA_CODE_10B5 0x02
1193 #define DC_SIA_CODE_10BT_FDX 0x04
1194 #define DC_SIA_CODE_EXT 0x40
1195
1196 /*
1197 * Note that the first word in the gpr and reset
1198 * sequences is always a control word.
1199 */
1200 struct dc_eblock_mii {
1201 struct dc_eblock_hdr dc_mii_hdr;
1202 u_int8_t dc_mii_phynum;
1203 u_int8_t dc_gpr_len;
1204 /* u_int16_t dc_gpr_dat[n]; */
1205 /* u_int8_t dc_reset_len; */
1206 /* u_int16_t dc_reset_dat[n]; */
1207 /* There are other fields after these, but we don't
1208 * care about them since they can be determined by looking
1209 * at the PHY.
1210 */
1211 };
1212
1213 struct dc_eblock_sym {
1214 struct dc_eblock_hdr dc_sym_hdr;
1215 u_int8_t dc_sym_code;
1216 u_int8_t dc_sym_gpio_ctl[2];
1217 u_int8_t dc_sym_gpio_dat[2];
1218 u_int8_t dc_sym_cmd[2];
1219 };
1220
1221 #define DC_SYM_CODE_100BT 0x03
1222 #define DC_SYM_CODE_100BT_FDX 0x05
1223 #define DC_SYM_CODE_100T4 0x06
1224 #define DC_SYM_CODE_100FX 0x07
1225 #define DC_SYM_CODE_100FX_FDX 0x08
1226
1227 struct dc_eblock_reset {
1228 struct dc_eblock_hdr dc_reset_hdr;
1229 u_int8_t dc_reset_len;
1230 /* u_int16_t dc_reset_dat[n]; */
1231 };
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