Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_fxp.c
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1 /* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Modifications to support NetBSD and media selection: 6 * Copyright (c) 1997 Jason R. Thorpe. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #include "bpfilter.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 46 #include <net/if.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #ifdef NS 51 #include <netns/ns.h> 52 #include <netns/ns_if.h> 53 #endif 54 55 #if NBPFILTER > 0 56 #include <net/bpf.h> 57 #endif 58 59 #if defined(__NetBSD__) 60 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #include <sys/device.h> 64 65 #include <net/if_dl.h> 66 #include <net/if_ether.h> 67 68 #include <netinet/if_inarp.h> 69 70 #include <vm/vm.h> 71 72 #include <machine/cpu.h> 73 #include <machine/bus.h> 74 #include <machine/intr.h> 75 76 #include <dev/pci/if_fxpreg.h> 77 #include <dev/pci/if_fxpvar.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 #ifdef __alpha__ /* XXX */ 84 /* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */ 85 #undef vtophys 86 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va)) 87 #endif /* __alpha__ */ 88 89 #else /* __FreeBSD__ */ 90 91 #include <sys/sockio.h> 92 93 #include <net/ethernet.h> 94 #include <net/if_arp.h> 95 96 #include <vm/vm.h> /* for vtophys */ 97 #include <vm/pmap.h> /* for vtophys */ 98 #include <machine/clock.h> /* for DELAY */ 99 100 #include <pci/pcivar.h> 101 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 102 #include <pci/if_fxpreg.h> 103 #include <pci/if_fxpvar.h> 104 105 #endif /* __NetBSD__ */ 106 107 #include "opt_bdg.h" 108 #ifdef BRIDGE 109 #include <net/if_types.h> 110 #include <net/bridge.h> 111 #endif 112 113 /* 114 * NOTE! On the Alpha, we have an alignment constraint. The 115 * card DMAs the packet immediately following the RFA. However, 116 * the first thing in the packet is a 14-byte Ethernet header. 117 * This means that the packet is misaligned. To compensate, 118 * we actually offset the RFA 2 bytes into the cluster. This 119 * alignes the packet after the Ethernet header at a 32-bit 120 * boundary. HOWEVER! This means that the RFA is misaligned! 121 */ 122 #define RFA_ALIGNMENT_FUDGE 2 123 124 /* 125 * Inline function to copy a 16-bit aligned 32-bit quantity. 126 */ 127 static __inline void fxp_lwcopy __P((volatile u_int32_t *, 128 volatile u_int32_t *)); 129 static __inline void 130 fxp_lwcopy(src, dst) 131 volatile u_int32_t *src, *dst; 132 { 133 volatile u_int16_t *a = (u_int16_t *)src; 134 volatile u_int16_t *b = (u_int16_t *)dst; 135 136 b[0] = a[0]; 137 b[1] = a[1]; 138 } 139 140 /* 141 * Template for default configuration parameters. 142 * See struct fxp_cb_config for the bit definitions. 143 */ 144 static u_char fxp_cb_config_template[] = { 145 0x0, 0x0, /* cb_status */ 146 0x80, 0x2, /* cb_command */ 147 0xff, 0xff, 0xff, 0xff, /* link_addr */ 148 0x16, /* 0 */ 149 0x8, /* 1 */ 150 0x0, /* 2 */ 151 0x0, /* 3 */ 152 0x0, /* 4 */ 153 0x80, /* 5 */ 154 0xb2, /* 6 */ 155 0x3, /* 7 */ 156 0x1, /* 8 */ 157 0x0, /* 9 */ 158 0x26, /* 10 */ 159 0x0, /* 11 */ 160 0x60, /* 12 */ 161 0x0, /* 13 */ 162 0xf2, /* 14 */ 163 0x48, /* 15 */ 164 0x0, /* 16 */ 165 0x40, /* 17 */ 166 0xf3, /* 18 */ 167 0x0, /* 19 */ 168 0x3f, /* 20 */ 169 0x5 /* 21 */ 170 }; 171 172 /* Supported media types. */ 173 struct fxp_supported_media { 174 const int fsm_phy; /* PHY type */ 175 const int *fsm_media; /* the media array */ 176 const int fsm_nmedia; /* the number of supported media */ 177 const int fsm_defmedia; /* default media for this PHY */ 178 }; 179 180 static const int fxp_media_standard[] = { 181 IFM_ETHER|IFM_10_T, 182 IFM_ETHER|IFM_10_T|IFM_FDX, 183 IFM_ETHER|IFM_100_TX, 184 IFM_ETHER|IFM_100_TX|IFM_FDX, 185 IFM_ETHER|IFM_AUTO, 186 }; 187 #define FXP_MEDIA_STANDARD_DEFMEDIA (IFM_ETHER|IFM_AUTO) 188 189 static const int fxp_media_default[] = { 190 IFM_ETHER|IFM_MANUAL, /* XXX IFM_AUTO ? */ 191 }; 192 #define FXP_MEDIA_DEFAULT_DEFMEDIA (IFM_ETHER|IFM_MANUAL) 193 194 static const struct fxp_supported_media fxp_media[] = { 195 { FXP_PHY_DP83840, fxp_media_standard, 196 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 197 FXP_MEDIA_STANDARD_DEFMEDIA }, 198 { FXP_PHY_DP83840A, fxp_media_standard, 199 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 200 FXP_MEDIA_STANDARD_DEFMEDIA }, 201 { FXP_PHY_82553A, fxp_media_standard, 202 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 203 FXP_MEDIA_STANDARD_DEFMEDIA }, 204 { FXP_PHY_82553C, fxp_media_standard, 205 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 206 FXP_MEDIA_STANDARD_DEFMEDIA }, 207 { FXP_PHY_82555, fxp_media_standard, 208 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 209 FXP_MEDIA_STANDARD_DEFMEDIA }, 210 { FXP_PHY_82555B, fxp_media_standard, 211 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 212 FXP_MEDIA_STANDARD_DEFMEDIA }, 213 { FXP_PHY_80C24, fxp_media_default, 214 sizeof(fxp_media_default) / sizeof(fxp_media_default[0]), 215 FXP_MEDIA_DEFAULT_DEFMEDIA }, 216 }; 217 #define NFXPMEDIA (sizeof(fxp_media) / sizeof(fxp_media[0])) 218 219 static int fxp_mediachange __P((struct ifnet *)); 220 static void fxp_mediastatus __P((struct ifnet *, struct ifmediareq *)); 221 static void fxp_set_media __P((struct fxp_softc *, int)); 222 static __inline void fxp_scb_wait __P((struct fxp_softc *)); 223 static FXP_INTR_TYPE fxp_intr __P((void *)); 224 static void fxp_start __P((struct ifnet *)); 225 static int fxp_ioctl __P((struct ifnet *, 226 FXP_IOCTLCMD_TYPE, caddr_t)); 227 static void fxp_init __P((void *)); 228 static void fxp_stop __P((struct fxp_softc *)); 229 static void fxp_watchdog __P((struct ifnet *)); 230 static int fxp_add_rfabuf __P((struct fxp_softc *, struct mbuf *)); 231 static int fxp_mdi_read __P((struct fxp_softc *, int, int)); 232 static void fxp_mdi_write __P((struct fxp_softc *, int, int, int)); 233 static void fxp_autosize_eeprom __P((struct fxp_softc *)); 234 static void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, 235 int, int)); 236 static int fxp_attach_common __P((struct fxp_softc *, u_int8_t *)); 237 static void fxp_stats_update __P((void *)); 238 static void fxp_mc_setup __P((struct fxp_softc *)); 239 240 /* 241 * Set initial transmit threshold at 64 (512 bytes). This is 242 * increased by 64 (512 bytes) at a time, to maximum of 192 243 * (1536 bytes), if an underrun occurs. 244 */ 245 static int tx_threshold = 64; 246 247 /* 248 * Number of transmit control blocks. This determines the number 249 * of transmit buffers that can be chained in the CB list. 250 * This must be a power of two. 251 */ 252 #define FXP_NTXCB 128 253 254 /* 255 * Number of completed TX commands at which point an interrupt 256 * will be generated to garbage collect the attached buffers. 257 * Must be at least one less than FXP_NTXCB, and should be 258 * enough less so that the transmitter doesn't becomes idle 259 * during the buffer rundown (which would reduce performance). 260 */ 261 #define FXP_CXINT_THRESH 120 262 263 /* 264 * TxCB list index mask. This is used to do list wrap-around. 265 */ 266 #define FXP_TXCB_MASK (FXP_NTXCB - 1) 267 268 /* 269 * Number of receive frame area buffers. These are large so chose 270 * wisely. 271 */ 272 #define FXP_NRFABUFS 64 273 274 /* 275 * Maximum number of seconds that the receiver can be idle before we 276 * assume it's dead and attempt to reset it by reprogramming the 277 * multicast filter. This is part of a work-around for a bug in the 278 * NIC. See fxp_stats_update(). 279 */ 280 #define FXP_MAX_RX_IDLE 15 281 282 /* 283 * Wait for the previous command to be accepted (but not necessarily 284 * completed). 285 */ 286 static __inline void 287 fxp_scb_wait(sc) 288 struct fxp_softc *sc; 289 { 290 int i = 10000; 291 292 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i); 293 } 294 295 /************************************************************* 296 * Operating system-specific autoconfiguration glue 297 *************************************************************/ 298 299 #if defined(__NetBSD__) 300 301 #ifdef __BROKEN_INDIRECT_CONFIG 302 static int fxp_match __P((struct device *, void *, void *)); 303 #else 304 static int fxp_match __P((struct device *, struct cfdata *, void *)); 305 #endif 306 static void fxp_attach __P((struct device *, struct device *, void *)); 307 308 static void fxp_shutdown __P((void *)); 309 310 /* Compensate for lack of a generic ether_ioctl() */ 311 static int fxp_ether_ioctl __P((struct ifnet *, 312 FXP_IOCTLCMD_TYPE, caddr_t)); 313 #define ether_ioctl fxp_ether_ioctl 314 315 struct cfattach fxp_ca = { 316 sizeof(struct fxp_softc), fxp_match, fxp_attach 317 }; 318 319 struct cfdriver fxp_cd = { 320 NULL, "fxp", DV_IFNET 321 }; 322 323 /* 324 * Check if a device is an 82557. 325 */ 326 static int 327 fxp_match(parent, match, aux) 328 struct device *parent; 329 #ifdef __BROKEN_INDIRECT_CONFIG 330 void *match; 331 #else 332 struct cfdata *match; 333 #endif 334 void *aux; 335 { 336 struct pci_attach_args *pa = aux; 337 338 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 339 return (0); 340 341 switch (PCI_PRODUCT(pa->pa_id)) { 342 case PCI_PRODUCT_INTEL_82557: 343 return (1); 344 } 345 346 return (0); 347 } 348 349 static void 350 fxp_attach(parent, self, aux) 351 struct device *parent, *self; 352 void *aux; 353 { 354 struct fxp_softc *sc = (struct fxp_softc *)self; 355 struct pci_attach_args *pa = aux; 356 pci_chipset_tag_t pc = pa->pa_pc; 357 pci_intr_handle_t ih; 358 const char *intrstr = NULL; 359 u_int8_t enaddr[6]; 360 struct ifnet *ifp; 361 362 /* 363 * Map control/status registers. 364 */ 365 if (pci_mapreg_map(pa, FXP_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0, 366 &sc->sc_st, &sc->sc_sh, NULL, NULL)) { 367 printf(": can't map registers\n"); 368 return; 369 } 370 printf(": Intel EtherExpress Pro 10/100B Ethernet\n"); 371 372 /* 373 * Allocate our interrupt. 374 */ 375 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 376 pa->pa_intrline, &ih)) { 377 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 378 return; 379 } 380 intrstr = pci_intr_string(pc, ih); 381 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 382 if (sc->sc_ih == NULL) { 383 printf("%s: couldn't establish interrupt", 384 sc->sc_dev.dv_xname); 385 if (intrstr != NULL) 386 printf(" at %s", intrstr); 387 printf("\n"); 388 return; 389 } 390 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 391 392 /* Do generic parts of attach. */ 393 if (fxp_attach_common(sc, enaddr)) { 394 /* Failed! */ 395 return; 396 } 397 398 printf("%s: Ethernet address %s%s\n", sc->sc_dev.dv_xname, 399 ether_sprintf(enaddr), sc->phy_10Mbps_only ? ", 10Mbps" : ""); 400 401 ifp = &sc->sc_ethercom.ec_if; 402 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 403 ifp->if_softc = sc; 404 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 405 ifp->if_ioctl = fxp_ioctl; 406 ifp->if_start = fxp_start; 407 ifp->if_watchdog = fxp_watchdog; 408 409 /* 410 * Attach the interface. 411 */ 412 if_attach(ifp); 413 /* 414 * Let the system queue as many packets as we have available 415 * TX descriptors. 416 */ 417 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 418 ether_ifattach(ifp, enaddr); 419 #if NBPFILTER > 0 420 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 421 sizeof(struct ether_header)); 422 #endif 423 424 /* 425 * Add shutdown hook so that DMA is disabled prior to reboot. Not 426 * doing do could allow DMA to corrupt kernel memory during the 427 * reboot before the driver initializes. 428 */ 429 shutdownhook_establish(fxp_shutdown, sc); 430 } 431 432 /* 433 * Device shutdown routine. Called at system shutdown after sync. The 434 * main purpose of this routine is to shut off receiver DMA so that 435 * kernel memory doesn't get clobbered during warmboot. 436 */ 437 static void 438 fxp_shutdown(sc) 439 void *sc; 440 { 441 fxp_stop((struct fxp_softc *) sc); 442 } 443 444 static int 445 fxp_ether_ioctl(ifp, cmd, data) 446 struct ifnet *ifp; 447 FXP_IOCTLCMD_TYPE cmd; 448 caddr_t data; 449 { 450 struct ifaddr *ifa = (struct ifaddr *) data; 451 struct fxp_softc *sc = ifp->if_softc; 452 453 switch (cmd) { 454 case SIOCSIFADDR: 455 ifp->if_flags |= IFF_UP; 456 457 switch (ifa->ifa_addr->sa_family) { 458 #ifdef INET 459 case AF_INET: 460 fxp_init(sc); 461 arp_ifinit(ifp, ifa); 462 break; 463 #endif 464 #ifdef NS 465 case AF_NS: 466 { 467 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 468 469 if (ns_nullhost(*ina)) 470 ina->x_host = *(union ns_host *) 471 LLADDR(ifp->if_sadl); 472 else 473 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 474 ifp->if_addrlen); 475 /* Set new address. */ 476 fxp_init(sc); 477 break; 478 } 479 #endif 480 default: 481 fxp_init(sc); 482 break; 483 } 484 break; 485 486 default: 487 return (EINVAL); 488 } 489 490 return (0); 491 } 492 493 #else /* __FreeBSD__ */ 494 495 static u_long fxp_count; 496 static const char *fxp_probe __P((pcici_t, pcidi_t)); 497 static void fxp_attach __P((pcici_t, int)); 498 499 static void fxp_shutdown __P((int, void *)); 500 501 static struct pci_device fxp_device = { 502 "fxp", 503 fxp_probe, 504 fxp_attach, 505 &fxp_count, 506 NULL 507 }; 508 DATA_SET(pcidevice_set, fxp_device); 509 510 /* 511 * Return identification string if this is device is ours. 512 */ 513 static const char * 514 fxp_probe(config_id, device_id) 515 pcici_t config_id; 516 pcidi_t device_id; 517 { 518 if (((device_id & 0xffff) == FXP_VENDORID_INTEL) && 519 ((device_id >> 16) & 0xffff) == FXP_DEVICEID_i82557) 520 return ("Intel EtherExpress Pro 10/100B Ethernet"); 521 if (((device_id & 0xffff) == FXP_VENDORID_INTEL) && 522 ((device_id >> 16) & 0xffff) == FXP_DEVICEID_i82559) 523 return ("Intel InBusiness 10/100 Ethernet"); 524 525 return NULL; 526 } 527 528 static void 529 fxp_attach(config_id, unit) 530 pcici_t config_id; 531 int unit; 532 { 533 struct fxp_softc *sc; 534 vm_offset_t pbase; 535 struct ifnet *ifp; 536 int s; 537 u_long val; 538 539 sc = malloc(sizeof(struct fxp_softc), M_DEVBUF, M_NOWAIT); 540 if (sc == NULL) 541 return; 542 bzero(sc, sizeof(struct fxp_softc)); 543 callout_handle_init(&sc->stat_ch); 544 545 s = splimp(); 546 547 /* 548 * Enable bus mastering. 549 */ 550 val = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 551 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 552 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, val); 553 554 /* 555 * Map control/status registers. 556 */ 557 if (!pci_map_mem(config_id, FXP_PCI_MMBA, 558 (vm_offset_t *)&sc->csr, &pbase)) { 559 printf("fxp%d: couldn't map memory\n", unit); 560 goto fail; 561 } 562 563 /* 564 * Allocate our interrupt. 565 */ 566 if (!pci_map_int(config_id, fxp_intr, sc, &net_imask)) { 567 printf("fxp%d: couldn't map interrupt\n", unit); 568 goto fail; 569 } 570 571 /* Do generic parts of attach. */ 572 if (fxp_attach_common(sc, sc->arpcom.ac_enaddr)) { 573 /* Failed! */ 574 (void) pci_unmap_int(config_id); 575 goto fail; 576 } 577 578 printf("fxp%d: Ethernet address %6D%s\n", unit, 579 sc->arpcom.ac_enaddr, ":", sc->phy_10Mbps_only ? ", 10Mbps" : ""); 580 581 ifp = &sc->arpcom.ac_if; 582 ifp->if_unit = unit; 583 ifp->if_name = "fxp"; 584 ifp->if_output = ether_output; 585 ifp->if_baudrate = 100000000; 586 ifp->if_init = fxp_init; 587 ifp->if_softc = sc; 588 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 589 ifp->if_ioctl = fxp_ioctl; 590 ifp->if_start = fxp_start; 591 ifp->if_watchdog = fxp_watchdog; 592 593 /* 594 * Attach the interface. 595 */ 596 if_attach(ifp); 597 /* 598 * Let the system queue as many packets as we have available 599 * TX descriptors. 600 */ 601 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 602 ether_ifattach(ifp); 603 #if NBPFILTER > 0 604 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 605 #endif 606 607 /* 608 * Add shutdown hook so that DMA is disabled prior to reboot. Not 609 * doing do could allow DMA to corrupt kernel memory during the 610 * reboot before the driver initializes. 611 */ 612 at_shutdown(fxp_shutdown, sc, SHUTDOWN_POST_SYNC); 613 614 splx(s); 615 return; 616 617 fail: 618 free(sc, M_DEVBUF); 619 splx(s); 620 } 621 622 /* 623 * Device shutdown routine. Called at system shutdown after sync. The 624 * main purpose of this routine is to shut off receiver DMA so that 625 * kernel memory doesn't get clobbered during warmboot. 626 */ 627 static void 628 fxp_shutdown(howto, sc) 629 int howto; 630 void *sc; 631 { 632 fxp_stop((struct fxp_softc *) sc); 633 } 634 635 #endif /* __NetBSD__ */ 636 637 /************************************************************* 638 * End of operating system-specific autoconfiguration glue 639 *************************************************************/ 640 641 /* 642 * Do generic parts of attach. 643 */ 644 static int 645 fxp_attach_common(sc, enaddr) 646 struct fxp_softc *sc; 647 u_int8_t *enaddr; 648 { 649 u_int16_t data; 650 int i, nmedia, defmedia; 651 const int *media; 652 653 /* 654 * Reset to a stable state. 655 */ 656 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 657 DELAY(10); 658 659 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 660 M_DEVBUF, M_NOWAIT); 661 if (sc->cbl_base == NULL) 662 goto fail; 663 bzero(sc->cbl_base, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 664 665 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, M_NOWAIT); 666 if (sc->fxp_stats == NULL) 667 goto fail; 668 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 669 670 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 671 if (sc->mcsp == NULL) 672 goto fail; 673 674 /* 675 * Pre-allocate our receive buffers. 676 */ 677 for (i = 0; i < FXP_NRFABUFS; i++) { 678 if (fxp_add_rfabuf(sc, NULL) != 0) { 679 goto fail; 680 } 681 } 682 683 /* 684 * Find out how large of an SEEPROM we have. 685 */ 686 fxp_autosize_eeprom(sc); 687 688 /* 689 * Get info about the primary PHY 690 */ 691 fxp_read_eeprom(sc, (u_int16_t *)&data, 6, 1); 692 sc->phy_primary_addr = data & 0xff; 693 sc->phy_primary_device = (data >> 8) & 0x3f; 694 sc->phy_10Mbps_only = data >> 15; 695 696 /* 697 * Read MAC address. 698 */ 699 fxp_read_eeprom(sc, (u_int16_t *)enaddr, 0, 3); 700 701 /* 702 * Initialize the media structures. 703 */ 704 705 media = fxp_media_default; 706 nmedia = sizeof(fxp_media_default) / sizeof(fxp_media_default[0]); 707 defmedia = FXP_MEDIA_DEFAULT_DEFMEDIA; 708 709 for (i = 0; i < NFXPMEDIA; i++) { 710 if (sc->phy_primary_device == fxp_media[i].fsm_phy) { 711 media = fxp_media[i].fsm_media; 712 nmedia = fxp_media[i].fsm_nmedia; 713 defmedia = fxp_media[i].fsm_defmedia; 714 } 715 } 716 717 ifmedia_init(&sc->sc_media, 0, fxp_mediachange, fxp_mediastatus); 718 for (i = 0; i < nmedia; i++) { 719 if (IFM_SUBTYPE(media[i]) == IFM_100_TX && sc->phy_10Mbps_only) 720 continue; 721 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 722 } 723 ifmedia_set(&sc->sc_media, defmedia); 724 725 return (0); 726 727 fail: 728 printf(FXP_FORMAT ": Failed to malloc memory\n", FXP_ARGS(sc)); 729 if (sc->cbl_base) 730 free(sc->cbl_base, M_DEVBUF); 731 if (sc->fxp_stats) 732 free(sc->fxp_stats, M_DEVBUF); 733 if (sc->mcsp) 734 free(sc->mcsp, M_DEVBUF); 735 /* frees entire chain */ 736 if (sc->rfa_headm) 737 m_freem(sc->rfa_headm); 738 739 return (ENOMEM); 740 } 741 742 /* 743 * From NetBSD: 744 * 745 * Figure out EEPROM size. 746 * 747 * 559's can have either 64-word or 256-word EEPROMs, the 558 748 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 749 * talks about the existance of 16 to 256 word EEPROMs. 750 * 751 * The only known sizes are 64 and 256, where the 256 version is used 752 * by CardBus cards to store CIS information. 753 * 754 * The address is shifted in msb-to-lsb, and after the last 755 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 756 * after which follows the actual data. We try to detect this zero, by 757 * probing the data-out bit in the EEPROM control register just after 758 * having shifted in a bit. If the bit is zero, we assume we've 759 * shifted enough address bits. The data-out should be tri-state, 760 * before this, which should translate to a logical one. 761 * 762 * Other ways to do this would be to try to read a register with known 763 * contents with a varying number of address bits, but no such 764 * register seem to be available. The high bits of register 10 are 01 765 * on the 558 and 559, but apparently not on the 557. 766 * 767 * The Linux driver computes a checksum on the EEPROM data, but the 768 * value of this checksum is not very well documented. 769 */ 770 static void 771 fxp_autosize_eeprom(sc) 772 struct fxp_softc *sc; 773 { 774 u_int16_t reg; 775 int x; 776 777 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 778 /* 779 * Shift in read opcode. 780 */ 781 for (x = 3; x > 0; x--) { 782 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 783 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 784 } else { 785 reg = FXP_EEPROM_EECS; 786 } 787 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 788 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 789 reg | FXP_EEPROM_EESK); 790 DELAY(1); 791 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 792 DELAY(1); 793 } 794 /* 795 * Shift in address. 796 * Wait for the dummy zero following a correct address shift. 797 */ 798 for (x = 1; x <= 8; x++) { 799 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 800 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 801 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 802 DELAY(1); 803 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) == 0) 804 break; 805 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 806 DELAY(1); 807 } 808 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 809 DELAY(1); 810 sc->eeprom_size = x; 811 } 812 /* 813 * Read from the serial EEPROM. Basically, you manually shift in 814 * the read opcode (one bit at a time) and then shift in the address, 815 * and then you shift out the data (all of this one bit at a time). 816 * The word size is 16 bits, so you have to provide the address for 817 * every 16 bits of data. 818 */ 819 static void 820 fxp_read_eeprom(sc, data, offset, words) 821 struct fxp_softc *sc; 822 u_short *data; 823 int offset; 824 int words; 825 { 826 u_int16_t reg; 827 int i, x; 828 829 for (i = 0; i < words; i++) { 830 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 831 /* 832 * Shift in read opcode. 833 */ 834 for (x = 3; x > 0; x--) { 835 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 836 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 837 } else { 838 reg = FXP_EEPROM_EECS; 839 } 840 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 841 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 842 reg | FXP_EEPROM_EESK); 843 DELAY(1); 844 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 845 DELAY(1); 846 } 847 /* 848 * Shift in address. 849 */ 850 for (x = sc->eeprom_size; x > 0; x--) { 851 if ((i + offset) & (1 << (x - 1))) { 852 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 853 } else { 854 reg = FXP_EEPROM_EECS; 855 } 856 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 857 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 858 reg | FXP_EEPROM_EESK); 859 DELAY(1); 860 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 861 DELAY(1); 862 } 863 reg = FXP_EEPROM_EECS; 864 data[i] = 0; 865 /* 866 * Shift out data. 867 */ 868 for (x = 16; x > 0; x--) { 869 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 870 reg | FXP_EEPROM_EESK); 871 DELAY(1); 872 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 873 FXP_EEPROM_EEDO) 874 data[i] |= (1 << (x - 1)); 875 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 876 DELAY(1); 877 } 878 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 879 DELAY(1); 880 } 881 } 882 883 /* 884 * Start packet transmission on the interface. 885 */ 886 static void 887 fxp_start(ifp) 888 struct ifnet *ifp; 889 { 890 struct fxp_softc *sc = ifp->if_softc; 891 struct fxp_cb_tx *txp; 892 893 /* 894 * See if we need to suspend xmit until the multicast filter 895 * has been reprogrammed (which can only be done at the head 896 * of the command chain). 897 */ 898 if (sc->need_mcsetup) 899 return; 900 901 txp = NULL; 902 903 /* 904 * We're finished if there is nothing more to add to the list or if 905 * we're all filled up with buffers to transmit. 906 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 907 * a NOP command when needed. 908 */ 909 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 910 struct mbuf *m, *mb_head; 911 int segment; 912 913 /* 914 * Grab a packet to transmit. 915 */ 916 IF_DEQUEUE(&ifp->if_snd, mb_head); 917 918 /* 919 * Get pointer to next available tx desc. 920 */ 921 txp = sc->cbl_last->next; 922 923 /* 924 * Go through each of the mbufs in the chain and initialize 925 * the transmit buffer descriptors with the physical address 926 * and size of the mbuf. 927 */ 928 tbdinit: 929 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 930 if (m->m_len != 0) { 931 if (segment == FXP_NTXSEG) 932 break; 933 txp->tbd[segment].tb_addr = 934 vtophys(mtod(m, vm_offset_t)); 935 txp->tbd[segment].tb_size = m->m_len; 936 segment++; 937 } 938 } 939 if (m != NULL) { 940 struct mbuf *mn; 941 942 /* 943 * We ran out of segments. We have to recopy this mbuf 944 * chain first. Bail out if we can't get the new buffers. 945 */ 946 MGETHDR(mn, M_DONTWAIT, MT_DATA); 947 if (mn == NULL) { 948 m_freem(mb_head); 949 break; 950 } 951 if (mb_head->m_pkthdr.len > MHLEN) { 952 MCLGET(mn, M_DONTWAIT); 953 if ((mn->m_flags & M_EXT) == 0) { 954 m_freem(mn); 955 m_freem(mb_head); 956 break; 957 } 958 } 959 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 960 mtod(mn, caddr_t)); 961 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 962 m_freem(mb_head); 963 mb_head = mn; 964 goto tbdinit; 965 } 966 967 txp->tbd_number = segment; 968 txp->mb_head = mb_head; 969 txp->cb_status = 0; 970 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 971 txp->cb_command = 972 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S; 973 } else { 974 txp->cb_command = 975 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 976 /* 977 * Set a 5 second timer just in case we don't hear from the 978 * card again. 979 */ 980 ifp->if_timer = 5; 981 } 982 txp->tx_threshold = tx_threshold; 983 984 /* 985 * Advance the end of list forward. 986 */ 987 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 988 sc->cbl_last = txp; 989 990 /* 991 * Advance the beginning of the list forward if there are 992 * no other packets queued (when nothing is queued, cbl_first 993 * sits on the last TxCB that was sent out). 994 */ 995 if (sc->tx_queued == 0) 996 sc->cbl_first = txp; 997 998 sc->tx_queued++; 999 1000 #if NBPFILTER > 0 1001 /* 1002 * Pass packet to bpf if there is a listener. 1003 */ 1004 if (ifp->if_bpf) 1005 bpf_mtap(FXP_BPFTAP_ARG(ifp), mb_head); 1006 #endif 1007 } 1008 1009 /* 1010 * We're finished. If we added to the list, issue a RESUME to get DMA 1011 * going again if suspended. 1012 */ 1013 if (txp != NULL) { 1014 fxp_scb_wait(sc); 1015 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 1016 } 1017 } 1018 1019 /* 1020 * Process interface interrupts. 1021 */ 1022 static FXP_INTR_TYPE 1023 fxp_intr(arg) 1024 void *arg; 1025 { 1026 struct fxp_softc *sc = arg; 1027 struct ifnet *ifp = &sc->sc_if; 1028 u_int8_t statack; 1029 #if defined(__NetBSD__) 1030 int claimed = 0; 1031 #endif 1032 1033 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1034 #if defined(__NetBSD__) 1035 claimed = 1; 1036 #endif 1037 /* 1038 * First ACK all the interrupts in this pass. 1039 */ 1040 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1041 1042 /* 1043 * Free any finished transmit mbuf chains. 1044 */ 1045 if (statack & FXP_SCB_STATACK_CXTNO) { 1046 struct fxp_cb_tx *txp; 1047 1048 for (txp = sc->cbl_first; sc->tx_queued && 1049 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1050 txp = txp->next) { 1051 if (txp->mb_head != NULL) { 1052 m_freem(txp->mb_head); 1053 txp->mb_head = NULL; 1054 } 1055 sc->tx_queued--; 1056 } 1057 sc->cbl_first = txp; 1058 ifp->if_timer = 0; 1059 if (sc->tx_queued == 0) { 1060 if (sc->need_mcsetup) 1061 fxp_mc_setup(sc); 1062 } 1063 /* 1064 * Try to start more packets transmitting. 1065 */ 1066 if (ifp->if_snd.ifq_head != NULL) 1067 fxp_start(ifp); 1068 } 1069 /* 1070 * Process receiver interrupts. If a no-resource (RNR) 1071 * condition exists, get whatever packets we can and 1072 * re-start the receiver. 1073 */ 1074 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1075 struct mbuf *m; 1076 struct fxp_rfa *rfa; 1077 rcvloop: 1078 m = sc->rfa_headm; 1079 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1080 RFA_ALIGNMENT_FUDGE); 1081 1082 if (rfa->rfa_status & FXP_RFA_STATUS_C) { 1083 /* 1084 * Remove first packet from the chain. 1085 */ 1086 sc->rfa_headm = m->m_next; 1087 m->m_next = NULL; 1088 1089 /* 1090 * Add a new buffer to the receive chain. 1091 * If this fails, the old buffer is recycled 1092 * instead. 1093 */ 1094 if (fxp_add_rfabuf(sc, m) == 0) { 1095 struct ether_header *eh; 1096 u_int16_t total_len; 1097 1098 total_len = rfa->actual_size & 1099 (MCLBYTES - 1); 1100 if (total_len < 1101 sizeof(struct ether_header)) { 1102 m_freem(m); 1103 goto rcvloop; 1104 } 1105 m->m_pkthdr.rcvif = ifp; 1106 m->m_pkthdr.len = m->m_len = 1107 total_len ; 1108 eh = mtod(m, struct ether_header *); 1109 #if NBPFILTER > 0 1110 if (ifp->if_bpf) 1111 bpf_tap(FXP_BPFTAP_ARG(ifp), 1112 mtod(m, caddr_t), 1113 total_len); 1114 #endif /* NBPFILTER > 0 */ 1115 #ifdef BRIDGE 1116 if (do_bridge) { 1117 struct ifnet *bdg_ifp ; 1118 bdg_ifp = bridge_in(m); 1119 if (bdg_ifp == BDG_DROP) 1120 goto dropit ; 1121 if (bdg_ifp != BDG_LOCAL) 1122 bdg_forward(&m, bdg_ifp); 1123 if (m == NULL) 1124 goto dropit ; 1125 if (bdg_ifp != BDG_LOCAL && 1126 bdg_ifp != BDG_BCAST && 1127 bdg_ifp != BDG_MCAST) 1128 goto dropit ; 1129 eh = mtod(m, struct ether_header *); 1130 } else 1131 #endif 1132 /* 1133 * Only pass this packet up 1134 * if it is for us. 1135 */ 1136 if ((ifp->if_flags & 1137 IFF_PROMISC) && 1138 (rfa->rfa_status & 1139 FXP_RFA_STATUS_IAMATCH) && 1140 (eh->ether_dhost[0] & 1) 1141 == 0) { 1142 dropit: 1143 if (m) 1144 m_freem(m); 1145 goto rcvloop; 1146 } 1147 m->m_data += 1148 sizeof(struct ether_header); 1149 m->m_len -= 1150 sizeof(struct ether_header); 1151 m->m_pkthdr.len = m->m_len ; 1152 ether_input(ifp, eh, m); 1153 } 1154 goto rcvloop; 1155 } 1156 if (statack & FXP_SCB_STATACK_RNR) { 1157 fxp_scb_wait(sc); 1158 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1159 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1160 RFA_ALIGNMENT_FUDGE); 1161 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1162 FXP_SCB_COMMAND_RU_START); 1163 } 1164 } 1165 } 1166 #if defined(__NetBSD__) 1167 return (claimed); 1168 #endif 1169 } 1170 1171 /* 1172 * Update packet in/out/collision statistics. The i82557 doesn't 1173 * allow you to access these counters without doing a fairly 1174 * expensive DMA to get _all_ of the statistics it maintains, so 1175 * we do this operation here only once per second. The statistics 1176 * counters in the kernel are updated from the previous dump-stats 1177 * DMA and then a new dump-stats DMA is started. The on-chip 1178 * counters are zeroed when the DMA completes. If we can't start 1179 * the DMA immediately, we don't wait - we just prepare to read 1180 * them again next time. 1181 */ 1182 static void 1183 fxp_stats_update(arg) 1184 void *arg; 1185 { 1186 struct fxp_softc *sc = arg; 1187 struct ifnet *ifp = &sc->sc_if; 1188 struct fxp_stats *sp = sc->fxp_stats; 1189 struct fxp_cb_tx *txp; 1190 int s; 1191 1192 ifp->if_opackets += sp->tx_good; 1193 ifp->if_collisions += sp->tx_total_collisions; 1194 if (sp->rx_good) { 1195 ifp->if_ipackets += sp->rx_good; 1196 sc->rx_idle_secs = 0; 1197 } else { 1198 /* 1199 * Receiver's been idle for another second. 1200 */ 1201 sc->rx_idle_secs++; 1202 } 1203 ifp->if_ierrors += 1204 sp->rx_crc_errors + 1205 sp->rx_alignment_errors + 1206 sp->rx_rnr_errors + 1207 sp->rx_overrun_errors; 1208 /* 1209 * If any transmit underruns occured, bump up the transmit 1210 * threshold by another 512 bytes (64 * 8). 1211 */ 1212 if (sp->tx_underruns) { 1213 ifp->if_oerrors += sp->tx_underruns; 1214 if (tx_threshold < 192) 1215 tx_threshold += 64; 1216 } 1217 s = splimp(); 1218 /* 1219 * Release any xmit buffers that have completed DMA. This isn't 1220 * strictly necessary to do here, but it's advantagous for mbufs 1221 * with external storage to be released in a timely manner rather 1222 * than being defered for a potentially long time. This limits 1223 * the delay to a maximum of one second. 1224 */ 1225 for (txp = sc->cbl_first; sc->tx_queued && 1226 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1227 txp = txp->next) { 1228 if (txp->mb_head != NULL) { 1229 m_freem(txp->mb_head); 1230 txp->mb_head = NULL; 1231 } 1232 sc->tx_queued--; 1233 } 1234 sc->cbl_first = txp; 1235 /* 1236 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1237 * then assume the receiver has locked up and attempt to clear 1238 * the condition by reprogramming the multicast filter. This is 1239 * a work-around for a bug in the 82557 where the receiver locks 1240 * up if it gets certain types of garbage in the syncronization 1241 * bits prior to the packet header. This bug is supposed to only 1242 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1243 * mode as well (perhaps due to a 10/100 speed transition). 1244 */ 1245 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1246 sc->rx_idle_secs = 0; 1247 fxp_mc_setup(sc); 1248 } 1249 /* 1250 * If there is no pending command, start another stats 1251 * dump. Otherwise punt for now. 1252 */ 1253 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1254 /* 1255 * Start another stats dump. 1256 */ 1257 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1258 FXP_SCB_COMMAND_CU_DUMPRESET); 1259 } else { 1260 /* 1261 * A previous command is still waiting to be accepted. 1262 * Just zero our copy of the stats and wait for the 1263 * next timer event to update them. 1264 */ 1265 sp->tx_good = 0; 1266 sp->tx_underruns = 0; 1267 sp->tx_total_collisions = 0; 1268 1269 sp->rx_good = 0; 1270 sp->rx_crc_errors = 0; 1271 sp->rx_alignment_errors = 0; 1272 sp->rx_rnr_errors = 0; 1273 sp->rx_overrun_errors = 0; 1274 } 1275 splx(s); 1276 /* 1277 * Schedule another timeout one second from now. 1278 */ 1279 sc->stat_ch = timeout(fxp_stats_update, sc, hz); 1280 } 1281 1282 /* 1283 * Stop the interface. Cancels the statistics updater and resets 1284 * the interface. 1285 */ 1286 static void 1287 fxp_stop(sc) 1288 struct fxp_softc *sc; 1289 { 1290 struct ifnet *ifp = &sc->sc_if; 1291 struct fxp_cb_tx *txp; 1292 int i; 1293 1294 /* 1295 * Cancel stats updater. 1296 */ 1297 untimeout(fxp_stats_update, sc, sc->stat_ch); 1298 1299 /* 1300 * Issue software reset 1301 */ 1302 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1303 DELAY(10); 1304 1305 /* 1306 * Release any xmit buffers. 1307 */ 1308 txp = sc->cbl_base; 1309 if (txp != NULL) { 1310 for (i = 0; i < FXP_NTXCB; i++) { 1311 if (txp[i].mb_head != NULL) { 1312 m_freem(txp[i].mb_head); 1313 txp[i].mb_head = NULL; 1314 } 1315 } 1316 } 1317 sc->tx_queued = 0; 1318 1319 /* 1320 * Free all the receive buffers then reallocate/reinitialize 1321 */ 1322 if (sc->rfa_headm != NULL) 1323 m_freem(sc->rfa_headm); 1324 sc->rfa_headm = NULL; 1325 sc->rfa_tailm = NULL; 1326 for (i = 0; i < FXP_NRFABUFS; i++) { 1327 if (fxp_add_rfabuf(sc, NULL) != 0) { 1328 /* 1329 * This "can't happen" - we're at splimp() 1330 * and we just freed all the buffers we need 1331 * above. 1332 */ 1333 panic("fxp_stop: no buffers!"); 1334 } 1335 } 1336 1337 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1338 ifp->if_timer = 0; 1339 } 1340 1341 /* 1342 * Watchdog/transmission transmit timeout handler. Called when a 1343 * transmission is started on the interface, but no interrupt is 1344 * received before the timeout. This usually indicates that the 1345 * card has wedged for some reason. 1346 */ 1347 static void 1348 fxp_watchdog(ifp) 1349 struct ifnet *ifp; 1350 { 1351 struct fxp_softc *sc = ifp->if_softc; 1352 1353 printf(FXP_FORMAT ": device timeout\n", FXP_ARGS(sc)); 1354 ifp->if_oerrors++; 1355 1356 fxp_init(sc); 1357 } 1358 1359 static void 1360 fxp_init(xsc) 1361 void *xsc; 1362 { 1363 struct fxp_softc *sc = xsc; 1364 struct ifnet *ifp = &sc->sc_if; 1365 struct fxp_cb_config *cbp; 1366 struct fxp_cb_ias *cb_ias; 1367 struct fxp_cb_tx *txp; 1368 int i, s, prm; 1369 1370 s = splimp(); 1371 /* 1372 * Cancel any pending I/O 1373 */ 1374 fxp_stop(sc); 1375 1376 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1377 1378 /* 1379 * Initialize base of CBL and RFA memory. Loading with zero 1380 * sets it up for regular linear addressing. 1381 */ 1382 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1383 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1384 1385 fxp_scb_wait(sc); 1386 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1387 1388 /* 1389 * Initialize base of dump-stats buffer. 1390 */ 1391 fxp_scb_wait(sc); 1392 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1393 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1394 1395 /* 1396 * We temporarily use memory that contains the TxCB list to 1397 * construct the config CB. The TxCB list memory is rebuilt 1398 * later. 1399 */ 1400 cbp = (struct fxp_cb_config *) sc->cbl_base; 1401 1402 /* 1403 * This bcopy is kind of disgusting, but there are a bunch of must be 1404 * zero and must be one bits in this structure and this is the easiest 1405 * way to initialize them all to proper values. 1406 */ 1407 bcopy(fxp_cb_config_template, (void *)&cbp->cb_status, 1408 sizeof(fxp_cb_config_template)); 1409 1410 cbp->cb_status = 0; 1411 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1412 cbp->link_addr = -1; /* (no) next command */ 1413 cbp->byte_count = 22; /* (22) bytes to config */ 1414 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1415 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1416 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1417 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1418 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1419 cbp->dma_bce = 0; /* (disable) dma max counters */ 1420 cbp->late_scb = 0; /* (don't) defer SCB update */ 1421 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1422 cbp->ci_int = 1; /* interrupt on CU idle */ 1423 cbp->save_bf = prm; /* save bad frames */ 1424 cbp->disc_short_rx = !prm; /* discard short packets */ 1425 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1426 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1427 cbp->nsai = 1; /* (don't) disable source addr insert */ 1428 cbp->preamble_length = 2; /* (7 byte) preamble */ 1429 cbp->loopback = 0; /* (don't) loopback */ 1430 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1431 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1432 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1433 cbp->promiscuous = prm; /* promiscuous mode */ 1434 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1435 cbp->crscdt = 0; /* (CRS only) */ 1436 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1437 cbp->padding = 1; /* (do) pad short tx packets */ 1438 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1439 cbp->force_fdx = 0; /* (don't) force full duplex */ 1440 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1441 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1442 cbp->mc_all = sc->all_mcasts;/* accept all multicasts */ 1443 1444 /* 1445 * Start the config command/DMA. 1446 */ 1447 fxp_scb_wait(sc); 1448 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1449 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1450 /* ...and wait for it to complete. */ 1451 while (!(cbp->cb_status & FXP_CB_STATUS_C)); 1452 1453 /* 1454 * Now initialize the station address. Temporarily use the TxCB 1455 * memory area like we did above for the config CB. 1456 */ 1457 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1458 cb_ias->cb_status = 0; 1459 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1460 cb_ias->link_addr = -1; 1461 #if defined(__NetBSD__) 1462 bcopy(LLADDR(ifp->if_sadl), (void *)cb_ias->macaddr, 6); 1463 #else 1464 bcopy(sc->arpcom.ac_enaddr, (void *)cb_ias->macaddr, 1465 sizeof(sc->arpcom.ac_enaddr)); 1466 #endif /* __NetBSD__ */ 1467 1468 /* 1469 * Start the IAS (Individual Address Setup) command/DMA. 1470 */ 1471 fxp_scb_wait(sc); 1472 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1473 /* ...and wait for it to complete. */ 1474 while (!(cb_ias->cb_status & FXP_CB_STATUS_C)); 1475 1476 /* 1477 * Initialize transmit control block (TxCB) list. 1478 */ 1479 1480 txp = sc->cbl_base; 1481 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1482 for (i = 0; i < FXP_NTXCB; i++) { 1483 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1484 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1485 txp[i].link_addr = vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1486 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1487 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1488 } 1489 /* 1490 * Set the suspend flag on the first TxCB and start the control 1491 * unit. It will execute the NOP and then suspend. 1492 */ 1493 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1494 sc->cbl_first = sc->cbl_last = txp; 1495 sc->tx_queued = 1; 1496 1497 fxp_scb_wait(sc); 1498 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1499 1500 /* 1501 * Initialize receiver buffer area - RFA. 1502 */ 1503 fxp_scb_wait(sc); 1504 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1505 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1506 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1507 1508 /* 1509 * Set current media. 1510 */ 1511 fxp_set_media(sc, sc->sc_media.ifm_cur->ifm_media); 1512 1513 ifp->if_flags |= IFF_RUNNING; 1514 ifp->if_flags &= ~IFF_OACTIVE; 1515 splx(s); 1516 1517 /* 1518 * Start stats updater. 1519 */ 1520 sc->stat_ch = timeout(fxp_stats_update, sc, hz); 1521 } 1522 1523 static void 1524 fxp_set_media(sc, media) 1525 struct fxp_softc *sc; 1526 int media; 1527 { 1528 1529 switch (sc->phy_primary_device) { 1530 case FXP_PHY_DP83840: 1531 case FXP_PHY_DP83840A: 1532 fxp_mdi_write(sc, sc->phy_primary_addr, FXP_DP83840_PCR, 1533 fxp_mdi_read(sc, sc->phy_primary_addr, FXP_DP83840_PCR) | 1534 FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */ 1535 FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */ 1536 FXP_DP83840_PCR_BIT10); /* XXX I have no idea */ 1537 /* fall through */ 1538 case FXP_PHY_82553A: 1539 case FXP_PHY_82553C: /* untested */ 1540 case FXP_PHY_82555: 1541 case FXP_PHY_82555B: 1542 if (IFM_SUBTYPE(media) != IFM_AUTO) { 1543 int flags; 1544 1545 flags = (IFM_SUBTYPE(media) == IFM_100_TX) ? 1546 FXP_PHY_BMCR_SPEED_100M : 0; 1547 flags |= (media & IFM_FDX) ? 1548 FXP_PHY_BMCR_FULLDUPLEX : 0; 1549 fxp_mdi_write(sc, sc->phy_primary_addr, 1550 FXP_PHY_BMCR, 1551 (fxp_mdi_read(sc, sc->phy_primary_addr, 1552 FXP_PHY_BMCR) & 1553 ~(FXP_PHY_BMCR_AUTOEN | FXP_PHY_BMCR_SPEED_100M | 1554 FXP_PHY_BMCR_FULLDUPLEX)) | flags); 1555 } else { 1556 fxp_mdi_write(sc, sc->phy_primary_addr, 1557 FXP_PHY_BMCR, 1558 (fxp_mdi_read(sc, sc->phy_primary_addr, 1559 FXP_PHY_BMCR) | FXP_PHY_BMCR_AUTOEN)); 1560 } 1561 break; 1562 /* 1563 * The Seeq 80c24 doesn't have a PHY programming interface, so do 1564 * nothing. 1565 */ 1566 case FXP_PHY_80C24: 1567 break; 1568 default: 1569 printf(FXP_FORMAT 1570 ": warning: unsupported PHY, type = %d, addr = %d\n", 1571 FXP_ARGS(sc), sc->phy_primary_device, 1572 sc->phy_primary_addr); 1573 } 1574 } 1575 1576 /* 1577 * Change media according to request. 1578 */ 1579 int 1580 fxp_mediachange(ifp) 1581 struct ifnet *ifp; 1582 { 1583 struct fxp_softc *sc = ifp->if_softc; 1584 struct ifmedia *ifm = &sc->sc_media; 1585 1586 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1587 return (EINVAL); 1588 1589 fxp_set_media(sc, ifm->ifm_media); 1590 return (0); 1591 } 1592 1593 /* 1594 * Notify the world which media we're using. 1595 */ 1596 void 1597 fxp_mediastatus(ifp, ifmr) 1598 struct ifnet *ifp; 1599 struct ifmediareq *ifmr; 1600 { 1601 struct fxp_softc *sc = ifp->if_softc; 1602 int flags, stsflags; 1603 1604 switch (sc->phy_primary_device) { 1605 case FXP_PHY_82555: 1606 case FXP_PHY_82555B: 1607 case FXP_PHY_DP83840: 1608 case FXP_PHY_DP83840A: 1609 ifmr->ifm_status = IFM_AVALID; /* IFM_ACTIVE will be valid */ 1610 ifmr->ifm_active = IFM_ETHER; 1611 /* 1612 * the following is not an error. 1613 * You need to read this register twice to get current 1614 * status. This is correct documented behaviour, the 1615 * first read gets latched values. 1616 */ 1617 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS); 1618 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS); 1619 if (stsflags & FXP_PHY_STS_LINK_STS) 1620 ifmr->ifm_status |= IFM_ACTIVE; 1621 1622 /* 1623 * If we are in auto mode, then try report the result. 1624 */ 1625 flags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_BMCR); 1626 if (flags & FXP_PHY_BMCR_AUTOEN) { 1627 ifmr->ifm_active |= IFM_AUTO; /* XXX presently 0 */ 1628 if (stsflags & FXP_PHY_STS_AUTO_DONE) { 1629 /* 1630 * Intel and National parts report 1631 * differently on what they found. 1632 */ 1633 if ((sc->phy_primary_device == FXP_PHY_82555) 1634 || (sc->phy_primary_device == FXP_PHY_82555B)) { 1635 flags = fxp_mdi_read(sc, 1636 sc->phy_primary_addr, 1637 FXP_PHY_USC); 1638 1639 if (flags & FXP_PHY_USC_SPEED) 1640 ifmr->ifm_active |= IFM_100_TX; 1641 else 1642 ifmr->ifm_active |= IFM_10_T; 1643 1644 if (flags & FXP_PHY_USC_DUPLEX) 1645 ifmr->ifm_active |= IFM_FDX; 1646 } else { /* it's National. only know speed */ 1647 flags = fxp_mdi_read(sc, 1648 sc->phy_primary_addr, 1649 FXP_DP83840_PAR); 1650 1651 if (flags & FXP_DP83840_PAR_SPEED_10) 1652 ifmr->ifm_active |= IFM_10_T; 1653 else 1654 ifmr->ifm_active |= IFM_100_TX; 1655 } 1656 } 1657 } else { /* in manual mode.. just report what we were set to */ 1658 if (flags & FXP_PHY_BMCR_SPEED_100M) 1659 ifmr->ifm_active |= IFM_100_TX; 1660 else 1661 ifmr->ifm_active |= IFM_10_T; 1662 1663 if (flags & FXP_PHY_BMCR_FULLDUPLEX) 1664 ifmr->ifm_active |= IFM_FDX; 1665 } 1666 break; 1667 1668 case FXP_PHY_80C24: 1669 default: 1670 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; /* XXX IFM_AUTO ? */ 1671 } 1672 } 1673 1674 /* 1675 * Add a buffer to the end of the RFA buffer list. 1676 * Return 0 if successful, 1 for failure. A failure results in 1677 * adding the 'oldm' (if non-NULL) on to the end of the list - 1678 * tossing out its old contents and recycling it. 1679 * The RFA struct is stuck at the beginning of mbuf cluster and the 1680 * data pointer is fixed up to point just past it. 1681 */ 1682 static int 1683 fxp_add_rfabuf(sc, oldm) 1684 struct fxp_softc *sc; 1685 struct mbuf *oldm; 1686 { 1687 u_int32_t v; 1688 struct mbuf *m; 1689 struct fxp_rfa *rfa, *p_rfa; 1690 1691 MGETHDR(m, M_DONTWAIT, MT_DATA); 1692 if (m != NULL) { 1693 MCLGET(m, M_DONTWAIT); 1694 if ((m->m_flags & M_EXT) == 0) { 1695 m_freem(m); 1696 if (oldm == NULL) 1697 return 1; 1698 m = oldm; 1699 m->m_data = m->m_ext.ext_buf; 1700 } 1701 } else { 1702 if (oldm == NULL) 1703 return 1; 1704 m = oldm; 1705 m->m_data = m->m_ext.ext_buf; 1706 } 1707 1708 /* 1709 * Move the data pointer up so that the incoming data packet 1710 * will be 32-bit aligned. 1711 */ 1712 m->m_data += RFA_ALIGNMENT_FUDGE; 1713 1714 /* 1715 * Get a pointer to the base of the mbuf cluster and move 1716 * data start past it. 1717 */ 1718 rfa = mtod(m, struct fxp_rfa *); 1719 m->m_data += sizeof(struct fxp_rfa); 1720 rfa->size = MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE; 1721 1722 /* 1723 * Initialize the rest of the RFA. Note that since the RFA 1724 * is misaligned, we cannot store values directly. Instead, 1725 * we use an optimized, inline copy. 1726 */ 1727 rfa->rfa_status = 0; 1728 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1729 rfa->actual_size = 0; 1730 1731 v = -1; 1732 fxp_lwcopy(&v, &rfa->link_addr); 1733 fxp_lwcopy(&v, &rfa->rbd_addr); 1734 1735 /* 1736 * If there are other buffers already on the list, attach this 1737 * one to the end by fixing up the tail to point to this one. 1738 */ 1739 if (sc->rfa_headm != NULL) { 1740 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1741 RFA_ALIGNMENT_FUDGE); 1742 sc->rfa_tailm->m_next = m; 1743 v = vtophys(rfa); 1744 fxp_lwcopy(&v, &p_rfa->link_addr); 1745 p_rfa->rfa_control &= ~FXP_RFA_CONTROL_EL; 1746 } else { 1747 sc->rfa_headm = m; 1748 } 1749 sc->rfa_tailm = m; 1750 1751 return (m == oldm); 1752 } 1753 1754 static volatile int 1755 fxp_mdi_read(sc, phy, reg) 1756 struct fxp_softc *sc; 1757 int phy; 1758 int reg; 1759 { 1760 int count = 10000; 1761 int value; 1762 1763 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1764 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1765 1766 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1767 && count--) 1768 DELAY(10); 1769 1770 if (count <= 0) 1771 printf(FXP_FORMAT ": fxp_mdi_read: timed out\n", 1772 FXP_ARGS(sc)); 1773 1774 return (value & 0xffff); 1775 } 1776 1777 static void 1778 fxp_mdi_write(sc, phy, reg, value) 1779 struct fxp_softc *sc; 1780 int phy; 1781 int reg; 1782 int value; 1783 { 1784 int count = 10000; 1785 1786 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1787 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1788 (value & 0xffff)); 1789 1790 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1791 count--) 1792 DELAY(10); 1793 1794 if (count <= 0) 1795 printf(FXP_FORMAT ": fxp_mdi_write: timed out\n", 1796 FXP_ARGS(sc)); 1797 } 1798 1799 static int 1800 fxp_ioctl(ifp, command, data) 1801 struct ifnet *ifp; 1802 FXP_IOCTLCMD_TYPE command; 1803 caddr_t data; 1804 { 1805 struct fxp_softc *sc = ifp->if_softc; 1806 struct ifreq *ifr = (struct ifreq *)data; 1807 int s, error = 0; 1808 1809 s = splimp(); 1810 1811 switch (command) { 1812 1813 case SIOCSIFADDR: 1814 #if !defined(__NetBSD__) 1815 case SIOCGIFADDR: 1816 case SIOCSIFMTU: 1817 #endif 1818 error = ether_ioctl(ifp, command, data); 1819 break; 1820 1821 case SIOCSIFFLAGS: 1822 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1823 1824 /* 1825 * If interface is marked up and not running, then start it. 1826 * If it is marked down and running, stop it. 1827 * XXX If it's up then re-initialize it. This is so flags 1828 * such as IFF_PROMISC are handled. 1829 */ 1830 if (ifp->if_flags & IFF_UP) { 1831 fxp_init(sc); 1832 } else { 1833 if (ifp->if_flags & IFF_RUNNING) 1834 fxp_stop(sc); 1835 } 1836 break; 1837 1838 case SIOCADDMULTI: 1839 case SIOCDELMULTI: 1840 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1841 #if defined(__NetBSD__) 1842 error = (command == SIOCADDMULTI) ? 1843 ether_addmulti(ifr, &sc->sc_ethercom) : 1844 ether_delmulti(ifr, &sc->sc_ethercom); 1845 1846 if (error == ENETRESET) { 1847 /* 1848 * Multicast list has changed; set the hardware 1849 * filter accordingly. 1850 */ 1851 if (!sc->all_mcasts) 1852 fxp_mc_setup(sc); 1853 /* 1854 * fxp_mc_setup() can turn on all_mcasts if we run 1855 * out of space, so check it again rather than else {}. 1856 */ 1857 if (sc->all_mcasts) 1858 fxp_init(sc); 1859 error = 0; 1860 } 1861 #else /* __FreeBSD__ */ 1862 /* 1863 * Multicast list has changed; set the hardware filter 1864 * accordingly. 1865 */ 1866 if (!sc->all_mcasts) 1867 fxp_mc_setup(sc); 1868 /* 1869 * fxp_mc_setup() can turn on sc->all_mcasts, so check it 1870 * again rather than else {}. 1871 */ 1872 if (sc->all_mcasts) 1873 fxp_init(sc); 1874 error = 0; 1875 #endif /* __NetBSD__ */ 1876 break; 1877 1878 case SIOCSIFMEDIA: 1879 case SIOCGIFMEDIA: 1880 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 1881 break; 1882 1883 default: 1884 error = EINVAL; 1885 } 1886 (void) splx(s); 1887 return (error); 1888 } 1889 1890 /* 1891 * Program the multicast filter. 1892 * 1893 * We have an artificial restriction that the multicast setup command 1894 * must be the first command in the chain, so we take steps to ensure 1895 * this. By requiring this, it allows us to keep up the performance of 1896 * the pre-initialized command ring (esp. link pointers) by not actually 1897 * inserting the mcsetup command in the ring - i.e. its link pointer 1898 * points to the TxCB ring, but the mcsetup descriptor itself is not part 1899 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 1900 * lead into the regular TxCB ring when it completes. 1901 * 1902 * This function must be called at splimp. 1903 */ 1904 static void 1905 fxp_mc_setup(sc) 1906 struct fxp_softc *sc; 1907 { 1908 struct fxp_cb_mcs *mcsp = sc->mcsp; 1909 struct ifnet *ifp = &sc->sc_if; 1910 struct ifmultiaddr *ifma; 1911 int nmcasts; 1912 1913 /* 1914 * If there are queued commands, we must wait until they are all 1915 * completed. If we are already waiting, then add a NOP command 1916 * with interrupt option so that we're notified when all commands 1917 * have been completed - fxp_start() ensures that no additional 1918 * TX commands will be added when need_mcsetup is true. 1919 */ 1920 if (sc->tx_queued) { 1921 struct fxp_cb_tx *txp; 1922 1923 /* 1924 * need_mcsetup will be true if we are already waiting for the 1925 * NOP command to be completed (see below). In this case, bail. 1926 */ 1927 if (sc->need_mcsetup) 1928 return; 1929 sc->need_mcsetup = 1; 1930 1931 /* 1932 * Add a NOP command with interrupt so that we are notified when all 1933 * TX commands have been processed. 1934 */ 1935 txp = sc->cbl_last->next; 1936 txp->mb_head = NULL; 1937 txp->cb_status = 0; 1938 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1939 /* 1940 * Advance the end of list forward. 1941 */ 1942 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1943 sc->cbl_last = txp; 1944 sc->tx_queued++; 1945 /* 1946 * Issue a resume in case the CU has just suspended. 1947 */ 1948 fxp_scb_wait(sc); 1949 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 1950 /* 1951 * Set a 5 second timer just in case we don't hear from the 1952 * card again. 1953 */ 1954 ifp->if_timer = 5; 1955 1956 return; 1957 } 1958 sc->need_mcsetup = 0; 1959 1960 /* 1961 * Initialize multicast setup descriptor. 1962 */ 1963 mcsp->next = sc->cbl_base; 1964 mcsp->mb_head = NULL; 1965 mcsp->cb_status = 0; 1966 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1967 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 1968 1969 nmcasts = 0; 1970 if (!sc->all_mcasts) { 1971 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1972 ifma = ifma->ifma_link.le_next) { 1973 if (ifma->ifma_addr->sa_family != AF_LINK) 1974 continue; 1975 if (nmcasts >= MAXMCADDR) { 1976 sc->all_mcasts = 1; 1977 nmcasts = 0; 1978 break; 1979 } 1980 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1981 (void *) &sc->mcsp->mc_addr[nmcasts][0], 6); 1982 nmcasts++; 1983 } 1984 } 1985 mcsp->mc_cnt = nmcasts * 6; 1986 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 1987 sc->tx_queued = 1; 1988 1989 /* 1990 * Wait until command unit is not active. This should never 1991 * be the case when nothing is queued, but make sure anyway. 1992 */ 1993 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1994 FXP_SCB_CUS_ACTIVE) ; 1995 1996 /* 1997 * Start the multicast setup command. 1998 */ 1999 fxp_scb_wait(sc); 2000 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2001 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 2002 2003 ifp->if_timer = 2; 2004 return; 2005 }
Cache object: be0fef77ee50c9602943a986d172b7b7
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