The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_fxpreg.h

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    1 /*
    2  * Copyright (c) 1995, David Greenman
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice unmodified, this list of conditions, and the following
   10  *    disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  * $FreeBSD$
   28  */
   29 
   30 #define FXP_VENDORID_INTEL      0x8086
   31 #define FXP_DEVICEID_i82557     0x1229  /* 82557 - 82559 "classic" */
   32 #define FXP_DEVICEID_i82559     0x1030  /* New 82559 device id.. */
   33 
   34 #define FXP_PCI_MMBA    0x10
   35 #define FXP_PCI_IOBA    0x14
   36 
   37 /*
   38  * Control/status registers.
   39  */
   40 #define FXP_CSR_SCB_RUSCUS      0       /* scb_rus/scb_cus (1 byte) */
   41 #define FXP_CSR_SCB_STATACK     1       /* scb_statack (1 byte) */
   42 #define FXP_CSR_SCB_COMMAND     2       /* scb_command (1 byte) */
   43 #define FXP_CSR_SCB_INTRCNTL    3       /* scb_intrcntl (1 byte) */
   44 #define FXP_CSR_SCB_GENERAL     4       /* scb_general (4 bytes) */
   45 #define FXP_CSR_PORT            8       /* port (4 bytes) */
   46 #define FXP_CSR_FLASHCONTROL    12      /* flash control (2 bytes) */
   47 #define FXP_CSR_EEPROMCONTROL   14      /* eeprom control (2 bytes) */
   48 #define FXP_CSR_MDICONTROL      16      /* mdi control (4 bytes) */
   49 
   50 /*
   51  * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS:
   52  *
   53  *      volatile u_int8_t       :2,
   54  *                              scb_rus:4,
   55  *                              scb_cus:2;
   56  */
   57 
   58 #define FXP_PORT_SOFTWARE_RESET         0
   59 #define FXP_PORT_SELFTEST               1
   60 #define FXP_PORT_SELECTIVE_RESET        2
   61 #define FXP_PORT_DUMP                   3
   62 
   63 #define FXP_SCB_RUS_IDLE                0
   64 #define FXP_SCB_RUS_SUSPENDED           1
   65 #define FXP_SCB_RUS_NORESOURCES         2
   66 #define FXP_SCB_RUS_READY               4
   67 #define FXP_SCB_RUS_SUSP_NORBDS         9
   68 #define FXP_SCB_RUS_NORES_NORBDS        10
   69 #define FXP_SCB_RUS_READY_NORBDS        12
   70 
   71 #define FXP_SCB_CUS_IDLE                0
   72 #define FXP_SCB_CUS_SUSPENDED           1
   73 #define FXP_SCB_CUS_ACTIVE              2
   74 
   75 #define FXP_SCB_STATACK_SWI             0x04
   76 #define FXP_SCB_STATACK_MDI             0x08
   77 #define FXP_SCB_STATACK_RNR             0x10
   78 #define FXP_SCB_STATACK_CNA             0x20
   79 #define FXP_SCB_STATACK_FR              0x40
   80 #define FXP_SCB_STATACK_CXTNO           0x80
   81 
   82 #define FXP_SCB_COMMAND_CU_NOP          0x00
   83 #define FXP_SCB_COMMAND_CU_START        0x10
   84 #define FXP_SCB_COMMAND_CU_RESUME       0x20
   85 #define FXP_SCB_COMMAND_CU_DUMP_ADR     0x40
   86 #define FXP_SCB_COMMAND_CU_DUMP         0x50
   87 #define FXP_SCB_COMMAND_CU_BASE         0x60
   88 #define FXP_SCB_COMMAND_CU_DUMPRESET    0x70
   89 
   90 #define FXP_SCB_COMMAND_RU_NOP          0
   91 #define FXP_SCB_COMMAND_RU_START        1
   92 #define FXP_SCB_COMMAND_RU_RESUME       2
   93 #define FXP_SCB_COMMAND_RU_ABORT        4
   94 #define FXP_SCB_COMMAND_RU_LOADHDS      5
   95 #define FXP_SCB_COMMAND_RU_BASE         6
   96 #define FXP_SCB_COMMAND_RU_RBDRESUME    7
   97 
   98 /*
   99  * Command block definitions
  100  */
  101 struct fxp_cb_nop {
  102         void *fill[2];
  103         volatile u_int16_t cb_status;
  104         volatile u_int16_t cb_command;
  105         volatile u_int32_t link_addr;
  106 };
  107 struct fxp_cb_ias {
  108         void *fill[2];
  109         volatile u_int16_t cb_status;
  110         volatile u_int16_t cb_command;
  111         volatile u_int32_t link_addr;
  112         volatile u_int8_t macaddr[6];
  113 };
  114 /* I hate bit-fields :-( */
  115 struct fxp_cb_config {
  116         void *fill[2];
  117         volatile u_int16_t      cb_status;
  118         volatile u_int16_t      cb_command;
  119         volatile u_int32_t      link_addr;
  120         volatile u_int          byte_count:6,
  121                                 :2;
  122         volatile u_int          rx_fifo_limit:4,
  123                                 tx_fifo_limit:3,
  124                                 :1;
  125         volatile u_int8_t       adaptive_ifs;
  126         volatile u_int          :8;
  127         volatile u_int          rx_dma_bytecount:7,
  128                                 :1;
  129         volatile u_int          tx_dma_bytecount:7,
  130                                 dma_bce:1;
  131         volatile u_int          late_scb:1,
  132                                 :1,
  133                                 tno_int:1,
  134                                 ci_int:1,
  135                                 :3,
  136                                 save_bf:1;
  137         volatile u_int          disc_short_rx:1,
  138                                 underrun_retry:2,
  139                                 :5;
  140         volatile u_int          mediatype:1,
  141                                 :7;
  142         volatile u_int          :8;
  143         volatile u_int          :3,
  144                                 nsai:1,
  145                                 preamble_length:2,
  146                                 loopback:2;
  147         volatile u_int          linear_priority:3,
  148                                 :5;
  149         volatile u_int          linear_pri_mode:1,
  150                                 :3,
  151                                 interfrm_spacing:4;
  152         volatile u_int          :8;
  153         volatile u_int          :8;
  154         volatile u_int          promiscuous:1,
  155                                 bcast_disable:1,
  156                                 :5,
  157                                 crscdt:1;
  158         volatile u_int          :8;
  159         volatile u_int          :8;
  160         volatile u_int          stripping:1,
  161                                 padding:1,
  162                                 rcv_crc_xfer:1,
  163                                 :5;
  164         volatile u_int          :6,
  165                                 force_fdx:1,
  166                                 fdx_pin_en:1;
  167         volatile u_int          :6,
  168                                 multi_ia:1,
  169                                 :1;
  170         volatile u_int          :3,
  171                                 mc_all:1,
  172                                 :4;
  173 };
  174 
  175 #define MAXMCADDR 80
  176 struct fxp_cb_mcs {
  177         struct fxp_cb_tx *next;
  178         struct mbuf *mb_head;
  179         volatile u_int16_t cb_status;
  180         volatile u_int16_t cb_command;
  181         volatile u_int32_t link_addr;
  182         volatile u_int16_t mc_cnt;
  183         volatile u_int8_t mc_addr[MAXMCADDR][6];
  184 };
  185 
  186 /*
  187  * Number of DMA segments in a TxCB. Note that this is carefully
  188  * chosen to make the total struct size an even power of two. It's
  189  * critical that no TxCB be split across a page boundry since
  190  * no attempt is made to allocate physically contiguous memory.
  191  * 
  192  */
  193 #ifdef __alpha__ /* XXX - should be conditional on pointer size */
  194 #define FXP_NTXSEG      28
  195 #else
  196 #define FXP_NTXSEG      29
  197 #endif
  198 
  199 struct fxp_tbd {
  200         volatile u_int32_t tb_addr;
  201         volatile u_int32_t tb_size;
  202 };
  203 struct fxp_cb_tx {
  204         struct fxp_cb_tx *next;
  205         struct mbuf *mb_head;
  206         volatile u_int16_t cb_status;
  207         volatile u_int16_t cb_command;
  208         volatile u_int32_t link_addr;
  209         volatile u_int32_t tbd_array_addr;
  210         volatile u_int16_t byte_count;
  211         volatile u_int8_t tx_threshold;
  212         volatile u_int8_t tbd_number;
  213         /*
  214          * The following isn't actually part of the TxCB.
  215          */
  216         volatile struct fxp_tbd tbd[FXP_NTXSEG];
  217 };
  218 
  219 /*
  220  * Control Block (CB) definitions
  221  */
  222 
  223 /* status */
  224 #define FXP_CB_STATUS_OK        0x2000
  225 #define FXP_CB_STATUS_C         0x8000
  226 /* commands */
  227 #define FXP_CB_COMMAND_NOP      0x0
  228 #define FXP_CB_COMMAND_IAS      0x1
  229 #define FXP_CB_COMMAND_CONFIG   0x2
  230 #define FXP_CB_COMMAND_MCAS     0x3
  231 #define FXP_CB_COMMAND_XMIT     0x4
  232 #define FXP_CB_COMMAND_RESRV    0x5
  233 #define FXP_CB_COMMAND_DUMP     0x6
  234 #define FXP_CB_COMMAND_DIAG     0x7
  235 /* command flags */
  236 #define FXP_CB_COMMAND_SF       0x0008  /* simple/flexible mode */
  237 #define FXP_CB_COMMAND_I        0x2000  /* generate interrupt on completion */
  238 #define FXP_CB_COMMAND_S        0x4000  /* suspend on completion */
  239 #define FXP_CB_COMMAND_EL       0x8000  /* end of list */
  240 
  241 /*
  242  * RFA definitions
  243  */
  244 
  245 struct fxp_rfa {
  246         volatile u_int16_t rfa_status;
  247         volatile u_int16_t rfa_control;
  248         volatile u_int32_t link_addr;
  249         volatile u_int32_t rbd_addr;
  250         volatile u_int16_t actual_size;
  251         volatile u_int16_t size;
  252 };
  253 #define FXP_RFA_STATUS_RCOL     0x0001  /* receive collision */
  254 #define FXP_RFA_STATUS_IAMATCH  0x0002  /* 0 = matches station address */
  255 #define FXP_RFA_STATUS_S4       0x0010  /* receive error from PHY */
  256 #define FXP_RFA_STATUS_TL       0x0020  /* type/length */
  257 #define FXP_RFA_STATUS_FTS      0x0080  /* frame too short */
  258 #define FXP_RFA_STATUS_OVERRUN  0x0100  /* DMA overrun */
  259 #define FXP_RFA_STATUS_RNR      0x0200  /* no resources */
  260 #define FXP_RFA_STATUS_ALIGN    0x0400  /* alignment error */
  261 #define FXP_RFA_STATUS_CRC      0x0800  /* CRC error */
  262 #define FXP_RFA_STATUS_OK       0x2000  /* packet received okay */
  263 #define FXP_RFA_STATUS_C        0x8000  /* packet reception complete */
  264 #define FXP_RFA_CONTROL_SF      0x08    /* simple/flexible memory mode */
  265 #define FXP_RFA_CONTROL_H       0x10    /* header RFD */
  266 #define FXP_RFA_CONTROL_S       0x4000  /* suspend after reception */
  267 #define FXP_RFA_CONTROL_EL      0x8000  /* end of list */
  268 
  269 /*
  270  * Statistics dump area definitions
  271  */
  272 struct fxp_stats {
  273         volatile u_int32_t tx_good;
  274         volatile u_int32_t tx_maxcols;
  275         volatile u_int32_t tx_latecols;
  276         volatile u_int32_t tx_underruns;
  277         volatile u_int32_t tx_lostcrs;
  278         volatile u_int32_t tx_deffered;
  279         volatile u_int32_t tx_single_collisions;
  280         volatile u_int32_t tx_multiple_collisions;
  281         volatile u_int32_t tx_total_collisions;
  282         volatile u_int32_t rx_good;
  283         volatile u_int32_t rx_crc_errors;
  284         volatile u_int32_t rx_alignment_errors;
  285         volatile u_int32_t rx_rnr_errors;
  286         volatile u_int32_t rx_overrun_errors;
  287         volatile u_int32_t rx_cdt_errors;
  288         volatile u_int32_t rx_shortframes;
  289         volatile u_int32_t completion_status;
  290 };
  291 #define FXP_STATS_DUMP_COMPLETE 0xa005
  292 #define FXP_STATS_DR_COMPLETE   0xa007
  293         
  294 /*
  295  * Serial EEPROM control register bits
  296  */
  297 /* shift clock */
  298 #define FXP_EEPROM_EESK         0x01
  299 /* chip select */
  300 #define FXP_EEPROM_EECS         0x02
  301 /* data in */
  302 #define FXP_EEPROM_EEDI         0x04
  303 /* data out */
  304 #define FXP_EEPROM_EEDO         0x08
  305 
  306 /*
  307  * Serial EEPROM opcodes, including start bit
  308  */
  309 #define FXP_EEPROM_OPC_ERASE    0x4
  310 #define FXP_EEPROM_OPC_WRITE    0x5
  311 #define FXP_EEPROM_OPC_READ     0x6
  312 
  313 /*
  314  * Management Data Interface opcodes
  315  */
  316 #define FXP_MDI_WRITE           0x1
  317 #define FXP_MDI_READ            0x2
  318 
  319 /*
  320  * PHY device types
  321  */
  322 #define FXP_PHY_NONE            0
  323 #define FXP_PHY_82553A          1
  324 #define FXP_PHY_82553C          2
  325 #define FXP_PHY_82503           3
  326 #define FXP_PHY_DP83840         4
  327 #define FXP_PHY_80C240          5
  328 #define FXP_PHY_80C24           6
  329 #define FXP_PHY_82555           7
  330 #define FXP_PHY_DP83840A        10
  331 #define FXP_PHY_82555B          11
  332 
  333 /*
  334  * PHY BMCR Basic Mode Control Register
  335  * Should probably be in i82555.h or dp83840.h (Intel/National names).
  336  * (Called "Management Data Interface Control Reg" in some Intel data books).
  337  * (*) indicates bit ignored in auto negotiation mode.
  338  */
  339 #define FXP_PHY_BMCR                    0x0 
  340 #define FXP_PHY_BMCR_COLTEST            0x0080 /* not on Intel parts */
  341 #define FXP_PHY_BMCR_FULLDUPLEX         0x0100 /* 1 = Fullduplex (*) */
  342 #define FXP_PHY_BMCR_RESTART_NEG        0x0200 /* ==> 1 to restart autoneg */
  343 #define FXP_PHY_BMCR_ISOLATE            0x0400 /* not on Intel parts */
  344 #define FXP_PHY_BMCR_POWERDOWN          0x0800 /* 1 = low power mode */
  345 #define FXP_PHY_BMCR_AUTOEN             0x1000 /* 1 = for auto mode */
  346 #define FXP_PHY_BMCR_SPEED_100M         0x2000 /* 1 = for 100Mb/sec (*) */
  347 #define FXP_PHY_BMCR_LOOPBACK           0x4000 /* 1 = loopback at the PHY */
  348 #define FXP_PHY_BMCR_RESET              0x8000 /* ==> 1 sets to defaults */
  349 
  350 /*
  351  * Basic Mode Status Register (National name)
  352  * Management Data Interface Status reg. (Intel name)
  353  * in both Intel and National parts.
  354  */
  355 #define FXP_PHY_STS                     0x1
  356 #define FXP_PHY_STS_EXND                0x0001 /* Extended regs enabled */
  357 #define FXP_PHY_STS_JABR                0x0002 /* Jabber detected */
  358 #define FXP_PHY_STS_LINK_STS            0x0004 /* Link valid */
  359 #define FXP_PHY_STS_CAN_AUTO            0x0008 /* Auto detection available */
  360 #define FXP_PHY_STS_REMT_FAULT          0x0010 /* remote fault detected */
  361 #define FXP_PHY_STS_AUTO_DONE           0x0020 /* auto negotiation completed */
  362 #define FXP_PHY_STS_MGMT_PREAMBLE       0x0040 /* real complicated */
  363 #define FXP_PHY_STS_10HDX_OK            0x0800 /* can do 10Mb HDX */
  364 #define FXP_PHY_STS_10FDX_OK            0x1000 /* can do 10Mb FDX */
  365 #define FXP_PHY_STS_100HDX_OK           0x2000 /* can do 100Mb HDX */
  366 #define FXP_PHY_STS_100FDX_OK           0x4000 /* can do 100Mb FDX */
  367 #define FXP_PHY_STS_100T4_OK            0x8000 /* can do 100bT4 -not Intel */
  368 
  369 /*
  370  * More Phy regs
  371  */
  372 #define FXP_PHY_ID1                     0x2
  373 #define FXP_PHY_ID2                     0x3
  374 
  375 /*
  376  * MDI Auto negotiation advertisement register.
  377  * What we advertise we can do..
  378  * The same bits are used to indicate the response too.
  379  */
  380 #define FXP_PHY_ADVRT                   0x4
  381 #define FXP_PHY_RMT_ADVRT               0x5 /* what the other end said */
  382 #define FXP_PHY_ADVRT_SELECT            0x001F /* real complicated */
  383 #define FXP_PHY_ADVRT_TECH_AVAIL        0x1FE0 /* can do 10Mb HDX */
  384 #define FXP_PHY_ADVRT_RMT_FAULT         0x2000 /* can do 10Mb FDX */
  385 #define FXP_PHY_ADVRT_ACK               0x4000 /* Acked */
  386 #define FXP_PHY_ADVRT_NXT_PAGE          0x8000 /* can do 100Mb FDX */
  387 
  388 /*
  389  * Phy Unit Status and Control Register (another one)
  390  * This is not in the National part!
  391  */
  392 #define FXP_PHY_USC                     0x10
  393 #define FXP_PHY_USC_DUPLEX              0x0001 /* in FDX mode */
  394 #define FXP_PHY_USC_SPEED               0x0002 /* 1 = in 100Mb mode */
  395 #define FXP_PHY_USC_POLARITY            0x0100 /* 1 = reverse polarity */
  396 #define FXP_PHY_USC_10_PWRDOWN          0x0200 /* 10Mb PHY powered down */
  397 #define FXP_PHY_USC_100_PWRDOWN         0x0400 /* 100Mb PHY powered down */
  398 #define FXP_PHY_USC_INSYNC              0x0800 /* 100Mb PHY is in sync */
  399 #define FXP_PHY_USC_TX_FLOWCNTRL        0x1000 /* TX FC mode in use */
  400 #define FXP_PHY_USC_PHY_FLOWCNTRL       0x8000 /* PHY FC mode in use */
  401 
  402 
  403 /*
  404  * DP83830 PHY, PCS Configuration Register
  405  * NOT compatible with Intel parts,
  406  * (where it is the 100BTX premature eof counter).
  407  */
  408 #define FXP_DP83840_PCR                 0x17
  409 #define FXP_DP83840_PCR_LED4_MODE       0x0002  /* 1 = LED4 always = FDX */
  410 #define FXP_DP83840_PCR_F_CONNECT       0x0020  /* 1 = link disconnect bypass */
  411 #define FXP_DP83840_PCR_BIT8            0x0100
  412 #define FXP_DP83840_PCR_BIT10           0x0400
  413 
  414 /*
  415  * DP83830 PHY, Address/status Register
  416  * NOT compatible with Intel parts,
  417  * (where it is the 10BT jabber detect counter).
  418  */
  419 #define FXP_DP83840_PAR                 0x19
  420 #define FXP_DP83840_PAR_PHYADDR         0x1F
  421 #define FXP_DP83840_PAR_CON_STATUS      0x20    
  422 #define FXP_DP83840_PAR_SPEED_10        0x40    /* 1 == running at 10 Mb/Sec */
  423 

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