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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_mn.c
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1 /* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $ 10 * 11 * Driver for Siemens reference design card "Easy321-R1". 12 * 13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 14 * controller. 15 * 16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't 17 * check it coming in. 18 * 19 * The FALC54 and MUNICH32X have far too many registers and weird modes for 20 * comfort, so I have not bothered typing it all into a "fooreg.h" file, 21 * you will (badly!) need the documentation anyway if you want to mess with 22 * this gadget. 23 * 24 * $FreeBSD: releng/5.0/sys/pci/if_mn.c 106626 2002-11-08 14:57:18Z jhb $ 25 */ 26 27 /* 28 * Stuff to describe the MUNIC32X and FALC54 chips. 29 */ 30 31 #define M32_CHAN 32 /* We have 32 channels */ 32 #define M32_TS 32 /* We have 32 timeslots */ 33 34 #define NG_MN_NODE_TYPE "mn" 35 36 #include <sys/param.h> 37 #include <sys/kernel.h> 38 #include <sys/sysctl.h> 39 #include <sys/bus.h> 40 #include <sys/mbuf.h> 41 #include <sys/systm.h> 42 #include <sys/malloc.h> 43 44 #include <pci/pcireg.h> 45 #include <pci/pcivar.h> 46 #include "pci_if.h" 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 51 #include <sys/rman.h> 52 53 #include <vm/vm.h> 54 #include <vm/pmap.h> 55 56 #include <netgraph/ng_message.h> 57 #include <netgraph/netgraph.h> 58 59 60 static int mn_maxlatency = 1000; 61 SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW, 62 &mn_maxlatency, 0, 63 "The number of milliseconds a packet is allowed to spend in the output queue. " 64 "If the output queue is longer than this number of milliseconds when the packet " 65 "arrives for output, the packet will be dropped." 66 ); 67 68 #ifndef NMN 69 /* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 70 #define NMN 4 71 #endif 72 73 /* From: PEB 20321 data sheet, p187, table 22 */ 74 struct m32xreg { 75 u_int32_t conf, cmd, stat, imask; 76 u_int32_t fill10, piqba, piql, fill1c; 77 u_int32_t mode1, mode2, ccba, txpoll; 78 u_int32_t tiqba, tiql, riqba, riql; 79 u_int32_t lconf, lccba, fill48, ltran; 80 u_int32_t ltiqba, ltiql, lriqba, lriql; 81 u_int32_t lreg0, lreg1, lreg2, lreg3; 82 u_int32_t lreg4, lreg5, lre6, lstat; 83 u_int32_t gpdir, gpdata, gpod, fill8c; 84 u_int32_t ssccon, sscbr, ssctb, sscrb; 85 u_int32_t ssccse, sscim, fillab, fillac; 86 u_int32_t iomcon1, iomcon2, iomstat, fillbc; 87 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 88 u_int32_t iomtmo, iomrmo, filld8, filldc; 89 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 90 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 91 }; 92 93 /* From: PEB 2254 data sheet, p80, table 10 */ 94 struct f54wreg { 95 u_int16_t xfifo; 96 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 97 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 98 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 99 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 100 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 101 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 102 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 103 u_int8_t lim2, fill39[7]; 104 u_int8_t fill40[8]; 105 u_int8_t fill48[8]; 106 u_int8_t fill50[8]; 107 u_int8_t fill58[8]; 108 u_int8_t dec, fill61, test2, fill63[5]; 109 u_int8_t fill68[8]; 110 u_int8_t xs[16]; 111 }; 112 113 /* From: PEB 2254 data sheet, p117, table 10 */ 114 struct f54rreg { 115 u_int16_t rfifo; 116 u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 117 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 118 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 119 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 120 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 121 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 122 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 123 u_int8_t lim2, fill39[7]; 124 u_int8_t fill40[8]; 125 u_int8_t fill48[4], frs0, frs1, rsw, rsp; 126 u_int16_t fec, cvc, cec1, ebc; 127 u_int16_t cec2, cec3; 128 u_int8_t rsa4, rsa5, rsa6, rsa7; 129 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 130 u_int16_t rbc; 131 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 132 u_int8_t rs[16]; 133 }; 134 135 /* Transmit & receive descriptors */ 136 struct trxd { 137 u_int32_t flags; 138 vm_offset_t next; 139 vm_offset_t data; 140 u_int32_t status; /* only used for receive */ 141 struct mbuf *m; /* software use only */ 142 struct trxd *vnext; /* software use only */ 143 }; 144 145 /* Channel specification */ 146 struct cspec { 147 u_int32_t flags; 148 vm_offset_t rdesc; 149 vm_offset_t tdesc; 150 u_int32_t itbs; 151 }; 152 153 struct m32_mem { 154 vm_offset_t csa; 155 u_int32_t ccb; 156 u_int32_t reserve1[2]; 157 u_int32_t ts[M32_TS]; 158 struct cspec cs[M32_CHAN]; 159 vm_offset_t crxd[M32_CHAN]; 160 vm_offset_t ctxd[M32_CHAN]; 161 }; 162 163 struct mn_softc; 164 struct sockaddr; 165 struct rtentry; 166 167 static int mn_probe (device_t self); 168 static int mn_attach (device_t self); 169 static void mn_create_channel(struct mn_softc *sc, int chan); 170 static int mn_reset(struct mn_softc *sc); 171 static struct trxd * mn_alloc_desc(void); 172 static void mn_free_desc(struct trxd *dp); 173 static void mn_intr(void *xsc); 174 static u_int32_t mn_parse_ts(const char *s, int *nbit); 175 #ifdef notyet 176 static void m32_dump(struct mn_softc *sc); 177 static void f54_dump(struct mn_softc *sc); 178 static void mn_fmt_ts(char *p, u_int32_t ts); 179 #endif /* notyet */ 180 static void f54_init(struct mn_softc *sc); 181 182 static ng_constructor_t ngmn_constructor; 183 static ng_rcvmsg_t ngmn_rcvmsg; 184 static ng_shutdown_t ngmn_shutdown; 185 static ng_newhook_t ngmn_newhook; 186 static ng_connect_t ngmn_connect; 187 static ng_rcvdata_t ngmn_rcvdata; 188 static ng_disconnect_t ngmn_disconnect; 189 190 static struct ng_type mntypestruct = { 191 NG_ABI_VERSION, 192 NG_MN_NODE_TYPE, 193 NULL, 194 ngmn_constructor, 195 ngmn_rcvmsg, 196 ngmn_shutdown, 197 ngmn_newhook, 198 NULL, 199 ngmn_connect, 200 ngmn_rcvdata, 201 ngmn_disconnect, 202 NULL 203 }; 204 205 static MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 206 207 #define NIQB 64 208 209 struct schan { 210 enum {DOWN, UP} state; 211 struct mn_softc *sc; 212 int chan; 213 u_int32_t ts; 214 char name[8]; 215 struct trxd *r1, *rl; 216 struct trxd *x1, *xl; 217 hook_p hook; 218 219 time_t last_recv; 220 time_t last_rxerr; 221 time_t last_xmit; 222 223 u_long rx_error; 224 225 u_long short_error; 226 u_long crc_error; 227 u_long dribble_error; 228 u_long long_error; 229 u_long abort_error; 230 u_long overflow_error; 231 232 int last_error; 233 int prev_error; 234 235 u_long tx_pending; 236 u_long tx_limit; 237 }; 238 239 enum framing {WHOKNOWS, E1, E1U, T1, T1U}; 240 241 struct mn_softc { 242 int unit; 243 device_t dev; 244 struct resource *irq; 245 void *intrhand; 246 enum framing framing; 247 int nhooks; 248 void *m0v, *m1v; 249 vm_offset_t m0p, m1p; 250 struct m32xreg *m32x; 251 struct f54wreg *f54w; 252 struct f54rreg *f54r; 253 struct m32_mem m32_mem; 254 u_int32_t tiqb[NIQB]; 255 u_int32_t riqb[NIQB]; 256 u_int32_t piqb[NIQB]; 257 u_int32_t ltiqb[NIQB]; 258 u_int32_t lriqb[NIQB]; 259 char name[8]; 260 u_int32_t falc_irq, falc_state, framer_state; 261 struct schan *ch[M32_CHAN]; 262 char nodename[NG_NODELEN + 1]; 263 node_p node; 264 265 u_long cnt_fec; 266 u_long cnt_cvc; 267 u_long cnt_cec1; 268 u_long cnt_ebc; 269 u_long cnt_cec2; 270 u_long cnt_cec3; 271 u_long cnt_rbc; 272 }; 273 274 static int 275 ngmn_constructor(node_p node) 276 { 277 278 return (EINVAL); 279 } 280 281 static int 282 ngmn_shutdown(node_p nodep) 283 { 284 285 return (EINVAL); 286 } 287 288 static void 289 ngmn_config(node_p node, char *set, char *ret) 290 { 291 struct mn_softc *sc; 292 enum framing wframing; 293 294 sc = NG_NODE_PRIVATE(node); 295 296 if (set != NULL) { 297 if (!strncmp(set, "line ", 5)) { 298 wframing = sc->framing; 299 if (!strcmp(set, "line e1")) { 300 wframing = E1; 301 } else if (!strcmp(set, "line e1u")) { 302 wframing = E1U; 303 } else { 304 strcat(ret, "ENOGROK\n"); 305 return; 306 } 307 if (wframing == sc->framing) 308 return; 309 if (sc->nhooks > 0) { 310 sprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks); 311 return; 312 } 313 sc->framing = wframing; 314 #if 1 315 f54_init(sc); 316 #else 317 mn_reset(sc); 318 #endif 319 } else { 320 printf("%s CONFIG SET [%s]\n", sc->nodename, set); 321 strcat(ret, "ENOGROK\n"); 322 return; 323 } 324 } 325 326 } 327 328 static int 329 ngmn_rcvmsg(node_p node, item_p item, hook_p lasthook) 330 { 331 struct mn_softc *sc; 332 struct ng_mesg *resp = NULL; 333 struct schan *sch; 334 char *s, *r; 335 int pos, i; 336 struct ng_mesg *msg; 337 338 NGI_GET_MSG(item, msg); 339 sc = NG_NODE_PRIVATE(node); 340 341 if (msg->header.typecookie != NGM_GENERIC_COOKIE) { 342 NG_FREE_ITEM(item); 343 NG_FREE_MSG(msg); 344 return (EINVAL); 345 } 346 347 if (msg->header.cmd != NGM_TEXT_CONFIG && 348 msg->header.cmd != NGM_TEXT_STATUS) { 349 NG_FREE_ITEM(item); 350 NG_FREE_MSG(msg); 351 return (EINVAL); 352 } 353 354 NG_MKRESPONSE(resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 355 M_NOWAIT); 356 if (resp == NULL) { 357 NG_FREE_ITEM(item); 358 NG_FREE_MSG(msg); 359 return (ENOMEM); 360 } 361 362 if (msg->header.arglen) 363 s = (char *)msg->data; 364 else 365 s = NULL; 366 r = (char *)resp->data; 367 *r = '\0'; 368 369 if (msg->header.cmd == NGM_TEXT_CONFIG) { 370 ngmn_config(node, s, r); 371 resp->header.arglen = strlen(r) + 1; 372 NG_RESPOND_MSG(i, node, item, resp); 373 FREE(msg, M_NETGRAPH); 374 return (0); 375 } 376 pos = 0; 377 pos += sprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\2" 378 "\40LOS\37AIS\36LFA\35RRA" 379 "\34AUXP\33NMF\32LMFA\31frs0.0" 380 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 381 "\24TS16LFA\23frs1.2\22XLS\21XLO" 382 "\20RS1\17rsw.6\16RRA\15RY0" 383 "\14RY1\13RY2\12RY3\11RY4" 384 "\10SI1\7SI2\6rsp.5\5rsp.4" 385 "\4rsp.3\3RSIF\2RS13\1RS15"); 386 pos += sprintf(pos + r," Framing errors: %lu", sc->cnt_fec); 387 pos += sprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc); 388 389 pos += sprintf(pos + r," Falc State %b;\n", sc->falc_state, "\2" 390 "\40LOS\37AIS\36LFA\35RRA" 391 "\34AUXP\33NMF\32LMFA\31frs0.0" 392 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 393 "\24TS16LFA\23frs1.2\22XLS\21XLO" 394 "\20RS1\17rsw.6\16RRA\15RY0" 395 "\14RY1\13RY2\12RY3\11RY4" 396 "\10SI1\7SI2\6rsp.5\5rsp.4" 397 "\4rsp.3\3RSIF\2RS13\1RS15"); 398 pos += sprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\2" 399 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 400 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 401 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 402 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 403 for (i = 0; i < M32_CHAN; i++) { 404 if (!sc->ch[i]) 405 continue; 406 sch = sc->ch[i]; 407 408 pos += sprintf(r + pos, " Chan %d <%s> ", 409 i, NG_HOOK_NAME(sch->hook)); 410 411 pos += sprintf(r + pos, " Last Rx: "); 412 if (sch->last_recv) 413 pos += sprintf(r + pos, "%lu s", 414 (unsigned long)(time_second - sch->last_recv)); 415 else 416 pos += sprintf(r + pos, "never"); 417 418 pos += sprintf(r + pos, ", last RxErr: "); 419 if (sch->last_rxerr) 420 pos += sprintf(r + pos, "%lu s", 421 (unsigned long)(time_second - sch->last_rxerr)); 422 else 423 pos += sprintf(r + pos, "never"); 424 425 pos += sprintf(r + pos, ", last Tx: "); 426 if (sch->last_xmit) 427 pos += sprintf(r + pos, "%lu s\n", 428 (unsigned long)(time_second - sch->last_xmit)); 429 else 430 pos += sprintf(r + pos, "never\n"); 431 432 pos += sprintf(r + pos, " RX error(s) %lu", sch->rx_error); 433 pos += sprintf(r + pos, " Short: %lu", sch->short_error); 434 pos += sprintf(r + pos, " CRC: %lu", sch->crc_error); 435 pos += sprintf(r + pos, " Mod8: %lu", sch->dribble_error); 436 pos += sprintf(r + pos, " Long: %lu", sch->long_error); 437 pos += sprintf(r + pos, " Abort: %lu", sch->abort_error); 438 pos += sprintf(r + pos, " Overflow: %lu\n", sch->overflow_error); 439 440 pos += sprintf(r + pos, " Last error: %b Prev error: %b\n", 441 sch->last_error, "\2\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 442 sch->prev_error, "\2\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 443 pos += sprintf(r + pos, " Xmit bytes pending %ld\n", 444 sch->tx_pending); 445 } 446 resp->header.arglen = pos + 1; 447 448 /* Take care of synchronous response, if any */ 449 NG_RESPOND_MSG(i, node, item, resp); 450 NG_FREE_MSG(msg); 451 return (0); 452 } 453 454 static int 455 ngmn_newhook(node_p node, hook_p hook, const char *name) 456 { 457 u_int32_t ts, chan; 458 struct mn_softc *sc; 459 int nbit; 460 461 sc = NG_NODE_PRIVATE(node); 462 463 if (name[0] != 't' || name[1] != 's') 464 return (EINVAL); 465 466 ts = mn_parse_ts(name + 2, &nbit); 467 printf("%d bits %x\n", nbit, ts); 468 if (sc->framing == E1 && (ts & 1)) 469 return (EINVAL); 470 if (sc->framing == E1U && nbit != 32) 471 return (EINVAL); 472 if (ts == 0) 473 return (EINVAL); 474 if (sc->framing == E1) 475 chan = ffs(ts) - 1; 476 else 477 chan = 1; 478 if (!sc->ch[chan]) 479 mn_create_channel(sc, chan); 480 else if (sc->ch[chan]->state == UP) 481 return (EBUSY); 482 sc->ch[chan]->ts = ts; 483 sc->ch[chan]->hook = hook; 484 sc->ch[chan]->tx_limit = nbit * 8; 485 NG_HOOK_SET_PRIVATE(hook, sc->ch[chan]); 486 sc->nhooks++; 487 return(0); 488 } 489 490 491 static struct trxd *mn_desc_free; 492 493 static struct trxd * 494 mn_alloc_desc(void) 495 { 496 struct trxd *dp; 497 498 dp = mn_desc_free; 499 if (dp) 500 mn_desc_free = dp->vnext; 501 else 502 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT); 503 return (dp); 504 } 505 506 static void 507 mn_free_desc(struct trxd *dp) 508 { 509 dp->vnext = mn_desc_free; 510 mn_desc_free = dp; 511 } 512 513 static u_int32_t 514 mn_parse_ts(const char *s, int *nbit) 515 { 516 unsigned r; 517 int i, j; 518 char *p; 519 520 r = 0; 521 j = -1; 522 *nbit = 0; 523 while(*s) { 524 i = strtol(s, &p, 0); 525 if (i < 0 || i > 31) 526 return (0); 527 while (j != -1 && j < i) { 528 r |= 1 << j++; 529 (*nbit)++; 530 } 531 j = -1; 532 r |= 1 << i; 533 (*nbit)++; 534 if (*p == ',') { 535 s = p + 1; 536 continue; 537 } else if (*p == '-') { 538 j = i + 1; 539 s = p + 1; 540 continue; 541 } else if (!*p) { 542 break; 543 } else { 544 return (0); 545 } 546 } 547 return (r); 548 } 549 550 #ifdef notyet 551 static void 552 mn_fmt_ts(char *p, u_int32_t ts) 553 { 554 char *s; 555 int j; 556 557 s = ""; 558 ts &= 0xffffffff; 559 for (j = 0; j < 32; j++) { 560 if (!(ts & (1 << j))) 561 continue; 562 sprintf(p, "%s%d", s, j); 563 p += strlen(p); 564 s = ","; 565 if (!(ts & (1 << (j+1)))) 566 continue; 567 for (; j < 32; j++) 568 if (!(ts & (1 << (j+1)))) 569 break; 570 sprintf(p, "-%d", j); 571 p += strlen(p); 572 s = ","; 573 } 574 } 575 #endif /* notyet */ 576 577 /* 578 * OUTPUT 579 */ 580 581 static int 582 ngmn_rcvdata(hook_p hook, item_p item) 583 { 584 struct mbuf *m2; 585 struct trxd *dp, *dp2; 586 struct schan *sch; 587 struct mn_softc *sc; 588 int chan, pitch, len; 589 struct mbuf *m; 590 591 sch = NG_HOOK_PRIVATE(hook); 592 sc = sch->sc; 593 chan = sch->chan; 594 595 if (sch->state != UP) { 596 NG_FREE_ITEM(item); 597 return (0); 598 } 599 NGI_GET_M(item, m); 600 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) { 601 NG_FREE_M(m); 602 NG_FREE_ITEM(item); 603 return (0); 604 } 605 NG_FREE_ITEM(item); 606 pitch = 0; 607 m2 = m; 608 dp2 = sc->ch[chan]->xl; 609 len = m->m_pkthdr.len; 610 while (len) { 611 dp = mn_alloc_desc(); 612 if (!dp) { 613 pitch++; 614 m_freem(m); 615 sc->ch[chan]->xl = dp2; 616 dp = dp2->vnext; 617 while (dp) { 618 dp2 = dp->vnext; 619 mn_free_desc(dp); 620 dp = dp2; 621 } 622 sc->ch[chan]->xl->vnext = 0; 623 break; 624 } 625 dp->data = vtophys(m2->m_data); 626 dp->flags = m2->m_len << 16; 627 dp->flags += 1; 628 len -= m2->m_len; 629 dp->next = vtophys(dp); 630 dp->vnext = 0; 631 sc->ch[chan]->xl->next = vtophys(dp); 632 sc->ch[chan]->xl->vnext = dp; 633 sc->ch[chan]->xl = dp; 634 if (!len) { 635 dp->m = m; 636 dp->flags |= 0xc0000000; 637 dp2->flags &= ~0x40000000; 638 } else { 639 dp->m = 0; 640 m2 = m2->m_next; 641 } 642 } 643 if (pitch) 644 printf("%s%d: Short on mem, pitched %d packets\n", 645 sc->name, chan, pitch); 646 else { 647 #if 0 648 printf("%d = %d + %d (%p)\n", 649 sch->tx_pending + m->m_pkthdr.len, 650 sch->tx_pending , m->m_pkthdr.len, m); 651 #endif 652 sch->tx_pending += m->m_pkthdr.len; 653 sc->m32x->txpoll &= ~(1 << chan); 654 } 655 return (0); 656 } 657 658 /* 659 * OPEN 660 */ 661 static int 662 ngmn_connect(hook_p hook) 663 { 664 int i, nts, chan; 665 struct trxd *dp, *dp2; 666 struct mbuf *m; 667 struct mn_softc *sc; 668 struct schan *sch; 669 u_int32_t u; 670 671 sch = NG_HOOK_PRIVATE(hook); 672 chan = sch->chan; 673 sc = sch->sc; 674 675 if (sch->state == UP) 676 return (0); 677 sch->state = UP; 678 679 /* Count and configure the timeslots for this channel */ 680 for (nts = i = 0; i < 32; i++) 681 if (sch->ts & (1 << i)) { 682 sc->m32_mem.ts[i] = 0x00ff00ff | 683 (chan << 24) | (chan << 8); 684 nts++; 685 } 686 687 /* Init the receiver & xmitter to HDLC */ 688 sc->m32_mem.cs[chan].flags = 0x80e90006; 689 /* Allocate two buffers per timeslot */ 690 if (nts == 32) 691 sc->m32_mem.cs[chan].itbs = 63; 692 else 693 sc->m32_mem.cs[chan].itbs = nts * 2; 694 695 /* Setup a transmit chain with one descriptor */ 696 /* XXX: we actually send a 1 byte packet */ 697 dp = mn_alloc_desc(); 698 MGETHDR(m, M_TRYWAIT, MT_DATA); 699 if (m == NULL) 700 return ENOBUFS; 701 m->m_pkthdr.len = 0; 702 dp->m = m; 703 dp->flags = 0xc0000000 + (1 << 16); 704 dp->next = vtophys(dp); 705 dp->vnext = 0; 706 dp->data = vtophys(sc->name); 707 sc->m32_mem.cs[chan].tdesc = vtophys(dp); 708 sc->ch[chan]->x1 = dp; 709 sc->ch[chan]->xl = dp; 710 711 /* Setup a receive chain with 5 + NTS descriptors */ 712 713 dp = mn_alloc_desc(); 714 m = NULL; 715 MGETHDR(m, M_TRYWAIT, MT_DATA); 716 if (m == NULL) { 717 mn_free_desc(dp); 718 return (ENOBUFS); 719 } 720 MCLGET(m, M_TRYWAIT); 721 if ((m->m_flags & M_EXT) == 0) { 722 mn_free_desc(dp); 723 m_freem(m); 724 return (ENOBUFS); 725 } 726 dp->m = m; 727 dp->data = vtophys(m->m_data); 728 dp->flags = 0x40000000; 729 dp->flags += 1600 << 16; 730 dp->next = vtophys(dp); 731 dp->vnext = 0; 732 sc->ch[chan]->rl = dp; 733 734 for (i = 0; i < (nts + 10); i++) { 735 dp2 = dp; 736 dp = mn_alloc_desc(); 737 m = NULL; 738 MGETHDR(m, M_TRYWAIT, MT_DATA); 739 if (m == NULL) { 740 mn_free_desc(dp); 741 m_freem(m); 742 return (ENOBUFS); 743 } 744 MCLGET(m, M_TRYWAIT); 745 if ((m->m_flags & M_EXT) == 0) { 746 mn_free_desc(dp); 747 m_freem(m); 748 return (ENOBUFS); 749 } 750 dp->m = m; 751 dp->data = vtophys(m->m_data); 752 dp->flags = 0x00000000; 753 dp->flags += 1600 << 16; 754 dp->next = vtophys(dp2); 755 dp->vnext = dp2; 756 } 757 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 758 sc->ch[chan]->r1 = dp; 759 760 /* Initialize this channel */ 761 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 762 sc->m32x->cmd = 0x1; 763 DELAY(1000); 764 u = sc->m32x->stat; 765 if (!(u & 1)) 766 printf("%s: init chan %d stat %08x\n", sc->name, chan, u); 767 sc->m32x->stat = 1; 768 /* probably not at splnet, force outward queueing */ 769 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook)); 770 771 return (0); 772 } 773 774 /* 775 * CLOSE 776 */ 777 static int 778 ngmn_disconnect(hook_p hook) 779 { 780 int chan, i; 781 struct mn_softc *sc; 782 struct schan *sch; 783 struct trxd *dp, *dp2; 784 u_int32_t u; 785 786 sch = NG_HOOK_PRIVATE(hook); 787 chan = sch->chan; 788 sc = sch->sc; 789 790 if (sch->state == DOWN) 791 return (0); 792 sch->state = DOWN; 793 794 /* Set receiver & transmitter off */ 795 sc->m32_mem.cs[chan].flags = 0x80920006; 796 sc->m32_mem.cs[chan].itbs = 0; 797 798 /* free the timeslots */ 799 for (i = 0; i < 32; i++) 800 if (sc->ch[chan]->ts & (1 << i)) 801 sc->m32_mem.ts[i] = 0x20002000; 802 803 /* Initialize this channel */ 804 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 805 sc->m32x->cmd = 0x1; 806 DELAY(30); 807 u = sc->m32x->stat; 808 if (!(u & 1)) 809 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 810 sc->m32x->stat = 1; 811 812 /* Free all receive descriptors and mbufs */ 813 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 814 if (dp->m) 815 m_freem(dp->m); 816 sc->ch[chan]->r1 = dp2 = dp->vnext; 817 mn_free_desc(dp); 818 } 819 820 /* Free all transmit descriptors and mbufs */ 821 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 822 if (dp->m) { 823 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len; 824 m_freem(dp->m); 825 } 826 sc->ch[chan]->x1 = dp2 = dp->vnext; 827 mn_free_desc(dp); 828 } 829 sc->nhooks--; 830 return(0); 831 } 832 833 /* 834 * Create a new channel. 835 */ 836 static void 837 mn_create_channel(struct mn_softc *sc, int chan) 838 { 839 struct schan *sch; 840 841 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan], 842 M_MN, M_WAITOK | M_ZERO); 843 sch->sc = sc; 844 sch->state = DOWN; 845 sch->chan = chan; 846 sprintf(sch->name, "%s%d", sc->name, chan); 847 return; 848 } 849 850 #ifdef notyet 851 /* 852 * Dump Munich32x state 853 */ 854 static void 855 m32_dump(struct mn_softc *sc) 856 { 857 u_int32_t *tp4; 858 int i, j; 859 860 printf("mn%d: MUNICH32X dump\n", sc->unit); 861 tp4 = (u_int32_t *)sc->m0v; 862 for(j = 0; j < 64; j += 8) { 863 printf("%02x", j * sizeof *tp4); 864 for(i = 0; i < 8; i++) 865 printf(" %08x", tp4[i+j]); 866 printf("\n"); 867 } 868 for(j = 0; j < M32_CHAN; j++) { 869 if (!sc->ch[j]) 870 continue; 871 printf("CH%d: state %d ts %08x", 872 j, sc->ch[j]->state, sc->ch[j]->ts); 873 printf(" %08x %08x %08x %08x %08x %08x\n", 874 sc->m32_mem.cs[j].flags, 875 sc->m32_mem.cs[j].rdesc, 876 sc->m32_mem.cs[j].tdesc, 877 sc->m32_mem.cs[j].itbs, 878 sc->m32_mem.crxd[j], 879 sc->m32_mem.ctxd[j] ); 880 } 881 } 882 883 /* 884 * Dump Falch54 state 885 */ 886 static void 887 f54_dump(struct mn_softc *sc) 888 { 889 u_int8_t *tp1; 890 int i, j; 891 892 printf("%s: FALC54 dump\n", sc->name); 893 tp1 = (u_int8_t *)sc->m1v; 894 for(j = 0; j < 128; j += 16) { 895 printf("%s: %02x |", sc->name, j * sizeof *tp1); 896 for(i = 0; i < 16; i++) 897 printf(" %02x", tp1[i+j]); 898 printf("\n"); 899 } 900 } 901 #endif /* notyet */ 902 903 /* 904 * Init Munich32x 905 */ 906 static void 907 m32_init(struct mn_softc *sc) 908 { 909 910 sc->m32x->conf = 0x00000000; 911 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 912 #if 1 913 sc->m32x->mode2 = 0x00000081; 914 sc->m32x->txpoll = 0xffffffff; 915 #elif 1 916 sc->m32x->mode2 = 0x00000081; 917 sc->m32x->txpoll = 0xffffffff; 918 #else 919 sc->m32x->mode2 = 0x00000101; 920 #endif 921 sc->m32x->lconf = 0x6060009B; 922 sc->m32x->imask = 0x00000000; 923 } 924 925 /* 926 * Init the Falc54 927 */ 928 static void 929 f54_init(struct mn_softc *sc) 930 { 931 sc->f54w->ipc = 0x07; 932 933 sc->f54w->xpm0 = 0xbd; 934 sc->f54w->xpm1 = 0x03; 935 sc->f54w->xpm2 = 0x00; 936 937 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 938 sc->f54w->imr1 = 0x08; /* XMB */ 939 sc->f54w->imr2 = 0x00; 940 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 941 sc->f54w->imr4 = 0x00; 942 943 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 944 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 945 if (sc->framing == E1) 946 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 947 else if (sc->framing == E1U) 948 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */ 949 950 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 951 sc->f54w->pcd = 0x0a; 952 sc->f54w->pcr = 0x15; 953 sc->f54w->xsw = 0x9f; /* fmr4 */ 954 if (sc->framing == E1) 955 sc->f54w->xsp = 0x1c; /* fmr5 */ 956 else if (sc->framing == E1U) 957 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */ 958 sc->f54w->xc0 = 0x07; 959 sc->f54w->xc1 = 0x3d; 960 sc->f54w->rc0 = 0x05; 961 sc->f54w->rc1 = 0x00; 962 sc->f54w->cmdr = 0x51; 963 } 964 965 static int 966 mn_reset(struct mn_softc *sc) 967 { 968 u_int32_t u; 969 int i; 970 971 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 972 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 973 974 bzero(sc->tiqb, sizeof sc->tiqb); 975 sc->m32x->tiqba = vtophys(&sc->tiqb); 976 sc->m32x->tiql = NIQB / 16 - 1; 977 978 bzero(sc->riqb, sizeof sc->riqb); 979 sc->m32x->riqba = vtophys(&sc->riqb); 980 sc->m32x->riql = NIQB / 16 - 1; 981 982 bzero(sc->ltiqb, sizeof sc->ltiqb); 983 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 984 sc->m32x->ltiql = NIQB / 16 - 1; 985 986 bzero(sc->lriqb, sizeof sc->lriqb); 987 sc->m32x->lriqba = vtophys(&sc->lriqb); 988 sc->m32x->lriql = NIQB / 16 - 1; 989 990 bzero(sc->piqb, sizeof sc->piqb); 991 sc->m32x->piqba = vtophys(&sc->piqb); 992 sc->m32x->piql = NIQB / 16 - 1; 993 994 m32_init(sc); 995 f54_init(sc); 996 997 u = sc->m32x->stat; 998 sc->m32x->stat = u; 999 sc->m32_mem.ccb = 0x4; 1000 sc->m32x->cmd = 0x1; 1001 DELAY(1000); 1002 u = sc->m32x->stat; 1003 sc->m32x->stat = u; 1004 1005 /* set all timeslots to known state */ 1006 for (i = 0; i < 32; i++) 1007 sc->m32_mem.ts[i] = 0x20002000; 1008 1009 if (!(u & 1)) { 1010 printf( 1011 "mn%d: WARNING: Controller failed the PCI bus-master test.\n" 1012 "mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 1013 sc->unit, sc->unit); 1014 return (0); 1015 } 1016 return (1); 1017 } 1018 1019 /* 1020 * FALC54 interrupt handling 1021 */ 1022 static void 1023 f54_intr(struct mn_softc *sc) 1024 { 1025 unsigned g, u, s; 1026 1027 g = sc->f54r->gis; 1028 u = sc->f54r->isr0 << 24; 1029 u |= sc->f54r->isr1 << 16; 1030 u |= sc->f54r->isr2 << 8; 1031 u |= sc->f54r->isr3; 1032 sc->falc_irq = u; 1033 /* don't chat about the 1 sec heart beat */ 1034 if (u & ~0x40) { 1035 #if 0 1036 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\2" 1037 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 1038 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 1039 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 1040 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 1041 #endif 1042 s = sc->f54r->frs0 << 24; 1043 s |= sc->f54r->frs1 << 16; 1044 s |= sc->f54r->rsw << 8; 1045 s |= sc->f54r->rsp; 1046 sc->falc_state = s; 1047 1048 s &= ~0x01844038; /* undefined or static bits */ 1049 s &= ~0x00009fc7; /* bits we don't care about */ 1050 s &= ~0x00780000; /* XXX: TS16 related */ 1051 s &= ~0x06000000; /* XXX: Multiframe related */ 1052 #if 0 1053 printf("%s*: FALC54 Status %b\n", sc->name, s, "\2" 1054 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 1055 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 1056 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 1057 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 1058 #endif 1059 if (s != sc->framer_state) { 1060 #if 0 1061 for (i = 0; i < M32_CHAN; i++) { 1062 if (!sc->ch[i]) 1063 continue; 1064 sp = &sc->ch[i]->ifsppp; 1065 if (!(sp->pp_if.if_flags & IFF_UP)) 1066 continue; 1067 if (s) 1068 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 1069 else 1070 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 1071 } 1072 #endif 1073 sc->framer_state = s; 1074 } 1075 } 1076 /* Once per second check error counters */ 1077 /* XXX: not clear if this is actually ok */ 1078 if (!(u & 0x40)) 1079 return; 1080 sc->cnt_fec += sc->f54r->fec; 1081 sc->cnt_cvc += sc->f54r->cvc; 1082 sc->cnt_cec1 += sc->f54r->cec1; 1083 sc->cnt_ebc += sc->f54r->ebc; 1084 sc->cnt_cec2 += sc->f54r->cec2; 1085 sc->cnt_cec3 += sc->f54r->cec3; 1086 sc->cnt_rbc += sc->f54r->rbc; 1087 } 1088 1089 /* 1090 * Transmit interrupt for one channel 1091 */ 1092 static void 1093 mn_tx_intr(struct mn_softc *sc, u_int32_t vector) 1094 { 1095 u_int32_t chan; 1096 struct trxd *dp; 1097 struct mbuf *m; 1098 1099 chan = vector & 0x1f; 1100 if (!sc->ch[chan]) 1101 return; 1102 if (sc->ch[chan]->state != UP) { 1103 printf("%s: tx_intr when not UP\n", sc->name); 1104 return; 1105 } 1106 for (;;) { 1107 dp = sc->ch[chan]->x1; 1108 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 1109 return; 1110 m = dp->m; 1111 if (m) { 1112 #if 0 1113 printf("%d = %d - %d (%p)\n", 1114 sc->ch[chan]->tx_pending - m->m_pkthdr.len, 1115 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m); 1116 #endif 1117 sc->ch[chan]->tx_pending -= m->m_pkthdr.len; 1118 m_freem(m); 1119 } 1120 sc->ch[chan]->last_xmit = time_second; 1121 sc->ch[chan]->x1 = dp->vnext; 1122 mn_free_desc(dp); 1123 } 1124 } 1125 1126 /* 1127 * Receive interrupt for one channel 1128 */ 1129 static void 1130 mn_rx_intr(struct mn_softc *sc, u_int32_t vector) 1131 { 1132 u_int32_t chan, err; 1133 struct trxd *dp; 1134 struct mbuf *m; 1135 struct schan *sch; 1136 1137 chan = vector & 0x1f; 1138 if (!sc->ch[chan]) 1139 return; 1140 sch = sc->ch[chan]; 1141 if (sch->state != UP) { 1142 printf("%s: rx_intr when not UP\n", sc->name); 1143 return; 1144 } 1145 vector &= ~0x1f; 1146 if (vector == 0x30000b00) 1147 sch->rx_error++; 1148 for (;;) { 1149 dp = sch->r1; 1150 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1151 return; 1152 m = dp->m; 1153 dp->m = 0; 1154 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1155 err = (dp->status >> 8) & 0xff; 1156 if (!err) { 1157 int error; 1158 NG_SEND_DATA_ONLY(error, sch->hook, m); 1159 sch->last_recv = time_second; 1160 /* we could be down by now... */ 1161 if (sch->state != UP) 1162 return; 1163 } else if (err & 0x40) { 1164 sch->short_error++; 1165 } else if (err & 0x10) { 1166 sch->crc_error++; 1167 } else if (err & 0x08) { 1168 sch->dribble_error++; 1169 } else if (err & 0x04) { 1170 sch->long_error++; 1171 } else if (err & 0x02) { 1172 sch->abort_error++; 1173 } else if (err & 0x01) { 1174 sch->overflow_error++; 1175 } 1176 if (err) { 1177 sch->last_rxerr = time_second; 1178 sch->prev_error = sch->last_error; 1179 sch->last_error = err; 1180 } 1181 1182 sc->ch[chan]->r1 = dp->vnext; 1183 1184 /* Replenish desc + mbuf supplies */ 1185 if (!m) { 1186 MGETHDR(m, M_DONTWAIT, MT_DATA); 1187 if (m == NULL) { 1188 mn_free_desc(dp); 1189 return; /* ENOBUFS */ 1190 } 1191 MCLGET(m, M_DONTWAIT); 1192 if((m->m_flags & M_EXT) == 0) { 1193 mn_free_desc(dp); 1194 m_freem(m); 1195 return; /* ENOBUFS */ 1196 } 1197 } 1198 dp->m = m; 1199 dp->data = vtophys(m->m_data); 1200 dp->flags = 0x40000000; 1201 dp->flags += 1600 << 16; 1202 dp->next = vtophys(dp); 1203 dp->vnext = 0; 1204 sc->ch[chan]->rl->next = vtophys(dp); 1205 sc->ch[chan]->rl->vnext = dp; 1206 sc->ch[chan]->rl->flags &= ~0x40000000; 1207 sc->ch[chan]->rl = dp; 1208 } 1209 } 1210 1211 1212 /* 1213 * Interupt handler 1214 */ 1215 1216 static void 1217 mn_intr(void *xsc) 1218 { 1219 struct mn_softc *sc; 1220 u_int32_t stat, lstat, u; 1221 int i, j; 1222 1223 sc = xsc; 1224 stat = sc->m32x->stat; 1225 lstat = sc->m32x->lstat; 1226 #if 0 1227 if (!stat && !(lstat & 2)) 1228 return; 1229 #endif 1230 1231 if (stat & ~0xc200) { 1232 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1233 } 1234 1235 if ((stat & 0x200) || (lstat & 2)) 1236 f54_intr(sc); 1237 1238 for (j = i = 0; i < 64; i ++) { 1239 u = sc->riqb[i]; 1240 if (u) { 1241 sc->riqb[i] = 0; 1242 mn_rx_intr(sc, u); 1243 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1244 continue; 1245 u &= ~0x30000400; /* bits we don't care about */ 1246 if ((u & ~0x1f) == 0x00000900) 1247 continue; 1248 if (!(u & ~0x1f)) 1249 continue; 1250 if (!j) 1251 printf("%s*: RIQB:", sc->name); 1252 printf(" [%d]=%08x", i, u); 1253 j++; 1254 } 1255 } 1256 if (j) 1257 printf("\n"); 1258 1259 for (j = i = 0; i < 64; i ++) { 1260 u = sc->tiqb[i]; 1261 if (u) { 1262 sc->tiqb[i] = 0; 1263 mn_tx_intr(sc, u); 1264 if ((u & ~0x1f) == 0x20000800) 1265 continue; 1266 u &= ~0x20000000; /* bits we don't care about */ 1267 if (!u) 1268 continue; 1269 if (!j) 1270 printf("%s*: TIQB:", sc->name); 1271 printf(" [%d]=%08x", i, u); 1272 j++; 1273 } 1274 } 1275 if (j) 1276 printf("\n"); 1277 sc->m32x->stat = stat; 1278 } 1279 1280 static void 1281 mn_timeout(void *xsc) 1282 { 1283 static int round = 0; 1284 struct mn_softc *sc; 1285 1286 mn_intr(xsc); 1287 sc = xsc; 1288 timeout(mn_timeout, xsc, 10 * hz); 1289 round++; 1290 if (round == 2) { 1291 sc->m32_mem.ccb = 0x00008004; 1292 sc->m32x->cmd = 0x1; 1293 } else if (round > 2) { 1294 printf("%s: timeout\n", sc->name); 1295 } 1296 } 1297 1298 /* 1299 * PCI initialization stuff 1300 */ 1301 1302 static int 1303 mn_probe (device_t self) 1304 { 1305 u_int id = pci_get_devid(self); 1306 1307 if (sizeof (struct m32xreg) != 256) { 1308 printf("MN: sizeof(struct m32xreg) = %zd, should have been 256\n", sizeof (struct m32xreg)); 1309 return (ENXIO); 1310 } 1311 if (sizeof (struct f54rreg) != 128) { 1312 printf("MN: sizeof(struct f54rreg) = %zd, should have been 128\n", sizeof (struct f54rreg)); 1313 return (ENXIO); 1314 } 1315 if (sizeof (struct f54wreg) != 128) { 1316 printf("MN: sizeof(struct f54wreg) = %zd, should have been 128\n", sizeof (struct f54wreg)); 1317 return (ENXIO); 1318 } 1319 1320 if (id != 0x2101110a) 1321 return (ENXIO); 1322 1323 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller"); 1324 return (0); 1325 } 1326 1327 static int 1328 mn_attach (device_t self) 1329 { 1330 struct mn_softc *sc; 1331 u_int32_t u; 1332 u_int32_t ver; 1333 static int once; 1334 int rid, error; 1335 struct resource *res; 1336 1337 if (!once) { 1338 if (ng_newtype(&mntypestruct)) 1339 printf("ng_newtype failed\n"); 1340 once++; 1341 } 1342 1343 sc = (struct mn_softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO); 1344 device_set_softc(self, sc); 1345 1346 sc->dev = self; 1347 sc->unit = device_get_unit(self); 1348 sc->framing = E1; 1349 sprintf(sc->name, "mn%d", sc->unit); 1350 1351 rid = PCIR_MAPS; 1352 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1353 0, ~0, 1, RF_ACTIVE); 1354 if (res == NULL) { 1355 device_printf(self, "Could not map memory\n"); 1356 free(sc, M_MN); 1357 return ENXIO; 1358 } 1359 sc->m0v = rman_get_virtual(res); 1360 sc->m0p = rman_get_start(res); 1361 1362 rid = PCIR_MAPS + 4; 1363 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1364 0, ~0, 1, RF_ACTIVE); 1365 if (res == NULL) { 1366 device_printf(self, "Could not map memory\n"); 1367 free(sc, M_MN); 1368 return ENXIO; 1369 } 1370 sc->m1v = rman_get_virtual(res); 1371 sc->m1p = rman_get_start(res); 1372 1373 /* Allocate interrupt */ 1374 rid = 0; 1375 sc->irq = bus_alloc_resource(self, SYS_RES_IRQ, &rid, 0, ~0, 1376 1, RF_SHAREABLE | RF_ACTIVE); 1377 1378 if (sc->irq == NULL) { 1379 printf("couldn't map interrupt\n"); 1380 free(sc, M_MN); 1381 return(ENXIO); 1382 } 1383 1384 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, mn_intr, sc, &sc->intrhand); 1385 1386 if (error) { 1387 printf("couldn't set up irq\n"); 1388 free(sc, M_MN); 1389 return(ENXIO); 1390 } 1391 1392 u = pci_read_config(self, PCIR_COMMAND, 1); 1393 printf("%x\n", u); 1394 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1); 1395 #if 0 1396 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4); 1397 #endif 1398 u = pci_read_config(self, PCIR_COMMAND, 1); 1399 printf("%x\n", u); 1400 1401 ver = pci_get_revid(self); 1402 1403 sc->m32x = (struct m32xreg *) sc->m0v; 1404 sc->f54w = (struct f54wreg *) sc->m1v; 1405 sc->f54r = (struct f54rreg *) sc->m1v; 1406 1407 /* We must reset before poking at FALC54 registers */ 1408 u = mn_reset(sc); 1409 if (!u) 1410 return (0); 1411 1412 printf("mn%d: Munich32X", sc->unit); 1413 switch (ver) { 1414 case 0x13: 1415 printf(" Rev 2.2"); 1416 break; 1417 default: 1418 printf(" Rev 0x%x\n", ver); 1419 } 1420 printf(", Falc54"); 1421 switch (sc->f54r->vstr) { 1422 case 0: 1423 printf(" Rev < 1.3\n"); 1424 break; 1425 case 1: 1426 printf(" Rev 1.3\n"); 1427 break; 1428 case 2: 1429 printf(" Rev 1.4\n"); 1430 break; 1431 case 0x10: 1432 printf("-LH Rev 1.1\n"); 1433 break; 1434 case 0x13: 1435 printf("-LH Rev 1.3\n"); 1436 break; 1437 default: 1438 printf(" Rev 0x%x\n", sc->f54r->vstr); 1439 } 1440 1441 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1442 printf("ng_make_node_common failed\n"); 1443 return (0); 1444 } 1445 NG_NODE_SET_PRIVATE(sc->node, sc); 1446 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1447 if (ng_name_node(sc->node, sc->nodename)) { 1448 NG_NODE_UNREF(sc->node); 1449 return (0); 1450 } 1451 1452 return (0); 1453 } 1454 1455 1456 static device_method_t mn_methods[] = { 1457 /* Device interface */ 1458 DEVMETHOD(device_probe, mn_probe), 1459 DEVMETHOD(device_attach, mn_attach), 1460 DEVMETHOD(device_suspend, bus_generic_suspend), 1461 DEVMETHOD(device_resume, bus_generic_resume), 1462 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1463 1464 {0, 0} 1465 }; 1466 1467 static driver_t mn_driver = { 1468 "mn", 1469 mn_methods, 1470 0 1471 }; 1472 1473 static devclass_t mn_devclass; 1474 1475 DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0);
Cache object: 0d196ba5dcb551c7887770622e8f9a85
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