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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_mn.c
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1 /* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $Id: if_mn.c,v 1.38 2003/06/11 06:24:36 obrien Exp $ 10 * 11 * Driver for Siemens reference design card "Easy321-R1". 12 * 13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 14 * controller. 15 * 16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't 17 * check it coming in. 18 * 19 * The FALC54 and MUNICH32X have far too many registers and weird modes for 20 * comfort, so I have not bothered typing it all into a "fooreg.h" file, 21 * you will (badly!) need the documentation anyway if you want to mess with 22 * this gadget. 23 */ 24 25 #include <sys/cdefs.h> 26 __FBSDID("$FreeBSD: releng/5.2/sys/pci/if_mn.c 119690 2003-09-02 17:30:40Z jhb $"); 27 28 /* 29 * Stuff to describe the MUNIC32X and FALC54 chips. 30 */ 31 32 #define M32_CHAN 32 /* We have 32 channels */ 33 #define M32_TS 32 /* We have 32 timeslots */ 34 35 #define NG_MN_NODE_TYPE "mn" 36 37 #include <sys/param.h> 38 #include <sys/kernel.h> 39 #include <sys/sysctl.h> 40 #include <sys/bus.h> 41 #include <sys/mbuf.h> 42 #include <sys/systm.h> 43 #include <sys/malloc.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include "pci_if.h" 48 49 #include <machine/bus.h> 50 #include <machine/resource.h> 51 52 #include <sys/rman.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 57 #include <netgraph/ng_message.h> 58 #include <netgraph/netgraph.h> 59 60 61 static int mn_maxlatency = 1000; 62 SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW, 63 &mn_maxlatency, 0, 64 "The number of milliseconds a packet is allowed to spend in the output queue. " 65 "If the output queue is longer than this number of milliseconds when the packet " 66 "arrives for output, the packet will be dropped." 67 ); 68 69 #ifndef NMN 70 /* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 71 #define NMN 4 72 #endif 73 74 /* From: PEB 20321 data sheet, p187, table 22 */ 75 struct m32xreg { 76 u_int32_t conf, cmd, stat, imask; 77 u_int32_t fill10, piqba, piql, fill1c; 78 u_int32_t mode1, mode2, ccba, txpoll; 79 u_int32_t tiqba, tiql, riqba, riql; 80 u_int32_t lconf, lccba, fill48, ltran; 81 u_int32_t ltiqba, ltiql, lriqba, lriql; 82 u_int32_t lreg0, lreg1, lreg2, lreg3; 83 u_int32_t lreg4, lreg5, lre6, lstat; 84 u_int32_t gpdir, gpdata, gpod, fill8c; 85 u_int32_t ssccon, sscbr, ssctb, sscrb; 86 u_int32_t ssccse, sscim, fillab, fillac; 87 u_int32_t iomcon1, iomcon2, iomstat, fillbc; 88 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 89 u_int32_t iomtmo, iomrmo, filld8, filldc; 90 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 91 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 92 }; 93 94 /* From: PEB 2254 data sheet, p80, table 10 */ 95 struct f54wreg { 96 u_int16_t xfifo; 97 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 98 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 99 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 100 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 101 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 102 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 103 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 104 u_int8_t lim2, fill39[7]; 105 u_int8_t fill40[8]; 106 u_int8_t fill48[8]; 107 u_int8_t fill50[8]; 108 u_int8_t fill58[8]; 109 u_int8_t dec, fill61, test2, fill63[5]; 110 u_int8_t fill68[8]; 111 u_int8_t xs[16]; 112 }; 113 114 /* From: PEB 2254 data sheet, p117, table 10 */ 115 struct f54rreg { 116 u_int16_t rfifo; 117 u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 118 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 119 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 120 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 121 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 122 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 123 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 124 u_int8_t lim2, fill39[7]; 125 u_int8_t fill40[8]; 126 u_int8_t fill48[4], frs0, frs1, rsw, rsp; 127 u_int16_t fec, cvc, cec1, ebc; 128 u_int16_t cec2, cec3; 129 u_int8_t rsa4, rsa5, rsa6, rsa7; 130 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 131 u_int16_t rbc; 132 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 133 u_int8_t rs[16]; 134 }; 135 136 /* Transmit & receive descriptors */ 137 struct trxd { 138 u_int32_t flags; 139 vm_offset_t next; 140 vm_offset_t data; 141 u_int32_t status; /* only used for receive */ 142 struct mbuf *m; /* software use only */ 143 struct trxd *vnext; /* software use only */ 144 }; 145 146 /* Channel specification */ 147 struct cspec { 148 u_int32_t flags; 149 vm_offset_t rdesc; 150 vm_offset_t tdesc; 151 u_int32_t itbs; 152 }; 153 154 struct m32_mem { 155 vm_offset_t csa; 156 u_int32_t ccb; 157 u_int32_t reserve1[2]; 158 u_int32_t ts[M32_TS]; 159 struct cspec cs[M32_CHAN]; 160 vm_offset_t crxd[M32_CHAN]; 161 vm_offset_t ctxd[M32_CHAN]; 162 }; 163 164 struct mn_softc; 165 struct sockaddr; 166 struct rtentry; 167 168 static int mn_probe (device_t self); 169 static int mn_attach (device_t self); 170 static void mn_create_channel(struct mn_softc *sc, int chan); 171 static int mn_reset(struct mn_softc *sc); 172 static struct trxd * mn_alloc_desc(void); 173 static void mn_free_desc(struct trxd *dp); 174 static void mn_intr(void *xsc); 175 static u_int32_t mn_parse_ts(const char *s, int *nbit); 176 #ifdef notyet 177 static void m32_dump(struct mn_softc *sc); 178 static void f54_dump(struct mn_softc *sc); 179 static void mn_fmt_ts(char *p, u_int32_t ts); 180 #endif /* notyet */ 181 static void f54_init(struct mn_softc *sc); 182 183 static ng_constructor_t ngmn_constructor; 184 static ng_rcvmsg_t ngmn_rcvmsg; 185 static ng_shutdown_t ngmn_shutdown; 186 static ng_newhook_t ngmn_newhook; 187 static ng_connect_t ngmn_connect; 188 static ng_rcvdata_t ngmn_rcvdata; 189 static ng_disconnect_t ngmn_disconnect; 190 191 static struct ng_type mntypestruct = { 192 NG_ABI_VERSION, 193 NG_MN_NODE_TYPE, 194 NULL, 195 ngmn_constructor, 196 ngmn_rcvmsg, 197 ngmn_shutdown, 198 ngmn_newhook, 199 NULL, 200 ngmn_connect, 201 ngmn_rcvdata, 202 ngmn_disconnect, 203 NULL 204 }; 205 206 static MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 207 208 #define NIQB 64 209 210 struct schan { 211 enum {DOWN, UP} state; 212 struct mn_softc *sc; 213 int chan; 214 u_int32_t ts; 215 char name[8]; 216 struct trxd *r1, *rl; 217 struct trxd *x1, *xl; 218 hook_p hook; 219 220 time_t last_recv; 221 time_t last_rxerr; 222 time_t last_xmit; 223 224 u_long rx_error; 225 226 u_long short_error; 227 u_long crc_error; 228 u_long dribble_error; 229 u_long long_error; 230 u_long abort_error; 231 u_long overflow_error; 232 233 int last_error; 234 int prev_error; 235 236 u_long tx_pending; 237 u_long tx_limit; 238 }; 239 240 enum framing {WHOKNOWS, E1, E1U, T1, T1U}; 241 242 struct mn_softc { 243 int unit; 244 device_t dev; 245 struct resource *irq; 246 void *intrhand; 247 enum framing framing; 248 int nhooks; 249 void *m0v, *m1v; 250 vm_offset_t m0p, m1p; 251 struct m32xreg *m32x; 252 struct f54wreg *f54w; 253 struct f54rreg *f54r; 254 struct m32_mem m32_mem; 255 u_int32_t tiqb[NIQB]; 256 u_int32_t riqb[NIQB]; 257 u_int32_t piqb[NIQB]; 258 u_int32_t ltiqb[NIQB]; 259 u_int32_t lriqb[NIQB]; 260 char name[8]; 261 u_int32_t falc_irq, falc_state, framer_state; 262 struct schan *ch[M32_CHAN]; 263 char nodename[NG_NODELEN + 1]; 264 node_p node; 265 266 u_long cnt_fec; 267 u_long cnt_cvc; 268 u_long cnt_cec1; 269 u_long cnt_ebc; 270 u_long cnt_cec2; 271 u_long cnt_cec3; 272 u_long cnt_rbc; 273 }; 274 275 static int 276 ngmn_constructor(node_p node) 277 { 278 279 return (EINVAL); 280 } 281 282 static int 283 ngmn_shutdown(node_p nodep) 284 { 285 286 return (EINVAL); 287 } 288 289 static void 290 ngmn_config(node_p node, char *set, char *ret) 291 { 292 struct mn_softc *sc; 293 enum framing wframing; 294 295 sc = NG_NODE_PRIVATE(node); 296 297 if (set != NULL) { 298 if (!strncmp(set, "line ", 5)) { 299 wframing = sc->framing; 300 if (!strcmp(set, "line e1")) { 301 wframing = E1; 302 } else if (!strcmp(set, "line e1u")) { 303 wframing = E1U; 304 } else { 305 strcat(ret, "ENOGROK\n"); 306 return; 307 } 308 if (wframing == sc->framing) 309 return; 310 if (sc->nhooks > 0) { 311 sprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks); 312 return; 313 } 314 sc->framing = wframing; 315 #if 1 316 f54_init(sc); 317 #else 318 mn_reset(sc); 319 #endif 320 } else { 321 printf("%s CONFIG SET [%s]\n", sc->nodename, set); 322 strcat(ret, "ENOGROK\n"); 323 return; 324 } 325 } 326 327 } 328 329 static int 330 ngmn_rcvmsg(node_p node, item_p item, hook_p lasthook) 331 { 332 struct mn_softc *sc; 333 struct ng_mesg *resp = NULL; 334 struct schan *sch; 335 char *s, *r; 336 int pos, i; 337 struct ng_mesg *msg; 338 339 NGI_GET_MSG(item, msg); 340 sc = NG_NODE_PRIVATE(node); 341 342 if (msg->header.typecookie != NGM_GENERIC_COOKIE) { 343 NG_FREE_ITEM(item); 344 NG_FREE_MSG(msg); 345 return (EINVAL); 346 } 347 348 if (msg->header.cmd != NGM_TEXT_CONFIG && 349 msg->header.cmd != NGM_TEXT_STATUS) { 350 NG_FREE_ITEM(item); 351 NG_FREE_MSG(msg); 352 return (EINVAL); 353 } 354 355 NG_MKRESPONSE(resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 356 M_NOWAIT); 357 if (resp == NULL) { 358 NG_FREE_ITEM(item); 359 NG_FREE_MSG(msg); 360 return (ENOMEM); 361 } 362 363 if (msg->header.arglen) 364 s = (char *)msg->data; 365 else 366 s = NULL; 367 r = (char *)resp->data; 368 *r = '\0'; 369 370 if (msg->header.cmd == NGM_TEXT_CONFIG) { 371 ngmn_config(node, s, r); 372 resp->header.arglen = strlen(r) + 1; 373 NG_RESPOND_MSG(i, node, item, resp); 374 FREE(msg, M_NETGRAPH); 375 return (0); 376 } 377 pos = 0; 378 pos += sprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\2" 379 "\40LOS\37AIS\36LFA\35RRA" 380 "\34AUXP\33NMF\32LMFA\31frs0.0" 381 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 382 "\24TS16LFA\23frs1.2\22XLS\21XLO" 383 "\20RS1\17rsw.6\16RRA\15RY0" 384 "\14RY1\13RY2\12RY3\11RY4" 385 "\10SI1\7SI2\6rsp.5\5rsp.4" 386 "\4rsp.3\3RSIF\2RS13\1RS15"); 387 pos += sprintf(pos + r," Framing errors: %lu", sc->cnt_fec); 388 pos += sprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc); 389 390 pos += sprintf(pos + r," Falc State %b;\n", sc->falc_state, "\2" 391 "\40LOS\37AIS\36LFA\35RRA" 392 "\34AUXP\33NMF\32LMFA\31frs0.0" 393 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 394 "\24TS16LFA\23frs1.2\22XLS\21XLO" 395 "\20RS1\17rsw.6\16RRA\15RY0" 396 "\14RY1\13RY2\12RY3\11RY4" 397 "\10SI1\7SI2\6rsp.5\5rsp.4" 398 "\4rsp.3\3RSIF\2RS13\1RS15"); 399 pos += sprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\2" 400 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 401 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 402 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 403 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 404 for (i = 0; i < M32_CHAN; i++) { 405 if (!sc->ch[i]) 406 continue; 407 sch = sc->ch[i]; 408 409 pos += sprintf(r + pos, " Chan %d <%s> ", 410 i, NG_HOOK_NAME(sch->hook)); 411 412 pos += sprintf(r + pos, " Last Rx: "); 413 if (sch->last_recv) 414 pos += sprintf(r + pos, "%lu s", 415 (unsigned long)(time_second - sch->last_recv)); 416 else 417 pos += sprintf(r + pos, "never"); 418 419 pos += sprintf(r + pos, ", last RxErr: "); 420 if (sch->last_rxerr) 421 pos += sprintf(r + pos, "%lu s", 422 (unsigned long)(time_second - sch->last_rxerr)); 423 else 424 pos += sprintf(r + pos, "never"); 425 426 pos += sprintf(r + pos, ", last Tx: "); 427 if (sch->last_xmit) 428 pos += sprintf(r + pos, "%lu s\n", 429 (unsigned long)(time_second - sch->last_xmit)); 430 else 431 pos += sprintf(r + pos, "never\n"); 432 433 pos += sprintf(r + pos, " RX error(s) %lu", sch->rx_error); 434 pos += sprintf(r + pos, " Short: %lu", sch->short_error); 435 pos += sprintf(r + pos, " CRC: %lu", sch->crc_error); 436 pos += sprintf(r + pos, " Mod8: %lu", sch->dribble_error); 437 pos += sprintf(r + pos, " Long: %lu", sch->long_error); 438 pos += sprintf(r + pos, " Abort: %lu", sch->abort_error); 439 pos += sprintf(r + pos, " Overflow: %lu\n", sch->overflow_error); 440 441 pos += sprintf(r + pos, " Last error: %b Prev error: %b\n", 442 sch->last_error, "\2\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 443 sch->prev_error, "\2\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 444 pos += sprintf(r + pos, " Xmit bytes pending %ld\n", 445 sch->tx_pending); 446 } 447 resp->header.arglen = pos + 1; 448 449 /* Take care of synchronous response, if any */ 450 NG_RESPOND_MSG(i, node, item, resp); 451 NG_FREE_MSG(msg); 452 return (0); 453 } 454 455 static int 456 ngmn_newhook(node_p node, hook_p hook, const char *name) 457 { 458 u_int32_t ts, chan; 459 struct mn_softc *sc; 460 int nbit; 461 462 sc = NG_NODE_PRIVATE(node); 463 464 if (name[0] != 't' || name[1] != 's') 465 return (EINVAL); 466 467 ts = mn_parse_ts(name + 2, &nbit); 468 printf("%d bits %x\n", nbit, ts); 469 if (sc->framing == E1 && (ts & 1)) 470 return (EINVAL); 471 if (sc->framing == E1U && nbit != 32) 472 return (EINVAL); 473 if (ts == 0) 474 return (EINVAL); 475 if (sc->framing == E1) 476 chan = ffs(ts) - 1; 477 else 478 chan = 1; 479 if (!sc->ch[chan]) 480 mn_create_channel(sc, chan); 481 else if (sc->ch[chan]->state == UP) 482 return (EBUSY); 483 sc->ch[chan]->ts = ts; 484 sc->ch[chan]->hook = hook; 485 sc->ch[chan]->tx_limit = nbit * 8; 486 NG_HOOK_SET_PRIVATE(hook, sc->ch[chan]); 487 sc->nhooks++; 488 return(0); 489 } 490 491 492 static struct trxd *mn_desc_free; 493 494 static struct trxd * 495 mn_alloc_desc(void) 496 { 497 struct trxd *dp; 498 499 dp = mn_desc_free; 500 if (dp) 501 mn_desc_free = dp->vnext; 502 else 503 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT); 504 return (dp); 505 } 506 507 static void 508 mn_free_desc(struct trxd *dp) 509 { 510 dp->vnext = mn_desc_free; 511 mn_desc_free = dp; 512 } 513 514 static u_int32_t 515 mn_parse_ts(const char *s, int *nbit) 516 { 517 unsigned r; 518 int i, j; 519 char *p; 520 521 r = 0; 522 j = -1; 523 *nbit = 0; 524 while(*s) { 525 i = strtol(s, &p, 0); 526 if (i < 0 || i > 31) 527 return (0); 528 while (j != -1 && j < i) { 529 r |= 1 << j++; 530 (*nbit)++; 531 } 532 j = -1; 533 r |= 1 << i; 534 (*nbit)++; 535 if (*p == ',') { 536 s = p + 1; 537 continue; 538 } else if (*p == '-') { 539 j = i + 1; 540 s = p + 1; 541 continue; 542 } else if (!*p) { 543 break; 544 } else { 545 return (0); 546 } 547 } 548 return (r); 549 } 550 551 #ifdef notyet 552 static void 553 mn_fmt_ts(char *p, u_int32_t ts) 554 { 555 char *s; 556 int j; 557 558 s = ""; 559 ts &= 0xffffffff; 560 for (j = 0; j < 32; j++) { 561 if (!(ts & (1 << j))) 562 continue; 563 sprintf(p, "%s%d", s, j); 564 p += strlen(p); 565 s = ","; 566 if (!(ts & (1 << (j+1)))) 567 continue; 568 for (; j < 32; j++) 569 if (!(ts & (1 << (j+1)))) 570 break; 571 sprintf(p, "-%d", j); 572 p += strlen(p); 573 s = ","; 574 } 575 } 576 #endif /* notyet */ 577 578 /* 579 * OUTPUT 580 */ 581 582 static int 583 ngmn_rcvdata(hook_p hook, item_p item) 584 { 585 struct mbuf *m2; 586 struct trxd *dp, *dp2; 587 struct schan *sch; 588 struct mn_softc *sc; 589 int chan, pitch, len; 590 struct mbuf *m; 591 592 sch = NG_HOOK_PRIVATE(hook); 593 sc = sch->sc; 594 chan = sch->chan; 595 596 if (sch->state != UP) { 597 NG_FREE_ITEM(item); 598 return (0); 599 } 600 NGI_GET_M(item, m); 601 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) { 602 NG_FREE_M(m); 603 NG_FREE_ITEM(item); 604 return (0); 605 } 606 NG_FREE_ITEM(item); 607 pitch = 0; 608 m2 = m; 609 dp2 = sc->ch[chan]->xl; 610 len = m->m_pkthdr.len; 611 while (len) { 612 dp = mn_alloc_desc(); 613 if (!dp) { 614 pitch++; 615 m_freem(m); 616 sc->ch[chan]->xl = dp2; 617 dp = dp2->vnext; 618 while (dp) { 619 dp2 = dp->vnext; 620 mn_free_desc(dp); 621 dp = dp2; 622 } 623 sc->ch[chan]->xl->vnext = 0; 624 break; 625 } 626 dp->data = vtophys(m2->m_data); 627 dp->flags = m2->m_len << 16; 628 dp->flags += 1; 629 len -= m2->m_len; 630 dp->next = vtophys(dp); 631 dp->vnext = 0; 632 sc->ch[chan]->xl->next = vtophys(dp); 633 sc->ch[chan]->xl->vnext = dp; 634 sc->ch[chan]->xl = dp; 635 if (!len) { 636 dp->m = m; 637 dp->flags |= 0xc0000000; 638 dp2->flags &= ~0x40000000; 639 } else { 640 dp->m = 0; 641 m2 = m2->m_next; 642 } 643 } 644 if (pitch) 645 printf("%s%d: Short on mem, pitched %d packets\n", 646 sc->name, chan, pitch); 647 else { 648 #if 0 649 printf("%d = %d + %d (%p)\n", 650 sch->tx_pending + m->m_pkthdr.len, 651 sch->tx_pending , m->m_pkthdr.len, m); 652 #endif 653 sch->tx_pending += m->m_pkthdr.len; 654 sc->m32x->txpoll &= ~(1 << chan); 655 } 656 return (0); 657 } 658 659 /* 660 * OPEN 661 */ 662 static int 663 ngmn_connect(hook_p hook) 664 { 665 int i, nts, chan; 666 struct trxd *dp, *dp2; 667 struct mbuf *m; 668 struct mn_softc *sc; 669 struct schan *sch; 670 u_int32_t u; 671 672 sch = NG_HOOK_PRIVATE(hook); 673 chan = sch->chan; 674 sc = sch->sc; 675 676 if (sch->state == UP) 677 return (0); 678 sch->state = UP; 679 680 /* Count and configure the timeslots for this channel */ 681 for (nts = i = 0; i < 32; i++) 682 if (sch->ts & (1 << i)) { 683 sc->m32_mem.ts[i] = 0x00ff00ff | 684 (chan << 24) | (chan << 8); 685 nts++; 686 } 687 688 /* Init the receiver & xmitter to HDLC */ 689 sc->m32_mem.cs[chan].flags = 0x80e90006; 690 /* Allocate two buffers per timeslot */ 691 if (nts == 32) 692 sc->m32_mem.cs[chan].itbs = 63; 693 else 694 sc->m32_mem.cs[chan].itbs = nts * 2; 695 696 /* Setup a transmit chain with one descriptor */ 697 /* XXX: we actually send a 1 byte packet */ 698 dp = mn_alloc_desc(); 699 MGETHDR(m, M_TRYWAIT, MT_DATA); 700 if (m == NULL) 701 return ENOBUFS; 702 m->m_pkthdr.len = 0; 703 dp->m = m; 704 dp->flags = 0xc0000000 + (1 << 16); 705 dp->next = vtophys(dp); 706 dp->vnext = 0; 707 dp->data = vtophys(sc->name); 708 sc->m32_mem.cs[chan].tdesc = vtophys(dp); 709 sc->ch[chan]->x1 = dp; 710 sc->ch[chan]->xl = dp; 711 712 /* Setup a receive chain with 5 + NTS descriptors */ 713 714 dp = mn_alloc_desc(); 715 m = NULL; 716 MGETHDR(m, M_TRYWAIT, MT_DATA); 717 if (m == NULL) { 718 mn_free_desc(dp); 719 return (ENOBUFS); 720 } 721 MCLGET(m, M_TRYWAIT); 722 if ((m->m_flags & M_EXT) == 0) { 723 mn_free_desc(dp); 724 m_freem(m); 725 return (ENOBUFS); 726 } 727 dp->m = m; 728 dp->data = vtophys(m->m_data); 729 dp->flags = 0x40000000; 730 dp->flags += 1600 << 16; 731 dp->next = vtophys(dp); 732 dp->vnext = 0; 733 sc->ch[chan]->rl = dp; 734 735 for (i = 0; i < (nts + 10); i++) { 736 dp2 = dp; 737 dp = mn_alloc_desc(); 738 m = NULL; 739 MGETHDR(m, M_TRYWAIT, MT_DATA); 740 if (m == NULL) { 741 mn_free_desc(dp); 742 m_freem(m); 743 return (ENOBUFS); 744 } 745 MCLGET(m, M_TRYWAIT); 746 if ((m->m_flags & M_EXT) == 0) { 747 mn_free_desc(dp); 748 m_freem(m); 749 return (ENOBUFS); 750 } 751 dp->m = m; 752 dp->data = vtophys(m->m_data); 753 dp->flags = 0x00000000; 754 dp->flags += 1600 << 16; 755 dp->next = vtophys(dp2); 756 dp->vnext = dp2; 757 } 758 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 759 sc->ch[chan]->r1 = dp; 760 761 /* Initialize this channel */ 762 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 763 sc->m32x->cmd = 0x1; 764 DELAY(1000); 765 u = sc->m32x->stat; 766 if (!(u & 1)) 767 printf("%s: init chan %d stat %08x\n", sc->name, chan, u); 768 sc->m32x->stat = 1; 769 /* probably not at splnet, force outward queueing */ 770 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook)); 771 772 return (0); 773 } 774 775 /* 776 * CLOSE 777 */ 778 static int 779 ngmn_disconnect(hook_p hook) 780 { 781 int chan, i; 782 struct mn_softc *sc; 783 struct schan *sch; 784 struct trxd *dp, *dp2; 785 u_int32_t u; 786 787 sch = NG_HOOK_PRIVATE(hook); 788 chan = sch->chan; 789 sc = sch->sc; 790 791 if (sch->state == DOWN) 792 return (0); 793 sch->state = DOWN; 794 795 /* Set receiver & transmitter off */ 796 sc->m32_mem.cs[chan].flags = 0x80920006; 797 sc->m32_mem.cs[chan].itbs = 0; 798 799 /* free the timeslots */ 800 for (i = 0; i < 32; i++) 801 if (sc->ch[chan]->ts & (1 << i)) 802 sc->m32_mem.ts[i] = 0x20002000; 803 804 /* Initialize this channel */ 805 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 806 sc->m32x->cmd = 0x1; 807 DELAY(30); 808 u = sc->m32x->stat; 809 if (!(u & 1)) 810 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 811 sc->m32x->stat = 1; 812 813 /* Free all receive descriptors and mbufs */ 814 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 815 if (dp->m) 816 m_freem(dp->m); 817 sc->ch[chan]->r1 = dp2 = dp->vnext; 818 mn_free_desc(dp); 819 } 820 821 /* Free all transmit descriptors and mbufs */ 822 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 823 if (dp->m) { 824 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len; 825 m_freem(dp->m); 826 } 827 sc->ch[chan]->x1 = dp2 = dp->vnext; 828 mn_free_desc(dp); 829 } 830 sc->nhooks--; 831 return(0); 832 } 833 834 /* 835 * Create a new channel. 836 */ 837 static void 838 mn_create_channel(struct mn_softc *sc, int chan) 839 { 840 struct schan *sch; 841 842 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan], 843 M_MN, M_WAITOK | M_ZERO); 844 sch->sc = sc; 845 sch->state = DOWN; 846 sch->chan = chan; 847 sprintf(sch->name, "%s%d", sc->name, chan); 848 return; 849 } 850 851 #ifdef notyet 852 /* 853 * Dump Munich32x state 854 */ 855 static void 856 m32_dump(struct mn_softc *sc) 857 { 858 u_int32_t *tp4; 859 int i, j; 860 861 printf("mn%d: MUNICH32X dump\n", sc->unit); 862 tp4 = (u_int32_t *)sc->m0v; 863 for(j = 0; j < 64; j += 8) { 864 printf("%02x", j * sizeof *tp4); 865 for(i = 0; i < 8; i++) 866 printf(" %08x", tp4[i+j]); 867 printf("\n"); 868 } 869 for(j = 0; j < M32_CHAN; j++) { 870 if (!sc->ch[j]) 871 continue; 872 printf("CH%d: state %d ts %08x", 873 j, sc->ch[j]->state, sc->ch[j]->ts); 874 printf(" %08x %08x %08x %08x %08x %08x\n", 875 sc->m32_mem.cs[j].flags, 876 sc->m32_mem.cs[j].rdesc, 877 sc->m32_mem.cs[j].tdesc, 878 sc->m32_mem.cs[j].itbs, 879 sc->m32_mem.crxd[j], 880 sc->m32_mem.ctxd[j] ); 881 } 882 } 883 884 /* 885 * Dump Falch54 state 886 */ 887 static void 888 f54_dump(struct mn_softc *sc) 889 { 890 u_int8_t *tp1; 891 int i, j; 892 893 printf("%s: FALC54 dump\n", sc->name); 894 tp1 = (u_int8_t *)sc->m1v; 895 for(j = 0; j < 128; j += 16) { 896 printf("%s: %02x |", sc->name, j * sizeof *tp1); 897 for(i = 0; i < 16; i++) 898 printf(" %02x", tp1[i+j]); 899 printf("\n"); 900 } 901 } 902 #endif /* notyet */ 903 904 /* 905 * Init Munich32x 906 */ 907 static void 908 m32_init(struct mn_softc *sc) 909 { 910 911 sc->m32x->conf = 0x00000000; 912 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 913 #if 1 914 sc->m32x->mode2 = 0x00000081; 915 sc->m32x->txpoll = 0xffffffff; 916 #elif 1 917 sc->m32x->mode2 = 0x00000081; 918 sc->m32x->txpoll = 0xffffffff; 919 #else 920 sc->m32x->mode2 = 0x00000101; 921 #endif 922 sc->m32x->lconf = 0x6060009B; 923 sc->m32x->imask = 0x00000000; 924 } 925 926 /* 927 * Init the Falc54 928 */ 929 static void 930 f54_init(struct mn_softc *sc) 931 { 932 sc->f54w->ipc = 0x07; 933 934 sc->f54w->xpm0 = 0xbd; 935 sc->f54w->xpm1 = 0x03; 936 sc->f54w->xpm2 = 0x00; 937 938 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 939 sc->f54w->imr1 = 0x08; /* XMB */ 940 sc->f54w->imr2 = 0x00; 941 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 942 sc->f54w->imr4 = 0x00; 943 944 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 945 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 946 if (sc->framing == E1) 947 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 948 else if (sc->framing == E1U) 949 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */ 950 951 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 952 sc->f54w->pcd = 0x0a; 953 sc->f54w->pcr = 0x15; 954 sc->f54w->xsw = 0x9f; /* fmr4 */ 955 if (sc->framing == E1) 956 sc->f54w->xsp = 0x1c; /* fmr5 */ 957 else if (sc->framing == E1U) 958 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */ 959 sc->f54w->xc0 = 0x07; 960 sc->f54w->xc1 = 0x3d; 961 sc->f54w->rc0 = 0x05; 962 sc->f54w->rc1 = 0x00; 963 sc->f54w->cmdr = 0x51; 964 } 965 966 static int 967 mn_reset(struct mn_softc *sc) 968 { 969 u_int32_t u; 970 int i; 971 972 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 973 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 974 975 bzero(sc->tiqb, sizeof sc->tiqb); 976 sc->m32x->tiqba = vtophys(&sc->tiqb); 977 sc->m32x->tiql = NIQB / 16 - 1; 978 979 bzero(sc->riqb, sizeof sc->riqb); 980 sc->m32x->riqba = vtophys(&sc->riqb); 981 sc->m32x->riql = NIQB / 16 - 1; 982 983 bzero(sc->ltiqb, sizeof sc->ltiqb); 984 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 985 sc->m32x->ltiql = NIQB / 16 - 1; 986 987 bzero(sc->lriqb, sizeof sc->lriqb); 988 sc->m32x->lriqba = vtophys(&sc->lriqb); 989 sc->m32x->lriql = NIQB / 16 - 1; 990 991 bzero(sc->piqb, sizeof sc->piqb); 992 sc->m32x->piqba = vtophys(&sc->piqb); 993 sc->m32x->piql = NIQB / 16 - 1; 994 995 m32_init(sc); 996 f54_init(sc); 997 998 u = sc->m32x->stat; 999 sc->m32x->stat = u; 1000 sc->m32_mem.ccb = 0x4; 1001 sc->m32x->cmd = 0x1; 1002 DELAY(1000); 1003 u = sc->m32x->stat; 1004 sc->m32x->stat = u; 1005 1006 /* set all timeslots to known state */ 1007 for (i = 0; i < 32; i++) 1008 sc->m32_mem.ts[i] = 0x20002000; 1009 1010 if (!(u & 1)) { 1011 printf( 1012 "mn%d: WARNING: Controller failed the PCI bus-master test.\n" 1013 "mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 1014 sc->unit, sc->unit); 1015 return (0); 1016 } 1017 return (1); 1018 } 1019 1020 /* 1021 * FALC54 interrupt handling 1022 */ 1023 static void 1024 f54_intr(struct mn_softc *sc) 1025 { 1026 unsigned g, u, s; 1027 1028 g = sc->f54r->gis; 1029 u = sc->f54r->isr0 << 24; 1030 u |= sc->f54r->isr1 << 16; 1031 u |= sc->f54r->isr2 << 8; 1032 u |= sc->f54r->isr3; 1033 sc->falc_irq = u; 1034 /* don't chat about the 1 sec heart beat */ 1035 if (u & ~0x40) { 1036 #if 0 1037 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\2" 1038 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 1039 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 1040 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 1041 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 1042 #endif 1043 s = sc->f54r->frs0 << 24; 1044 s |= sc->f54r->frs1 << 16; 1045 s |= sc->f54r->rsw << 8; 1046 s |= sc->f54r->rsp; 1047 sc->falc_state = s; 1048 1049 s &= ~0x01844038; /* undefined or static bits */ 1050 s &= ~0x00009fc7; /* bits we don't care about */ 1051 s &= ~0x00780000; /* XXX: TS16 related */ 1052 s &= ~0x06000000; /* XXX: Multiframe related */ 1053 #if 0 1054 printf("%s*: FALC54 Status %b\n", sc->name, s, "\2" 1055 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 1056 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 1057 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 1058 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 1059 #endif 1060 if (s != sc->framer_state) { 1061 #if 0 1062 for (i = 0; i < M32_CHAN; i++) { 1063 if (!sc->ch[i]) 1064 continue; 1065 sp = &sc->ch[i]->ifsppp; 1066 if (!(sp->pp_if.if_flags & IFF_UP)) 1067 continue; 1068 if (s) 1069 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 1070 else 1071 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 1072 } 1073 #endif 1074 sc->framer_state = s; 1075 } 1076 } 1077 /* Once per second check error counters */ 1078 /* XXX: not clear if this is actually ok */ 1079 if (!(u & 0x40)) 1080 return; 1081 sc->cnt_fec += sc->f54r->fec; 1082 sc->cnt_cvc += sc->f54r->cvc; 1083 sc->cnt_cec1 += sc->f54r->cec1; 1084 sc->cnt_ebc += sc->f54r->ebc; 1085 sc->cnt_cec2 += sc->f54r->cec2; 1086 sc->cnt_cec3 += sc->f54r->cec3; 1087 sc->cnt_rbc += sc->f54r->rbc; 1088 } 1089 1090 /* 1091 * Transmit interrupt for one channel 1092 */ 1093 static void 1094 mn_tx_intr(struct mn_softc *sc, u_int32_t vector) 1095 { 1096 u_int32_t chan; 1097 struct trxd *dp; 1098 struct mbuf *m; 1099 1100 chan = vector & 0x1f; 1101 if (!sc->ch[chan]) 1102 return; 1103 if (sc->ch[chan]->state != UP) { 1104 printf("%s: tx_intr when not UP\n", sc->name); 1105 return; 1106 } 1107 for (;;) { 1108 dp = sc->ch[chan]->x1; 1109 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 1110 return; 1111 m = dp->m; 1112 if (m) { 1113 #if 0 1114 printf("%d = %d - %d (%p)\n", 1115 sc->ch[chan]->tx_pending - m->m_pkthdr.len, 1116 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m); 1117 #endif 1118 sc->ch[chan]->tx_pending -= m->m_pkthdr.len; 1119 m_freem(m); 1120 } 1121 sc->ch[chan]->last_xmit = time_second; 1122 sc->ch[chan]->x1 = dp->vnext; 1123 mn_free_desc(dp); 1124 } 1125 } 1126 1127 /* 1128 * Receive interrupt for one channel 1129 */ 1130 static void 1131 mn_rx_intr(struct mn_softc *sc, u_int32_t vector) 1132 { 1133 u_int32_t chan, err; 1134 struct trxd *dp; 1135 struct mbuf *m; 1136 struct schan *sch; 1137 1138 chan = vector & 0x1f; 1139 if (!sc->ch[chan]) 1140 return; 1141 sch = sc->ch[chan]; 1142 if (sch->state != UP) { 1143 printf("%s: rx_intr when not UP\n", sc->name); 1144 return; 1145 } 1146 vector &= ~0x1f; 1147 if (vector == 0x30000b00) 1148 sch->rx_error++; 1149 for (;;) { 1150 dp = sch->r1; 1151 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1152 return; 1153 m = dp->m; 1154 dp->m = 0; 1155 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1156 err = (dp->status >> 8) & 0xff; 1157 if (!err) { 1158 int error; 1159 NG_SEND_DATA_ONLY(error, sch->hook, m); 1160 sch->last_recv = time_second; 1161 /* we could be down by now... */ 1162 if (sch->state != UP) 1163 return; 1164 } else if (err & 0x40) { 1165 sch->short_error++; 1166 } else if (err & 0x10) { 1167 sch->crc_error++; 1168 } else if (err & 0x08) { 1169 sch->dribble_error++; 1170 } else if (err & 0x04) { 1171 sch->long_error++; 1172 } else if (err & 0x02) { 1173 sch->abort_error++; 1174 } else if (err & 0x01) { 1175 sch->overflow_error++; 1176 } 1177 if (err) { 1178 sch->last_rxerr = time_second; 1179 sch->prev_error = sch->last_error; 1180 sch->last_error = err; 1181 } 1182 1183 sc->ch[chan]->r1 = dp->vnext; 1184 1185 /* Replenish desc + mbuf supplies */ 1186 if (!m) { 1187 MGETHDR(m, M_DONTWAIT, MT_DATA); 1188 if (m == NULL) { 1189 mn_free_desc(dp); 1190 return; /* ENOBUFS */ 1191 } 1192 MCLGET(m, M_DONTWAIT); 1193 if((m->m_flags & M_EXT) == 0) { 1194 mn_free_desc(dp); 1195 m_freem(m); 1196 return; /* ENOBUFS */ 1197 } 1198 } 1199 dp->m = m; 1200 dp->data = vtophys(m->m_data); 1201 dp->flags = 0x40000000; 1202 dp->flags += 1600 << 16; 1203 dp->next = vtophys(dp); 1204 dp->vnext = 0; 1205 sc->ch[chan]->rl->next = vtophys(dp); 1206 sc->ch[chan]->rl->vnext = dp; 1207 sc->ch[chan]->rl->flags &= ~0x40000000; 1208 sc->ch[chan]->rl = dp; 1209 } 1210 } 1211 1212 1213 /* 1214 * Interupt handler 1215 */ 1216 1217 static void 1218 mn_intr(void *xsc) 1219 { 1220 struct mn_softc *sc; 1221 u_int32_t stat, lstat, u; 1222 int i, j; 1223 1224 sc = xsc; 1225 stat = sc->m32x->stat; 1226 lstat = sc->m32x->lstat; 1227 #if 0 1228 if (!stat && !(lstat & 2)) 1229 return; 1230 #endif 1231 1232 if (stat & ~0xc200) { 1233 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1234 } 1235 1236 if ((stat & 0x200) || (lstat & 2)) 1237 f54_intr(sc); 1238 1239 for (j = i = 0; i < 64; i ++) { 1240 u = sc->riqb[i]; 1241 if (u) { 1242 sc->riqb[i] = 0; 1243 mn_rx_intr(sc, u); 1244 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1245 continue; 1246 u &= ~0x30000400; /* bits we don't care about */ 1247 if ((u & ~0x1f) == 0x00000900) 1248 continue; 1249 if (!(u & ~0x1f)) 1250 continue; 1251 if (!j) 1252 printf("%s*: RIQB:", sc->name); 1253 printf(" [%d]=%08x", i, u); 1254 j++; 1255 } 1256 } 1257 if (j) 1258 printf("\n"); 1259 1260 for (j = i = 0; i < 64; i ++) { 1261 u = sc->tiqb[i]; 1262 if (u) { 1263 sc->tiqb[i] = 0; 1264 mn_tx_intr(sc, u); 1265 if ((u & ~0x1f) == 0x20000800) 1266 continue; 1267 u &= ~0x20000000; /* bits we don't care about */ 1268 if (!u) 1269 continue; 1270 if (!j) 1271 printf("%s*: TIQB:", sc->name); 1272 printf(" [%d]=%08x", i, u); 1273 j++; 1274 } 1275 } 1276 if (j) 1277 printf("\n"); 1278 sc->m32x->stat = stat; 1279 } 1280 1281 static void 1282 mn_timeout(void *xsc) 1283 { 1284 static int round = 0; 1285 struct mn_softc *sc; 1286 1287 mn_intr(xsc); 1288 sc = xsc; 1289 timeout(mn_timeout, xsc, 10 * hz); 1290 round++; 1291 if (round == 2) { 1292 sc->m32_mem.ccb = 0x00008004; 1293 sc->m32x->cmd = 0x1; 1294 } else if (round > 2) { 1295 printf("%s: timeout\n", sc->name); 1296 } 1297 } 1298 1299 /* 1300 * PCI initialization stuff 1301 */ 1302 1303 static int 1304 mn_probe (device_t self) 1305 { 1306 u_int id = pci_get_devid(self); 1307 1308 if (sizeof (struct m32xreg) != 256) { 1309 printf("MN: sizeof(struct m32xreg) = %zd, should have been 256\n", sizeof (struct m32xreg)); 1310 return (ENXIO); 1311 } 1312 if (sizeof (struct f54rreg) != 128) { 1313 printf("MN: sizeof(struct f54rreg) = %zd, should have been 128\n", sizeof (struct f54rreg)); 1314 return (ENXIO); 1315 } 1316 if (sizeof (struct f54wreg) != 128) { 1317 printf("MN: sizeof(struct f54wreg) = %zd, should have been 128\n", sizeof (struct f54wreg)); 1318 return (ENXIO); 1319 } 1320 1321 if (id != 0x2101110a) 1322 return (ENXIO); 1323 1324 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller"); 1325 return (0); 1326 } 1327 1328 static int 1329 mn_attach (device_t self) 1330 { 1331 struct mn_softc *sc; 1332 u_int32_t u; 1333 u_int32_t ver; 1334 static int once; 1335 int rid, error; 1336 struct resource *res; 1337 1338 if (!once) { 1339 if (ng_newtype(&mntypestruct)) 1340 printf("ng_newtype failed\n"); 1341 once++; 1342 } 1343 1344 sc = (struct mn_softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO); 1345 device_set_softc(self, sc); 1346 1347 sc->dev = self; 1348 sc->unit = device_get_unit(self); 1349 sc->framing = E1; 1350 sprintf(sc->name, "mn%d", sc->unit); 1351 1352 rid = PCIR_BAR(0); 1353 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1354 0, ~0, 1, RF_ACTIVE); 1355 if (res == NULL) { 1356 device_printf(self, "Could not map memory\n"); 1357 free(sc, M_MN); 1358 return ENXIO; 1359 } 1360 sc->m0v = rman_get_virtual(res); 1361 sc->m0p = rman_get_start(res); 1362 1363 rid = PCIR_BAR(1); 1364 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1365 0, ~0, 1, RF_ACTIVE); 1366 if (res == NULL) { 1367 device_printf(self, "Could not map memory\n"); 1368 free(sc, M_MN); 1369 return ENXIO; 1370 } 1371 sc->m1v = rman_get_virtual(res); 1372 sc->m1p = rman_get_start(res); 1373 1374 /* Allocate interrupt */ 1375 rid = 0; 1376 sc->irq = bus_alloc_resource(self, SYS_RES_IRQ, &rid, 0, ~0, 1377 1, RF_SHAREABLE | RF_ACTIVE); 1378 1379 if (sc->irq == NULL) { 1380 printf("couldn't map interrupt\n"); 1381 free(sc, M_MN); 1382 return(ENXIO); 1383 } 1384 1385 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, mn_intr, sc, &sc->intrhand); 1386 1387 if (error) { 1388 printf("couldn't set up irq\n"); 1389 free(sc, M_MN); 1390 return(ENXIO); 1391 } 1392 1393 u = pci_read_config(self, PCIR_COMMAND, 1); 1394 printf("%x\n", u); 1395 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1); 1396 #if 0 1397 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4); 1398 #endif 1399 u = pci_read_config(self, PCIR_COMMAND, 1); 1400 printf("%x\n", u); 1401 1402 ver = pci_get_revid(self); 1403 1404 sc->m32x = (struct m32xreg *) sc->m0v; 1405 sc->f54w = (struct f54wreg *) sc->m1v; 1406 sc->f54r = (struct f54rreg *) sc->m1v; 1407 1408 /* We must reset before poking at FALC54 registers */ 1409 u = mn_reset(sc); 1410 if (!u) 1411 return (0); 1412 1413 printf("mn%d: Munich32X", sc->unit); 1414 switch (ver) { 1415 case 0x13: 1416 printf(" Rev 2.2"); 1417 break; 1418 default: 1419 printf(" Rev 0x%x\n", ver); 1420 } 1421 printf(", Falc54"); 1422 switch (sc->f54r->vstr) { 1423 case 0: 1424 printf(" Rev < 1.3\n"); 1425 break; 1426 case 1: 1427 printf(" Rev 1.3\n"); 1428 break; 1429 case 2: 1430 printf(" Rev 1.4\n"); 1431 break; 1432 case 0x10: 1433 printf("-LH Rev 1.1\n"); 1434 break; 1435 case 0x13: 1436 printf("-LH Rev 1.3\n"); 1437 break; 1438 default: 1439 printf(" Rev 0x%x\n", sc->f54r->vstr); 1440 } 1441 1442 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1443 printf("ng_make_node_common failed\n"); 1444 return (0); 1445 } 1446 NG_NODE_SET_PRIVATE(sc->node, sc); 1447 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1448 if (ng_name_node(sc->node, sc->nodename)) { 1449 NG_NODE_UNREF(sc->node); 1450 return (0); 1451 } 1452 1453 return (0); 1454 } 1455 1456 1457 static device_method_t mn_methods[] = { 1458 /* Device interface */ 1459 DEVMETHOD(device_probe, mn_probe), 1460 DEVMETHOD(device_attach, mn_attach), 1461 DEVMETHOD(device_suspend, bus_generic_suspend), 1462 DEVMETHOD(device_resume, bus_generic_resume), 1463 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1464 1465 {0, 0} 1466 }; 1467 1468 static driver_t mn_driver = { 1469 "mn", 1470 mn_methods, 1471 0 1472 }; 1473 1474 static devclass_t mn_devclass; 1475 1476 DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0);
Cache object: 8e9ef30427f7ca7dd1aaa45569d71008
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