The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_mx.c

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    1 /*
    2  * Copyright (c) 1997, 1998
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD$
   33  */
   34 
   35 /*
   36  * Macronix PMAC fast ethernet PCI NIC driver
   37  *
   38  * Written by Bill Paul <wpaul@ctr.columbia.edu>
   39  * Electrical Engineering Department
   40  * Columbia University, New York City
   41  */
   42 
   43 /*
   44  * The Macronix 98713, 98715 and 98725 chips are still more tulip clones.
   45  * The 98713 has an internal transceiver and an MII bus for external PHYs.
   46  * The other two chips have only the internal transceiver. All have
   47  * support for built-in autonegotiation. Additionally, there are 98713A
   48  * and 98715A chips which support power management. The 98725 chip
   49  * supports power management as well.
   50  *
   51  * Datasheets for the Macronix parts can be obtained from www.macronix.com.
   52  * Note however that the datasheets do not describe the TX and RX
   53  * descriptor structures or the setup frame format(s). For this, you should
   54  * obtain a DEC 21x4x datasheet from developer.intel.com. The Macronix
   55  * chips look to be fairly straightforward tulip clones, except for
   56  * the NWAY support.
   57  */
   58 
   59 #include "bpfilter.h"
   60 
   61 #include <sys/param.h>
   62 #include <sys/systm.h>
   63 #include <sys/sockio.h>
   64 #include <sys/mbuf.h>
   65 #include <sys/malloc.h>
   66 #include <sys/kernel.h>
   67 #include <sys/socket.h>
   68 
   69 #include <net/if.h>
   70 #include <net/if_arp.h>
   71 #include <net/ethernet.h>
   72 #include <net/if_dl.h>
   73 #include <net/if_media.h>
   74 
   75 #if NBPFILTER > 0
   76 #include <net/bpf.h>
   77 #endif
   78 
   79 #include <vm/vm.h>              /* for vtophys */
   80 #include <vm/pmap.h>            /* for vtophys */
   81 #include <machine/clock.h>      /* for DELAY */
   82 #include <machine/bus_pio.h>
   83 #include <machine/bus_memio.h>
   84 #include <machine/bus.h>
   85 
   86 #include <pci/pcireg.h>
   87 #include <pci/pcivar.h>
   88 
   89 #define MX_USEIOSPACE
   90 
   91 /* #define MX_BACKGROUND_AUTONEG */
   92 
   93 #include <pci/if_mxreg.h>
   94 
   95 #ifndef lint
   96 static const char rcsid[] =
   97   "$FreeBSD$";
   98 #endif
   99 
  100 /*
  101  * Various supported device vendors/types and their names.
  102  */
  103 static struct mx_type mx_devs[] = {
  104         { MX_VENDORID, MX_DEVICEID_98713,
  105                 "Macronix 98713 10/100BaseTX" },
  106         { MX_VENDORID, MX_DEVICEID_98713,
  107                 "Macronix 98713A 10/100BaseTX" },
  108         { CP_VENDORID, CP_DEVICEID_98713,
  109                 "Compex RL100-TX 10/100BaseTX" },
  110         { CP_VENDORID, CP_DEVICEID_98713,
  111                 "Compex RL100-TX 10/100BaseTX" },
  112         { MX_VENDORID, MX_DEVICEID_987x5,
  113                 "Macronix 98715/98715A 10/100BaseTX" },
  114         { MX_VENDORID, MX_DEVICEID_987x5,
  115                 "Macronix 98725 10/100BaseTX" },
  116         { PN_VENDORID, PN_DEVICEID_PNIC_II,
  117                 "LC82C115 PNIC II 10/100BaseTX" },
  118         { 0, 0, NULL }
  119 };
  120 
  121 /*
  122  * Various supported PHY vendors/types and their names. Note that
  123  * this driver will work with pretty much any MII-compliant PHY,
  124  * so failure to positively identify the chip is not a fatal error.
  125  */
  126 
  127 static struct mx_type mx_phys[] = {
  128         { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
  129         { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
  130         { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
  131         { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 
  132         { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
  133         { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
  134         { 0, 0, "<MII-compliant physical interface>" }
  135 };
  136 
  137 static unsigned long mx_count = 0;
  138 static const char *mx_probe     __P((pcici_t, pcidi_t));
  139 static void mx_attach           __P((pcici_t, int));
  140 static struct mx_type *mx_devtype       __P((pcici_t, pcidi_t));
  141 static int mx_newbuf            __P((struct mx_softc *,
  142                                                 struct mx_chain_onefrag *));
  143 static int mx_encap             __P((struct mx_softc *, struct mx_chain *,
  144                                                 struct mbuf *));
  145 
  146 static void mx_rxeof            __P((struct mx_softc *));
  147 static void mx_rxeoc            __P((struct mx_softc *));
  148 static void mx_txeof            __P((struct mx_softc *));
  149 static void mx_txeoc            __P((struct mx_softc *));
  150 static void mx_intr             __P((void *));
  151 static void mx_start            __P((struct ifnet *));
  152 static int mx_ioctl             __P((struct ifnet *, u_long, caddr_t));
  153 static void mx_init             __P((void *));
  154 static void mx_stop             __P((struct mx_softc *));
  155 static void mx_watchdog         __P((struct ifnet *));
  156 static void mx_shutdown         __P((int, void *));
  157 static int mx_ifmedia_upd       __P((struct ifnet *));
  158 static void mx_ifmedia_sts      __P((struct ifnet *, struct ifmediareq *));
  159 
  160 static void mx_delay            __P((struct mx_softc *));
  161 static void mx_eeprom_idle      __P((struct mx_softc *));
  162 static void mx_eeprom_putbyte   __P((struct mx_softc *, int));
  163 static void mx_eeprom_getword   __P((struct mx_softc *, int, u_int16_t *));
  164 static void mx_read_eeprom      __P((struct mx_softc *, caddr_t, int,
  165                                                         int, int));
  166 
  167 static void mx_mii_writebit     __P((struct mx_softc *, int));
  168 static int mx_mii_readbit       __P((struct mx_softc *));
  169 static void mx_mii_sync         __P((struct mx_softc *));
  170 static void mx_mii_send         __P((struct mx_softc *, u_int32_t, int));
  171 static int mx_mii_readreg       __P((struct mx_softc *, struct mx_mii_frame *));
  172 static int mx_mii_writereg      __P((struct mx_softc *, struct mx_mii_frame *));
  173 static u_int16_t mx_phy_readreg __P((struct mx_softc *, int));
  174 static void mx_phy_writereg     __P((struct mx_softc *, int, int));
  175 
  176 static void mx_autoneg_xmit     __P((struct mx_softc *));
  177 static void mx_autoneg_mii      __P((struct mx_softc *, int, int));
  178 static void mx_autoneg          __P((struct mx_softc *, int, int));
  179 static void mx_setmode_mii      __P((struct mx_softc *, int));
  180 static void mx_setmode          __P((struct mx_softc *, int, int));
  181 static void mx_getmode_mii      __P((struct mx_softc *));
  182 static void mx_setcfg           __P((struct mx_softc *, int));
  183 static u_int32_t mx_calchash    __P((struct mx_softc *, caddr_t));
  184 static void mx_setfilt          __P((struct mx_softc *));
  185 static void mx_reset            __P((struct mx_softc *));
  186 static int mx_list_rx_init      __P((struct mx_softc *));
  187 static int mx_list_tx_init      __P((struct mx_softc *));
  188 
  189 #define MX_SETBIT(sc, reg, x)                           \
  190         CSR_WRITE_4(sc, reg,                            \
  191                 CSR_READ_4(sc, reg) | x)
  192 
  193 #define MX_CLRBIT(sc, reg, x)                           \
  194         CSR_WRITE_4(sc, reg,                            \
  195                 CSR_READ_4(sc, reg) & ~x)
  196 
  197 #define SIO_SET(x)                                      \
  198         CSR_WRITE_4(sc, MX_SIO,                         \
  199                 CSR_READ_4(sc, MX_SIO) | x)
  200 
  201 #define SIO_CLR(x)                                      \
  202         CSR_WRITE_4(sc, MX_SIO,                         \
  203                 CSR_READ_4(sc, MX_SIO) & ~x)
  204 
  205 static void mx_delay(sc)
  206         struct mx_softc         *sc;
  207 {
  208         int                     idx;
  209 
  210         for (idx = (300 / 33) + 1; idx > 0; idx--)
  211                 CSR_READ_4(sc, MX_BUSCTL);
  212 }
  213 
  214 static void mx_eeprom_idle(sc)
  215         struct mx_softc         *sc;
  216 {
  217         register int            i;
  218 
  219         CSR_WRITE_4(sc, MX_SIO, MX_SIO_EESEL);
  220         mx_delay(sc);
  221         MX_SETBIT(sc, MX_SIO,  MX_SIO_ROMCTL_READ);
  222         mx_delay(sc);
  223         MX_SETBIT(sc, MX_SIO, MX_SIO_EE_CS);
  224         mx_delay(sc);
  225         MX_SETBIT(sc, MX_SIO, MX_SIO_EE_CLK);
  226         mx_delay(sc);
  227 
  228         for (i = 0; i < 25; i++) {
  229                 MX_CLRBIT(sc, MX_SIO, MX_SIO_EE_CLK);
  230                 mx_delay(sc);
  231                 MX_SETBIT(sc, MX_SIO, MX_SIO_EE_CLK);
  232                 mx_delay(sc);
  233         }
  234 
  235         MX_CLRBIT(sc, MX_SIO, MX_SIO_EE_CLK);
  236         mx_delay(sc);
  237         MX_CLRBIT(sc, MX_SIO, MX_SIO_EE_CS);
  238         mx_delay(sc);
  239         CSR_WRITE_4(sc, MX_SIO, 0x00000000);
  240 
  241         return;
  242 }
  243 
  244 /*
  245  * Send a read command and address to the EEPROM, check for ACK.
  246  */
  247 static void mx_eeprom_putbyte(sc, addr)
  248         struct mx_softc         *sc;
  249         int                     addr;
  250 {
  251         register int            d, i;
  252 
  253         d = addr | MX_EECMD_READ;
  254 
  255         /*
  256          * Feed in each bit and stobe the clock.
  257          */
  258         for (i = 0x400; i; i >>= 1) {
  259                 if (d & i) {
  260                         SIO_SET(MX_SIO_EE_DATAIN);
  261                 } else {
  262                         SIO_CLR(MX_SIO_EE_DATAIN);
  263                 }
  264                 mx_delay(sc);
  265                 SIO_SET(MX_SIO_EE_CLK);
  266                 mx_delay(sc);
  267                 SIO_CLR(MX_SIO_EE_CLK);
  268                 mx_delay(sc);
  269         }
  270 
  271         return;
  272 }
  273 
  274 /*
  275  * Read a word of data stored in the EEPROM at address 'addr.'
  276  */
  277 static void mx_eeprom_getword(sc, addr, dest)
  278         struct mx_softc         *sc;
  279         int                     addr;
  280         u_int16_t               *dest;
  281 {
  282         register int            i;
  283         u_int16_t               word = 0;
  284 
  285         /* Force EEPROM to idle state. */
  286         mx_eeprom_idle(sc);
  287 
  288         /* Enter EEPROM access mode. */
  289         CSR_WRITE_4(sc, MX_SIO, MX_SIO_EESEL);
  290         mx_delay(sc);
  291         MX_SETBIT(sc, MX_SIO,  MX_SIO_ROMCTL_READ);
  292         mx_delay(sc);
  293         MX_SETBIT(sc, MX_SIO, MX_SIO_EE_CS);
  294         mx_delay(sc);
  295         MX_SETBIT(sc, MX_SIO, MX_SIO_EE_CLK);
  296         mx_delay(sc);
  297 
  298         /*
  299          * Send address of word we want to read.
  300          */
  301         mx_eeprom_putbyte(sc, addr);
  302 
  303         /*
  304          * Start reading bits from EEPROM.
  305          */
  306         for (i = 0x8000; i; i >>= 1) {
  307                 SIO_SET(MX_SIO_EE_CLK);
  308                 mx_delay(sc);
  309                 if (CSR_READ_4(sc, MX_SIO) & MX_SIO_EE_DATAOUT)
  310                         word |= i;
  311                 mx_delay(sc);
  312                 SIO_CLR(MX_SIO_EE_CLK);
  313                 mx_delay(sc);
  314         }
  315 
  316         /* Turn off EEPROM access mode. */
  317         mx_eeprom_idle(sc);
  318 
  319         *dest = word;
  320 
  321         return;
  322 }
  323 
  324 /*
  325  * Read a sequence of words from the EEPROM.
  326  */
  327 static void mx_read_eeprom(sc, dest, off, cnt, swap)
  328         struct mx_softc         *sc;
  329         caddr_t                 dest;
  330         int                     off;
  331         int                     cnt;
  332         int                     swap;
  333 {
  334         int                     i;
  335         u_int16_t               word = 0, *ptr;
  336 
  337         for (i = 0; i < cnt; i++) {
  338                 mx_eeprom_getword(sc, off + i, &word);
  339                 ptr = (u_int16_t *)(dest + (i * 2));
  340                 if (swap)
  341                         *ptr = ntohs(word);
  342                 else
  343                         *ptr = word;
  344         }
  345 
  346         return;
  347 }
  348 
  349 /*
  350  * The following two routines are taken from the Macronix 98713
  351  * Application Notes pp.19-21.
  352  */
  353 /*
  354  * Write a bit to the MII bus.
  355  */
  356 static void mx_mii_writebit(sc, bit)
  357         struct mx_softc         *sc;
  358         int                     bit;
  359 {
  360         if (bit)
  361                 CSR_WRITE_4(sc, MX_SIO, MX_SIO_ROMCTL_WRITE|MX_SIO_MII_DATAOUT);
  362         else
  363                 CSR_WRITE_4(sc, MX_SIO, MX_SIO_ROMCTL_WRITE);
  364 
  365         MX_SETBIT(sc, MX_SIO, MX_SIO_MII_CLK);
  366         MX_CLRBIT(sc, MX_SIO, MX_SIO_MII_CLK);
  367 
  368         return;
  369 }
  370 
  371 /*
  372  * Read a bit from the MII bus.
  373  */
  374 static int mx_mii_readbit(sc)
  375         struct mx_softc         *sc;
  376 {
  377         CSR_WRITE_4(sc, MX_SIO, MX_SIO_ROMCTL_READ|MX_SIO_MII_DIR);
  378         CSR_READ_4(sc, MX_SIO);
  379         MX_SETBIT(sc, MX_SIO, MX_SIO_MII_CLK);
  380         MX_CLRBIT(sc, MX_SIO, MX_SIO_MII_CLK);
  381         if (CSR_READ_4(sc, MX_SIO) & MX_SIO_MII_DATAIN)
  382                 return(1);
  383 
  384         return(0);
  385 }
  386 
  387 /*
  388  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  389  */
  390 static void mx_mii_sync(sc)
  391         struct mx_softc         *sc;
  392 {
  393         register int            i;
  394 
  395         CSR_WRITE_4(sc, MX_SIO, MX_SIO_ROMCTL_WRITE);
  396 
  397         for (i = 0; i < 32; i++)
  398                 mx_mii_writebit(sc, 1);
  399 
  400         return;
  401 }
  402 
  403 /*
  404  * Clock a series of bits through the MII.
  405  */
  406 static void mx_mii_send(sc, bits, cnt)
  407         struct mx_softc         *sc;
  408         u_int32_t               bits;
  409         int                     cnt;
  410 {
  411         int                     i;
  412 
  413         for (i = (0x1 << (cnt - 1)); i; i >>= 1)
  414                 mx_mii_writebit(sc, bits & i);
  415 }
  416 
  417 /*
  418  * Read an PHY register through the MII.
  419  */
  420 static int mx_mii_readreg(sc, frame)
  421         struct mx_softc         *sc;
  422         struct mx_mii_frame     *frame;
  423         
  424 {
  425         int                     i, ack, s;
  426 
  427         s = splimp();
  428 
  429         /*
  430          * Set up frame for RX.
  431          */
  432         frame->mii_stdelim = MX_MII_STARTDELIM;
  433         frame->mii_opcode = MX_MII_READOP;
  434         frame->mii_turnaround = 0;
  435         frame->mii_data = 0;
  436         
  437         /*
  438          * Sync the PHYs.
  439          */
  440         mx_mii_sync(sc);
  441 
  442         /*
  443          * Send command/address info.
  444          */
  445         mx_mii_send(sc, frame->mii_stdelim, 2);
  446         mx_mii_send(sc, frame->mii_opcode, 2);
  447         mx_mii_send(sc, frame->mii_phyaddr, 5);
  448         mx_mii_send(sc, frame->mii_regaddr, 5);
  449 
  450 #ifdef notdef
  451         /* Idle bit */
  452         mx_mii_writebit(sc, 1);
  453         mx_mii_writebit(sc, 0);
  454 #endif
  455 
  456         /* Check for ack */
  457         ack = mx_mii_readbit(sc);
  458 
  459         /*
  460          * Now try reading data bits. If the ack failed, we still
  461          * need to clock through 16 cycles to keep the PHY(s) in sync.
  462          */
  463         if (ack) {
  464                 for(i = 0; i < 16; i++) {
  465                         mx_mii_readbit(sc);
  466                 }
  467                 goto fail;
  468         }
  469 
  470         for (i = 0x8000; i; i >>= 1) {
  471                 if (!ack) {
  472                         if (mx_mii_readbit(sc))
  473                                 frame->mii_data |= i;
  474                 }
  475         }
  476 
  477 fail:
  478 
  479         mx_mii_writebit(sc, 0);
  480         mx_mii_writebit(sc, 0);
  481 
  482         splx(s);
  483 
  484         if (ack)
  485                 return(1);
  486         return(0);
  487 }
  488 
  489 /*
  490  * Write to a PHY register through the MII.
  491  */
  492 static int mx_mii_writereg(sc, frame)
  493         struct mx_softc         *sc;
  494         struct mx_mii_frame     *frame;
  495         
  496 {
  497         int                     s;
  498 
  499         s = splimp();
  500         /*
  501          * Set up frame for TX.
  502          */
  503 
  504         frame->mii_stdelim = MX_MII_STARTDELIM;
  505         frame->mii_opcode = MX_MII_WRITEOP;
  506         frame->mii_turnaround = MX_MII_TURNAROUND;
  507 
  508         /*
  509          * Sync the PHYs.
  510          */     
  511         mx_mii_sync(sc);
  512 
  513         mx_mii_send(sc, frame->mii_stdelim, 2);
  514         mx_mii_send(sc, frame->mii_opcode, 2);
  515         mx_mii_send(sc, frame->mii_phyaddr, 5);
  516         mx_mii_send(sc, frame->mii_regaddr, 5);
  517         mx_mii_send(sc, frame->mii_turnaround, 2);
  518         mx_mii_send(sc, frame->mii_data, 16);
  519 
  520         /* Idle bit. */
  521         mx_mii_writebit(sc, 0);
  522         mx_mii_writebit(sc, 0);
  523 
  524         splx(s);
  525 
  526         return(0);
  527 }
  528 
  529 static u_int16_t mx_phy_readreg(sc, reg)
  530         struct mx_softc         *sc;
  531         int                     reg;
  532 {
  533         struct mx_mii_frame     frame;
  534         u_int32_t               cfg;
  535 
  536         bzero((char *)&frame, sizeof(frame));
  537 
  538         frame.mii_phyaddr = sc->mx_phy_addr;
  539         frame.mii_regaddr = reg;
  540         cfg = CSR_READ_4(sc, MX_NETCFG);
  541         MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_PORTSEL);
  542         mx_mii_readreg(sc, &frame);
  543         CSR_WRITE_4(sc, MX_NETCFG, cfg);
  544 
  545         return(frame.mii_data);
  546 }
  547 
  548 static void mx_phy_writereg(sc, reg, data)
  549         struct mx_softc         *sc;
  550         int                     reg;
  551         int                     data;
  552 {
  553         struct mx_mii_frame     frame;
  554         u_int32_t               cfg;
  555 
  556         bzero((char *)&frame, sizeof(frame));
  557 
  558         frame.mii_phyaddr = sc->mx_phy_addr;
  559         frame.mii_regaddr = reg;
  560         frame.mii_data = data;
  561 
  562         cfg = CSR_READ_4(sc, MX_NETCFG);
  563         MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_PORTSEL);
  564         mx_mii_writereg(sc, &frame);
  565         CSR_WRITE_4(sc, MX_NETCFG, cfg);
  566 
  567         return;
  568 }
  569 
  570 #define MX_POLY         0xEDB88320
  571 #define MX_BITS         9
  572 #define MX_BITS_PNIC_II 7
  573 
  574 static u_int32_t mx_calchash(sc, addr)
  575         struct mx_softc         *sc;
  576         caddr_t                 addr;
  577 {
  578         u_int32_t               idx, bit, data, crc;
  579 
  580         /* Compute CRC for the address value. */
  581         crc = 0xFFFFFFFF; /* initial value */
  582 
  583         for (idx = 0; idx < 6; idx++) {
  584                 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
  585                         crc = (crc >> 1) ^ (((crc ^ data) & 1) ? MX_POLY : 0);
  586         }
  587 
  588         /* The hash table on the PNIC II is only 128 bits wide. */
  589         if (sc->mx_info->mx_vid == PN_VENDORID)
  590                 return (crc & ((1 << MX_BITS_PNIC_II) - 1));
  591 
  592         return (crc & ((1 << MX_BITS) - 1));
  593 }
  594 
  595 /*
  596  * Initiate an autonegotiation session.
  597  */
  598 static void mx_autoneg_xmit(sc)
  599         struct mx_softc         *sc;
  600 {
  601         u_int16_t               phy_sts;
  602 
  603         mx_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
  604         DELAY(500);
  605         while(mx_phy_readreg(sc, PHY_BMCR)
  606                         & PHY_BMCR_RESET);
  607 
  608         phy_sts = mx_phy_readreg(sc, PHY_BMCR);
  609         phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
  610         mx_phy_writereg(sc, PHY_BMCR, phy_sts);
  611 
  612         return;
  613 }
  614 
  615 /*
  616  * Invoke autonegotiation on a PHY.
  617  */
  618 static void mx_autoneg_mii(sc, flag, verbose)
  619         struct mx_softc         *sc;
  620         int                     flag;
  621         int                     verbose;
  622 {
  623         u_int16_t               phy_sts = 0, media, advert, ability;
  624         struct ifnet            *ifp;
  625         struct ifmedia          *ifm;
  626 
  627         ifm = &sc->ifmedia;
  628         ifp = &sc->arpcom.ac_if;
  629 
  630         ifm->ifm_media = IFM_ETHER | IFM_AUTO;
  631 
  632         switch (flag) {
  633         case MX_FLAG_FORCEDELAY:
  634                 /*
  635                  * XXX Never use this option anywhere but in the probe
  636                  * routine: making the kernel stop dead in its tracks
  637                  * for three whole seconds after we've gone multi-user
  638                  * is really bad manners.
  639                  */
  640                 mx_autoneg_xmit(sc);
  641                 DELAY(5000000);
  642                 break;
  643         case MX_FLAG_SCHEDDELAY:
  644                 /*
  645                  * Wait for the transmitter to go idle before starting
  646                  * an autoneg session, otherwise mx_start() may clobber
  647                  * our timeout, and we don't want to allow transmission
  648                  * during an autoneg session since that can screw it up.
  649                  */
  650                 if (sc->mx_cdata.mx_tx_head != NULL) {
  651                         sc->mx_want_auto = 1;
  652                         return;
  653                 }
  654                 mx_autoneg_xmit(sc);
  655                 ifp->if_timer = 5;
  656                 sc->mx_autoneg = 1;
  657                 sc->mx_want_auto = 0;
  658                 return;
  659                 break;
  660         case MX_FLAG_DELAYTIMEO:
  661                 ifp->if_timer = 0;
  662                 sc->mx_autoneg = 0;
  663                 break;
  664         default:
  665                 printf("mx%d: invalid autoneg flag: %d\n", sc->mx_unit, flag);
  666                 return;
  667         }
  668 
  669         if (mx_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
  670                 if (verbose)
  671                         printf("mx%d: autoneg complete, ", sc->mx_unit);
  672                 phy_sts = mx_phy_readreg(sc, PHY_BMSR);
  673         } else {
  674                 if (verbose)
  675                         printf("mx%d: autoneg not complete, ", sc->mx_unit);
  676         }
  677 
  678         media = mx_phy_readreg(sc, PHY_BMCR);
  679 
  680         /* Link is good. Report modes and set duplex mode. */
  681         if (mx_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
  682                 if (verbose)
  683                         printf("link status good ");
  684                 advert = mx_phy_readreg(sc, PHY_ANAR);
  685                 ability = mx_phy_readreg(sc, PHY_LPAR);
  686 
  687                 if (advert & PHY_ANAR_100BTXFULL &&
  688                         ability & PHY_ANAR_100BTXFULL) {
  689                         ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
  690                         media |= PHY_BMCR_SPEEDSEL;
  691                         media |= PHY_BMCR_DUPLEX;
  692                         printf("(full-duplex, 100Mbps)\n");
  693                 } else if (advert & PHY_ANAR_100BTXHALF &&
  694                         ability & PHY_ANAR_100BTXHALF) {
  695                         ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
  696                         media |= PHY_BMCR_SPEEDSEL;
  697                         media &= ~PHY_BMCR_DUPLEX;
  698                         printf("(half-duplex, 100Mbps)\n");
  699                 } else if (advert & PHY_ANAR_10BTFULL &&
  700                         ability & PHY_ANAR_10BTFULL) {
  701                         ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
  702                         media &= ~PHY_BMCR_SPEEDSEL;
  703                         media |= PHY_BMCR_DUPLEX;
  704                         printf("(full-duplex, 10Mbps)\n");
  705                 } else if (advert & PHY_ANAR_10BTHALF &&
  706                         ability & PHY_ANAR_10BTHALF) {
  707                         ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
  708                         media &= ~PHY_BMCR_SPEEDSEL;
  709                         media &= ~PHY_BMCR_DUPLEX;
  710                         printf("(half-duplex, 10Mbps)\n");
  711                 }
  712 
  713                 media &= ~PHY_BMCR_AUTONEGENBL;
  714 
  715                 /* Set ASIC's duplex mode to match the PHY. */
  716                 mx_setcfg(sc, media);
  717                 mx_phy_writereg(sc, PHY_BMCR, media);
  718         } else {
  719                 if (verbose)
  720                         printf("no carrier\n");
  721         }
  722 
  723         mx_init(sc);
  724 
  725         if (sc->mx_tx_pend) {
  726                 sc->mx_autoneg = 0;
  727                 sc->mx_tx_pend = 0;
  728                 mx_start(ifp);
  729         }
  730 
  731         return;
  732 }
  733 
  734 /*
  735  * Invoke autoneg using internal NWAY.
  736  */
  737 static void mx_autoneg(sc, flag, verbose)
  738         struct mx_softc         *sc;
  739         int                     flag;
  740         int                     verbose;
  741 {
  742         u_int32_t               media, ability;
  743         struct ifnet            *ifp;
  744         struct ifmedia          *ifm;
  745 
  746         ifm = &sc->ifmedia;
  747         ifp = &sc->arpcom.ac_if;
  748 
  749         ifm->ifm_media = IFM_ETHER | IFM_AUTO;
  750 
  751         switch (flag) {
  752         case MX_FLAG_FORCEDELAY:
  753                 /*
  754                  * XXX Never use this option anywhere but in the probe
  755                  * routine: making the kernel stop dead in its tracks
  756                  * for three whole seconds after we've gone multi-user
  757                  * is really bad manners.
  758                  */
  759                 MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_PORTSEL);
  760                 MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_FULLDUPLEX);
  761                 MX_SETBIT(sc, MX_10BTCTRL, MX_TCTL_AUTONEGENBL);
  762                 MX_SETBIT(sc, MX_10BTCTRL, MX_ASTAT_TXDISABLE);
  763                 DELAY(5000000);
  764                 break;
  765         case MX_FLAG_SCHEDDELAY:
  766                 /*
  767                  * Wait for the transmitter to go idle before starting
  768                  * an autoneg session, otherwise mx_start() may clobber
  769                  * our timeout, and we don't want to allow transmission
  770                  * during an autoneg session since that can screw it up.
  771                  */
  772                 if (sc->mx_cdata.mx_tx_head != NULL) {
  773                         sc->mx_want_auto = 1;
  774                         return;
  775                 }
  776                 MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_PORTSEL);
  777                 MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_FULLDUPLEX);
  778                 MX_SETBIT(sc, MX_10BTCTRL, MX_TCTL_AUTONEGENBL);
  779                 MX_SETBIT(sc, MX_10BTCTRL, MX_ASTAT_TXDISABLE);
  780                 ifp->if_timer = 5;
  781                 sc->mx_autoneg = 1;
  782                 sc->mx_want_auto = 0;
  783                 return;
  784                 break;
  785         case MX_FLAG_DELAYTIMEO:
  786                 ifp->if_timer = 0;
  787                 sc->mx_autoneg = 0;
  788                 break;
  789         default:
  790                 printf("mx%d: invalid autoneg flag: %d\n", sc->mx_unit, flag);
  791                 return;
  792         }
  793 
  794         if ((CSR_READ_4(sc, MX_10BTSTAT) & MX_TSTAT_ANEGSTAT) ==
  795                                                 MX_ASTAT_AUTONEGCMP) {
  796                 if (verbose)
  797                         printf("mx%d: autoneg complete, ", sc->mx_unit);
  798         } else {
  799                 if (verbose)
  800                         printf("mx%d: autoneg not complete, ", sc->mx_unit);
  801         }
  802 
  803         media = CSR_READ_4(sc, MX_NETCFG);
  804 
  805         /* Link is good. Report modes and set duplex mode. */
  806         if (!(CSR_READ_4(sc, MX_10BTSTAT) & MX_TSTAT_LS10) ||
  807                 !(CSR_READ_4(sc, MX_10BTSTAT) & MX_TSTAT_LS100)) {
  808                 if (verbose)
  809                         printf("link status good ");
  810                 ability = CSR_READ_4(sc, MX_10BTSTAT) >> 16;
  811                 if (ability & PHY_ANAR_100BTXFULL) {
  812                         ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
  813                         media |= MX_NETCFG_PORTSEL|MX_NETCFG_PCS|
  814                                         MX_NETCFG_SCRAMBLER;
  815                         media |= MX_NETCFG_FULLDUPLEX;
  816                         media &= ~MX_NETCFG_SPEEDSEL;
  817                         printf("(full-duplex, 100Mbps)\n");
  818                 } else if (ability &  PHY_ANAR_100BTXHALF) {
  819                         ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
  820                         media |= MX_NETCFG_PORTSEL|MX_NETCFG_PCS|
  821                                         MX_NETCFG_SCRAMBLER;
  822                         media &= ~(MX_NETCFG_FULLDUPLEX|MX_NETCFG_SPEEDSEL);
  823                         printf("(half-duplex, 100Mbps)\n");
  824                 } else if (ability & PHY_ANAR_10BTFULL) {
  825                         ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
  826                         media &= ~MX_NETCFG_PORTSEL;
  827                         media |= (MX_NETCFG_FULLDUPLEX|MX_NETCFG_SPEEDSEL);
  828                         printf("(full-duplex, 10Mbps)\n");
  829                 } else {
  830                         ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
  831                         media &= ~MX_NETCFG_PORTSEL;
  832                         media &= ~MX_NETCFG_FULLDUPLEX;
  833                         media |= MX_NETCFG_SPEEDSEL;
  834                         printf("(half-duplex, 10Mbps)\n");
  835                 }
  836 
  837                 CSR_WRITE_4(sc, MX_NETCFG, media);
  838                 MX_CLRBIT(sc, MX_10BTCTRL, MX_TCTL_AUTONEGENBL);
  839         } else {
  840                 if (verbose)
  841                         printf("no carrier\n");
  842         }
  843 
  844         mx_init(sc);
  845 
  846         if (sc->mx_tx_pend) {
  847                 sc->mx_autoneg = 0;
  848                 sc->mx_tx_pend = 0;
  849                 mx_start(ifp);
  850         }
  851 
  852         return;
  853 }
  854 
  855 static void mx_getmode_mii(sc)
  856         struct mx_softc         *sc;
  857 {
  858         u_int16_t               bmsr;
  859         struct ifnet            *ifp;
  860 
  861         ifp = &sc->arpcom.ac_if;
  862 
  863         bmsr = mx_phy_readreg(sc, PHY_BMSR);
  864         if (bootverbose)
  865                 printf("mx%d: PHY status word: %x\n", sc->mx_unit, bmsr);
  866 
  867         /* fallback */
  868         sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
  869 
  870         if (bmsr & PHY_BMSR_10BTHALF) {
  871                 if (bootverbose)
  872                         printf("mx%d: 10Mbps half-duplex mode supported\n",
  873                                                                 sc->mx_unit);
  874                 ifmedia_add(&sc->ifmedia,
  875                         IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
  876                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
  877         }
  878 
  879         if (bmsr & PHY_BMSR_10BTFULL) {
  880                 if (bootverbose)
  881                         printf("mx%d: 10Mbps full-duplex mode supported\n",
  882                                                                 sc->mx_unit);
  883                 ifmedia_add(&sc->ifmedia,
  884                         IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
  885                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
  886         }
  887 
  888         if (bmsr & PHY_BMSR_100BTXHALF) {
  889                 if (bootverbose)
  890                         printf("mx%d: 100Mbps half-duplex mode supported\n",
  891                                                                 sc->mx_unit);
  892                 ifp->if_baudrate = 100000000;
  893                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
  894                 ifmedia_add(&sc->ifmedia,
  895                         IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
  896                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
  897         }
  898 
  899         if (bmsr & PHY_BMSR_100BTXFULL) {
  900                 if (bootverbose)
  901                         printf("mx%d: 100Mbps full-duplex mode supported\n",
  902                                                                 sc->mx_unit);
  903                 ifp->if_baudrate = 100000000;
  904                 ifmedia_add(&sc->ifmedia,
  905                         IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
  906                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
  907         }
  908 
  909         if (bmsr & PHY_BMSR_CANAUTONEG) {
  910                 if (bootverbose)
  911                         printf("mx%d: autoneg supported\n", sc->mx_unit);
  912                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
  913                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
  914         }
  915 
  916         return;
  917 }
  918 
  919 /*
  920  * Set speed and duplex mode.
  921  */
  922 static void mx_setmode_mii(sc, media)
  923         struct mx_softc         *sc;
  924         int                     media;
  925 {
  926         u_int16_t               bmcr;
  927         struct ifnet            *ifp;
  928 
  929         ifp = &sc->arpcom.ac_if;
  930 
  931         /*
  932          * If an autoneg session is in progress, stop it.
  933          */
  934         if (sc->mx_autoneg) {
  935                 printf("mx%d: canceling autoneg session\n", sc->mx_unit);
  936                 ifp->if_timer = sc->mx_autoneg = sc->mx_want_auto = 0;
  937                 bmcr = mx_phy_readreg(sc, PHY_BMCR);
  938                 bmcr &= ~PHY_BMCR_AUTONEGENBL;
  939                 mx_phy_writereg(sc, PHY_BMCR, bmcr);
  940         }
  941 
  942         printf("mx%d: selecting MII, ", sc->mx_unit);
  943 
  944         bmcr = mx_phy_readreg(sc, PHY_BMCR);
  945 
  946         bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL|
  947                         PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK);
  948 
  949         if (IFM_SUBTYPE(media) == IFM_100_TX) {
  950                 printf("100Mbps, ");
  951                 bmcr |= PHY_BMCR_SPEEDSEL;
  952         }
  953 
  954         if (IFM_SUBTYPE(media) == IFM_10_T) {
  955                 printf("10Mbps, ");
  956                 bmcr &= ~PHY_BMCR_SPEEDSEL;
  957         }
  958 
  959         if ((media & IFM_GMASK) == IFM_FDX) {
  960                 printf("full duplex\n");
  961                 bmcr |= PHY_BMCR_DUPLEX;
  962         } else {
  963                 printf("half duplex\n");
  964                 bmcr &= ~PHY_BMCR_DUPLEX;
  965         }
  966 
  967         mx_setcfg(sc, bmcr);
  968         mx_phy_writereg(sc, PHY_BMCR, bmcr);
  969 
  970         return;
  971 }
  972 
  973 /*
  974  * Set speed and duplex mode on internal transceiver.
  975  */
  976 static void mx_setmode(sc, media, verbose)
  977         struct mx_softc         *sc;
  978         int                     media;
  979         int                     verbose;
  980 {
  981         struct ifnet            *ifp;
  982         u_int32_t               mode;
  983 
  984         ifp = &sc->arpcom.ac_if;
  985 
  986         /*
  987          * If an autoneg session is in progress, stop it.
  988          */
  989         if (sc->mx_autoneg) {
  990                 printf("mx%d: canceling autoneg session\n", sc->mx_unit);
  991                 ifp->if_timer = sc->mx_autoneg = sc->mx_want_auto = 0;
  992                 MX_CLRBIT(sc, MX_10BTCTRL, MX_TCTL_AUTONEGENBL);
  993         }
  994 
  995         if (verbose)
  996                 printf("mx%d: selecting NWAY, ", sc->mx_unit);
  997 
  998         mode = CSR_READ_4(sc, MX_NETCFG);
  999 
 1000         mode &= ~(MX_NETCFG_FULLDUPLEX|MX_NETCFG_PORTSEL|
 1001                 MX_NETCFG_PCS|MX_NETCFG_SCRAMBLER|MX_NETCFG_SPEEDSEL);
 1002 
 1003         if (IFM_SUBTYPE(media) == IFM_100_TX) {
 1004                 if (verbose)
 1005                         printf("100Mbps, ");
 1006                 mode |= MX_NETCFG_PORTSEL|MX_NETCFG_PCS|MX_NETCFG_SCRAMBLER;
 1007         }
 1008 
 1009         if (IFM_SUBTYPE(media) == IFM_10_T) {
 1010                 if (verbose)
 1011                         printf("10Mbps, ");
 1012                 mode &= ~MX_NETCFG_PORTSEL;
 1013                 mode |= MX_NETCFG_SPEEDSEL;
 1014         }
 1015 
 1016         if ((media & IFM_GMASK) == IFM_FDX) {
 1017                 if (verbose)
 1018                         printf("full duplex\n");
 1019                 mode |= MX_NETCFG_FULLDUPLEX;
 1020         } else {
 1021                 if (verbose)
 1022                         printf("half duplex\n");
 1023                 mode &= ~MX_NETCFG_FULLDUPLEX;
 1024         }
 1025 
 1026         CSR_WRITE_4(sc, MX_NETCFG, mode);
 1027 
 1028         return;
 1029 }
 1030 
 1031 /*
 1032  * Programming the receiver filter on the tulip/PMAC is gross. You
 1033  * have to construct a special setup frame and download it to the
 1034  * chip via the transmit DMA engine. This routine is also somewhat
 1035  * gross, as the setup frame is sent synchronously rather than putting
 1036  * on the transmit queue. The transmitter has to be stopped, then we
 1037  * can download the frame and wait for the 'owned' bit to clear.
 1038  *
 1039  * We always program the chip using 'hash perfect' mode, i.e. one perfect
 1040  * address (our node address) and a 512-bit hash filter for multicast
 1041  * frames. We also sneak the broadcast address into the hash filter since
 1042  * we need that too.
 1043  */
 1044 void mx_setfilt(sc)
 1045         struct mx_softc         *sc;
 1046 {
 1047         struct mx_desc          *sframe;
 1048         u_int32_t               h, *sp;
 1049         struct ifmultiaddr      *ifma;
 1050         struct ifnet            *ifp;
 1051         int                     i;
 1052 
 1053         ifp = &sc->arpcom.ac_if;
 1054 
 1055         MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_TX_ON);
 1056         MX_SETBIT(sc, MX_ISR, MX_ISR_TX_IDLE);
 1057 
 1058         sframe = &sc->mx_cdata.mx_sframe;
 1059         sp = (u_int32_t *)&sc->mx_cdata.mx_sbuf;
 1060         bzero((char *)sp, MX_SFRAME_LEN);
 1061 
 1062         sframe->mx_next = vtophys(&sc->mx_ldata->mx_tx_list[0]);
 1063         sframe->mx_data = vtophys(&sc->mx_cdata.mx_sbuf);
 1064         sframe->mx_ctl = MX_SFRAME_LEN | MX_TXCTL_TLINK |
 1065                         MX_TXCTL_SETUP | MX_FILTER_HASHPERF;
 1066 
 1067         /* If we want promiscuous mode, set the allframes bit. */
 1068         if (ifp->if_flags & IFF_PROMISC)
 1069                 MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_RX_PROMISC);
 1070         else
 1071                 MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_RX_PROMISC);
 1072 
 1073         if (ifp->if_flags & IFF_ALLMULTI)
 1074                 MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_RX_ALLMULTI);
 1075 
 1076         for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
 1077                                 ifma = ifma->ifma_link.le_next) {
 1078                 if (ifma->ifma_addr->sa_family != AF_LINK)
 1079                         continue;
 1080                 h = mx_calchash(sc,
 1081                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
 1082                 sp[h >> 4] |= 1 << (h & 0xF);
 1083         }
 1084 
 1085         if (ifp->if_flags & IFF_BROADCAST) {
 1086                 h = mx_calchash(sc, (caddr_t)&etherbroadcastaddr);
 1087                 sp[h >> 4] |= 1 << (h & 0xF);
 1088         }
 1089 
 1090         sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
 1091         sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
 1092         sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
 1093 
 1094         CSR_WRITE_4(sc, MX_TXADDR, vtophys(sframe));
 1095         MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_TX_ON);
 1096         sframe->mx_status = MX_TXSTAT_OWN;
 1097         CSR_WRITE_4(sc, MX_TXSTART, 0xFFFFFFFF);
 1098 
 1099         /*
 1100          * Wait for chip to clear the 'own' bit.
 1101          */
 1102         for (i = 0; i < MX_TIMEOUT; i++) {
 1103                 DELAY(10);
 1104                 if (sframe->mx_status != MX_TXSTAT_OWN)
 1105                         break;
 1106         }
 1107 
 1108         if (i == MX_TIMEOUT)
 1109                 printf("mx%d: failed to send setup frame\n", sc->mx_unit);
 1110 
 1111         MX_SETBIT(sc, MX_ISR, MX_ISR_TX_NOBUF|MX_ISR_TX_IDLE);
 1112 
 1113         return;
 1114 }
 1115 
 1116 /*
 1117  * In order to fiddle with the
 1118  * 'full-duplex' and '100Mbps' bits in the netconfig register, we
 1119  * first have to put the transmit and/or receive logic in the idle state.
 1120  */
 1121 static void mx_setcfg(sc, bmcr)
 1122         struct mx_softc         *sc;
 1123         int                     bmcr;
 1124 {
 1125         int                     i, restart = 0;
 1126 
 1127         if (CSR_READ_4(sc, MX_NETCFG) & (MX_NETCFG_TX_ON|MX_NETCFG_RX_ON)) {
 1128                 restart = 1;
 1129                 MX_CLRBIT(sc, MX_NETCFG, (MX_NETCFG_TX_ON|MX_NETCFG_RX_ON));
 1130 
 1131                 for (i = 0; i < MX_TIMEOUT; i++) {
 1132                         DELAY(10);
 1133                         if (CSR_READ_4(sc, MX_ISR) & MX_ISR_TX_IDLE)
 1134                                 break;
 1135                 }
 1136 
 1137                 if (i == MX_TIMEOUT)
 1138                         printf("mx%d: failed to force tx and "
 1139                                 "rx to idle state\n", sc->mx_unit);
 1140 
 1141         }
 1142 
 1143         if (bmcr & PHY_BMCR_SPEEDSEL) {
 1144                 MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_SPEEDSEL);
 1145                 if (sc->mx_phy_addr == 0) {
 1146                         MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_PORTSEL|
 1147                                 MX_NETCFG_PCS|MX_NETCFG_SCRAMBLER);
 1148                 }
 1149         } else
 1150                 MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_SPEEDSEL);
 1151 
 1152         if (bmcr & PHY_BMCR_DUPLEX)
 1153                 MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_FULLDUPLEX);
 1154         else
 1155                 MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_FULLDUPLEX);
 1156 
 1157         if (restart)
 1158                 MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_TX_ON|MX_NETCFG_RX_ON);
 1159 
 1160         return;
 1161 }
 1162 
 1163 static void mx_reset(sc)
 1164         struct mx_softc         *sc;
 1165 {
 1166         register int            i;
 1167 
 1168         MX_SETBIT(sc, MX_BUSCTL, MX_BUSCTL_RESET);
 1169 
 1170         for (i = 0; i < MX_TIMEOUT; i++) {
 1171                 DELAY(10);
 1172                 if (!(CSR_READ_4(sc, MX_BUSCTL) & MX_BUSCTL_RESET))
 1173                         break;
 1174         }
 1175         if (i == MX_TIMEOUT)
 1176                 printf("mx%d: reset never completed!\n", sc->mx_unit);
 1177 
 1178         /* Wait a little while for the chip to get its brains in order. */
 1179         DELAY(1000);
 1180         return;
 1181 }
 1182 
 1183 static struct mx_type *mx_devtype(config_id, device_id)
 1184         pcici_t                 config_id;
 1185         pcidi_t                 device_id;
 1186 {
 1187         struct mx_type          *t;
 1188         u_int32_t               rev;
 1189 
 1190         t = mx_devs;
 1191 
 1192         while(t->mx_name != NULL) {
 1193                 if ((device_id & 0xFFFF) == t->mx_vid &&
 1194                     ((device_id >> 16) & 0xFFFF) == t->mx_did) {
 1195                         /* Check the PCI revision */
 1196                         rev = pci_conf_read(config_id, MX_PCI_REVID) & 0xFF;
 1197                         if (t->mx_did == MX_DEVICEID_98713 &&
 1198                                                 rev >= MX_REVISION_98713A)
 1199                                 t++;
 1200                         if (t->mx_did == CP_DEVICEID_98713 &&
 1201                                                 rev >= MX_REVISION_98713A)
 1202                                 t++;
 1203                         if (t->mx_did == MX_DEVICEID_987x5 &&
 1204                                                 rev >= MX_REVISION_98725)
 1205                                 t++;
 1206                         return(t);
 1207                 }
 1208                 t++;
 1209         }
 1210 
 1211         return(NULL);
 1212 }
 1213 
 1214 /*
 1215  * Probe for a Macronix PMAC chip. Check the PCI vendor and device
 1216  * IDs against our list and return a device name if we find a match.
 1217  * We do a little bit of extra work to identify the exact type of
 1218  * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
 1219  * but different revision IDs. The same is true for 98715/98715A
 1220  * chips and the 98725. This doesn't affect a whole lot, but it
 1221  * lets us tell the user exactly what type of device they have
 1222  * in the probe output.
 1223  */
 1224 static const char *
 1225 mx_probe(config_id, device_id)
 1226         pcici_t                 config_id;
 1227         pcidi_t                 device_id;
 1228 {
 1229         struct mx_type          *t;
 1230 
 1231         t = mx_devtype(config_id, device_id);
 1232 
 1233         if (t != NULL)
 1234                 return(t->mx_name);
 1235 
 1236         return(NULL);
 1237 }
 1238 
 1239 /*
 1240  * Attach the interface. Allocate softc structures, do ifmedia
 1241  * setup and ethernet/BPF attach.
 1242  */
 1243 static void
 1244 mx_attach(config_id, unit)
 1245         pcici_t                 config_id;
 1246         int                     unit;
 1247 {
 1248         int                     s, i;
 1249 #ifndef MX_USEIOSPACE
 1250         vm_offset_t             pbase, vbase;
 1251 #endif
 1252         u_char                  eaddr[ETHER_ADDR_LEN];
 1253         u_int32_t               command;
 1254         struct mx_softc         *sc;
 1255         struct ifnet            *ifp;
 1256         int                     media = IFM_ETHER|IFM_100_TX|IFM_FDX;
 1257         unsigned int            round;
 1258         caddr_t                 roundptr;
 1259         struct mx_type          *p;
 1260         u_int16_t               phy_vid, phy_did, phy_sts, mac_offset = 0;
 1261         u_int32_t               revision, pci_id;
 1262 
 1263         s = splimp();
 1264 
 1265         sc = malloc(sizeof(struct mx_softc), M_DEVBUF, M_NOWAIT);
 1266         if (sc == NULL) {
 1267                 printf("mx%d: no memory for softc struct!\n", unit);
 1268                 goto fail;
 1269         }
 1270         bzero(sc, sizeof(struct mx_softc));
 1271 
 1272         /*
 1273          * Handle power management nonsense.
 1274          */
 1275 
 1276         command = pci_conf_read(config_id, MX_PCI_CAPID) & 0x000000FF;
 1277         if (command == 0x01) {
 1278 
 1279                 command = pci_conf_read(config_id, MX_PCI_PWRMGMTCTRL);
 1280                 if (command & MX_PSTATE_MASK) {
 1281                         u_int32_t               iobase, membase, irq;
 1282 
 1283                         /* Save important PCI config data. */
 1284                         iobase = pci_conf_read(config_id, MX_PCI_LOIO);
 1285                         membase = pci_conf_read(config_id, MX_PCI_LOMEM);
 1286                         irq = pci_conf_read(config_id, MX_PCI_INTLINE);
 1287 
 1288                         /* Reset the power state. */
 1289                         printf("mx%d: chip is in D%d power mode "
 1290                         "-- setting to D0\n", unit, command & MX_PSTATE_MASK);
 1291                         command &= 0xFFFFFFFC;
 1292                         pci_conf_write(config_id, MX_PCI_PWRMGMTCTRL, command);
 1293 
 1294                         /* Restore PCI config data. */
 1295                         pci_conf_write(config_id, MX_PCI_LOIO, iobase);
 1296                         pci_conf_write(config_id, MX_PCI_LOMEM, membase);
 1297                         pci_conf_write(config_id, MX_PCI_INTLINE, irq);
 1298                 }
 1299         }
 1300 
 1301         /*
 1302          * Map control/status registers.
 1303          */
 1304         command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
 1305         command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
 1306         pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command);
 1307         command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
 1308 
 1309 #ifdef MX_USEIOSPACE
 1310         if (!(command & PCIM_CMD_PORTEN)) {
 1311                 printf("mx%d: failed to enable I/O ports!\n", unit);
 1312                 free(sc, M_DEVBUF);
 1313                 goto fail;
 1314         }
 1315 
 1316         if (!pci_map_port(config_id, MX_PCI_LOIO,
 1317                                         (u_short *)&(sc->mx_bhandle))) {
 1318                 printf ("mx%d: couldn't map ports\n", unit);
 1319                 goto fail;
 1320         }
 1321 #ifdef __i386__
 1322         sc->mx_btag = I386_BUS_SPACE_IO;
 1323 #endif
 1324 #ifdef __alpha__
 1325         sc->mx_btag = ALPHA_BUS_SPACE_IO;
 1326 #endif
 1327 #else
 1328         if (!(command & PCIM_CMD_MEMEN)) {
 1329                 printf("mx%d: failed to enable memory mapping!\n", unit);
 1330                 goto fail;
 1331         }
 1332 
 1333         if (!pci_map_mem(config_id, MX_PCI_LOMEM, &vbase, &pbase)) {
 1334                 printf ("mx%d: couldn't map memory\n", unit);
 1335                 goto fail;
 1336         }
 1337 #ifdef __i386__
 1338         sc->mx_btag = I386_BUS_SPACE_MEM;
 1339 #endif
 1340 #ifdef __alpha__
 1341         sc->mx_btag = ALPHA_BUS_SPACE_MEM;
 1342 #endif
 1343         sc->mx_bhandle = vbase;
 1344 #endif
 1345 
 1346         /* Allocate interrupt */
 1347         if (!pci_map_int(config_id, mx_intr, sc, &net_imask)) {
 1348                 printf("mx%d: couldn't map interrupt\n", unit);
 1349                 goto fail;
 1350         }
 1351 
 1352         /* Need this info to decide on a chip type. */
 1353         revision = pci_conf_read(config_id, MX_PCI_REVID) & 0x000000FF;
 1354         pci_id = (pci_conf_read(config_id,MX_PCI_VENDOR_ID) >> 16) & 0x0000FFFF;
 1355 
 1356         if (pci_id == MX_DEVICEID_98713 && revision < MX_REVISION_98713A)
 1357                 sc->mx_type = MX_TYPE_98713;
 1358         else if (pci_id == CP_DEVICEID_98713 && revision < MX_REVISION_98713A)
 1359                 sc->mx_type = MX_TYPE_98713;
 1360         else if (pci_id == MX_DEVICEID_98713 && revision >= MX_REVISION_98713A)
 1361                 sc->mx_type = MX_TYPE_98713A;
 1362         else
 1363                 sc->mx_type = MX_TYPE_987x5;
 1364 
 1365         /* Save the cache line size. */
 1366         sc->mx_cachesize = pci_conf_read(config_id, MX_PCI_CACHELEN) & 0xFF;
 1367 
 1368         /* Save the device info; the PNIC II requires special handling. */
 1369         pci_id = pci_conf_read(config_id,MX_PCI_VENDOR_ID);
 1370         sc->mx_info = mx_devtype(config_id, pci_id);
 1371 
 1372         /* Reset the adapter. */
 1373         mx_reset(sc);
 1374 
 1375         /*
 1376          * Get station address from the EEPROM.
 1377          */
 1378         mx_read_eeprom(sc, (caddr_t)&mac_offset,
 1379                         (MX_EE_NODEADDR_OFFSET / 2), 1, 0);
 1380         mx_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
 1381 
 1382         /*
 1383          * A PMAC chip was detected. Inform the world.
 1384          */
 1385         printf("mx%d: Ethernet address: %6D\n", unit, eaddr, ":");
 1386 
 1387         sc->mx_unit = unit;
 1388         bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
 1389 
 1390         sc->mx_ldata_ptr = malloc(sizeof(struct mx_list_data) + 8,
 1391                                 M_DEVBUF, M_NOWAIT);
 1392         if (sc->mx_ldata_ptr == NULL) {
 1393                 free(sc, M_DEVBUF);
 1394                 printf("mx%d: no memory for list buffers!\n", unit);
 1395                 goto fail;
 1396         }
 1397 
 1398         sc->mx_ldata = (struct mx_list_data *)sc->mx_ldata_ptr;
 1399         round = (unsigned int)sc->mx_ldata_ptr & 0xF;
 1400         roundptr = sc->mx_ldata_ptr;
 1401         for (i = 0; i < 8; i++) {
 1402                 if (round % 8) {
 1403                         round++;
 1404                         roundptr++;
 1405                 }
 1406                         break;
 1407         }
 1408         sc->mx_ldata = (struct mx_list_data *)roundptr;
 1409         bzero(sc->mx_ldata, sizeof(struct mx_list_data));
 1410 
 1411         ifp = &sc->arpcom.ac_if;
 1412         ifp->if_softc = sc;
 1413         ifp->if_unit = unit;
 1414         ifp->if_name = "mx";
 1415         ifp->if_mtu = ETHERMTU;
 1416         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 1417         ifp->if_ioctl = mx_ioctl;
 1418         ifp->if_output = ether_output;
 1419         ifp->if_start = mx_start;
 1420         ifp->if_watchdog = mx_watchdog;
 1421         ifp->if_init = mx_init;
 1422         ifp->if_baudrate = 10000000;
 1423         ifp->if_snd.ifq_maxlen = MX_TX_LIST_CNT - 1;
 1424 
 1425         if (sc->mx_type == MX_TYPE_98713) {
 1426                 if (bootverbose)
 1427                         printf("mx%d: probing for a PHY\n", sc->mx_unit);
 1428                 for (i = MX_PHYADDR_MIN; i < MX_PHYADDR_MAX + 1; i++) {
 1429                         if (bootverbose)
 1430                                 printf("mx%d: checking address: %d\n",
 1431                                                         sc->mx_unit, i);
 1432                         sc->mx_phy_addr = i;
 1433                         mx_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
 1434                         DELAY(500);
 1435                         while(mx_phy_readreg(sc, PHY_BMCR)
 1436                                         & PHY_BMCR_RESET);
 1437                         if ((phy_sts = mx_phy_readreg(sc, PHY_BMSR)))
 1438                                 break;
 1439                 }
 1440                 if (phy_sts) {
 1441                         phy_vid = mx_phy_readreg(sc, PHY_VENID);
 1442                         phy_did = mx_phy_readreg(sc, PHY_DEVID);
 1443                         if (bootverbose)
 1444                                 printf("mx%d: found PHY at address %d, ",
 1445                                         sc->mx_unit, sc->mx_phy_addr);
 1446                         if (bootverbose)
 1447                                 printf("vendor id: %x device id: %x\n",
 1448                                 phy_vid, phy_did);
 1449                         p = mx_phys;
 1450                         while(p->mx_vid) {
 1451                                 if (phy_vid == p->mx_vid &&
 1452                                         (phy_did | 0x000F) == p->mx_did) {
 1453                                         sc->mx_pinfo = p;
 1454                                         break;
 1455                                 }
 1456                                 p++;
 1457                         }
 1458                         if (sc->mx_pinfo == NULL)
 1459                                 sc->mx_pinfo = &mx_phys[PHY_UNKNOWN];
 1460                         if (bootverbose)
 1461                                 printf("mx%d: PHY type: %s\n",
 1462                                         sc->mx_unit, sc->mx_pinfo->mx_name);
 1463                 } else {
 1464 #ifdef DIAGNOSTIC
 1465                         printf("mx%d: MII without any phy!\n", sc->mx_unit);
 1466 #endif
 1467                 }
 1468         }
 1469 
 1470         /*
 1471          * Do ifmedia setup.
 1472          */
 1473         ifmedia_init(&sc->ifmedia, 0, mx_ifmedia_upd, mx_ifmedia_sts);
 1474 
 1475         if (sc->mx_type == MX_TYPE_98713 && sc->mx_pinfo != NULL) {
 1476                 mx_getmode_mii(sc);
 1477                 mx_autoneg_mii(sc, MX_FLAG_FORCEDELAY, 1);
 1478         } else {
 1479                 ifmedia_add(&sc->ifmedia,
 1480                         IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
 1481                 ifmedia_add(&sc->ifmedia,
 1482                         IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
 1483                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
 1484                 ifmedia_add(&sc->ifmedia,
 1485                         IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
 1486                 ifmedia_add(&sc->ifmedia,
 1487                         IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
 1488                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
 1489                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
 1490                 mx_autoneg(sc, MX_FLAG_FORCEDELAY, 1);
 1491         }
 1492 
 1493         media = sc->ifmedia.ifm_media;
 1494         mx_stop(sc);
 1495 
 1496         ifmedia_set(&sc->ifmedia, media);
 1497 
 1498         /*
 1499          * Call MI attach routines.
 1500          */
 1501         if_attach(ifp);
 1502         ether_ifattach(ifp);
 1503 
 1504 #if NBPFILTER > 0
 1505         bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
 1506 #endif
 1507         at_shutdown(mx_shutdown, sc, SHUTDOWN_POST_SYNC);
 1508 
 1509 fail:
 1510         splx(s);
 1511         return;
 1512 }
 1513 
 1514 /*
 1515  * Initialize the transmit descriptors.
 1516  */
 1517 static int mx_list_tx_init(sc)
 1518         struct mx_softc         *sc;
 1519 {
 1520         struct mx_chain_data    *cd;
 1521         struct mx_list_data     *ld;
 1522         int                     i;
 1523 
 1524         cd = &sc->mx_cdata;
 1525         ld = sc->mx_ldata;
 1526         for (i = 0; i < MX_TX_LIST_CNT; i++) {
 1527                 cd->mx_tx_chain[i].mx_ptr = &ld->mx_tx_list[i];
 1528                 if (i == (MX_TX_LIST_CNT - 1))
 1529                         cd->mx_tx_chain[i].mx_nextdesc =
 1530                                 &cd->mx_tx_chain[0];
 1531                 else
 1532                         cd->mx_tx_chain[i].mx_nextdesc =
 1533                                 &cd->mx_tx_chain[i + 1];
 1534         }
 1535 
 1536         cd->mx_tx_free = &cd->mx_tx_chain[0];
 1537         cd->mx_tx_tail = cd->mx_tx_head = NULL;
 1538 
 1539         return(0);
 1540 }
 1541 
 1542 
 1543 /*
 1544  * Initialize the RX descriptors and allocate mbufs for them. Note that
 1545  * we arrange the descriptors in a closed ring, so that the last descriptor
 1546  * points back to the first.
 1547  */
 1548 static int mx_list_rx_init(sc)
 1549         struct mx_softc         *sc;
 1550 {
 1551         struct mx_chain_data    *cd;
 1552         struct mx_list_data     *ld;
 1553         int                     i;
 1554 
 1555         cd = &sc->mx_cdata;
 1556         ld = sc->mx_ldata;
 1557 
 1558         for (i = 0; i < MX_RX_LIST_CNT; i++) {
 1559                 cd->mx_rx_chain[i].mx_ptr =
 1560                         (struct mx_desc *)&ld->mx_rx_list[i];
 1561                 if (mx_newbuf(sc, &cd->mx_rx_chain[i]) == ENOBUFS)
 1562                         return(ENOBUFS);
 1563                 if (i == (MX_RX_LIST_CNT - 1)) {
 1564                         cd->mx_rx_chain[i].mx_nextdesc = &cd->mx_rx_chain[0];
 1565                         ld->mx_rx_list[i].mx_next =
 1566                                         vtophys(&ld->mx_rx_list[0]);
 1567                 } else {
 1568                         cd->mx_rx_chain[i].mx_nextdesc = &cd->mx_rx_chain[i + 1];
 1569                         ld->mx_rx_list[i].mx_next =
 1570                                         vtophys(&ld->mx_rx_list[i + 1]);
 1571                 }
 1572         }
 1573 
 1574         cd->mx_rx_head = &cd->mx_rx_chain[0];
 1575 
 1576         return(0);
 1577 }
 1578 
 1579 /*
 1580  * Initialize an RX descriptor and attach an MBUF cluster.
 1581  * Note: the length fields are only 11 bits wide, which means the
 1582  * largest size we can specify is 2047. This is important because
 1583  * MCLBYTES is 2048, so we have to subtract one otherwise we'll
 1584  * overflow the field and make a mess.
 1585  */
 1586 static int mx_newbuf(sc, c)
 1587         struct mx_softc         *sc;
 1588         struct mx_chain_onefrag *c;
 1589 {
 1590         struct mbuf             *m_new = NULL;
 1591 
 1592         MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1593         if (m_new == NULL) {
 1594                 printf("mx%d: no memory for rx list -- packet dropped!\n",
 1595                                                                 sc->mx_unit);
 1596                 return(ENOBUFS);
 1597         }
 1598 
 1599         MCLGET(m_new, M_DONTWAIT);
 1600         if (!(m_new->m_flags & M_EXT)) {
 1601                 printf("mx%d: no memory for rx list -- packet dropped!\n",
 1602                                                                 sc->mx_unit);
 1603                 m_freem(m_new);
 1604                 return(ENOBUFS);
 1605         }
 1606 
 1607         c->mx_mbuf = m_new;
 1608         c->mx_ptr->mx_status = MX_RXSTAT;
 1609         c->mx_ptr->mx_data = vtophys(mtod(m_new, caddr_t));
 1610         c->mx_ptr->mx_ctl = MX_RXCTL_RLINK | (MCLBYTES - 1);
 1611 
 1612         return(0);
 1613 }
 1614 
 1615 /*
 1616  * A frame has been uploaded: pass the resulting mbuf chain up to
 1617  * the higher level protocols.
 1618  */
 1619 static void mx_rxeof(sc)
 1620         struct mx_softc         *sc;
 1621 {
 1622         struct ether_header     *eh;
 1623         struct mbuf             *m;
 1624         struct ifnet            *ifp;
 1625         struct mx_chain_onefrag *cur_rx;
 1626         int                     total_len = 0;
 1627         u_int32_t               rxstat;
 1628 
 1629         ifp = &sc->arpcom.ac_if;
 1630 
 1631         while(!((rxstat = sc->mx_cdata.mx_rx_head->mx_ptr->mx_status) &
 1632                                                         MX_RXSTAT_OWN)) {
 1633 #ifdef __alpha__
 1634                 struct mbuf             *m0 = NULL;
 1635 #endif
 1636                 cur_rx = sc->mx_cdata.mx_rx_head;
 1637                 sc->mx_cdata.mx_rx_head = cur_rx->mx_nextdesc;
 1638 
 1639                 /*
 1640                  * If an error occurs, update stats, clear the
 1641                  * status word and leave the mbuf cluster in place:
 1642                  * it should simply get re-used next time this descriptor
 1643                  * comes up in the ring.
 1644                  */
 1645                 if (rxstat & MX_RXSTAT_RXERR) {
 1646                         ifp->if_ierrors++;
 1647                         if (rxstat & MX_RXSTAT_COLLSEEN)
 1648                                 ifp->if_collisions++;
 1649                         cur_rx->mx_ptr->mx_status = MX_RXSTAT;
 1650                         cur_rx->mx_ptr->mx_ctl =
 1651                                 MX_RXCTL_RLINK | (MCLBYTES - 1);
 1652                         continue;
 1653                 }
 1654 
 1655                 /* No errors; receive the packet. */    
 1656                 m = cur_rx->mx_mbuf;
 1657                 total_len = MX_RXBYTES(cur_rx->mx_ptr->mx_status);
 1658 
 1659                 /*
 1660                  * XXX The Macronix chips includes the CRC with every
 1661                  * received frame, and there's no way to turn this
 1662                  * behavior off (at least, I can't find anything in
 1663                  * the manual that explains how to do it) so we have
 1664                  * to trim off the CRC manually.
 1665                  */
 1666                 total_len -= ETHER_CRC_LEN;
 1667 
 1668                 /*
 1669                  * Try to conjure up a new mbuf cluster. If that
 1670                  * fails, it means we have an out of memory condition and
 1671                  * should leave the buffer in place and continue. This will
 1672                  * result in a lost packet, but there's little else we
 1673                  * can do in this situation.
 1674                  */
 1675                 if (mx_newbuf(sc, cur_rx) == ENOBUFS) {
 1676                         ifp->if_ierrors++;
 1677                         cur_rx->mx_ptr->mx_status = MX_RXSTAT;
 1678                         cur_rx->mx_ptr->mx_ctl =
 1679                                         MX_RXCTL_RLINK | (MCLBYTES - 1);
 1680                         continue;
 1681                 }
 1682 
 1683 #ifdef __alpha__
 1684                 /*
 1685                  * Deal with alignment on alpha.
 1686                  */
 1687                 MGETHDR(m0, M_DONTWAIT, MT_DATA);
 1688                 if (m0 == NULL) {
 1689                         ifp->if_ierrors++;
 1690                         cur_rx->mx_ptr->mx_status = MX_RXSTAT;
 1691                         cur_rx->mx_ptr->mx_ctl =
 1692                                         MX_RXCTL_RLINK | (MCLBYTES - 1);
 1693                         bzero((char *)mtod(cur_rx->mx_mbuf, char *), MCLBYTES);
 1694                         continue;
 1695                 }
 1696 
 1697                 m0->m_data += 2;
 1698                 if (total_len <= (MHLEN - 2)) {
 1699                         bcopy(mtod(m, caddr_t), mtod(m0, caddr_t), total_len);                          m_freem(m);
 1700                         m = m0;
 1701                         m->m_pkthdr.len = m->m_len = total_len;
 1702                 } else {
 1703                         bcopy(mtod(m, caddr_t), mtod(m0, caddr_t), (MHLEN - 2));
 1704                         m->m_len = total_len - (MHLEN - 2);
 1705                         m->m_data += (MHLEN - 2);
 1706                         m0->m_next = m;
 1707                         m0->m_len = (MHLEN - 2);
 1708                         m = m0;
 1709                         m->m_pkthdr.len = total_len;
 1710                 }
 1711 #else
 1712                 m->m_pkthdr.len = m->m_len = total_len;
 1713 #endif
 1714                 ifp->if_ipackets++;
 1715                 eh = mtod(m, struct ether_header *);
 1716                 m->m_pkthdr.rcvif = ifp;
 1717 
 1718 #if NBPFILTER > 0
 1719                 /*
 1720                  * Handle BPF listeners. Let the BPF user see the packet, but
 1721                  * don't pass it up to the ether_input() layer unless it's
 1722                  * a broadcast packet, multicast packet, matches our ethernet
 1723                  * address or the interface is in promiscuous mode.
 1724                  */
 1725                 if (ifp->if_bpf) {
 1726                         bpf_mtap(ifp, m);
 1727                         if (ifp->if_flags & IFF_PROMISC &&
 1728                                 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
 1729                                                 ETHER_ADDR_LEN) &&
 1730                                         (eh->ether_dhost[0] & 1) == 0)) {
 1731                                 m_freem(m);
 1732                                 continue;
 1733                         }
 1734                 }
 1735 #endif
 1736                 /* Remove header from mbuf and pass it on. */
 1737                 m_adj(m, sizeof(struct ether_header));
 1738                 ether_input(ifp, eh, m);
 1739         }
 1740 
 1741         return;
 1742 }
 1743 
 1744 void mx_rxeoc(sc)
 1745         struct mx_softc         *sc;
 1746 {
 1747 
 1748         mx_rxeof(sc);
 1749         MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_RX_ON);
 1750         CSR_WRITE_4(sc, MX_RXADDR, vtophys(sc->mx_cdata.mx_rx_head->mx_ptr));
 1751         MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_RX_ON);
 1752         CSR_WRITE_4(sc, MX_RXSTART, 0xFFFFFFFF);
 1753 
 1754         return;
 1755 }
 1756 
 1757 /*
 1758  * A frame was downloaded to the chip. It's safe for us to clean up
 1759  * the list buffers.
 1760  */
 1761 
 1762 static void mx_txeof(sc)
 1763         struct mx_softc         *sc;
 1764 {
 1765         struct mx_chain         *cur_tx;
 1766         struct ifnet            *ifp;
 1767 
 1768         ifp = &sc->arpcom.ac_if;
 1769 
 1770         /* Clear the timeout timer. */
 1771         ifp->if_timer = 0;
 1772 
 1773         if (sc->mx_cdata.mx_tx_head == NULL)
 1774                 return;
 1775 
 1776         /*
 1777          * Go through our tx list and free mbufs for those
 1778          * frames that have been transmitted.
 1779          */
 1780         while(sc->mx_cdata.mx_tx_head->mx_mbuf != NULL) {
 1781                 u_int32_t               txstat;
 1782 
 1783                 cur_tx = sc->mx_cdata.mx_tx_head;
 1784                 txstat = MX_TXSTATUS(cur_tx);
 1785 
 1786                 if (txstat & MX_TXSTAT_OWN)
 1787                         break;
 1788 
 1789                 if (txstat & MX_TXSTAT_ERRSUM) {
 1790                         ifp->if_oerrors++;
 1791                         if (txstat & MX_TXSTAT_EXCESSCOLL)
 1792                                 ifp->if_collisions++;
 1793                         if (txstat & MX_TXSTAT_LATECOLL)
 1794                                 ifp->if_collisions++;
 1795                 }
 1796 
 1797                 ifp->if_collisions += (txstat & MX_TXSTAT_COLLCNT) >> 3;
 1798 
 1799                 ifp->if_opackets++;
 1800                 m_freem(cur_tx->mx_mbuf);
 1801                 cur_tx->mx_mbuf = NULL;
 1802 
 1803                 if (sc->mx_cdata.mx_tx_head == sc->mx_cdata.mx_tx_tail) {
 1804                         sc->mx_cdata.mx_tx_head = NULL;
 1805                         sc->mx_cdata.mx_tx_tail = NULL;
 1806                         break;
 1807                 }
 1808 
 1809                 sc->mx_cdata.mx_tx_head = cur_tx->mx_nextdesc;
 1810         }
 1811 
 1812         return;
 1813 }
 1814 
 1815 /*
 1816  * TX 'end of channel' interrupt handler.
 1817  */
 1818 static void mx_txeoc(sc)
 1819         struct mx_softc         *sc;
 1820 {
 1821         struct ifnet            *ifp;
 1822 
 1823         ifp = &sc->arpcom.ac_if;
 1824 
 1825         ifp->if_timer = 0;
 1826 
 1827         if (sc->mx_cdata.mx_tx_head == NULL) {
 1828                 ifp->if_flags &= ~IFF_OACTIVE;
 1829                 sc->mx_cdata.mx_tx_tail = NULL;
 1830                 if (sc->mx_want_auto) {
 1831                         if (sc->mx_type == MX_TYPE_98713 &&
 1832                                                 sc->mx_pinfo != NULL)
 1833                                 mx_autoneg_mii(sc, MX_FLAG_DELAYTIMEO, 1);
 1834                         else
 1835                                 mx_autoneg(sc, MX_FLAG_DELAYTIMEO, 1);
 1836                 }
 1837         }
 1838 
 1839         return;
 1840 }
 1841 
 1842 static void mx_intr(arg)
 1843         void                    *arg;
 1844 {
 1845         struct mx_softc         *sc;
 1846         struct ifnet            *ifp;
 1847         u_int32_t               status;
 1848 
 1849         sc = arg;
 1850         ifp = &sc->arpcom.ac_if;
 1851 
 1852         /* Supress unwanted interrupts */
 1853         if (!(ifp->if_flags & IFF_UP)) {
 1854                 mx_stop(sc);
 1855                 return;
 1856         }
 1857 
 1858         /* Disable interrupts. */
 1859         CSR_WRITE_4(sc, MX_IMR, 0x00000000);
 1860 
 1861         for (;;) {
 1862                 status = CSR_READ_4(sc, MX_ISR);
 1863                 if (status)
 1864                         CSR_WRITE_4(sc, MX_ISR, status);
 1865 
 1866                 if ((status & MX_INTRS) == 0)
 1867                         break;
 1868 
 1869                 if (status & MX_ISR_TX_OK)
 1870                         mx_txeof(sc);
 1871 
 1872                 if (status & MX_ISR_TX_NOBUF)
 1873                         mx_txeoc(sc);
 1874 
 1875                 if (status & MX_ISR_TX_IDLE) {
 1876                         mx_txeof(sc);
 1877                         if (sc->mx_cdata.mx_tx_head != NULL) {
 1878                                 MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_TX_ON);
 1879                                 CSR_WRITE_4(sc, MX_TXSTART, 0xFFFFFFFF);
 1880                         }
 1881                 }
 1882 
 1883                 if (status & MX_ISR_TX_UNDERRUN) {
 1884                         u_int32_t               cfg;
 1885                         cfg = CSR_READ_4(sc, MX_NETCFG);
 1886                         if ((cfg & MX_NETCFG_TX_THRESH) == MX_TXTHRESH_160BYTES)
 1887                                 MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_STORENFWD);
 1888                         else
 1889                                 CSR_WRITE_4(sc, MX_NETCFG, cfg + 0x4000);
 1890                 }
 1891 
 1892                 if (status & MX_ISR_RX_OK)
 1893                         mx_rxeof(sc);
 1894 
 1895                 if ((status & MX_ISR_RX_WATDOGTIMEO)
 1896                                         || (status & MX_ISR_RX_NOBUF))
 1897                         mx_rxeoc(sc);
 1898 
 1899                 if (status & MX_ISR_BUS_ERR) {
 1900                         mx_reset(sc);
 1901                         mx_init(sc);
 1902                 }
 1903         }
 1904 
 1905         /* Re-enable interrupts. */
 1906         CSR_WRITE_4(sc, MX_IMR, MX_INTRS);
 1907 
 1908         if (ifp->if_snd.ifq_head != NULL) {
 1909                 mx_start(ifp);
 1910         }
 1911 
 1912         return;
 1913 }
 1914 
 1915 /*
 1916  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
 1917  * pointers to the fragment pointers.
 1918  */
 1919 static int mx_encap(sc, c, m_head)
 1920         struct mx_softc         *sc;
 1921         struct mx_chain         *c;
 1922         struct mbuf             *m_head;
 1923 {
 1924         int                     frag = 0;
 1925         struct mx_desc          *f = NULL;
 1926         int                     total_len;
 1927         struct mbuf             *m;
 1928 
 1929         /*
 1930          * Start packing the mbufs in this chain into
 1931          * the fragment pointers. Stop when we run out
 1932          * of fragments or hit the end of the mbuf chain.
 1933          */
 1934         m = m_head;
 1935         total_len = 0;
 1936 
 1937         for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
 1938                 if (m->m_len != 0) {
 1939                         if (frag == MX_MAXFRAGS)
 1940                                 break;
 1941                         total_len += m->m_len;
 1942                         f = &c->mx_ptr->mx_frag[frag];
 1943                         f->mx_ctl = MX_TXCTL_TLINK | m->m_len;
 1944                         if (frag == 0) {
 1945                                 f->mx_status = 0;
 1946                                 f->mx_ctl |= MX_TXCTL_FIRSTFRAG;
 1947                         } else
 1948                                 f->mx_status = MX_TXSTAT_OWN;
 1949                         f->mx_next = vtophys(&c->mx_ptr->mx_frag[frag + 1]);
 1950                         f->mx_data = vtophys(mtod(m, vm_offset_t));
 1951                         frag++;
 1952                 }
 1953         }
 1954 
 1955         /*
 1956          * Handle special case: we ran out of fragments,
 1957          * but we have more mbufs left in the chain. Copy the
 1958          * data into an mbuf cluster. Note that we don't
 1959          * bother clearing the values in the other fragment
 1960          * pointers/counters; it wouldn't gain us anything,
 1961          * and would waste cycles.
 1962          */
 1963         if (m != NULL) {
 1964                 struct mbuf             *m_new = NULL;
 1965 
 1966                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1967                 if (m_new == NULL) {
 1968                         printf("mx%d: no memory for tx list", sc->mx_unit);
 1969                         return(1);
 1970                 }
 1971                 if (m_head->m_pkthdr.len > MHLEN) {
 1972                         MCLGET(m_new, M_DONTWAIT);
 1973                         if (!(m_new->m_flags & M_EXT)) {
 1974                                 m_freem(m_new);
 1975                                 printf("mx%d: no memory for tx list",
 1976                                                 sc->mx_unit);
 1977                                 return(1);
 1978                         }
 1979                 }
 1980                 m_copydata(m_head, 0, m_head->m_pkthdr.len,     
 1981                                         mtod(m_new, caddr_t));
 1982                 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
 1983                 m_freem(m_head);
 1984                 m_head = m_new;
 1985                 f = &c->mx_ptr->mx_frag[0];
 1986                 f->mx_status = 0;
 1987                 f->mx_data = vtophys(mtod(m_new, caddr_t));
 1988                 f->mx_ctl = total_len = m_new->m_len;
 1989                 f->mx_ctl |= MX_TXCTL_TLINK|MX_TXCTL_FIRSTFRAG;
 1990                 frag = 1;
 1991         }
 1992 
 1993 
 1994         if (total_len < MX_MIN_FRAMELEN) {
 1995                 f = &c->mx_ptr->mx_frag[frag];
 1996                 f->mx_ctl = MX_MIN_FRAMELEN - total_len;
 1997                 f->mx_data = vtophys(&sc->mx_cdata.mx_pad);
 1998                 f->mx_ctl |= MX_TXCTL_TLINK;
 1999                 f->mx_status = MX_TXSTAT_OWN;
 2000                 frag++;
 2001         }
 2002 
 2003         c->mx_mbuf = m_head;
 2004         c->mx_lastdesc = frag - 1;
 2005         MX_TXCTL(c) |= MX_TXCTL_LASTFRAG|MX_TXCTL_FINT;
 2006         MX_TXNEXT(c) = vtophys(&c->mx_nextdesc->mx_ptr->mx_frag[0]);
 2007         return(0);
 2008 }
 2009 
 2010 /*
 2011  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 2012  * to the mbuf data regions directly in the transmit lists. We also save a
 2013  * copy of the pointers since the transmit list fragment pointers are
 2014  * physical addresses.
 2015  */
 2016 
 2017 static void mx_start(ifp)
 2018         struct ifnet            *ifp;
 2019 {
 2020         struct mx_softc         *sc;
 2021         struct mbuf             *m_head = NULL;
 2022         struct mx_chain         *cur_tx = NULL, *start_tx;
 2023 
 2024         sc = ifp->if_softc;
 2025 
 2026         if (sc->mx_autoneg) {
 2027                 sc->mx_tx_pend = 1;
 2028                 return;
 2029         }
 2030 
 2031         if (ifp->if_flags & IFF_OACTIVE)
 2032                 return;
 2033 
 2034         /*
 2035          * Check for an available queue slot. If there are none,
 2036          * punt.
 2037          */
 2038         if (sc->mx_cdata.mx_tx_free->mx_mbuf != NULL) {
 2039                 ifp->if_flags |= IFF_OACTIVE;
 2040                 return;
 2041         }
 2042 
 2043         start_tx = sc->mx_cdata.mx_tx_free;
 2044 
 2045         while(sc->mx_cdata.mx_tx_free->mx_mbuf == NULL) {
 2046                 IF_DEQUEUE(&ifp->if_snd, m_head);
 2047                 if (m_head == NULL)
 2048                         break;
 2049 
 2050                 /* Pick a descriptor off the free list. */
 2051                 cur_tx = sc->mx_cdata.mx_tx_free;
 2052                 sc->mx_cdata.mx_tx_free = cur_tx->mx_nextdesc;
 2053 
 2054                 /* Pack the data into the descriptor. */
 2055                 mx_encap(sc, cur_tx, m_head);
 2056                 if (cur_tx != start_tx)
 2057                         MX_TXOWN(cur_tx) = MX_TXSTAT_OWN;
 2058 
 2059 #if NBPFILTER > 0
 2060                 /*
 2061                  * If there's a BPF listener, bounce a copy of this frame
 2062                  * to him.
 2063                  */
 2064                 if (ifp->if_bpf)
 2065                         bpf_mtap(ifp, cur_tx->mx_mbuf);
 2066 #endif
 2067                 MX_TXOWN(cur_tx) = MX_TXSTAT_OWN;
 2068                 CSR_WRITE_4(sc, MX_TXSTART, 0xFFFFFFFF);
 2069 
 2070         }
 2071 
 2072         /*
 2073          * If there are no frames queued, bail.
 2074          */
 2075         if (cur_tx == NULL)
 2076                 return;
 2077 
 2078         sc->mx_cdata.mx_tx_tail = cur_tx;
 2079 
 2080         if (sc->mx_cdata.mx_tx_head == NULL)
 2081                 sc->mx_cdata.mx_tx_head = start_tx;
 2082 
 2083         /*
 2084          * Set a timeout in case the chip goes out to lunch.
 2085          */
 2086         ifp->if_timer = 5;
 2087 
 2088         return;
 2089 }
 2090 
 2091 static void mx_init(xsc)
 2092         void                    *xsc;
 2093 {
 2094         struct mx_softc         *sc = xsc;
 2095         struct ifnet            *ifp = &sc->arpcom.ac_if;
 2096         u_int16_t               phy_bmcr = 0;
 2097         int                     s;
 2098 
 2099         if (sc->mx_autoneg)
 2100                 return;
 2101 
 2102         s = splimp();
 2103 
 2104         if (sc->mx_pinfo != NULL)
 2105                 phy_bmcr = mx_phy_readreg(sc, PHY_BMCR);
 2106 
 2107         /*
 2108          * Cancel pending I/O and free all RX/TX buffers.
 2109          */
 2110         mx_stop(sc);
 2111         mx_reset(sc);
 2112 
 2113         /*
 2114          * Set cache alignment and burst length.
 2115          */
 2116         CSR_WRITE_4(sc, MX_BUSCTL, MX_BUSCTL_MUSTBEONE|MX_BUSCTL_ARBITRATION);
 2117         MX_SETBIT(sc, MX_BUSCTL, MX_BURSTLEN_16LONG);
 2118         switch(sc->mx_cachesize) {
 2119         case 32:
 2120                 MX_SETBIT(sc, MX_BUSCTL, MX_CACHEALIGN_32LONG);
 2121                 break;
 2122         case 16:
 2123                 MX_SETBIT(sc, MX_BUSCTL, MX_CACHEALIGN_16LONG);
 2124                 break; 
 2125         case 8:
 2126                 MX_SETBIT(sc, MX_BUSCTL, MX_CACHEALIGN_8LONG);
 2127                 break;  
 2128         case 0:
 2129         default:
 2130                 MX_SETBIT(sc, MX_BUSCTL, MX_CACHEALIGN_NONE);
 2131                 break;
 2132         }
 2133 
 2134         MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_NO_RXCRC);
 2135         MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_HEARTBEAT);
 2136         MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_STORENFWD);
 2137         MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_TX_BACKOFF);
 2138 
 2139         /*
 2140          * The app notes for the 98713 and 98715A say that
 2141          * in order to have the chips operate properly, a magic
 2142          * number must be written to CSR16. Macronix does not
 2143          * document the meaning of these bits so there's no way
 2144          * to know exactly what they mean. The 98713 has a magic
 2145          * number all its own; the rest all use a different one.
 2146          */
 2147         MX_CLRBIT(sc, MX_MAGICPACKET, 0xFFFF0000);
 2148         if (sc->mx_type == MX_TYPE_98713)
 2149                 MX_SETBIT(sc, MX_MAGICPACKET, MX_MAGIC_98713);
 2150         else
 2151                 MX_SETBIT(sc, MX_MAGICPACKET, MX_MAGIC_98715);
 2152 
 2153         if (sc->mx_pinfo != NULL) {
 2154                 MX_SETBIT(sc, MX_WATCHDOG, MX_WDOG_JABBERDIS);
 2155                 mx_setcfg(sc, mx_phy_readreg(sc, PHY_BMCR));
 2156         } else
 2157                 mx_setmode(sc, sc->ifmedia.ifm_media, 0);
 2158 
 2159         MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_TX_THRESH);
 2160         /*MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_SPEEDSEL);*/
 2161 
 2162         if (IFM_SUBTYPE(sc->ifmedia.ifm_media) == IFM_10_T)
 2163                 MX_SETBIT(sc, MX_NETCFG, MX_TXTHRESH_160BYTES);
 2164         else
 2165                 MX_SETBIT(sc, MX_NETCFG, MX_TXTHRESH_72BYTES);
 2166 
 2167         /* Init circular RX list. */
 2168         if (mx_list_rx_init(sc) == ENOBUFS) {
 2169                 printf("mx%d: initialization failed: no "
 2170                         "memory for rx buffers\n", sc->mx_unit);
 2171                 mx_stop(sc);
 2172                 (void)splx(s);
 2173                 return;
 2174         }
 2175 
 2176         /*
 2177          * Init tx descriptors.
 2178          */
 2179         mx_list_tx_init(sc);
 2180 
 2181         /*
 2182          * Load the address of the RX list.
 2183          */
 2184         CSR_WRITE_4(sc, MX_RXADDR, vtophys(sc->mx_cdata.mx_rx_head->mx_ptr));
 2185 
 2186         /*
 2187          * Load the RX/multicast filter.
 2188          */
 2189         mx_setfilt(sc);
 2190 
 2191         /*
 2192          * Enable interrupts.
 2193          */
 2194         CSR_WRITE_4(sc, MX_IMR, MX_INTRS);
 2195         CSR_WRITE_4(sc, MX_ISR, 0xFFFFFFFF);
 2196 
 2197         /* Enable receiver and transmitter. */
 2198         MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_TX_ON|MX_NETCFG_RX_ON);
 2199         CSR_WRITE_4(sc, MX_RXSTART, 0xFFFFFFFF);
 2200 
 2201         /* Restore state of BMCR */
 2202         if (sc->mx_pinfo != NULL)
 2203                 mx_phy_writereg(sc, PHY_BMCR, phy_bmcr);
 2204 
 2205         ifp->if_flags |= IFF_RUNNING;
 2206         ifp->if_flags &= ~IFF_OACTIVE;
 2207 
 2208         (void)splx(s);
 2209 
 2210         return;
 2211 }
 2212 
 2213 /*
 2214  * Set media options.
 2215  */
 2216 static int mx_ifmedia_upd(ifp)
 2217         struct ifnet            *ifp;
 2218 {
 2219         struct mx_softc         *sc;
 2220         struct ifmedia          *ifm;
 2221 
 2222         sc = ifp->if_softc;
 2223         ifm = &sc->ifmedia;
 2224 
 2225         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 2226                 return(EINVAL);
 2227 
 2228         if (sc->mx_type == MX_TYPE_98713 && sc->mx_pinfo != NULL) {
 2229                 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
 2230                         mx_autoneg_mii(sc, MX_FLAG_SCHEDDELAY, 1);
 2231                 else
 2232                         mx_setmode_mii(sc, ifm->ifm_media);
 2233         } else {
 2234                 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
 2235                         mx_autoneg(sc, MX_FLAG_SCHEDDELAY, 1);
 2236                 else
 2237                         mx_setmode(sc, ifm->ifm_media, 1);
 2238         }
 2239 
 2240         return(0);
 2241 }
 2242 
 2243 /*
 2244  * Report current media status.
 2245  */
 2246 static void mx_ifmedia_sts(ifp, ifmr)
 2247         struct ifnet            *ifp;
 2248         struct ifmediareq       *ifmr;
 2249 {
 2250         struct mx_softc         *sc;
 2251         u_int16_t               advert = 0, ability = 0;
 2252         u_int32_t               media = 0;
 2253 
 2254         sc = ifp->if_softc;
 2255 
 2256         ifmr->ifm_active = IFM_ETHER;
 2257 
 2258         if (sc->mx_type != MX_TYPE_98713 || sc->mx_pinfo == NULL) {
 2259                 media = CSR_READ_4(sc, MX_NETCFG);
 2260                 if (media & MX_NETCFG_PORTSEL)
 2261                         ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
 2262                 else
 2263                         ifmr->ifm_active = IFM_ETHER|IFM_10_T;
 2264                 if (media & MX_NETCFG_FULLDUPLEX)
 2265                         ifmr->ifm_active |= IFM_FDX;
 2266                 else
 2267                         ifmr->ifm_active |= IFM_HDX;
 2268                 return;
 2269         }
 2270 
 2271         if (!(mx_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
 2272                 if (mx_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
 2273                         ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
 2274                 else
 2275                         ifmr->ifm_active = IFM_ETHER|IFM_10_T;
 2276                 if (mx_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
 2277                         ifmr->ifm_active |= IFM_FDX;
 2278                 else
 2279                         ifmr->ifm_active |= IFM_HDX;
 2280                 return;
 2281         }
 2282 
 2283         ability = mx_phy_readreg(sc, PHY_LPAR);
 2284         advert = mx_phy_readreg(sc, PHY_ANAR);
 2285         if (advert & PHY_ANAR_100BTXFULL &&
 2286                 ability & PHY_ANAR_100BTXFULL) {
 2287                 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
 2288         } else if (advert & PHY_ANAR_100BTXHALF &&
 2289                 ability & PHY_ANAR_100BTXHALF) {
 2290                 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX;
 2291         } else if (advert & PHY_ANAR_10BTFULL &&
 2292                 ability & PHY_ANAR_10BTFULL) {
 2293                 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX;
 2294         } else if (advert & PHY_ANAR_10BTHALF &&
 2295                 ability & PHY_ANAR_10BTHALF) {
 2296                 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX;
 2297         }
 2298 
 2299         return;
 2300 }
 2301 
 2302 static int mx_ioctl(ifp, command, data)
 2303         struct ifnet            *ifp;
 2304         u_long                  command;
 2305         caddr_t                 data;
 2306 {
 2307         struct mx_softc         *sc = ifp->if_softc;
 2308         struct ifreq            *ifr = (struct ifreq *) data;
 2309         int                     s, error = 0;
 2310 
 2311         s = splimp();
 2312 
 2313         switch(command) {
 2314         case SIOCSIFADDR:
 2315         case SIOCGIFADDR:
 2316         case SIOCSIFMTU:
 2317                 error = ether_ioctl(ifp, command, data);
 2318                 break;
 2319         case SIOCSIFFLAGS:
 2320                 if (ifp->if_flags & IFF_UP) {
 2321                         mx_init(sc);
 2322                 } else {
 2323                         if (ifp->if_flags & IFF_RUNNING)
 2324                                 mx_stop(sc);
 2325                 }
 2326                 error = 0;
 2327                 break;
 2328         case SIOCADDMULTI:
 2329         case SIOCDELMULTI:
 2330                 mx_init(sc);
 2331                 error = 0;
 2332                 break;
 2333         case SIOCGIFMEDIA:
 2334         case SIOCSIFMEDIA:
 2335                 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
 2336                 break;
 2337         default:
 2338                 error = EINVAL;
 2339                 break;
 2340         }
 2341 
 2342         (void)splx(s);
 2343 
 2344         return(error);
 2345 }
 2346 
 2347 static void mx_watchdog(ifp)
 2348         struct ifnet            *ifp;
 2349 {
 2350         struct mx_softc         *sc;
 2351 
 2352         sc = ifp->if_softc;
 2353 
 2354         if (sc->mx_autoneg) {
 2355                 if (sc->mx_type == MX_TYPE_98713 && sc->mx_pinfo != NULL)
 2356                         mx_autoneg_mii(sc, MX_FLAG_DELAYTIMEO, 1);
 2357                 else
 2358                         mx_autoneg(sc, MX_FLAG_DELAYTIMEO, 1);
 2359                 return;
 2360         }
 2361 
 2362         ifp->if_oerrors++;
 2363         printf("mx%d: watchdog timeout\n", sc->mx_unit);
 2364 
 2365         if (sc->mx_pinfo == NULL) {
 2366                 if (!(CSR_READ_4(sc, MX_10BTSTAT) & MX_TSTAT_LS10) ||
 2367                         !(CSR_READ_4(sc, MX_10BTSTAT) & MX_TSTAT_LS100))
 2368                         printf("mx%d: no carrier - transceiver "
 2369                                 "cable problem?\n", sc->mx_unit);
 2370         } else {
 2371                 if (!(mx_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
 2372                         printf("mx%d: no carrier - transceiver "
 2373                                 "cable problem?\n", sc->mx_unit);
 2374         }
 2375 
 2376         mx_stop(sc);
 2377         mx_reset(sc);
 2378         mx_init(sc);
 2379 
 2380         if (ifp->if_snd.ifq_head != NULL)
 2381                 mx_start(ifp);
 2382 
 2383         return;
 2384 }
 2385 
 2386 /*
 2387  * Stop the adapter and free any mbufs allocated to the
 2388  * RX and TX lists.
 2389  */
 2390 static void mx_stop(sc)
 2391         struct mx_softc         *sc;
 2392 {
 2393         register int            i;
 2394         struct ifnet            *ifp;
 2395 
 2396         ifp = &sc->arpcom.ac_if;
 2397         ifp->if_timer = 0;
 2398 
 2399         MX_CLRBIT(sc, MX_NETCFG, (MX_NETCFG_RX_ON|MX_NETCFG_TX_ON));
 2400         CSR_WRITE_4(sc, MX_IMR, 0x00000000);
 2401         CSR_WRITE_4(sc, MX_TXADDR, 0x00000000);
 2402         CSR_WRITE_4(sc, MX_RXADDR, 0x00000000);
 2403 
 2404         /*
 2405          * Free data in the RX lists.
 2406          */
 2407         for (i = 0; i < MX_RX_LIST_CNT; i++) {
 2408                 if (sc->mx_cdata.mx_rx_chain[i].mx_mbuf != NULL) {
 2409                         m_freem(sc->mx_cdata.mx_rx_chain[i].mx_mbuf);
 2410                         sc->mx_cdata.mx_rx_chain[i].mx_mbuf = NULL;
 2411                 }
 2412         }
 2413         bzero((char *)&sc->mx_ldata->mx_rx_list,
 2414                 sizeof(sc->mx_ldata->mx_rx_list));
 2415 
 2416         /*
 2417          * Free the TX list buffers.
 2418          */
 2419         for (i = 0; i < MX_TX_LIST_CNT; i++) {
 2420                 if (sc->mx_cdata.mx_tx_chain[i].mx_mbuf != NULL) {
 2421                         m_freem(sc->mx_cdata.mx_tx_chain[i].mx_mbuf);
 2422                         sc->mx_cdata.mx_tx_chain[i].mx_mbuf = NULL;
 2423                 }
 2424         }
 2425 
 2426         bzero((char *)&sc->mx_ldata->mx_tx_list,
 2427                 sizeof(sc->mx_ldata->mx_tx_list));
 2428 
 2429         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 2430 
 2431         return;
 2432 }
 2433 
 2434 /*
 2435  * Stop all chip I/O so that the kernel's probe routines don't
 2436  * get confused by errant DMAs when rebooting.
 2437  */
 2438 static void mx_shutdown(howto, arg)
 2439         int                     howto;
 2440         void                    *arg;
 2441 {
 2442         struct mx_softc         *sc = (struct mx_softc *)arg;
 2443 
 2444         mx_stop(sc);
 2445 
 2446         return;
 2447 }
 2448 
 2449 static struct pci_device mx_device = {
 2450         "mx",
 2451         mx_probe,
 2452         mx_attach,
 2453         &mx_count,
 2454         NULL
 2455 };
 2456 DATA_SET(pcidevice_set, mx_device);

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