FreeBSD/Linux Kernel Cross Reference
sys/pci/if_mxreg.h
1 /*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD$
33 */
34
35 /*
36 * Macronix register definitions.
37 */
38
39 #define MX_BUSCTL 0x00 /* bus control */
40 #define MX_TXSTART 0x08 /* tx start demand */
41 #define MX_RXSTART 0x10 /* rx start demand */
42 #define MX_RXADDR 0x18 /* rx descriptor list start addr */
43 #define MX_TXADDR 0x20 /* tx descriptor list start addr */
44 #define MX_ISR 0x28 /* interrupt status register */
45 #define MX_NETCFG 0x30 /* network config register */
46 #define MX_IMR 0x38 /* interrupt mask */
47 #define MX_FRAMESDISCARDED 0x40 /* # of discarded frames */
48 #define MX_SIO 0x48 /* MII and ROM/EEPROM access */
49 #define MX_RESERVED 0x50
50 #define MX_TIMER 0x58 /* general timer */
51 #define MX_10BTSTAT 0x60
52 #define MX_SIARESET 0x68
53 #define MX_10BTCTRL 0x70
54 #define MX_WATCHDOG 0x78
55 #define MX_MAGICPACKET 0x80
56 #define MX_NWAYSTAT 0xA0
57
58 /*
59 * These are magic values that must be written into CSR16
60 * (MX_MAGICPACKET) in order to put the chip into proper
61 * operating mode. The magic numbers are documented in the
62 * Macronix 98715 application notes.
63 */
64 #define MX_MAGIC_98713 0x0F370000
65 #define MX_MAGIC_98713A 0x0B3C0000
66 #define MX_MAGIC_98715 0x0B3C0000
67 #define MX_MAGIC_98725 0x0B3C0000
68
69 #define MX_REVISION_98713 0x00
70 #define MX_REVISION_98713A 0x10
71 #define MX_REVISION_98715 0x20
72 #define MX_REVISION_98725 0x30
73
74 /*
75 * As far as the driver is concerned, there are two 'types' of
76 * chips to be concerned with. One is a 98713 with an external
77 * PHY on the MII. The other covers pretty much everything else,
78 * since all the other Macronix chips have built-in transceivers.
79 * This type setting governs what which mode selection routines
80 * we use (MII or built-in). It also govers which of the 'magic'
81 * numbers we write into CSR16.
82 */
83 #define MX_TYPE_98713 0x1
84 #define MX_TYPE_98713A 0x2
85 #define MX_TYPE_987x5 0x3
86
87 /*
88 * Bus control bits.
89 */
90 #define MX_BUSCTL_RESET 0x00000001
91 #define MX_BUSCTL_ARBITRATION 0x00000002
92 #define MX_BUSCTL_SKIPLEN 0x0000007C
93 #define MX_BUSCTL_BUF_BIGENDIAN 0x00000080
94 #define MX_BUSCTL_BURSTLEN 0x00003F00
95 #define MX_BUSCTL_CACHEALIGN 0x0000C000
96 #define MX_BUSCTL_TXPOLL 0x000E0000
97 #define MX_BUSCTL_MUSTBEONE 0x04000000
98
99 #define MX_SKIPLEN_1LONG 0x00000004
100 #define MX_SKIPLEN_2LONG 0x00000008
101 #define MX_SKIPLEN_3LONG 0x00000010
102 #define MX_SKIPLEN_4LONG 0x00000020
103 #define MX_SKIPLEN_5LONG 0x00000040
104
105 #define MX_CACHEALIGN_NONE 0x00000000
106 #define MX_CACHEALIGN_8LONG 0x00004000
107 #define MX_CACHEALIGN_16LONG 0x00008000
108 #define MX_CACHEALIGN_32LONG 0x0000C000
109
110 #define MX_BURSTLEN_USECA 0x00000000
111 #define MX_BURSTLEN_1LONG 0x00000100
112 #define MX_BURSTLEN_2LONG 0x00000200
113 #define MX_BURSTLEN_4LONG 0x00000400
114 #define MX_BURSTLEN_8LONG 0x00000800
115 #define MX_BURSTLEN_16LONG 0x00001000
116 #define MX_BURSTLEN_32LONG 0x00002000
117
118 #define MX_TXPOLL_OFF 0x00000000
119 #define MX_TXPOLL_200U 0x00020000
120 #define MX_TXPOLL_800U 0x00040000
121 #define MX_TXPOLL_1600U 0x00060000
122
123 #define MX_BUSCTL_CONFIG (MX_BUSCTL_ARBITRATION|MX_CACHEALIGN_8LONG| \
124 MX_BURSTLEN_8LONG)
125
126 /*
127 * Interrupt status bits.
128 */
129 #define MX_ISR_TX_OK 0x00000001
130 #define MX_ISR_TX_IDLE 0x00000002
131 #define MX_ISR_TX_NOBUF 0x00000004
132 #define MX_ISR_TX_JABBERTIMEO 0x00000008
133 #define MX_ISR_LINKGOOD 0x00000010
134 #define MX_ISR_TX_UNDERRUN 0x00000020
135 #define MX_ISR_RX_OK 0x00000040
136 #define MX_ISR_RX_NOBUF 0x00000080
137 #define MX_ISR_RX_READ 0x00000100
138 #define MX_ISR_RX_WATDOGTIMEO 0x00000200
139 #define MX_ISR_TX_EARLY 0x00000400
140 #define MX_ISR_TIMER_EXPIRED 0x00000800
141 #define MX_ISR_LINKFAIL 0x00001000
142 #define MX_ISR_BUS_ERR 0x00002000
143 #define MX_ISR_RX_EARLY 0x00004000
144 #define MX_ISR_ABNORMAL 0x00008000
145 #define MX_ISR_NORMAL 0x00010000
146 #define MX_ISR_RX_STATE 0x000E0000
147 #define MX_ISR_TX_STATE 0x00700000
148 #define MX_ISR_BUSERRTYPE 0x03800000
149 #define MX_ISR_100MBPSLINK 0x08000000
150 #define MX_ISR_MAGICKPACK 0x10000000
151
152 #define MX_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
153 #define MX_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
154 #define MX_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
155 #define MX_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
156 #define MX_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
157 #define MX_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
158 #define MX_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
159 #define MX_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
160
161 #define MX_TXSTATE_RESET 0x00000000 /* 000 - reset */
162 #define MX_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
163 #define MX_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
164 #define MX_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
165 #define MX_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
166 #define MX_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
167 #define MX_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
168 #define MX_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
169
170 /*
171 * Network config bits.
172 */
173 #define MX_NETCFG_RX_HASHPERF 0x00000001
174 #define MX_NETCFG_RX_ON 0x00000002
175 #define MX_NETCFG_RX_HASHONLY 0x00000004
176 #define MX_NETCFG_RX_BADFRAMES 0x00000008
177 #define MX_NETCFG_RX_INVFILT 0x00000010
178 #define MX_NETCFG_BACKOFFCNT 0x00000020
179 #define MX_NETCFG_RX_PROMISC 0x00000040
180 #define MX_NETCFG_RX_ALLMULTI 0x00000080
181 #define MX_NETCFG_FULLDUPLEX 0x00000200
182 #define MX_NETCFG_LOOPBACK 0x00000C00
183 #define MX_NETCFG_FORCECOLL 0x00001000
184 #define MX_NETCFG_TX_ON 0x00002000
185 #define MX_NETCFG_TX_THRESH 0x0000C000
186 #define MX_NETCFG_TX_BACKOFF 0x00020000
187 #define MX_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */
188 #define MX_NETCFG_HEARTBEAT 0x00080000
189 #define MX_NETCFG_STORENFWD 0x00200000
190 #define MX_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
191 #define MX_NETCFG_PCS 0x00800000
192 #define MX_NETCFG_SCRAMBLER 0x01000000
193 #define MX_NETCFG_NO_RXCRC 0x02000000
194
195 #define MX_OPMODE_NORM 0x00000000
196 #define MX_OPMODE_INTLOOP 0x00000400
197 #define MX_OPMODE_EXTLOOP 0x00000800
198
199 #define MX_TXTHRESH_72BYTES 0x00000000
200 #define MX_TXTHRESH_96BYTES 0x00004000
201 #define MX_TXTHRESH_128BYTES 0x00008000
202 #define MX_TXTHRESH_160BYTES 0x0000C000
203
204
205 /*
206 * Interrupt mask bits.
207 */
208 #define MX_IMR_TX_OK 0x00000001
209 #define MX_IMR_TX_IDLE 0x00000002
210 #define MX_IMR_TX_NOBUF 0x00000004
211 #define MX_IMR_TX_JABBERTIMEO 0x00000008
212 #define MX_IMR_LINKGOOD 0x00000010
213 #define MX_IMR_TX_UNDERRUN 0x00000020
214 #define MX_IMR_RX_OK 0x00000040
215 #define MX_IMR_RX_NOBUF 0x00000080
216 #define MX_IMR_RX_READ 0x00000100
217 #define MX_IMR_RX_WATDOGTIMEO 0x00000200
218 #define MX_IMR_TX_EARLY 0x00000400
219 #define MX_IMR_TIMER_EXPIRED 0x00000800
220 #define MX_IMR_LINKFAIL 0x00001000
221 #define MX_IMR_BUS_ERR 0x00002000
222 #define MX_IMR_RX_EARLY 0x00004000
223 #define MX_IMR_ABNORMAL 0x00008000
224 #define MX_IMR_NORMAL 0x00010000
225 #define MX_IMR_100MBPSLINK 0x08000000
226 #define MX_IMR_MAGICKPACK 0x10000000
227
228 #define MX_INTRS \
229 (MX_IMR_RX_OK|MX_IMR_TX_OK|MX_IMR_RX_NOBUF|MX_IMR_RX_WATDOGTIMEO|\
230 MX_IMR_TX_NOBUF|MX_IMR_TX_UNDERRUN|MX_IMR_BUS_ERR| \
231 MX_IMR_ABNORMAL|MX_IMR_NORMAL/*|MX_IMR_TX_EARLY*/)
232 /*
233 * Serial I/O (EEPROM/ROM) bits.
234 */
235 #define MX_SIO_EE_CS 0x00000001 /* EEPROM chip select */
236 #define MX_SIO_EE_CLK 0x00000002 /* EEPROM clock */
237 #define MX_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
238 #define MX_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
239 #define MX_SIO_ROMDATA4 0x00000010
240 #define MX_SIO_ROMDATA5 0x00000020
241 #define MX_SIO_ROMDATA6 0x00000040
242 #define MX_SIO_ROMDATA7 0x00000080
243 #define MX_SIO_EESEL 0x00000800
244 #define MX_SIO_ROMSEL 0x00001000
245 #define MX_SIO_ROMCTL_WRITE 0x00002000
246 #define MX_SIO_ROMCTL_READ 0x00004000
247 #define MX_SIO_MII_CLK 0x00010000 /* MDIO clock */
248 #define MX_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
249 #define MX_SIO_MII_DIR 0x00040000 /* MDIO dir */
250 #define MX_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
251
252 #define MX_EECMD_WRITE 0x140
253 #define MX_EECMD_READ 0x180
254 #define MX_EECMD_ERASE 0x1c0
255
256 #define MX_EE_NODEADDR_OFFSET 0x70
257 #define MX_EE_NODEADDR 10
258
259 /*
260 * General purpose timer register
261 */
262 #define MX_TIMER_VALUE 0x0000FFFF
263 #define MX_TIMER_CONTINUUS 0x00010000
264
265 /*
266 * 10baseT status register
267 */
268 #define MX_TSTAT_LS100 0x00000002 /* link status of 100baseTX */
269 #define MX_TSTAT_LS10 0x00000004 /* link status of 10baseT */
270 #define MX_TSTAT_AUTOPOLARITY 0x00000008
271 #define MX_TSTAT_REMFAULT 0x00000800
272 #define MX_TSTAT_ANEGSTAT 0x00007000
273 #define MX_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */
274 #define MX_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */
275
276 #define MX_ASTAT_DISABLE 0x00000000
277 #define MX_ASTAT_TXDISABLE 0x00001000
278 #define MX_ASTAT_ABDETECT 0x00002000
279 #define MX_ASTAT_ACKDETECT 0x00003000
280 #define MX_ASTAT_CMPACKDETECT 0x00004000
281 #define MX_ASTAT_AUTONEGCMP 0x00005000
282 #define MX_ASTAT_LINKCHECK 0x00006000
283
284 /*
285 * PHY reset register
286 */
287 #define MX_SIA_RESET_NWAY 0x00000001
288 #define MX_SIA_RESET_100TX 0x00000002
289
290 /*
291 * 10baseT control register
292 */
293 #define MX_TCTL_LOOPBACK 0x00000002
294 #define MX_TCTL_POWERDOWN 0x00000004
295 #define MX_TCTL_HALFDUPLEX 0x00000040
296 #define MX_TCTL_AUTONEGENBL 0x00000080
297 #define MX_TCTL_RX_SQUELCH 0x00000100
298 #define MX_TCTL_LINKTEST 0x00001000
299 #define MX_TCTL_100BTXHALF 0x00010000
300 #define MX_TCTL_100BTXFULL 0x00020000
301 #define MX_TCTL_100BT4 0x00040000
302
303 /*
304 * Watchdog timer register
305 */
306 #define MX_WDOG_JABBERDIS 0x00000001
307 #define MX_WDOG_HOSTUNJAB 0x00000002
308 #define MX_WDOG_JABBERCLK 0x00000004
309 #define MX_WDOG_RXWDOGDIS 0x00000010
310 #define MX_WDOG_RXWDOGCLK 0x00000020
311 #define MX_WDOG_MUSTBEZERO 0x00000100
312
313 /*
314 * Magic packet register
315 */
316 #define MX_MPACK_DISABLE 0x00400000
317
318 /*
319 * NWAY status register.
320 */
321 #define MX_NWAY_10BTHALF 0x08000000
322 #define MX_NWAY_10BTFULL 0x10000000
323 #define MX_NWAY_100BTHALF 0x20000000
324 #define MX_NWAY_100BTFULL 0x40000000
325 #define MX_NWAY_100BT4 0x80000000
326
327 /*
328 * Size of a setup frame.
329 */
330 #define MX_SFRAME_LEN 192
331
332 /*
333 * Macronix TX/RX list structure.
334 */
335
336 struct mx_desc {
337 u_int32_t mx_status;
338 u_int32_t mx_ctl;
339 u_int32_t mx_ptr1;
340 u_int32_t mx_ptr2;
341 };
342
343 #define mx_data mx_ptr1
344 #define mx_next mx_ptr2
345
346 #define MX_RXSTAT_FIFOOFLOW 0x00000001
347 #define MX_RXSTAT_CRCERR 0x00000002
348 #define MX_RXSTAT_DRIBBLE 0x00000004
349 #define MX_RXSTAT_WATCHDOG 0x00000010
350 #define MX_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
351 #define MX_RXSTAT_COLLSEEN 0x00000040
352 #define MX_RXSTAT_GIANT 0x00000080
353 #define MX_RXSTAT_LASTFRAG 0x00000100
354 #define MX_RXSTAT_FIRSTFRAG 0x00000200
355 #define MX_RXSTAT_MULTICAST 0x00000400
356 #define MX_RXSTAT_RUNT 0x00000800
357 #define MX_RXSTAT_RXTYPE 0x00003000
358 #define MX_RXSTAT_RXERR 0x00008000
359 #define MX_RXSTAT_RXLEN 0x3FFF0000
360 #define MX_RXSTAT_OWN 0x80000000
361
362 #define MX_RXBYTES(x) ((x & MX_RXSTAT_RXLEN) >> 16)
363 #define MX_RXSTAT (MX_RXSTAT_FIRSTFRAG|MX_RXSTAT_LASTFRAG|MX_RXSTAT_OWN)
364
365 #define MX_RXCTL_BUFLEN1 0x00000FFF
366 #define MX_RXCTL_BUFLEN2 0x00FFF000
367 #define MX_RXCTL_RLINK 0x01000000
368 #define MX_RXCTL_RLAST 0x02000000
369
370 #define MX_TXSTAT_DEFER 0x00000001
371 #define MX_TXSTAT_UNDERRUN 0x00000002
372 #define MX_TXSTAT_LINKFAIl 0x00000003
373 #define MX_TXSTAT_COLLCNT 0x00000078
374 #define MX_TXSTAT_SQE 0x00000080
375 #define MX_TXSTAT_EXCESSCOLL 0x00000100
376 #define MX_TXSTAT_LATECOLL 0x00000200
377 #define MX_TXSTAT_NOCARRIER 0x00000400
378 #define MX_TXSTAT_CARRLOST 0x00000800
379 #define MX_TXSTAT_JABTIMEO 0x00004000
380 #define MX_TXSTAT_ERRSUM 0x00008000
381 #define MX_TXSTAT_OWN 0x80000000
382
383 #define MX_TXCTL_BUFLEN1 0x000007FF
384 #define MX_TXCTL_BUFLEN2 0x003FF800
385 #define MX_TXCTL_FILTTYPE0 0x00400000
386 #define MX_TXCTL_PAD 0x00800000
387 #define MX_TXCTL_TLINK 0x01000000
388 #define MX_TXCTL_TLAST 0x02000000
389 #define MX_TXCTL_NOCRC 0x04000000
390 #define MX_TXCTL_SETUP 0x08000000
391 #define MX_TXCTL_FILTTYPE1 0x10000000
392 #define MX_TXCTL_FIRSTFRAG 0x20000000
393 #define MX_TXCTL_LASTFRAG 0x40000000
394 #define MX_TXCTL_FINT 0x80000000
395
396 #define MX_FILTER_PERFECT 0x00000000
397 #define MX_FILTER_HASHPERF 0x00400000
398 #define MX_FILTER_INVERSE 0x10000000
399 #define MX_FILTER_HASHONLY 0x10400000
400
401 #define MX_MAXFRAGS 16
402 #define MX_RX_LIST_CNT 64
403 #define MX_TX_LIST_CNT 128
404 #define MX_MIN_FRAMELEN 60
405
406 /*
407 * A tx 'super descriptor' is actually 16 regular descriptors
408 * back to back.
409 */
410 struct mx_txdesc {
411 struct mx_desc mx_frag[MX_MAXFRAGS];
412 };
413
414 #define MX_TXNEXT(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_next
415 #define MX_TXSTATUS(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_status
416 #define MX_TXCTL(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_ctl
417 #define MX_TXDATA(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_data
418
419 #define MX_TXOWN(x) x->mx_ptr->mx_frag[0].mx_status
420
421 struct mx_list_data {
422 struct mx_desc mx_rx_list[MX_RX_LIST_CNT];
423 struct mx_txdesc mx_tx_list[MX_TX_LIST_CNT];
424 };
425
426 struct mx_chain {
427 struct mx_txdesc *mx_ptr;
428 struct mbuf *mx_mbuf;
429 struct mx_chain *mx_nextdesc;
430 u_int8_t mx_lastdesc;
431 };
432
433 struct mx_chain_onefrag {
434 struct mx_desc *mx_ptr;
435 struct mbuf *mx_mbuf;
436 struct mx_chain_onefrag *mx_nextdesc;
437 };
438
439 struct mx_chain_data {
440 struct mx_desc mx_sframe;
441 u_int32_t mx_sbuf[MX_SFRAME_LEN/sizeof(u_int32_t)];
442 u_int8_t mx_pad[MX_MIN_FRAMELEN];
443 struct mx_chain_onefrag mx_rx_chain[MX_RX_LIST_CNT];
444 struct mx_chain mx_tx_chain[MX_TX_LIST_CNT];
445
446 struct mx_chain_onefrag *mx_rx_head;
447
448 struct mx_chain *mx_tx_head;
449 struct mx_chain *mx_tx_tail;
450 struct mx_chain *mx_tx_free;
451 };
452
453 struct mx_type {
454 u_int16_t mx_vid;
455 u_int16_t mx_did;
456 char *mx_name;
457 };
458
459 struct mx_mii_frame {
460 u_int8_t mii_stdelim;
461 u_int8_t mii_opcode;
462 u_int8_t mii_phyaddr;
463 u_int8_t mii_regaddr;
464 u_int8_t mii_turnaround;
465 u_int16_t mii_data;
466 };
467
468 /*
469 * MII constants
470 */
471 #define MX_MII_STARTDELIM 0x01
472 #define MX_MII_READOP 0x02
473 #define MX_MII_WRITEOP 0x01
474 #define MX_MII_TURNAROUND 0x02
475
476 #define MX_FLAG_FORCEDELAY 1
477 #define MX_FLAG_SCHEDDELAY 2
478 #define MX_FLAG_DELAYTIMEO 3
479
480 struct mx_softc {
481 struct arpcom arpcom; /* interface info */
482 struct ifmedia ifmedia; /* media info */
483 bus_space_handle_t mx_bhandle; /* bus space handle */
484 bus_space_tag_t mx_btag; /* bus space tag */
485 struct mx_type *mx_info; /* Macronix adapter info */
486 struct mx_type *mx_pinfo; /* phy info */
487 u_int8_t mx_unit; /* interface number */
488 u_int8_t mx_type;
489 u_int8_t mx_phy_addr; /* PHY address */
490 u_int8_t mx_tx_pend; /* TX pending */
491 u_int8_t mx_want_auto;
492 u_int8_t mx_autoneg;
493 u_int8_t mx_cachesize;
494 caddr_t mx_ldata_ptr;
495 struct mx_list_data *mx_ldata;
496 struct mx_chain_data mx_cdata;
497 };
498
499 /*
500 * register space access macros
501 */
502 #define CSR_WRITE_4(sc, reg, val) \
503 bus_space_write_4(sc->mx_btag, sc->mx_bhandle, reg, val)
504 #define CSR_WRITE_2(sc, reg, val) \
505 bus_space_write_2(sc->mx_btag, sc->mx_bhandle, reg, val)
506 #define CSR_WRITE_1(sc, reg, val) \
507 bus_space_write_1(sc->mx_btag, sc->mx_bhandle, reg, val)
508
509 #define CSR_READ_4(sc, reg) \
510 bus_space_read_4(sc->mx_btag, sc->mx_bhandle, reg)
511 #define CSR_READ_2(sc, reg) \
512 bus_space_read_2(sc->mx_btag, sc->mx_bhandle, reg)
513 #define CSR_READ_1(sc, reg) \
514 bus_space_read_1(sc->mx_btag, sc->mx_bhandle, reg)
515
516 #define MX_TIMEOUT 1000
517
518 /*
519 * General constants that are fun to know.
520 *
521 * Macronix PCI vendor ID
522 */
523 #define MX_VENDORID 0x10D9
524
525 /*
526 * Macronix PMAC device IDs.
527 */
528 #define MX_DEVICEID_98713 0x0512
529 #define MX_DEVICEID_987x5 0x0531
530
531 /*
532 * Compex PCI vendor ID.
533 */
534 #define CP_VENDORID 0x11F6
535
536 /*
537 * Compex PMAC PCI device IDs.
538 */
539 #define CP_DEVICEID_98713 0x9881
540
541 /*
542 * Lite-On PNIC PCI vendor ID
543 */
544 #define PN_VENDORID 0x11AD
545
546 /*
547 * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A
548 * with wake on lan/magic packet support.
549 */
550 #define PN_DEVICEID_PNIC_II 0xc115
551
552 /*
553 * Texas Instruments PHY identifiers
554 */
555 #define TI_PHY_VENDORID 0x4000
556 #define TI_PHY_10BT 0x501F
557 #define TI_PHY_100VGPMI 0x502F
558
559 /*
560 * These ID values are for the NS DP83840A 10/100 PHY
561 */
562 #define NS_PHY_VENDORID 0x2000
563 #define NS_PHY_83840A 0x5C0F
564
565 /*
566 * Level 1 10/100 PHY
567 */
568 #define LEVEL1_PHY_VENDORID 0x7810
569 #define LEVEL1_PHY_LXT970 0x000F
570
571 /*
572 * Intel 82555 10/100 PHY
573 */
574 #define INTEL_PHY_VENDORID 0x0A28
575 #define INTEL_PHY_82555 0x015F
576
577 /*
578 * SEEQ 80220 10/100 PHY
579 */
580 #define SEEQ_PHY_VENDORID 0x0016
581 #define SEEQ_PHY_80220 0xF83F
582
583
584 /*
585 * PCI low memory base and low I/O base register, and
586 * other PCI registers.
587 */
588
589 #define MX_PCI_VENDOR_ID 0x00
590 #define MX_PCI_DEVICE_ID 0x02
591 #define MX_PCI_COMMAND 0x04
592 #define MX_PCI_STATUS 0x06
593 #define MX_PCI_REVID 0x08
594 #define MX_PCI_CLASSCODE 0x09
595 #define MX_PCI_CACHELEN 0x0C
596 #define MX_PCI_LATENCY_TIMER 0x0D
597 #define MX_PCI_HEADER_TYPE 0x0E
598 #define MX_PCI_LOIO 0x10
599 #define MX_PCI_LOMEM 0x14
600 #define MX_PCI_BIOSROM 0x30
601 #define MX_PCI_INTLINE 0x3C
602 #define MX_PCI_INTPIN 0x3D
603 #define MX_PCI_MINGNT 0x3E
604 #define MX_PCI_MINLAT 0x0F
605 #define MX_PCI_RESETOPT 0x48
606 #define MX_PCI_EEPROM_DATA 0x4C
607
608 /* power management registers */
609 #define MX_PCI_CAPID 0x44 /* 8 bits */
610 #define MX_PCI_NEXTPTR 0x45 /* 8 bits */
611 #define MX_PCI_PWRMGMTCAP 0x46 /* 16 bits */
612 #define MX_PCI_PWRMGMTCTRL 0x48 /* 16 bits */
613
614 #define MX_PSTATE_MASK 0x0003
615 #define MX_PSTATE_D0 0x0000
616 #define MX_PSTATE_D1 0x0001
617 #define MX_PSTATE_D2 0x0002
618 #define MX_PSTATE_D3 0x0003
619 #define MX_PME_EN 0x0010
620 #define MX_PME_STATUS 0x8000
621
622 #define PHY_UNKNOWN 6
623
624 #define MX_PHYADDR_MIN 0x00
625 #define MX_PHYADDR_MAX 0x1F
626
627 #define PHY_BMCR 0x00
628 #define PHY_BMSR 0x01
629 #define PHY_VENID 0x02
630 #define PHY_DEVID 0x03
631 #define PHY_ANAR 0x04
632 #define PHY_LPAR 0x05
633 #define PHY_ANEXP 0x06
634
635 #define PHY_ANAR_NEXTPAGE 0x8000
636 #define PHY_ANAR_RSVD0 0x4000
637 #define PHY_ANAR_TLRFLT 0x2000
638 #define PHY_ANAR_RSVD1 0x1000
639 #define PHY_ANAR_RSVD2 0x0800
640 #define PHY_ANAR_RSVD3 0x0400
641 #define PHY_ANAR_100BT4 0x0200
642 #define PHY_ANAR_100BTXFULL 0x0100
643 #define PHY_ANAR_100BTXHALF 0x0080
644 #define PHY_ANAR_10BTFULL 0x0040
645 #define PHY_ANAR_10BTHALF 0x0020
646 #define PHY_ANAR_PROTO4 0x0010
647 #define PHY_ANAR_PROTO3 0x0008
648 #define PHY_ANAR_PROTO2 0x0004
649 #define PHY_ANAR_PROTO1 0x0002
650 #define PHY_ANAR_PROTO0 0x0001
651
652 /*
653 * These are the register definitions for the PHY (physical layer
654 * interface chip).
655 */
656 /*
657 * PHY BMCR Basic Mode Control Register
658 */
659 #define PHY_BMCR_RESET 0x8000
660 #define PHY_BMCR_LOOPBK 0x4000
661 #define PHY_BMCR_SPEEDSEL 0x2000
662 #define PHY_BMCR_AUTONEGENBL 0x1000
663 #define PHY_BMCR_RSVD0 0x0800 /* write as zero */
664 #define PHY_BMCR_ISOLATE 0x0400
665 #define PHY_BMCR_AUTONEGRSTR 0x0200
666 #define PHY_BMCR_DUPLEX 0x0100
667 #define PHY_BMCR_COLLTEST 0x0080
668 #define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
669 #define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
670 #define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
671 #define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
672 #define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
673 #define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
674 #define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
675 /*
676 * RESET: 1 == software reset, 0 == normal operation
677 * Resets status and control registers to default values.
678 * Relatches all hardware config values.
679 *
680 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
681 *
682 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
683 * Link speed is selected byt his bit or if auto-negotiation if bit
684 * 12 (AUTONEGENBL) is set (in which case the value of this register
685 * is ignored).
686 *
687 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
688 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
689 * determine speed and mode. Should be cleared and then set if PHY configured
690 * for no autoneg on startup.
691 *
692 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
693 *
694 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
695 *
696 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
697 *
698 * COLLTEST: 1 == collision test enabled, 0 == normal operation
699 */
700
701 /*
702 * PHY, BMSR Basic Mode Status Register
703 */
704 #define PHY_BMSR_100BT4 0x8000
705 #define PHY_BMSR_100BTXFULL 0x4000
706 #define PHY_BMSR_100BTXHALF 0x2000
707 #define PHY_BMSR_10BTFULL 0x1000
708 #define PHY_BMSR_10BTHALF 0x0800
709 #define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
710 #define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
711 #define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
712 #define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
713 #define PHY_BMSR_MFPRESUP 0x0040
714 #define PHY_BMSR_AUTONEGCOMP 0x0020
715 #define PHY_BMSR_REMFAULT 0x0010
716 #define PHY_BMSR_CANAUTONEG 0x0008
717 #define PHY_BMSR_LINKSTAT 0x0004
718 #define PHY_BMSR_JABBER 0x0002
719 #define PHY_BMSR_EXTENDED 0x0001
720
721 #ifdef __alpha__
722 #undef vtophys
723 #define vtophys(va) (pmap_kextract(((vm_offset_t) (va))) \
724 + 1*1024*1024*1024)
725 #endif
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