Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_pcn.c
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1 /* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36 /* 37 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available 38 * from http://www.amd.com. 39 * 40 * Written by Bill Paul <wpaul@osd.bsdi.com> 41 */ 42 43 /* 44 * The AMD PCnet/PCI controllers are more advanced and functional 45 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 46 * backwards compatibility with the LANCE and thus can be made 47 * to work with older LANCE drivers. This is in fact how the 48 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 49 * is that the PCnet/PCI devices offer several performance enhancements 50 * which can't be exploited in LANCE compatibility mode. Chief among 51 * these enhancements is the ability to perform PCI DMA operations 52 * using 32-bit addressing (which eliminates the need for ISA 53 * bounce-buffering), and special receive buffer alignment (which 54 * allows the receive handler to pass packets to the upper protocol 55 * layers without copying on both the x86 and alpha platforms). 56 */ 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/sockio.h> 61 #include <sys/mbuf.h> 62 #include <sys/malloc.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 66 #include <net/if.h> 67 #include <net/if_arp.h> 68 #include <net/ethernet.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 72 #include <net/bpf.h> 73 74 #include <vm/vm.h> /* for vtophys */ 75 #include <vm/pmap.h> /* for vtophys */ 76 #include <machine/clock.h> /* for DELAY */ 77 #include <machine/bus_pio.h> 78 #include <machine/bus_memio.h> 79 #include <machine/bus.h> 80 #include <machine/resource.h> 81 #include <sys/bus.h> 82 #include <sys/rman.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 87 #include <pci/pcireg.h> 88 #include <pci/pcivar.h> 89 90 #define PCN_USEIOSPACE 91 92 #include <pci/if_pcnreg.h> 93 94 /* "controller miibus0" required. See GENERIC if you get errors here. */ 95 #include "miibus_if.h" 96 97 #ifndef lint 98 static const char rcsid[] = 99 "$FreeBSD$"; 100 #endif 101 102 /* 103 * Various supported device vendors/types and their names. 104 */ 105 static struct pcn_type pcn_devs[] = { 106 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 107 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 108 { 0, 0, NULL } 109 }; 110 111 static u_int32_t pcn_csr_read __P((struct pcn_softc *, int)); 112 static u_int16_t pcn_csr_read16 __P((struct pcn_softc *, int)); 113 static u_int16_t pcn_bcr_read16 __P((struct pcn_softc *, int)); 114 static void pcn_csr_write __P((struct pcn_softc *, int, int)); 115 static u_int32_t pcn_bcr_read __P((struct pcn_softc *, int)); 116 static void pcn_bcr_write __P((struct pcn_softc *, int, int)); 117 118 static int pcn_probe __P((device_t)); 119 static int pcn_attach __P((device_t)); 120 static int pcn_detach __P((device_t)); 121 122 static int pcn_newbuf __P((struct pcn_softc *, int, struct mbuf *)); 123 static int pcn_encap __P((struct pcn_softc *, 124 struct mbuf *, u_int32_t *)); 125 static void pcn_rxeof __P((struct pcn_softc *)); 126 static void pcn_txeof __P((struct pcn_softc *)); 127 static void pcn_intr __P((void *)); 128 static void pcn_tick __P((void *)); 129 static void pcn_start __P((struct ifnet *)); 130 static int pcn_ioctl __P((struct ifnet *, u_long, caddr_t)); 131 static void pcn_init __P((void *)); 132 static void pcn_stop __P((struct pcn_softc *)); 133 static void pcn_watchdog __P((struct ifnet *)); 134 static void pcn_shutdown __P((device_t)); 135 static int pcn_ifmedia_upd __P((struct ifnet *)); 136 static void pcn_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 137 138 static int pcn_miibus_readreg __P((device_t, int, int)); 139 static int pcn_miibus_writereg __P((device_t, int, int, int)); 140 static void pcn_miibus_statchg __P((device_t)); 141 142 static void pcn_setfilt __P((struct ifnet *)); 143 static void pcn_setmulti __P((struct pcn_softc *)); 144 static u_int32_t pcn_crc __P((caddr_t)); 145 static void pcn_reset __P((struct pcn_softc *)); 146 static int pcn_list_rx_init __P((struct pcn_softc *)); 147 static int pcn_list_tx_init __P((struct pcn_softc *)); 148 149 #ifdef PCN_USEIOSPACE 150 #define PCN_RES SYS_RES_IOPORT 151 #define PCN_RID PCN_PCI_LOIO 152 #else 153 #define PCN_RES SYS_RES_MEMORY 154 #define PCN_RID PCN_PCI_LOMEM 155 #endif 156 157 static device_method_t pcn_methods[] = { 158 /* Device interface */ 159 DEVMETHOD(device_probe, pcn_probe), 160 DEVMETHOD(device_attach, pcn_attach), 161 DEVMETHOD(device_detach, pcn_detach), 162 DEVMETHOD(device_shutdown, pcn_shutdown), 163 164 /* bus interface */ 165 DEVMETHOD(bus_print_child, bus_generic_print_child), 166 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 167 168 /* MII interface */ 169 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 170 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 171 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 172 173 { 0, 0 } 174 }; 175 176 static driver_t pcn_driver = { 177 "pcn", 178 pcn_methods, 179 sizeof(struct pcn_softc) 180 }; 181 182 static devclass_t pcn_devclass; 183 184 DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0); 185 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 186 187 #define PCN_CSR_SETBIT(sc, reg, x) \ 188 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 189 190 #define PCN_CSR_CLRBIT(sc, reg, x) \ 191 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 192 193 #define PCN_BCR_SETBIT(sc, reg, x) \ 194 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 195 196 #define PCN_BCR_CLRBIT(sc, reg, x) \ 197 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 198 199 static u_int32_t pcn_csr_read(sc, reg) 200 struct pcn_softc *sc; 201 int reg; 202 { 203 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 204 return(CSR_READ_4(sc, PCN_IO32_RDP)); 205 } 206 207 static u_int16_t pcn_csr_read16(sc, reg) 208 struct pcn_softc *sc; 209 int reg; 210 { 211 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 212 return(CSR_READ_2(sc, PCN_IO16_RDP)); 213 } 214 215 static void pcn_csr_write(sc, reg, val) 216 struct pcn_softc *sc; 217 int reg; 218 { 219 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 220 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 221 return; 222 } 223 224 static u_int32_t pcn_bcr_read(sc, reg) 225 struct pcn_softc *sc; 226 int reg; 227 { 228 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 229 return(CSR_READ_4(sc, PCN_IO32_BDP)); 230 } 231 232 static u_int16_t pcn_bcr_read16(sc, reg) 233 struct pcn_softc *sc; 234 int reg; 235 { 236 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 237 return(CSR_READ_2(sc, PCN_IO16_BDP)); 238 } 239 240 static void pcn_bcr_write(sc, reg, val) 241 struct pcn_softc *sc; 242 int reg; 243 { 244 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 245 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 246 return; 247 } 248 249 static int pcn_miibus_readreg(dev, phy, reg) 250 device_t dev; 251 int phy, reg; 252 { 253 struct pcn_softc *sc; 254 int val; 255 256 sc = device_get_softc(dev); 257 258 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 259 return(0); 260 261 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 262 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 263 if (val == 0xFFFF) 264 return(0); 265 266 sc->pcn_phyaddr = phy; 267 268 return(val); 269 } 270 271 static int pcn_miibus_writereg(dev, phy, reg, data) 272 device_t dev; 273 int phy, reg, data; 274 { 275 struct pcn_softc *sc; 276 277 sc = device_get_softc(dev); 278 279 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 280 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 281 282 return(0); 283 } 284 285 static void pcn_miibus_statchg(dev) 286 device_t dev; 287 { 288 struct pcn_softc *sc; 289 struct mii_data *mii; 290 291 sc = device_get_softc(dev); 292 mii = device_get_softc(sc->pcn_miibus); 293 294 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 295 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 296 } else { 297 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 298 } 299 300 return; 301 } 302 303 #define DC_POLY 0xEDB88320 304 305 static u_int32_t pcn_crc(addr) 306 caddr_t addr; 307 { 308 u_int32_t idx, bit, data, crc; 309 310 /* Compute CRC for the address value. */ 311 crc = 0xFFFFFFFF; /* initial value */ 312 313 for (idx = 0; idx < 6; idx++) { 314 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 315 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 316 } 317 318 return ((crc >> 26) & 0x3F); 319 } 320 321 static void pcn_setmulti(sc) 322 struct pcn_softc *sc; 323 { 324 struct ifnet *ifp; 325 struct ifmultiaddr *ifma; 326 u_int32_t h, i; 327 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 328 329 ifp = &sc->arpcom.ac_if; 330 331 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 332 333 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 334 for (i = 0; i < 4; i++) 335 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 336 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 337 return; 338 } 339 340 /* first, zot all the existing hash bits */ 341 for (i = 0; i < 4; i++) 342 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 343 344 /* now program new ones */ 345 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 346 ifma = ifma->ifma_link.le_next) { 347 if (ifma->ifma_addr->sa_family != AF_LINK) 348 continue; 349 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 350 hashes[h >> 4] |= 1 << (h & 0xF); 351 } 352 353 for (i = 0; i < 4; i++) 354 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 355 356 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 357 358 return; 359 } 360 361 static void pcn_reset(sc) 362 struct pcn_softc *sc; 363 { 364 /* 365 * Issue a reset by reading from the RESET register. 366 * Note that we don't know if the chip is operating in 367 * 16-bit or 32-bit mode at this point, so we attempt 368 * to reset the chip both ways. If one fails, the other 369 * will succeed. 370 */ 371 CSR_READ_2(sc, PCN_IO16_RESET); 372 CSR_READ_4(sc, PCN_IO32_RESET); 373 374 /* Wait a little while for the chip to get its brains in order. */ 375 DELAY(1000); 376 377 /* Select 32-bit (DWIO) mode */ 378 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 379 380 /* Select software style 3. */ 381 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 382 383 return; 384 } 385 386 /* 387 * Probe for an AMD chip. Check the PCI vendor and device 388 * IDs against our list and return a device name if we find a match. 389 */ 390 static int pcn_probe(dev) 391 device_t dev; 392 { 393 struct pcn_type *t; 394 struct pcn_softc *sc; 395 int rid; 396 u_int32_t chip_id; 397 398 t = pcn_devs; 399 sc = device_get_softc(dev); 400 401 while(t->pcn_name != NULL) { 402 if ((pci_get_vendor(dev) == t->pcn_vid) && 403 (pci_get_device(dev) == t->pcn_did)) { 404 /* 405 * Temporarily map the I/O space 406 * so we can read the chip ID register. 407 */ 408 rid = PCN_RID; 409 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 410 0, ~0, 1, RF_ACTIVE); 411 if (sc->pcn_res == NULL) { 412 device_printf(dev, 413 "couldn't map ports/memory\n"); 414 return(ENXIO); 415 } 416 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 417 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 418 /* 419 * Note: we can *NOT* put the chip into 420 * 32-bit mode yet. The lnc driver will only 421 * work in 16-bit mode, and once the chip 422 * goes into 32-bit mode, the only way to 423 * get it out again is with a hardware reset. 424 * So if pcn_probe() is called before the 425 * lnc driver's probe routine, the chip will 426 * be locked into 32-bit operation and the lnc 427 * driver will be unable to attach to it. 428 * Note II: if the chip happens to already 429 * be in 32-bit mode, we still need to check 430 * the chip ID, but first we have to detect 431 * 32-bit mode using only 16-bit operations. 432 * The safest way to do this is to read the 433 * PCI subsystem ID from BCR23/24 and compare 434 * that with the value read from PCI config 435 * space. 436 */ 437 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 438 chip_id <<= 16; 439 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 440 /* 441 * Note III: the test for 0x10001000 is a hack to 442 * pacify VMware, who's pseudo-PCnet interface is 443 * broken. Reading the subsystem register from PCI 444 * config space yields 0x00000000 while reading the 445 * same value from I/O space yields 0x10001000. It's 446 * not supposed to be that way. 447 */ 448 if (chip_id == pci_read_config(dev, 449 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 450 /* We're in 16-bit mode. */ 451 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 452 chip_id <<= 16; 453 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 454 } else { 455 /* We're in 32-bit mode. */ 456 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 457 chip_id <<= 16; 458 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 459 } 460 bus_release_resource(dev, PCN_RES, 461 PCN_RID, sc->pcn_res); 462 chip_id >>= 12; 463 sc->pcn_type = chip_id & PART_MASK; 464 switch(sc->pcn_type) { 465 case Am79C971: 466 case Am79C972: 467 case Am79C973: 468 case Am79C975: 469 case Am79C976: 470 case Am79C978: 471 break; 472 default: 473 return(ENXIO); 474 break; 475 } 476 device_set_desc(dev, t->pcn_name); 477 return(0); 478 } 479 t++; 480 } 481 482 return(ENXIO); 483 } 484 485 /* 486 * Attach the interface. Allocate softc structures, do ifmedia 487 * setup and ethernet/BPF attach. 488 */ 489 static int pcn_attach(dev) 490 device_t dev; 491 { 492 int s; 493 u_int32_t eaddr[2]; 494 u_int32_t command; 495 struct pcn_softc *sc; 496 struct ifnet *ifp; 497 int unit, error = 0, rid; 498 499 s = splimp(); 500 501 sc = device_get_softc(dev); 502 unit = device_get_unit(dev); 503 504 /* 505 * Handle power management nonsense. 506 */ 507 508 command = pci_read_config(dev, PCN_PCI_CAPID, 4) & 0x000000FF; 509 if (command == 0x01) { 510 511 command = pci_read_config(dev, PCN_PCI_PWRMGMTCTRL, 4); 512 if (command & PCN_PSTATE_MASK) { 513 u_int32_t iobase, membase, irq; 514 515 /* Save important PCI config data. */ 516 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 517 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 518 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 519 520 /* Reset the power state. */ 521 printf("pcn%d: chip is in D%d power mode " 522 "-- setting to D0\n", unit, command & PCN_PSTATE_MASK); 523 command &= 0xFFFFFFFC; 524 pci_write_config(dev, PCN_PCI_PWRMGMTCTRL, command, 4); 525 526 /* Restore PCI config data. */ 527 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 528 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 529 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 530 } 531 } 532 533 /* 534 * Map control/status registers. 535 */ 536 command = pci_read_config(dev, PCIR_COMMAND, 4); 537 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 538 pci_write_config(dev, PCIR_COMMAND, command, 4); 539 command = pci_read_config(dev, PCIR_COMMAND, 4); 540 541 #ifdef PCN_USEIOSPACE 542 if (!(command & PCIM_CMD_PORTEN)) { 543 printf("pcn%d: failed to enable I/O ports!\n", unit); 544 error = ENXIO;; 545 goto fail; 546 } 547 #else 548 if (!(command & PCIM_CMD_MEMEN)) { 549 printf("pcn%d: failed to enable memory mapping!\n", unit); 550 error = ENXIO;; 551 goto fail; 552 } 553 #endif 554 555 rid = PCN_RID; 556 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 557 0, ~0, 1, RF_ACTIVE); 558 559 if (sc->pcn_res == NULL) { 560 printf("pcn%d: couldn't map ports/memory\n", unit); 561 error = ENXIO; 562 goto fail; 563 } 564 565 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 566 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 567 568 /* Allocate interrupt */ 569 rid = 0; 570 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 571 RF_SHAREABLE | RF_ACTIVE); 572 573 if (sc->pcn_irq == NULL) { 574 printf("pcn%d: couldn't map interrupt\n", unit); 575 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 576 error = ENXIO; 577 goto fail; 578 } 579 580 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 581 pcn_intr, sc, &sc->pcn_intrhand); 582 583 if (error) { 584 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_res); 585 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 586 printf("pcn%d: couldn't set up irq\n", unit); 587 goto fail; 588 } 589 590 /* Reset the adapter. */ 591 pcn_reset(sc); 592 593 /* 594 * Get station address from the EEPROM. 595 */ 596 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 597 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 598 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 599 600 /* 601 * An AMD chip was detected. Inform the world. 602 */ 603 printf("pcn%d: Ethernet address: %6D\n", unit, 604 sc->arpcom.ac_enaddr, ":"); 605 606 sc->pcn_unit = unit; 607 callout_handle_init(&sc->pcn_stat_ch); 608 609 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 610 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 611 612 if (sc->pcn_ldata == NULL) { 613 printf("pcn%d: no memory for list buffers!\n", unit); 614 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 615 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 616 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 617 error = ENXIO; 618 goto fail; 619 } 620 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 621 622 ifp = &sc->arpcom.ac_if; 623 ifp->if_softc = sc; 624 ifp->if_unit = unit; 625 ifp->if_name = "pcn"; 626 ifp->if_mtu = ETHERMTU; 627 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 628 ifp->if_ioctl = pcn_ioctl; 629 ifp->if_output = ether_output; 630 ifp->if_start = pcn_start; 631 ifp->if_watchdog = pcn_watchdog; 632 ifp->if_init = pcn_init; 633 ifp->if_baudrate = 10000000; 634 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 635 636 /* 637 * Do MII setup. 638 */ 639 if (mii_phy_probe(dev, &sc->pcn_miibus, 640 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 641 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 642 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 643 M_DEVBUF); 644 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 645 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 646 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 647 error = ENXIO; 648 goto fail; 649 } 650 651 /* 652 * Call MI attach routine. 653 */ 654 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 655 callout_handle_init(&sc->pcn_stat_ch); 656 657 fail: 658 splx(s); 659 return(error); 660 } 661 662 static int pcn_detach(dev) 663 device_t dev; 664 { 665 struct pcn_softc *sc; 666 struct ifnet *ifp; 667 int s; 668 669 s = splimp(); 670 671 sc = device_get_softc(dev); 672 ifp = &sc->arpcom.ac_if; 673 674 pcn_reset(sc); 675 pcn_stop(sc); 676 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 677 678 if (sc->pcn_miibus != NULL) { 679 bus_generic_detach(dev); 680 device_delete_child(dev, sc->pcn_miibus); 681 } 682 683 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 684 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 685 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 686 687 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), M_DEVBUF); 688 689 splx(s); 690 691 return(0); 692 } 693 694 /* 695 * Initialize the transmit descriptors. 696 */ 697 static int pcn_list_tx_init(sc) 698 struct pcn_softc *sc; 699 { 700 struct pcn_list_data *ld; 701 struct pcn_ring_data *cd; 702 int i; 703 704 cd = &sc->pcn_cdata; 705 ld = sc->pcn_ldata; 706 707 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 708 cd->pcn_tx_chain[i] = NULL; 709 ld->pcn_tx_list[i].pcn_tbaddr = 0; 710 ld->pcn_tx_list[i].pcn_txctl = 0; 711 ld->pcn_tx_list[i].pcn_txstat = 0; 712 } 713 714 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 715 716 return(0); 717 } 718 719 720 /* 721 * Initialize the RX descriptors and allocate mbufs for them. 722 */ 723 static int pcn_list_rx_init(sc) 724 struct pcn_softc *sc; 725 { 726 struct pcn_list_data *ld; 727 struct pcn_ring_data *cd; 728 int i; 729 730 ld = sc->pcn_ldata; 731 cd = &sc->pcn_cdata; 732 733 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 734 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 735 return(ENOBUFS); 736 } 737 738 cd->pcn_rx_prod = 0; 739 740 return(0); 741 } 742 743 /* 744 * Initialize an RX descriptor and attach an MBUF cluster. 745 */ 746 static int pcn_newbuf(sc, idx, m) 747 struct pcn_softc *sc; 748 int idx; 749 struct mbuf *m; 750 { 751 struct mbuf *m_new = NULL; 752 struct pcn_rx_desc *c; 753 754 c = &sc->pcn_ldata->pcn_rx_list[idx]; 755 756 if (m == NULL) { 757 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 758 if (m_new == NULL) 759 return(ENOBUFS); 760 761 MCLGET(m_new, M_DONTWAIT); 762 if (!(m_new->m_flags & M_EXT)) { 763 m_freem(m_new); 764 return(ENOBUFS); 765 } 766 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 767 } else { 768 m_new = m; 769 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 770 m_new->m_data = m_new->m_ext.ext_buf; 771 } 772 773 m_adj(m_new, ETHER_ALIGN); 774 775 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 776 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 777 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 778 c->pcn_bufsz |= PCN_RXLEN_MBO; 779 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 780 781 return(0); 782 } 783 784 /* 785 * A frame has been uploaded: pass the resulting mbuf chain up to 786 * the higher level protocols. 787 */ 788 static void pcn_rxeof(sc) 789 struct pcn_softc *sc; 790 { 791 struct ether_header *eh; 792 struct mbuf *m; 793 struct ifnet *ifp; 794 struct pcn_rx_desc *cur_rx; 795 int i; 796 797 ifp = &sc->arpcom.ac_if; 798 i = sc->pcn_cdata.pcn_rx_prod; 799 800 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 801 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 802 m = sc->pcn_cdata.pcn_rx_chain[i]; 803 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 804 805 /* 806 * If an error occurs, update stats, clear the 807 * status word and leave the mbuf cluster in place: 808 * it should simply get re-used next time this descriptor 809 * comes up in the ring. 810 */ 811 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 812 ifp->if_ierrors++; 813 pcn_newbuf(sc, i, m); 814 PCN_INC(i, PCN_RX_LIST_CNT); 815 continue; 816 } 817 818 if (pcn_newbuf(sc, i, NULL)) { 819 /* Ran out of mbufs; recycle this one. */ 820 pcn_newbuf(sc, i, m); 821 ifp->if_ierrors++; 822 PCN_INC(i, PCN_RX_LIST_CNT); 823 continue; 824 } 825 826 PCN_INC(i, PCN_RX_LIST_CNT); 827 828 /* No errors; receive the packet. */ 829 ifp->if_ipackets++; 830 eh = mtod(m, struct ether_header *); 831 m->m_len = m->m_pkthdr.len = 832 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 833 m->m_pkthdr.rcvif = ifp; 834 835 /* Remove header from mbuf and pass it on. */ 836 m_adj(m, sizeof(struct ether_header)); 837 ether_input(ifp, eh, m); 838 } 839 840 sc->pcn_cdata.pcn_rx_prod = i; 841 842 return; 843 } 844 845 /* 846 * A frame was downloaded to the chip. It's safe for us to clean up 847 * the list buffers. 848 */ 849 850 static void pcn_txeof(sc) 851 struct pcn_softc *sc; 852 { 853 struct pcn_tx_desc *cur_tx = NULL; 854 struct ifnet *ifp; 855 u_int32_t idx; 856 857 ifp = &sc->arpcom.ac_if; 858 859 /* 860 * Go through our tx list and free mbufs for those 861 * frames that have been transmitted. 862 */ 863 idx = sc->pcn_cdata.pcn_tx_cons; 864 while (idx != sc->pcn_cdata.pcn_tx_prod) { 865 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 866 867 if (!PCN_OWN_TXDESC(cur_tx)) 868 break; 869 870 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 871 sc->pcn_cdata.pcn_tx_cnt--; 872 PCN_INC(idx, PCN_TX_LIST_CNT); 873 continue; 874 } 875 876 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 877 ifp->if_oerrors++; 878 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 879 ifp->if_collisions++; 880 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 881 ifp->if_collisions++; 882 } 883 884 ifp->if_collisions += 885 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 886 887 ifp->if_opackets++; 888 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 889 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 890 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 891 } 892 893 sc->pcn_cdata.pcn_tx_cnt--; 894 PCN_INC(idx, PCN_TX_LIST_CNT); 895 } 896 897 if (idx != sc->pcn_cdata.pcn_tx_cons) { 898 /* Some buffers have been freed. */ 899 sc->pcn_cdata.pcn_tx_cons = idx; 900 ifp->if_flags &= ~IFF_OACTIVE; 901 } 902 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 903 904 return; 905 } 906 907 static void pcn_tick(xsc) 908 void *xsc; 909 { 910 struct pcn_softc *sc; 911 struct mii_data *mii; 912 struct ifnet *ifp; 913 int s; 914 915 s = splimp(); 916 917 sc = xsc; 918 ifp = &sc->arpcom.ac_if; 919 920 mii = device_get_softc(sc->pcn_miibus); 921 mii_tick(mii); 922 923 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 924 sc->pcn_link = 0; 925 926 if (!sc->pcn_link) { 927 mii_pollstat(mii); 928 if (mii->mii_media_status & IFM_ACTIVE && 929 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 930 sc->pcn_link++; 931 if (ifp->if_snd.ifq_head != NULL) 932 pcn_start(ifp); 933 } 934 935 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 936 937 splx(s); 938 939 return; 940 } 941 942 static void pcn_intr(arg) 943 void *arg; 944 { 945 struct pcn_softc *sc; 946 struct ifnet *ifp; 947 u_int32_t status; 948 949 sc = arg; 950 ifp = &sc->arpcom.ac_if; 951 952 /* Suppress unwanted interrupts */ 953 if (!(ifp->if_flags & IFF_UP)) { 954 pcn_stop(sc); 955 return; 956 } 957 958 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 959 960 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 961 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 962 963 if (status & PCN_CSR_RINT) 964 pcn_rxeof(sc); 965 966 if (status & PCN_CSR_TINT) 967 pcn_txeof(sc); 968 969 if (status & PCN_CSR_ERR) { 970 pcn_init(sc); 971 break; 972 } 973 } 974 975 if (ifp->if_snd.ifq_head != NULL) 976 pcn_start(ifp); 977 978 return; 979 } 980 981 /* 982 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 983 * pointers to the fragment pointers. 984 */ 985 static int pcn_encap(sc, m_head, txidx) 986 struct pcn_softc *sc; 987 struct mbuf *m_head; 988 u_int32_t *txidx; 989 { 990 struct pcn_tx_desc *f = NULL; 991 struct mbuf *m; 992 int frag, cur, cnt = 0; 993 994 /* 995 * Start packing the mbufs in this chain into 996 * the fragment pointers. Stop when we run out 997 * of fragments or hit the end of the mbuf chain. 998 */ 999 m = m_head; 1000 cur = frag = *txidx; 1001 1002 for (m = m_head; m != NULL; m = m->m_next) { 1003 if (m->m_len != 0) { 1004 if ((PCN_TX_LIST_CNT - 1005 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1006 return(ENOBUFS); 1007 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1008 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1009 f->pcn_txctl |= PCN_TXCTL_MBO; 1010 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1011 if (cnt == 0) 1012 f->pcn_txctl |= PCN_TXCTL_STP; 1013 else 1014 f->pcn_txctl |= PCN_TXCTL_OWN; 1015 cur = frag; 1016 PCN_INC(frag, PCN_TX_LIST_CNT); 1017 cnt++; 1018 } 1019 } 1020 1021 if (m != NULL) 1022 return(ENOBUFS); 1023 1024 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1025 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1026 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1027 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1028 sc->pcn_cdata.pcn_tx_cnt += cnt; 1029 *txidx = frag; 1030 1031 return(0); 1032 } 1033 1034 /* 1035 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1036 * to the mbuf data regions directly in the transmit lists. We also save a 1037 * copy of the pointers since the transmit list fragment pointers are 1038 * physical addresses. 1039 */ 1040 static void pcn_start(ifp) 1041 struct ifnet *ifp; 1042 { 1043 struct pcn_softc *sc; 1044 struct mbuf *m_head = NULL; 1045 u_int32_t idx; 1046 1047 sc = ifp->if_softc; 1048 1049 if (!sc->pcn_link) 1050 return; 1051 1052 idx = sc->pcn_cdata.pcn_tx_prod; 1053 1054 if (ifp->if_flags & IFF_OACTIVE) 1055 return; 1056 1057 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1058 IF_DEQUEUE(&ifp->if_snd, m_head); 1059 if (m_head == NULL) 1060 break; 1061 1062 if (pcn_encap(sc, m_head, &idx)) { 1063 IF_PREPEND(&ifp->if_snd, m_head); 1064 ifp->if_flags |= IFF_OACTIVE; 1065 break; 1066 } 1067 1068 /* 1069 * If there's a BPF listener, bounce a copy of this frame 1070 * to him. 1071 */ 1072 if (ifp->if_bpf) 1073 bpf_mtap(ifp, m_head); 1074 1075 } 1076 1077 /* Transmit */ 1078 sc->pcn_cdata.pcn_tx_prod = idx; 1079 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1080 1081 /* 1082 * Set a timeout in case the chip goes out to lunch. 1083 */ 1084 ifp->if_timer = 5; 1085 1086 return; 1087 } 1088 1089 void pcn_setfilt(ifp) 1090 struct ifnet *ifp; 1091 { 1092 struct pcn_softc *sc; 1093 1094 sc = ifp->if_softc; 1095 1096 /* If we want promiscuous mode, set the allframes bit. */ 1097 if (ifp->if_flags & IFF_PROMISC) { 1098 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1099 } else { 1100 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1101 } 1102 1103 /* Set the capture broadcast bit to capture broadcast frames. */ 1104 if (ifp->if_flags & IFF_BROADCAST) { 1105 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1106 } else { 1107 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1108 } 1109 1110 return; 1111 } 1112 1113 static void pcn_init(xsc) 1114 void *xsc; 1115 { 1116 struct pcn_softc *sc = xsc; 1117 struct ifnet *ifp = &sc->arpcom.ac_if; 1118 struct mii_data *mii = NULL; 1119 int s; 1120 1121 s = splimp(); 1122 1123 /* 1124 * Cancel pending I/O and free all RX/TX buffers. 1125 */ 1126 pcn_stop(sc); 1127 pcn_reset(sc); 1128 1129 mii = device_get_softc(sc->pcn_miibus); 1130 1131 /* Set MAC address */ 1132 pcn_csr_write(sc, PCN_CSR_PAR0, 1133 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1134 pcn_csr_write(sc, PCN_CSR_PAR1, 1135 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1136 pcn_csr_write(sc, PCN_CSR_PAR2, 1137 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1138 1139 /* Init circular RX list. */ 1140 if (pcn_list_rx_init(sc) == ENOBUFS) { 1141 printf("pcn%d: initialization failed: no " 1142 "memory for rx buffers\n", sc->pcn_unit); 1143 pcn_stop(sc); 1144 (void)splx(s); 1145 return; 1146 } 1147 1148 /* Set up RX filter. */ 1149 pcn_setfilt(ifp); 1150 1151 /* 1152 * Init tx descriptors. 1153 */ 1154 pcn_list_tx_init(sc); 1155 1156 /* Set up the mode register. */ 1157 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1158 1159 /* 1160 * Load the multicast filter. 1161 */ 1162 pcn_setmulti(sc); 1163 1164 /* 1165 * Load the addresses of the RX and TX lists. 1166 */ 1167 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1168 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1169 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1170 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1171 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1172 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1173 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1174 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1175 1176 /* Set the RX and TX ring sizes. */ 1177 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1178 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1179 1180 /* We're not using the initialization block. */ 1181 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1182 1183 /* Enable fast suspend mode. */ 1184 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1185 1186 /* 1187 * Enable burst read and write. Also set the no underflow 1188 * bit. This will avoid transmit underruns in certain 1189 * conditions while still providing decent performance. 1190 */ 1191 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1192 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1193 1194 /* Enable graceful recovery from underflow. */ 1195 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1196 1197 /* Enable auto-padding of short TX frames. */ 1198 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1199 1200 /* Disable MII autoneg (we handle this ourselves). */ 1201 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1202 1203 if (sc->pcn_type == Am79C978) 1204 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1205 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1206 1207 /* Enable interrupts and start the controller running. */ 1208 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1209 1210 mii_mediachg(mii); 1211 1212 ifp->if_flags |= IFF_RUNNING; 1213 ifp->if_flags &= ~IFF_OACTIVE; 1214 1215 (void)splx(s); 1216 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1217 1218 return; 1219 } 1220 1221 /* 1222 * Set media options. 1223 */ 1224 static int pcn_ifmedia_upd(ifp) 1225 struct ifnet *ifp; 1226 { 1227 struct pcn_softc *sc; 1228 struct mii_data *mii; 1229 1230 sc = ifp->if_softc; 1231 mii = device_get_softc(sc->pcn_miibus); 1232 1233 sc->pcn_link = 0; 1234 if (mii->mii_instance) { 1235 struct mii_softc *miisc; 1236 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1237 miisc = LIST_NEXT(miisc, mii_list)) 1238 mii_phy_reset(miisc); 1239 } 1240 mii_mediachg(mii); 1241 1242 return(0); 1243 } 1244 1245 /* 1246 * Report current media status. 1247 */ 1248 static void pcn_ifmedia_sts(ifp, ifmr) 1249 struct ifnet *ifp; 1250 struct ifmediareq *ifmr; 1251 { 1252 struct pcn_softc *sc; 1253 struct mii_data *mii; 1254 1255 sc = ifp->if_softc; 1256 1257 mii = device_get_softc(sc->pcn_miibus); 1258 mii_pollstat(mii); 1259 ifmr->ifm_active = mii->mii_media_active; 1260 ifmr->ifm_status = mii->mii_media_status; 1261 1262 return; 1263 } 1264 1265 static int pcn_ioctl(ifp, command, data) 1266 struct ifnet *ifp; 1267 u_long command; 1268 caddr_t data; 1269 { 1270 struct pcn_softc *sc = ifp->if_softc; 1271 struct ifreq *ifr = (struct ifreq *) data; 1272 struct mii_data *mii = NULL; 1273 int s, error = 0; 1274 1275 s = splimp(); 1276 1277 switch(command) { 1278 case SIOCSIFADDR: 1279 case SIOCGIFADDR: 1280 case SIOCSIFMTU: 1281 error = ether_ioctl(ifp, command, data); 1282 break; 1283 case SIOCSIFFLAGS: 1284 if (ifp->if_flags & IFF_UP) { 1285 if (ifp->if_flags & IFF_RUNNING && 1286 ifp->if_flags & IFF_PROMISC && 1287 !(sc->pcn_if_flags & IFF_PROMISC)) { 1288 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1289 PCN_EXTCTL1_SPND); 1290 pcn_setfilt(ifp); 1291 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1292 PCN_EXTCTL1_SPND); 1293 pcn_csr_write(sc, PCN_CSR_CSR, 1294 PCN_CSR_INTEN|PCN_CSR_START); 1295 } else if (ifp->if_flags & IFF_RUNNING && 1296 !(ifp->if_flags & IFF_PROMISC) && 1297 sc->pcn_if_flags & IFF_PROMISC) { 1298 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1299 PCN_EXTCTL1_SPND); 1300 pcn_setfilt(ifp); 1301 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1302 PCN_EXTCTL1_SPND); 1303 pcn_csr_write(sc, PCN_CSR_CSR, 1304 PCN_CSR_INTEN|PCN_CSR_START); 1305 } else if (!(ifp->if_flags & IFF_RUNNING)) 1306 pcn_init(sc); 1307 } else { 1308 if (ifp->if_flags & IFF_RUNNING) 1309 pcn_stop(sc); 1310 } 1311 sc->pcn_if_flags = ifp->if_flags; 1312 error = 0; 1313 break; 1314 case SIOCADDMULTI: 1315 case SIOCDELMULTI: 1316 pcn_setmulti(sc); 1317 error = 0; 1318 break; 1319 case SIOCGIFMEDIA: 1320 case SIOCSIFMEDIA: 1321 mii = device_get_softc(sc->pcn_miibus); 1322 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1323 break; 1324 default: 1325 error = EINVAL; 1326 break; 1327 } 1328 1329 (void)splx(s); 1330 1331 return(error); 1332 } 1333 1334 static void pcn_watchdog(ifp) 1335 struct ifnet *ifp; 1336 { 1337 struct pcn_softc *sc; 1338 1339 sc = ifp->if_softc; 1340 1341 ifp->if_oerrors++; 1342 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1343 1344 pcn_stop(sc); 1345 pcn_reset(sc); 1346 pcn_init(sc); 1347 1348 if (ifp->if_snd.ifq_head != NULL) 1349 pcn_start(ifp); 1350 1351 return; 1352 } 1353 1354 /* 1355 * Stop the adapter and free any mbufs allocated to the 1356 * RX and TX lists. 1357 */ 1358 static void pcn_stop(sc) 1359 struct pcn_softc *sc; 1360 { 1361 register int i; 1362 struct ifnet *ifp; 1363 1364 ifp = &sc->arpcom.ac_if; 1365 ifp->if_timer = 0; 1366 1367 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1368 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1369 sc->pcn_link = 0; 1370 1371 /* 1372 * Free data in the RX lists. 1373 */ 1374 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1375 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1376 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1377 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1378 } 1379 } 1380 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1381 sizeof(sc->pcn_ldata->pcn_rx_list)); 1382 1383 /* 1384 * Free the TX list buffers. 1385 */ 1386 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1387 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1388 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1389 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1390 } 1391 } 1392 1393 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1394 sizeof(sc->pcn_ldata->pcn_tx_list)); 1395 1396 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1397 1398 return; 1399 } 1400 1401 /* 1402 * Stop all chip I/O so that the kernel's probe routines don't 1403 * get confused by errant DMAs when rebooting. 1404 */ 1405 static void pcn_shutdown(dev) 1406 device_t dev; 1407 { 1408 struct pcn_softc *sc; 1409 1410 sc = device_get_softc(dev); 1411 1412 pcn_reset(sc); 1413 pcn_stop(sc); 1414 1415 return; 1416 }
Cache object: efae609d79159e7b308be8864f973dc8
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