The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/pci/if_pcn.c

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*
    2  * Copyright (c) 2000 Berkeley Software Design, Inc.
    3  * Copyright (c) 1997, 1998, 1999, 2000
    4  *      Bill Paul <wpaul@osd.bsdi.com>.  All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 3. All advertising materials mentioning features or use of this software
   15  *    must display the following acknowledgement:
   16  *      This product includes software developed by Bill Paul.
   17  * 4. Neither the name of the author nor the names of any co-contributors
   18  *    may be used to endorse or promote products derived from this software
   19  *    without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   31  * THE POSSIBILITY OF SUCH DAMAGE.
   32  *
   33  * $FreeBSD: releng/5.0/sys/pci/if_pcn.c 106936 2002-11-14 23:49:09Z sam $
   34  */
   35 
   36 /*
   37  * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available
   38  * from http://www.amd.com.
   39  *
   40  * Written by Bill Paul <wpaul@osd.bsdi.com>
   41  */
   42 
   43 /*
   44  * The AMD PCnet/PCI controllers are more advanced and functional
   45  * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
   46  * backwards compatibility with the LANCE and thus can be made
   47  * to work with older LANCE drivers. This is in fact how the
   48  * PCnet/PCI chips were supported in FreeBSD originally. The trouble
   49  * is that the PCnet/PCI devices offer several performance enhancements
   50  * which can't be exploited in LANCE compatibility mode. Chief among
   51  * these enhancements is the ability to perform PCI DMA operations
   52  * using 32-bit addressing (which eliminates the need for ISA
   53  * bounce-buffering), and special receive buffer alignment (which
   54  * allows the receive handler to pass packets to the upper protocol
   55  * layers without copying on both the x86 and alpha platforms).
   56  */
   57 
   58 #include <sys/param.h>
   59 #include <sys/systm.h>
   60 #include <sys/sockio.h>
   61 #include <sys/mbuf.h>
   62 #include <sys/malloc.h>
   63 #include <sys/kernel.h>
   64 #include <sys/socket.h>
   65 
   66 #include <net/if.h>
   67 #include <net/if_arp.h>
   68 #include <net/ethernet.h>
   69 #include <net/if_dl.h>
   70 #include <net/if_media.h>
   71 
   72 #include <net/bpf.h>
   73 
   74 #include <vm/vm.h>              /* for vtophys */
   75 #include <vm/pmap.h>            /* for vtophys */
   76 #include <machine/bus_pio.h>
   77 #include <machine/bus_memio.h>
   78 #include <machine/bus.h>
   79 #include <machine/resource.h>
   80 #include <sys/bus.h>
   81 #include <sys/rman.h>
   82 
   83 #include <dev/mii/mii.h>
   84 #include <dev/mii/miivar.h>
   85 
   86 #include <pci/pcireg.h>
   87 #include <pci/pcivar.h>
   88 
   89 #define PCN_USEIOSPACE
   90 
   91 #include <pci/if_pcnreg.h>
   92 
   93 MODULE_DEPEND(pcn, miibus, 1, 1, 1);
   94 
   95 /* "controller miibus0" required.  See GENERIC if you get errors here. */
   96 #include "miibus_if.h"
   97 
   98 #ifndef lint
   99 static const char rcsid[] =
  100   "$FreeBSD: releng/5.0/sys/pci/if_pcn.c 106936 2002-11-14 23:49:09Z sam $";
  101 #endif
  102 
  103 /*
  104  * Various supported device vendors/types and their names.
  105  */
  106 static struct pcn_type pcn_devs[] = {
  107         { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
  108         { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
  109         { 0, 0, NULL }
  110 };
  111 
  112 static u_int32_t pcn_csr_read   (struct pcn_softc *, int);
  113 static u_int16_t pcn_csr_read16 (struct pcn_softc *, int);
  114 static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int);
  115 static void pcn_csr_write       (struct pcn_softc *, int, int);
  116 static u_int32_t pcn_bcr_read   (struct pcn_softc *, int);
  117 static void pcn_bcr_write       (struct pcn_softc *, int, int);
  118 
  119 static int pcn_probe            (device_t);
  120 static int pcn_attach           (device_t);
  121 static int pcn_detach           (device_t);
  122 
  123 static int pcn_newbuf           (struct pcn_softc *, int, struct mbuf *);
  124 static int pcn_encap            (struct pcn_softc *,
  125                                         struct mbuf *, u_int32_t *);
  126 static void pcn_rxeof           (struct pcn_softc *);
  127 static void pcn_txeof           (struct pcn_softc *);
  128 static void pcn_intr            (void *);
  129 static void pcn_tick            (void *);
  130 static void pcn_start           (struct ifnet *);
  131 static int pcn_ioctl            (struct ifnet *, u_long, caddr_t);
  132 static void pcn_init            (void *);
  133 static void pcn_stop            (struct pcn_softc *);
  134 static void pcn_watchdog                (struct ifnet *);
  135 static void pcn_shutdown                (device_t);
  136 static int pcn_ifmedia_upd      (struct ifnet *);
  137 static void pcn_ifmedia_sts     (struct ifnet *, struct ifmediareq *);
  138 
  139 static int pcn_miibus_readreg   (device_t, int, int);
  140 static int pcn_miibus_writereg  (device_t, int, int, int);
  141 static void pcn_miibus_statchg  (device_t);
  142 
  143 static void pcn_setfilt         (struct ifnet *);
  144 static void pcn_setmulti        (struct pcn_softc *);
  145 static u_int32_t pcn_crc        (caddr_t);
  146 static void pcn_reset           (struct pcn_softc *);
  147 static int pcn_list_rx_init     (struct pcn_softc *);
  148 static int pcn_list_tx_init     (struct pcn_softc *);
  149 
  150 #ifdef PCN_USEIOSPACE
  151 #define PCN_RES                 SYS_RES_IOPORT
  152 #define PCN_RID                 PCN_PCI_LOIO
  153 #else
  154 #define PCN_RES                 SYS_RES_MEMORY
  155 #define PCN_RID                 PCN_PCI_LOMEM
  156 #endif
  157 
  158 static device_method_t pcn_methods[] = {
  159         /* Device interface */
  160         DEVMETHOD(device_probe,         pcn_probe),
  161         DEVMETHOD(device_attach,        pcn_attach),
  162         DEVMETHOD(device_detach,        pcn_detach),
  163         DEVMETHOD(device_shutdown,      pcn_shutdown),
  164 
  165         /* bus interface */
  166         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  167         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
  168 
  169         /* MII interface */
  170         DEVMETHOD(miibus_readreg,       pcn_miibus_readreg),
  171         DEVMETHOD(miibus_writereg,      pcn_miibus_writereg),
  172         DEVMETHOD(miibus_statchg,       pcn_miibus_statchg),
  173 
  174         { 0, 0 }
  175 };
  176 
  177 static driver_t pcn_driver = {
  178         "pcn",
  179         pcn_methods,
  180         sizeof(struct pcn_softc)
  181 };
  182 
  183 static devclass_t pcn_devclass;
  184 
  185 DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0);
  186 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
  187 
  188 #define PCN_CSR_SETBIT(sc, reg, x)                      \
  189         pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
  190 
  191 #define PCN_CSR_CLRBIT(sc, reg, x)                      \
  192         pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
  193 
  194 #define PCN_BCR_SETBIT(sc, reg, x)                      \
  195         pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
  196 
  197 #define PCN_BCR_CLRBIT(sc, reg, x)                      \
  198         pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
  199 
  200 static u_int32_t
  201 pcn_csr_read(sc, reg)
  202         struct pcn_softc        *sc;
  203         int                     reg;
  204 {
  205         CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
  206         return(CSR_READ_4(sc, PCN_IO32_RDP));
  207 }
  208 
  209 static u_int16_t
  210 pcn_csr_read16(sc, reg)
  211         struct pcn_softc        *sc;
  212         int                     reg;
  213 {
  214         CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
  215         return(CSR_READ_2(sc, PCN_IO16_RDP));
  216 }
  217 
  218 static void
  219 pcn_csr_write(sc, reg, val)
  220         struct pcn_softc        *sc;
  221         int                     reg;
  222 {
  223         CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
  224         CSR_WRITE_4(sc, PCN_IO32_RDP, val);
  225         return;
  226 }
  227 
  228 static u_int32_t
  229 pcn_bcr_read(sc, reg)
  230         struct pcn_softc        *sc;
  231         int                     reg;
  232 {
  233         CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
  234         return(CSR_READ_4(sc, PCN_IO32_BDP));
  235 }
  236 
  237 static u_int16_t
  238 pcn_bcr_read16(sc, reg)
  239         struct pcn_softc        *sc;
  240         int                     reg;
  241 {
  242         CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
  243         return(CSR_READ_2(sc, PCN_IO16_BDP));
  244 }
  245 
  246 static void
  247 pcn_bcr_write(sc, reg, val)
  248         struct pcn_softc        *sc;
  249         int                     reg;
  250 {
  251         CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
  252         CSR_WRITE_4(sc, PCN_IO32_BDP, val);
  253         return;
  254 }
  255 
  256 static int
  257 pcn_miibus_readreg(dev, phy, reg)
  258         device_t                dev;
  259         int                     phy, reg;
  260 {
  261         struct pcn_softc        *sc;
  262         int                     val;
  263 
  264         sc = device_get_softc(dev);
  265 
  266         if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr)
  267                 return(0);
  268 
  269         pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
  270         val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
  271         if (val == 0xFFFF)
  272                 return(0);
  273 
  274         sc->pcn_phyaddr = phy;
  275 
  276         return(val);
  277 }
  278 
  279 static int
  280 pcn_miibus_writereg(dev, phy, reg, data)
  281         device_t                dev;
  282         int                     phy, reg, data;
  283 {
  284         struct pcn_softc        *sc;
  285 
  286         sc = device_get_softc(dev);
  287 
  288         pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
  289         pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
  290 
  291         return(0);
  292 }
  293 
  294 static void
  295 pcn_miibus_statchg(dev)
  296         device_t                dev;
  297 {
  298         struct pcn_softc        *sc;
  299         struct mii_data         *mii;
  300 
  301         sc = device_get_softc(dev);
  302         mii = device_get_softc(sc->pcn_miibus);
  303 
  304         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
  305                 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
  306         } else {
  307                 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
  308         }
  309 
  310         return;
  311 }
  312 
  313 #define DC_POLY         0xEDB88320
  314 
  315 static u_int32_t
  316 pcn_crc(addr)
  317         caddr_t                 addr;
  318 {
  319         u_int32_t               idx, bit, data, crc;
  320 
  321         /* Compute CRC for the address value. */
  322         crc = 0xFFFFFFFF; /* initial value */
  323 
  324         for (idx = 0; idx < 6; idx++) {
  325                 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
  326                         crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
  327         }
  328 
  329         return ((crc >> 26) & 0x3F);
  330 }
  331 
  332 static void
  333 pcn_setmulti(sc)
  334         struct pcn_softc        *sc;
  335 {
  336         struct ifnet            *ifp;
  337         struct ifmultiaddr      *ifma;
  338         u_int32_t               h, i;
  339         u_int16_t               hashes[4] = { 0, 0, 0, 0 };
  340 
  341         ifp = &sc->arpcom.ac_if;
  342 
  343         PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
  344 
  345         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
  346                 for (i = 0; i < 4; i++)
  347                         pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
  348                 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
  349                 return;
  350         }
  351 
  352         /* first, zot all the existing hash bits */
  353         for (i = 0; i < 4; i++)
  354                 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
  355 
  356         /* now program new ones */
  357         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
  358                 if (ifma->ifma_addr->sa_family != AF_LINK)
  359                         continue;
  360                 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
  361                 hashes[h >> 4] |= 1 << (h & 0xF);
  362         }
  363 
  364         for (i = 0; i < 4; i++)
  365                 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
  366 
  367         PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
  368 
  369         return;
  370 }
  371 
  372 static void
  373 pcn_reset(sc)
  374         struct pcn_softc        *sc;
  375 {
  376         /*
  377          * Issue a reset by reading from the RESET register.
  378          * Note that we don't know if the chip is operating in
  379          * 16-bit or 32-bit mode at this point, so we attempt
  380          * to reset the chip both ways. If one fails, the other
  381          * will succeed.
  382          */
  383         CSR_READ_2(sc, PCN_IO16_RESET);
  384         CSR_READ_4(sc, PCN_IO32_RESET);
  385 
  386         /* Wait a little while for the chip to get its brains in order. */
  387         DELAY(1000);
  388 
  389         /* Select 32-bit (DWIO) mode */
  390         CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
  391 
  392         /* Select software style 3. */
  393         pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
  394 
  395         return;
  396 }
  397 
  398 /*
  399  * Probe for an AMD chip. Check the PCI vendor and device
  400  * IDs against our list and return a device name if we find a match.
  401  */
  402 static int
  403 pcn_probe(dev)
  404         device_t                dev;
  405 {
  406         struct pcn_type         *t;
  407         struct pcn_softc        *sc;
  408         int                     rid;
  409         u_int32_t               chip_id;
  410 
  411         t = pcn_devs;
  412         sc = device_get_softc(dev);
  413 
  414         while(t->pcn_name != NULL) {
  415                 if ((pci_get_vendor(dev) == t->pcn_vid) &&
  416                     (pci_get_device(dev) == t->pcn_did)) {
  417                         /*
  418                          * Temporarily map the I/O space
  419                          * so we can read the chip ID register.
  420                          */
  421                         rid = PCN_RID;
  422                         sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid,
  423                             0, ~0, 1, RF_ACTIVE);
  424                         if (sc->pcn_res == NULL) {
  425                                 device_printf(dev,
  426                                     "couldn't map ports/memory\n");
  427                                 return(ENXIO);
  428                         }
  429                         sc->pcn_btag = rman_get_bustag(sc->pcn_res);
  430                         sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
  431                         mtx_init(&sc->pcn_mtx,
  432                             device_get_nameunit(dev), MTX_NETWORK_LOCK,
  433                             MTX_DEF);
  434                         PCN_LOCK(sc);
  435                         /*
  436                          * Note: we can *NOT* put the chip into
  437                          * 32-bit mode yet. The lnc driver will only
  438                          * work in 16-bit mode, and once the chip
  439                          * goes into 32-bit mode, the only way to
  440                          * get it out again is with a hardware reset.
  441                          * So if pcn_probe() is called before the
  442                          * lnc driver's probe routine, the chip will
  443                          * be locked into 32-bit operation and the lnc
  444                          * driver will be unable to attach to it.
  445                          * Note II: if the chip happens to already
  446                          * be in 32-bit mode, we still need to check
  447                          * the chip ID, but first we have to detect
  448                          * 32-bit mode using only 16-bit operations.
  449                          * The safest way to do this is to read the
  450                          * PCI subsystem ID from BCR23/24 and compare
  451                          * that with the value read from PCI config
  452                          * space.
  453                          */
  454                         chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
  455                         chip_id <<= 16;
  456                         chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
  457                         /*
  458                          * Note III: the test for 0x10001000 is a hack to
  459                          * pacify VMware, who's pseudo-PCnet interface is
  460                          * broken. Reading the subsystem register from PCI
  461                          * config space yeilds 0x00000000 while reading the
  462                          * same value from I/O space yeilds 0x10001000. It's
  463                          * not supposed to be that way.
  464                          */
  465                         if (chip_id == pci_read_config(dev,
  466                             PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
  467                                 /* We're in 16-bit mode. */
  468                                 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
  469                                 chip_id <<= 16;
  470                                 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
  471                         } else {
  472                                 /* We're in 32-bit mode. */
  473                                 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
  474                                 chip_id <<= 16;
  475                                 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
  476                         }
  477                         bus_release_resource(dev, PCN_RES,
  478                             PCN_RID, sc->pcn_res);
  479                         PCN_UNLOCK(sc);
  480                         mtx_destroy(&sc->pcn_mtx);
  481                         chip_id >>= 12;
  482                         sc->pcn_type = chip_id & PART_MASK;
  483                         switch(sc->pcn_type) {
  484                         case Am79C971:
  485                         case Am79C972:
  486                         case Am79C973:
  487                         case Am79C975:
  488                         case Am79C976:
  489                         case Am79C978:
  490                                 break;
  491                         default:
  492                                 return(ENXIO);
  493                                 break;
  494                         }
  495                         device_set_desc(dev, t->pcn_name);
  496                         return(0);
  497                 }
  498                 t++;
  499         }
  500 
  501         return(ENXIO);
  502 }
  503 
  504 /*
  505  * Attach the interface. Allocate softc structures, do ifmedia
  506  * setup and ethernet/BPF attach.
  507  */
  508 static int
  509 pcn_attach(dev)
  510         device_t                dev;
  511 {
  512         u_int32_t               eaddr[2];
  513         u_int32_t               command;
  514         struct pcn_softc        *sc;
  515         struct ifnet            *ifp;
  516         int                     unit, error = 0, rid;
  517 
  518         sc = device_get_softc(dev);
  519         unit = device_get_unit(dev);
  520 
  521         /* Initialize our mutex. */
  522         mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
  523             MTX_DEF | MTX_RECURSE);
  524         PCN_LOCK(sc);
  525 
  526         /*
  527          * Handle power management nonsense.
  528          */
  529         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
  530                 u_int32_t               iobase, membase, irq;
  531 
  532                 /* Save important PCI config data. */
  533                 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4);
  534                 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4);
  535                 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4);
  536 
  537                 /* Reset the power state. */
  538                 printf("pcn%d: chip is in D%d power mode "
  539                     "-- setting to D0\n", unit,
  540                     pci_get_powerstate(dev));
  541                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
  542 
  543                 /* Restore PCI config data. */
  544                 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4);
  545                 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4);
  546                 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4);
  547         }
  548 
  549         /*
  550          * Map control/status registers.
  551          */
  552         pci_enable_busmaster(dev);
  553         pci_enable_io(dev, SYS_RES_IOPORT);
  554         pci_enable_io(dev, SYS_RES_MEMORY);
  555         command = pci_read_config(dev, PCIR_COMMAND, 4);
  556 
  557 #ifdef PCN_USEIOSPACE
  558         if (!(command & PCIM_CMD_PORTEN)) {
  559                 printf("pcn%d: failed to enable I/O ports!\n", unit);
  560                 error = ENXIO;;
  561                 goto fail;
  562         }
  563 #else
  564         if (!(command & PCIM_CMD_MEMEN)) {
  565                 printf("pcn%d: failed to enable memory mapping!\n", unit);
  566                 error = ENXIO;;
  567                 goto fail;
  568         }
  569 #endif
  570 
  571         rid = PCN_RID;
  572         sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid,
  573             0, ~0, 1, RF_ACTIVE);
  574 
  575         if (sc->pcn_res == NULL) {
  576                 printf("pcn%d: couldn't map ports/memory\n", unit);
  577                 error = ENXIO;
  578                 goto fail;
  579         }
  580 
  581         sc->pcn_btag = rman_get_bustag(sc->pcn_res);
  582         sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
  583 
  584         /* Allocate interrupt */
  585         rid = 0;
  586         sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
  587             RF_SHAREABLE | RF_ACTIVE);
  588 
  589         if (sc->pcn_irq == NULL) {
  590                 printf("pcn%d: couldn't map interrupt\n", unit);
  591                 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
  592                 error = ENXIO;
  593                 goto fail;
  594         }
  595 
  596         error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET,
  597             pcn_intr, sc, &sc->pcn_intrhand);
  598 
  599         if (error) {
  600                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_res);
  601                 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
  602                 printf("pcn%d: couldn't set up irq\n", unit);
  603                 goto fail;
  604         }
  605 
  606         /* Reset the adapter. */
  607         pcn_reset(sc);
  608 
  609         /*
  610          * Get station address from the EEPROM.
  611          */
  612         eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00);
  613         eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01);
  614         bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
  615 
  616         /*
  617          * An AMD chip was detected. Inform the world.
  618          */
  619         printf("pcn%d: Ethernet address: %6D\n", unit,
  620             sc->arpcom.ac_enaddr, ":");
  621 
  622         sc->pcn_unit = unit;
  623         callout_handle_init(&sc->pcn_stat_ch);
  624 
  625         sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
  626             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
  627 
  628         if (sc->pcn_ldata == NULL) {
  629                 printf("pcn%d: no memory for list buffers!\n", unit);
  630                 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
  631                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
  632                 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
  633                 error = ENXIO;
  634                 goto fail;
  635         }
  636         bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
  637 
  638         ifp = &sc->arpcom.ac_if;
  639         ifp->if_softc = sc;
  640         ifp->if_unit = unit;
  641         ifp->if_name = "pcn";
  642         ifp->if_mtu = ETHERMTU;
  643         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
  644         ifp->if_ioctl = pcn_ioctl;
  645         ifp->if_output = ether_output;
  646         ifp->if_start = pcn_start;
  647         ifp->if_watchdog = pcn_watchdog;
  648         ifp->if_init = pcn_init;
  649         ifp->if_baudrate = 10000000;
  650         ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1;
  651 
  652         /*
  653          * Do MII setup.
  654          */
  655         if (mii_phy_probe(dev, &sc->pcn_miibus,
  656             pcn_ifmedia_upd, pcn_ifmedia_sts)) {
  657                 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit);
  658                 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
  659                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
  660                 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
  661                 error = ENXIO;
  662                 goto fail;
  663         }
  664 
  665         /*
  666          * Call MI attach routine.
  667          */
  668         ether_ifattach(ifp, (u_int8_t *) eaddr);
  669         callout_handle_init(&sc->pcn_stat_ch);
  670         PCN_UNLOCK(sc);
  671         return(0);
  672 
  673 fail:
  674         PCN_UNLOCK(sc);
  675         mtx_destroy(&sc->pcn_mtx);
  676 
  677         return(error);
  678 }
  679 
  680 static int
  681 pcn_detach(dev)
  682         device_t                dev;
  683 {
  684         struct pcn_softc        *sc;
  685         struct ifnet            *ifp;
  686 
  687         sc = device_get_softc(dev);
  688         ifp = &sc->arpcom.ac_if;
  689 
  690         PCN_LOCK(sc);
  691 
  692         pcn_reset(sc);
  693         pcn_stop(sc);
  694         ether_ifdetach(ifp);
  695 
  696         if (sc->pcn_miibus != NULL) {
  697                 bus_generic_detach(dev);
  698                 device_delete_child(dev, sc->pcn_miibus);
  699         }
  700 
  701         bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
  702         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
  703         bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
  704 
  705         contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), M_DEVBUF);
  706         PCN_UNLOCK(sc);
  707 
  708         mtx_destroy(&sc->pcn_mtx);
  709 
  710         return(0);
  711 }
  712 
  713 /*
  714  * Initialize the transmit descriptors.
  715  */
  716 static int
  717 pcn_list_tx_init(sc)
  718         struct pcn_softc        *sc;
  719 {
  720         struct pcn_list_data    *ld;
  721         struct pcn_ring_data    *cd;
  722         int                     i;
  723 
  724         cd = &sc->pcn_cdata;
  725         ld = sc->pcn_ldata;
  726 
  727         for (i = 0; i < PCN_TX_LIST_CNT; i++) {
  728                 cd->pcn_tx_chain[i] = NULL;
  729                 ld->pcn_tx_list[i].pcn_tbaddr = 0;
  730                 ld->pcn_tx_list[i].pcn_txctl = 0;
  731                 ld->pcn_tx_list[i].pcn_txstat = 0;
  732         }
  733 
  734         cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
  735 
  736         return(0);
  737 }
  738 
  739 
  740 /*
  741  * Initialize the RX descriptors and allocate mbufs for them.
  742  */
  743 static int
  744 pcn_list_rx_init(sc)
  745         struct pcn_softc        *sc;
  746 {
  747         struct pcn_list_data    *ld;
  748         struct pcn_ring_data    *cd;
  749         int                     i;
  750 
  751         ld = sc->pcn_ldata;
  752         cd = &sc->pcn_cdata;
  753 
  754         for (i = 0; i < PCN_RX_LIST_CNT; i++) {
  755                 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
  756                         return(ENOBUFS);
  757         }
  758 
  759         cd->pcn_rx_prod = 0;
  760 
  761         return(0);
  762 }
  763 
  764 /*
  765  * Initialize an RX descriptor and attach an MBUF cluster.
  766  */
  767 static int
  768 pcn_newbuf(sc, idx, m)
  769         struct pcn_softc        *sc;
  770         int                     idx;
  771         struct mbuf             *m;
  772 {
  773         struct mbuf             *m_new = NULL;
  774         struct pcn_rx_desc      *c;
  775 
  776         c = &sc->pcn_ldata->pcn_rx_list[idx];
  777 
  778         if (m == NULL) {
  779                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
  780                 if (m_new == NULL)
  781                         return(ENOBUFS);
  782 
  783                 MCLGET(m_new, M_DONTWAIT);
  784                 if (!(m_new->m_flags & M_EXT)) {
  785                         m_freem(m_new);
  786                         return(ENOBUFS);
  787                 }
  788                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
  789         } else {
  790                 m_new = m;
  791                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
  792                 m_new->m_data = m_new->m_ext.ext_buf;
  793         }
  794 
  795         m_adj(m_new, ETHER_ALIGN);
  796 
  797         sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
  798         c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
  799         c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
  800         c->pcn_bufsz |= PCN_RXLEN_MBO;
  801         c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
  802 
  803         return(0);
  804 }
  805 
  806 /*
  807  * A frame has been uploaded: pass the resulting mbuf chain up to
  808  * the higher level protocols.
  809  */
  810 static void
  811 pcn_rxeof(sc)
  812         struct pcn_softc        *sc;
  813 {
  814         struct ether_header     *eh;
  815         struct mbuf             *m;
  816         struct ifnet            *ifp;
  817         struct pcn_rx_desc      *cur_rx;
  818         int                     i;
  819 
  820         ifp = &sc->arpcom.ac_if;
  821         i = sc->pcn_cdata.pcn_rx_prod;
  822 
  823         while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
  824                 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
  825                 m = sc->pcn_cdata.pcn_rx_chain[i];
  826                 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
  827 
  828                 /*
  829                  * If an error occurs, update stats, clear the
  830                  * status word and leave the mbuf cluster in place:
  831                  * it should simply get re-used next time this descriptor
  832                  * comes up in the ring.
  833                  */
  834                 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
  835                         ifp->if_ierrors++;
  836                         pcn_newbuf(sc, i, m);
  837                         PCN_INC(i, PCN_RX_LIST_CNT);
  838                         continue;
  839                 }
  840 
  841                 if (pcn_newbuf(sc, i, NULL)) {
  842                         /* Ran out of mbufs; recycle this one. */
  843                         pcn_newbuf(sc, i, m);
  844                         ifp->if_ierrors++;
  845                         PCN_INC(i, PCN_RX_LIST_CNT);
  846                         continue;
  847                 }
  848 
  849                 PCN_INC(i, PCN_RX_LIST_CNT);
  850 
  851                 /* No errors; receive the packet. */
  852                 ifp->if_ipackets++;
  853                 eh = mtod(m, struct ether_header *);
  854                 m->m_len = m->m_pkthdr.len =
  855                     cur_rx->pcn_rxlen - ETHER_CRC_LEN;
  856                 m->m_pkthdr.rcvif = ifp;
  857 
  858                 (*ifp->if_input)(ifp, m);
  859         }
  860 
  861         sc->pcn_cdata.pcn_rx_prod = i;
  862 
  863         return;
  864 }
  865 
  866 /*
  867  * A frame was downloaded to the chip. It's safe for us to clean up
  868  * the list buffers.
  869  */
  870 
  871 static void
  872 pcn_txeof(sc)
  873         struct pcn_softc        *sc;
  874 {
  875         struct pcn_tx_desc      *cur_tx = NULL;
  876         struct ifnet            *ifp;
  877         u_int32_t               idx;
  878 
  879         ifp = &sc->arpcom.ac_if;
  880 
  881         /*
  882          * Go through our tx list and free mbufs for those
  883          * frames that have been transmitted.
  884          */
  885         idx = sc->pcn_cdata.pcn_tx_cons;
  886         while (idx != sc->pcn_cdata.pcn_tx_prod) {
  887                 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
  888 
  889                 if (!PCN_OWN_TXDESC(cur_tx))
  890                         break;
  891 
  892                 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
  893                         sc->pcn_cdata.pcn_tx_cnt--;
  894                         PCN_INC(idx, PCN_TX_LIST_CNT);
  895                         continue;
  896                 }
  897 
  898                 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
  899                         ifp->if_oerrors++;
  900                         if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
  901                                 ifp->if_collisions++;
  902                         if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
  903                                 ifp->if_collisions++;
  904                 }
  905 
  906                 ifp->if_collisions +=
  907                     cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
  908 
  909                 ifp->if_opackets++;
  910                 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
  911                         m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
  912                         sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
  913                 }
  914 
  915                 sc->pcn_cdata.pcn_tx_cnt--;
  916                 PCN_INC(idx, PCN_TX_LIST_CNT);
  917         }
  918 
  919         if (idx != sc->pcn_cdata.pcn_tx_cons) {
  920                 /* Some buffers have been freed. */
  921                 sc->pcn_cdata.pcn_tx_cons = idx;
  922                 ifp->if_flags &= ~IFF_OACTIVE;
  923         }
  924         ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
  925 
  926         return;
  927 }
  928 
  929 static void
  930 pcn_tick(xsc)
  931         void                    *xsc;
  932 {
  933         struct pcn_softc        *sc;
  934         struct mii_data         *mii;
  935         struct ifnet            *ifp;
  936 
  937         sc = xsc;
  938         ifp = &sc->arpcom.ac_if;
  939         PCN_LOCK(sc);
  940 
  941         mii = device_get_softc(sc->pcn_miibus);
  942         mii_tick(mii);
  943 
  944         /* link just died */
  945         if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
  946                 sc->pcn_link = 0;
  947 
  948         /* link just came up, restart */
  949         if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE &&
  950             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
  951                 sc->pcn_link++;
  952                 if (ifp->if_snd.ifq_head != NULL)
  953                         pcn_start(ifp);
  954         }
  955 
  956         sc->pcn_stat_ch = timeout(pcn_tick, sc, hz);
  957 
  958         PCN_UNLOCK(sc);
  959 
  960         return;
  961 }
  962 
  963 static void
  964 pcn_intr(arg)
  965         void                    *arg;
  966 {
  967         struct pcn_softc        *sc;
  968         struct ifnet            *ifp;
  969         u_int32_t               status;
  970 
  971         sc = arg;
  972         ifp = &sc->arpcom.ac_if;
  973 
  974         /* Supress unwanted interrupts */
  975         if (!(ifp->if_flags & IFF_UP)) {
  976                 pcn_stop(sc);
  977                 return;
  978         }
  979 
  980         CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
  981 
  982         while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
  983                 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
  984 
  985                 if (status & PCN_CSR_RINT)
  986                         pcn_rxeof(sc);
  987 
  988                 if (status & PCN_CSR_TINT)
  989                         pcn_txeof(sc);
  990 
  991                 if (status & PCN_CSR_ERR) {
  992                         pcn_init(sc);
  993                         break;
  994                 }
  995         }
  996 
  997         if (ifp->if_snd.ifq_head != NULL)
  998                 pcn_start(ifp);
  999 
 1000         return;
 1001 }
 1002 
 1003 /*
 1004  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
 1005  * pointers to the fragment pointers.
 1006  */
 1007 static int
 1008 pcn_encap(sc, m_head, txidx)
 1009         struct pcn_softc        *sc;
 1010         struct mbuf             *m_head;
 1011         u_int32_t               *txidx;
 1012 {
 1013         struct pcn_tx_desc      *f = NULL;
 1014         struct mbuf             *m;
 1015         int                     frag, cur, cnt = 0;
 1016 
 1017         /*
 1018          * Start packing the mbufs in this chain into
 1019          * the fragment pointers. Stop when we run out
 1020          * of fragments or hit the end of the mbuf chain.
 1021          */
 1022         m = m_head;
 1023         cur = frag = *txidx;
 1024 
 1025         for (m = m_head; m != NULL; m = m->m_next) {
 1026                 if (m->m_len != 0) {
 1027                         if ((PCN_TX_LIST_CNT -
 1028                             (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
 1029                                 return(ENOBUFS);
 1030                         f = &sc->pcn_ldata->pcn_tx_list[frag];
 1031                         f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
 1032                         f->pcn_txctl |= PCN_TXCTL_MBO;
 1033                         f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
 1034                         if (cnt == 0)
 1035                                 f->pcn_txctl |= PCN_TXCTL_STP;
 1036                         else
 1037                                 f->pcn_txctl |= PCN_TXCTL_OWN;
 1038                         cur = frag;
 1039                         PCN_INC(frag, PCN_TX_LIST_CNT);
 1040                         cnt++;
 1041                 }
 1042         }
 1043 
 1044         if (m != NULL)
 1045                 return(ENOBUFS);
 1046 
 1047         sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
 1048         sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
 1049             PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
 1050         sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
 1051         sc->pcn_cdata.pcn_tx_cnt += cnt;
 1052         *txidx = frag;
 1053 
 1054         return(0);
 1055 }
 1056 
 1057 /*
 1058  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 1059  * to the mbuf data regions directly in the transmit lists. We also save a
 1060  * copy of the pointers since the transmit list fragment pointers are
 1061  * physical addresses.
 1062  */
 1063 static void
 1064 pcn_start(ifp)
 1065         struct ifnet            *ifp;
 1066 {
 1067         struct pcn_softc        *sc;
 1068         struct mbuf             *m_head = NULL;
 1069         u_int32_t               idx;
 1070 
 1071         sc = ifp->if_softc;
 1072 
 1073         PCN_LOCK(sc);
 1074 
 1075         if (!sc->pcn_link) {
 1076                 PCN_UNLOCK(sc);
 1077                 return;
 1078         }
 1079 
 1080         idx = sc->pcn_cdata.pcn_tx_prod;
 1081 
 1082         if (ifp->if_flags & IFF_OACTIVE) {
 1083                 PCN_UNLOCK(sc);
 1084                 return;
 1085         }
 1086 
 1087         while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
 1088                 IF_DEQUEUE(&ifp->if_snd, m_head);
 1089                 if (m_head == NULL)
 1090                         break;
 1091 
 1092                 if (pcn_encap(sc, m_head, &idx)) {
 1093                         IF_PREPEND(&ifp->if_snd, m_head);
 1094                         ifp->if_flags |= IFF_OACTIVE;
 1095                         break;
 1096                 }
 1097 
 1098                 /*
 1099                  * If there's a BPF listener, bounce a copy of this frame
 1100                  * to him.
 1101                  */
 1102                 BPF_MTAP(ifp, m_head);
 1103 
 1104         }
 1105 
 1106         /* Transmit */
 1107         sc->pcn_cdata.pcn_tx_prod = idx;
 1108         pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
 1109 
 1110         /*
 1111          * Set a timeout in case the chip goes out to lunch.
 1112          */
 1113         ifp->if_timer = 5;
 1114 
 1115         PCN_UNLOCK(sc);
 1116 
 1117         return;
 1118 }
 1119 
 1120 static void
 1121 pcn_setfilt(ifp)
 1122         struct ifnet            *ifp;
 1123 {
 1124         struct pcn_softc        *sc;
 1125 
 1126         sc = ifp->if_softc;
 1127 
 1128          /* If we want promiscuous mode, set the allframes bit. */
 1129         if (ifp->if_flags & IFF_PROMISC) {
 1130                 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
 1131         } else {
 1132                 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
 1133         }
 1134 
 1135         /* Set the capture broadcast bit to capture broadcast frames. */
 1136         if (ifp->if_flags & IFF_BROADCAST) {
 1137                 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
 1138         } else {
 1139                 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
 1140         }
 1141 
 1142         return;
 1143 }
 1144 
 1145 static void
 1146 pcn_init(xsc)
 1147         void                    *xsc;
 1148 {
 1149         struct pcn_softc        *sc = xsc;
 1150         struct ifnet            *ifp = &sc->arpcom.ac_if;
 1151         struct mii_data         *mii = NULL;
 1152 
 1153         PCN_LOCK(sc);
 1154 
 1155         /*
 1156          * Cancel pending I/O and free all RX/TX buffers.
 1157          */
 1158         pcn_stop(sc);
 1159         pcn_reset(sc);
 1160 
 1161         mii = device_get_softc(sc->pcn_miibus);
 1162 
 1163         /* Set MAC address */
 1164         pcn_csr_write(sc, PCN_CSR_PAR0,
 1165             ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
 1166         pcn_csr_write(sc, PCN_CSR_PAR1,
 1167             ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
 1168         pcn_csr_write(sc, PCN_CSR_PAR2,
 1169             ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
 1170 
 1171         /* Init circular RX list. */
 1172         if (pcn_list_rx_init(sc) == ENOBUFS) {
 1173                 printf("pcn%d: initialization failed: no "
 1174                     "memory for rx buffers\n", sc->pcn_unit);
 1175                 pcn_stop(sc);
 1176                 PCN_UNLOCK(sc);
 1177                 return;
 1178         }
 1179 
 1180         /*
 1181          * Init tx descriptors.
 1182          */
 1183         pcn_list_tx_init(sc);
 1184 
 1185         /* Set up the mode register. */
 1186         pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
 1187 
 1188         /* Set up RX filter. */
 1189         pcn_setfilt(ifp);
 1190 
 1191         /*
 1192          * Load the multicast filter.
 1193          */
 1194         pcn_setmulti(sc);
 1195 
 1196         /*
 1197          * Load the addresses of the RX and TX lists.
 1198          */
 1199         pcn_csr_write(sc, PCN_CSR_RXADDR0,
 1200             vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
 1201         pcn_csr_write(sc, PCN_CSR_RXADDR1,
 1202             (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
 1203         pcn_csr_write(sc, PCN_CSR_TXADDR0,
 1204             vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
 1205         pcn_csr_write(sc, PCN_CSR_TXADDR1,
 1206             (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
 1207 
 1208         /* Set the RX and TX ring sizes. */
 1209         pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
 1210         pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
 1211 
 1212         /* We're not using the initialization block. */
 1213         pcn_csr_write(sc, PCN_CSR_IAB1, 0);
 1214 
 1215         /* Enable fast suspend mode. */
 1216         PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
 1217 
 1218         /*
 1219          * Enable burst read and write. Also set the no underflow
 1220          * bit. This will avoid transmit underruns in certain
 1221          * conditions while still providing decent performance.
 1222          */
 1223         PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
 1224             PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
 1225 
 1226         /* Enable graceful recovery from underflow. */
 1227         PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
 1228 
 1229         /* Enable auto-padding of short TX frames. */
 1230         PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
 1231 
 1232         /* Disable MII autoneg (we handle this ourselves). */
 1233         PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
 1234 
 1235         if (sc->pcn_type == Am79C978)
 1236                 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
 1237                     PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
 1238 
 1239         /* Enable interrupts and start the controller running. */
 1240         pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
 1241 
 1242         mii_mediachg(mii);
 1243 
 1244         ifp->if_flags |= IFF_RUNNING;
 1245         ifp->if_flags &= ~IFF_OACTIVE;
 1246 
 1247         sc->pcn_stat_ch = timeout(pcn_tick, sc, hz);
 1248         PCN_UNLOCK(sc);
 1249 
 1250         return;
 1251 }
 1252 
 1253 /*
 1254  * Set media options.
 1255  */
 1256 static int
 1257 pcn_ifmedia_upd(ifp)
 1258         struct ifnet            *ifp;
 1259 {
 1260         struct pcn_softc        *sc;
 1261         struct mii_data         *mii;
 1262 
 1263         sc = ifp->if_softc;
 1264         mii = device_get_softc(sc->pcn_miibus);
 1265 
 1266         sc->pcn_link = 0;
 1267         if (mii->mii_instance) {
 1268                 struct mii_softc        *miisc;
 1269                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 1270                         mii_phy_reset(miisc);
 1271         }
 1272         mii_mediachg(mii);
 1273 
 1274         return(0);
 1275 }
 1276 
 1277 /*
 1278  * Report current media status.
 1279  */
 1280 static void
 1281 pcn_ifmedia_sts(ifp, ifmr)
 1282         struct ifnet            *ifp;
 1283         struct ifmediareq       *ifmr;
 1284 {
 1285         struct pcn_softc        *sc;
 1286         struct mii_data         *mii;
 1287 
 1288         sc = ifp->if_softc;
 1289 
 1290         mii = device_get_softc(sc->pcn_miibus);
 1291         mii_pollstat(mii);
 1292         ifmr->ifm_active = mii->mii_media_active;
 1293         ifmr->ifm_status = mii->mii_media_status;
 1294 
 1295         return;
 1296 }
 1297 
 1298 static int
 1299 pcn_ioctl(ifp, command, data)
 1300         struct ifnet            *ifp;
 1301         u_long                  command;
 1302         caddr_t                 data;
 1303 {
 1304         struct pcn_softc        *sc = ifp->if_softc;
 1305         struct ifreq            *ifr = (struct ifreq *) data;
 1306         struct mii_data         *mii = NULL;
 1307         int                     error = 0;
 1308 
 1309         PCN_LOCK(sc);
 1310 
 1311         switch(command) {
 1312         case SIOCSIFFLAGS:
 1313                 if (ifp->if_flags & IFF_UP) {
 1314                         if (ifp->if_flags & IFF_RUNNING &&
 1315                             ifp->if_flags & IFF_PROMISC &&
 1316                             !(sc->pcn_if_flags & IFF_PROMISC)) {
 1317                                 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
 1318                                     PCN_EXTCTL1_SPND);
 1319                                 pcn_setfilt(ifp);
 1320                                 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
 1321                                     PCN_EXTCTL1_SPND);
 1322                                 pcn_csr_write(sc, PCN_CSR_CSR,
 1323                                     PCN_CSR_INTEN|PCN_CSR_START);
 1324                         } else if (ifp->if_flags & IFF_RUNNING &&
 1325                             !(ifp->if_flags & IFF_PROMISC) &&
 1326                                 sc->pcn_if_flags & IFF_PROMISC) {
 1327                                 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
 1328                                     PCN_EXTCTL1_SPND);
 1329                                 pcn_setfilt(ifp);
 1330                                 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
 1331                                     PCN_EXTCTL1_SPND);
 1332                                 pcn_csr_write(sc, PCN_CSR_CSR,
 1333                                     PCN_CSR_INTEN|PCN_CSR_START);
 1334                         } else if (!(ifp->if_flags & IFF_RUNNING))
 1335                                 pcn_init(sc);
 1336                 } else {
 1337                         if (ifp->if_flags & IFF_RUNNING)
 1338                                 pcn_stop(sc);
 1339                 }
 1340                 sc->pcn_if_flags = ifp->if_flags;
 1341                 error = 0;
 1342                 break;
 1343         case SIOCADDMULTI:
 1344         case SIOCDELMULTI:
 1345                 pcn_setmulti(sc);
 1346                 error = 0;
 1347                 break;
 1348         case SIOCGIFMEDIA:
 1349         case SIOCSIFMEDIA:
 1350                 mii = device_get_softc(sc->pcn_miibus);
 1351                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 1352                 break;
 1353         default:
 1354                 error = ether_ioctl(ifp, command, data);
 1355                 break;
 1356         }
 1357 
 1358         PCN_UNLOCK(sc);
 1359 
 1360         return(error);
 1361 }
 1362 
 1363 static void
 1364 pcn_watchdog(ifp)
 1365         struct ifnet            *ifp;
 1366 {
 1367         struct pcn_softc        *sc;
 1368 
 1369         sc = ifp->if_softc;
 1370 
 1371         PCN_LOCK(sc);
 1372 
 1373         ifp->if_oerrors++;
 1374         printf("pcn%d: watchdog timeout\n", sc->pcn_unit);
 1375 
 1376         pcn_stop(sc);
 1377         pcn_reset(sc);
 1378         pcn_init(sc);
 1379 
 1380         if (ifp->if_snd.ifq_head != NULL)
 1381                 pcn_start(ifp);
 1382 
 1383         PCN_UNLOCK(sc);
 1384 
 1385         return;
 1386 }
 1387 
 1388 /*
 1389  * Stop the adapter and free any mbufs allocated to the
 1390  * RX and TX lists.
 1391  */
 1392 static void
 1393 pcn_stop(sc)
 1394         struct pcn_softc        *sc;
 1395 {
 1396         register int            i;
 1397         struct ifnet            *ifp;
 1398 
 1399         ifp = &sc->arpcom.ac_if;
 1400         PCN_LOCK(sc);
 1401         ifp->if_timer = 0;
 1402 
 1403         untimeout(pcn_tick, sc, sc->pcn_stat_ch);
 1404         PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
 1405         sc->pcn_link = 0;
 1406 
 1407         /*
 1408          * Free data in the RX lists.
 1409          */
 1410         for (i = 0; i < PCN_RX_LIST_CNT; i++) {
 1411                 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
 1412                         m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
 1413                         sc->pcn_cdata.pcn_rx_chain[i] = NULL;
 1414                 }
 1415         }
 1416         bzero((char *)&sc->pcn_ldata->pcn_rx_list,
 1417                 sizeof(sc->pcn_ldata->pcn_rx_list));
 1418 
 1419         /*
 1420          * Free the TX list buffers.
 1421          */
 1422         for (i = 0; i < PCN_TX_LIST_CNT; i++) {
 1423                 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
 1424                         m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
 1425                         sc->pcn_cdata.pcn_tx_chain[i] = NULL;
 1426                 }
 1427         }
 1428 
 1429         bzero((char *)&sc->pcn_ldata->pcn_tx_list,
 1430                 sizeof(sc->pcn_ldata->pcn_tx_list));
 1431 
 1432         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 1433         PCN_UNLOCK(sc);
 1434 
 1435         return;
 1436 }
 1437 
 1438 /*
 1439  * Stop all chip I/O so that the kernel's probe routines don't
 1440  * get confused by errant DMAs when rebooting.
 1441  */
 1442 static void
 1443 pcn_shutdown(dev)
 1444         device_t                dev;
 1445 {
 1446         struct pcn_softc        *sc;
 1447 
 1448         sc = device_get_softc(dev);
 1449 
 1450         PCN_LOCK(sc);
 1451         pcn_reset(sc);
 1452         pcn_stop(sc);
 1453         PCN_UNLOCK(sc);
 1454 
 1455         return;
 1456 }

Cache object: 4cd25cd5797cc01fad3127a0acdd47a6


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.