FreeBSD/Linux Kernel Cross Reference
sys/pci/if_pcn.c
1 /*-
2 * Copyright (c) 2000 Berkeley Software Design, Inc.
3 * Copyright (c) 1997, 1998, 1999, 2000
4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: src/sys/pci/if_pcn.c,v 1.59.2.4 2006/01/29 15:39:08 emaste Exp $");
36
37 /*
38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available
39 * from http://www.amd.com.
40 *
41 * The AMD PCnet/PCI controllers are more advanced and functional
42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
43 * backwards compatibility with the LANCE and thus can be made
44 * to work with older LANCE drivers. This is in fact how the
45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble
46 * is that the PCnet/PCI devices offer several performance enhancements
47 * which can't be exploited in LANCE compatibility mode. Chief among
48 * these enhancements is the ability to perform PCI DMA operations
49 * using 32-bit addressing (which eliminates the need for ISA
50 * bounce-buffering), and special receive buffer alignment (which
51 * allows the receive handler to pass packets to the upper protocol
52 * layers without copying on both the x86 and alpha platforms).
53 */
54
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/sockio.h>
58 #include <sys/mbuf.h>
59 #include <sys/malloc.h>
60 #include <sys/kernel.h>
61 #include <sys/module.h>
62 #include <sys/socket.h>
63
64 #include <net/if.h>
65 #include <net/if_arp.h>
66 #include <net/ethernet.h>
67 #include <net/if_dl.h>
68 #include <net/if_media.h>
69
70 #include <net/bpf.h>
71
72 #include <vm/vm.h> /* for vtophys */
73 #include <vm/pmap.h> /* for vtophys */
74 #include <machine/bus_pio.h>
75 #include <machine/bus_memio.h>
76 #include <machine/bus.h>
77 #include <machine/resource.h>
78 #include <sys/bus.h>
79 #include <sys/rman.h>
80
81 #include <dev/mii/mii.h>
82 #include <dev/mii/miivar.h>
83
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86
87 #define PCN_USEIOSPACE
88
89 #include <pci/if_pcnreg.h>
90
91 MODULE_DEPEND(pcn, pci, 1, 1, 1);
92 MODULE_DEPEND(pcn, ether, 1, 1, 1);
93 MODULE_DEPEND(pcn, miibus, 1, 1, 1);
94
95 /* "controller miibus0" required. See GENERIC if you get errors here. */
96 #include "miibus_if.h"
97
98 /*
99 * Various supported device vendors/types and their names.
100 */
101 static struct pcn_type pcn_devs[] = {
102 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
103 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
104 { 0, 0, NULL }
105 };
106
107 static u_int32_t pcn_csr_read (struct pcn_softc *, int);
108 static u_int16_t pcn_csr_read16 (struct pcn_softc *, int);
109 static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int);
110 static void pcn_csr_write (struct pcn_softc *, int, int);
111 static u_int32_t pcn_bcr_read (struct pcn_softc *, int);
112 static void pcn_bcr_write (struct pcn_softc *, int, int);
113
114 static int pcn_probe (device_t);
115 static int pcn_attach (device_t);
116 static int pcn_detach (device_t);
117
118 static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *);
119 static int pcn_encap (struct pcn_softc *,
120 struct mbuf *, u_int32_t *);
121 static void pcn_rxeof (struct pcn_softc *);
122 static void pcn_txeof (struct pcn_softc *);
123 static void pcn_intr (void *);
124 static void pcn_tick (void *);
125 static void pcn_start (struct ifnet *);
126 static int pcn_ioctl (struct ifnet *, u_long, caddr_t);
127 static void pcn_init (void *);
128 static void pcn_stop (struct pcn_softc *);
129 static void pcn_watchdog (struct ifnet *);
130 static void pcn_shutdown (device_t);
131 static int pcn_ifmedia_upd (struct ifnet *);
132 static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *);
133
134 static int pcn_miibus_readreg (device_t, int, int);
135 static int pcn_miibus_writereg (device_t, int, int, int);
136 static void pcn_miibus_statchg (device_t);
137
138 static void pcn_setfilt (struct ifnet *);
139 static void pcn_setmulti (struct pcn_softc *);
140 static void pcn_reset (struct pcn_softc *);
141 static int pcn_list_rx_init (struct pcn_softc *);
142 static int pcn_list_tx_init (struct pcn_softc *);
143
144 #ifdef PCN_USEIOSPACE
145 #define PCN_RES SYS_RES_IOPORT
146 #define PCN_RID PCN_PCI_LOIO
147 #else
148 #define PCN_RES SYS_RES_MEMORY
149 #define PCN_RID PCN_PCI_LOMEM
150 #endif
151
152 static device_method_t pcn_methods[] = {
153 /* Device interface */
154 DEVMETHOD(device_probe, pcn_probe),
155 DEVMETHOD(device_attach, pcn_attach),
156 DEVMETHOD(device_detach, pcn_detach),
157 DEVMETHOD(device_shutdown, pcn_shutdown),
158
159 /* bus interface */
160 DEVMETHOD(bus_print_child, bus_generic_print_child),
161 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
162
163 /* MII interface */
164 DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
165 DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
166 DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
167
168 { 0, 0 }
169 };
170
171 static driver_t pcn_driver = {
172 "pcn",
173 pcn_methods,
174 sizeof(struct pcn_softc)
175 };
176
177 static devclass_t pcn_devclass;
178
179 DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0);
180 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
181
182 #define PCN_CSR_SETBIT(sc, reg, x) \
183 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
184
185 #define PCN_CSR_CLRBIT(sc, reg, x) \
186 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
187
188 #define PCN_BCR_SETBIT(sc, reg, x) \
189 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
190
191 #define PCN_BCR_CLRBIT(sc, reg, x) \
192 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
193
194 static u_int32_t
195 pcn_csr_read(sc, reg)
196 struct pcn_softc *sc;
197 int reg;
198 {
199 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
200 return(CSR_READ_4(sc, PCN_IO32_RDP));
201 }
202
203 static u_int16_t
204 pcn_csr_read16(sc, reg)
205 struct pcn_softc *sc;
206 int reg;
207 {
208 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
209 return(CSR_READ_2(sc, PCN_IO16_RDP));
210 }
211
212 static void
213 pcn_csr_write(sc, reg, val)
214 struct pcn_softc *sc;
215 int reg;
216 int val;
217 {
218 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
219 CSR_WRITE_4(sc, PCN_IO32_RDP, val);
220 return;
221 }
222
223 static u_int32_t
224 pcn_bcr_read(sc, reg)
225 struct pcn_softc *sc;
226 int reg;
227 {
228 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
229 return(CSR_READ_4(sc, PCN_IO32_BDP));
230 }
231
232 static u_int16_t
233 pcn_bcr_read16(sc, reg)
234 struct pcn_softc *sc;
235 int reg;
236 {
237 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
238 return(CSR_READ_2(sc, PCN_IO16_BDP));
239 }
240
241 static void
242 pcn_bcr_write(sc, reg, val)
243 struct pcn_softc *sc;
244 int reg;
245 int val;
246 {
247 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
248 CSR_WRITE_4(sc, PCN_IO32_BDP, val);
249 return;
250 }
251
252 static int
253 pcn_miibus_readreg(dev, phy, reg)
254 device_t dev;
255 int phy, reg;
256 {
257 struct pcn_softc *sc;
258 int val;
259
260 sc = device_get_softc(dev);
261
262 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr)
263 return(0);
264
265 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
266 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
267 if (val == 0xFFFF)
268 return(0);
269
270 sc->pcn_phyaddr = phy;
271
272 return(val);
273 }
274
275 static int
276 pcn_miibus_writereg(dev, phy, reg, data)
277 device_t dev;
278 int phy, reg, data;
279 {
280 struct pcn_softc *sc;
281
282 sc = device_get_softc(dev);
283
284 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
285 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
286
287 return(0);
288 }
289
290 static void
291 pcn_miibus_statchg(dev)
292 device_t dev;
293 {
294 struct pcn_softc *sc;
295 struct mii_data *mii;
296
297 sc = device_get_softc(dev);
298 mii = device_get_softc(sc->pcn_miibus);
299
300 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
301 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
302 } else {
303 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
304 }
305
306 return;
307 }
308
309 static void
310 pcn_setmulti(sc)
311 struct pcn_softc *sc;
312 {
313 struct ifnet *ifp;
314 struct ifmultiaddr *ifma;
315 u_int32_t h, i;
316 u_int16_t hashes[4] = { 0, 0, 0, 0 };
317
318 ifp = &sc->arpcom.ac_if;
319
320 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
321
322 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
323 for (i = 0; i < 4; i++)
324 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
325 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
326 return;
327 }
328
329 /* first, zot all the existing hash bits */
330 for (i = 0; i < 4; i++)
331 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
332
333 /* now program new ones */
334 IF_ADDR_LOCK(ifp);
335 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
336 if (ifma->ifma_addr->sa_family != AF_LINK)
337 continue;
338 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
339 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
340 hashes[h >> 4] |= 1 << (h & 0xF);
341 }
342 IF_ADDR_UNLOCK(ifp);
343
344 for (i = 0; i < 4; i++)
345 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
346
347 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
348
349 return;
350 }
351
352 static void
353 pcn_reset(sc)
354 struct pcn_softc *sc;
355 {
356 /*
357 * Issue a reset by reading from the RESET register.
358 * Note that we don't know if the chip is operating in
359 * 16-bit or 32-bit mode at this point, so we attempt
360 * to reset the chip both ways. If one fails, the other
361 * will succeed.
362 */
363 CSR_READ_2(sc, PCN_IO16_RESET);
364 CSR_READ_4(sc, PCN_IO32_RESET);
365
366 /* Wait a little while for the chip to get its brains in order. */
367 DELAY(1000);
368
369 /* Select 32-bit (DWIO) mode */
370 CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
371
372 /* Select software style 3. */
373 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
374
375 return;
376 }
377
378 /*
379 * Probe for an AMD chip. Check the PCI vendor and device
380 * IDs against our list and return a device name if we find a match.
381 */
382 static int
383 pcn_probe(dev)
384 device_t dev;
385 {
386 struct pcn_type *t;
387 struct pcn_softc *sc;
388 int rid;
389 u_int32_t chip_id;
390
391 t = pcn_devs;
392 sc = device_get_softc(dev);
393
394 while(t->pcn_name != NULL) {
395 if ((pci_get_vendor(dev) == t->pcn_vid) &&
396 (pci_get_device(dev) == t->pcn_did)) {
397 /*
398 * Temporarily map the I/O space
399 * so we can read the chip ID register.
400 */
401 rid = PCN_RID;
402 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid,
403 RF_ACTIVE);
404 if (sc->pcn_res == NULL) {
405 device_printf(dev,
406 "couldn't map ports/memory\n");
407 return(ENXIO);
408 }
409 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
410 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
411 mtx_init(&sc->pcn_mtx,
412 device_get_nameunit(dev), MTX_NETWORK_LOCK,
413 MTX_DEF);
414 PCN_LOCK(sc);
415 /*
416 * Note: we can *NOT* put the chip into
417 * 32-bit mode yet. The lnc driver will only
418 * work in 16-bit mode, and once the chip
419 * goes into 32-bit mode, the only way to
420 * get it out again is with a hardware reset.
421 * So if pcn_probe() is called before the
422 * lnc driver's probe routine, the chip will
423 * be locked into 32-bit operation and the lnc
424 * driver will be unable to attach to it.
425 * Note II: if the chip happens to already
426 * be in 32-bit mode, we still need to check
427 * the chip ID, but first we have to detect
428 * 32-bit mode using only 16-bit operations.
429 * The safest way to do this is to read the
430 * PCI subsystem ID from BCR23/24 and compare
431 * that with the value read from PCI config
432 * space.
433 */
434 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
435 chip_id <<= 16;
436 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
437 /*
438 * Note III: the test for 0x10001000 is a hack to
439 * pacify VMware, who's pseudo-PCnet interface is
440 * broken. Reading the subsystem register from PCI
441 * config space yields 0x00000000 while reading the
442 * same value from I/O space yields 0x10001000. It's
443 * not supposed to be that way.
444 */
445 if (chip_id == pci_read_config(dev,
446 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
447 /* We're in 16-bit mode. */
448 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
449 chip_id <<= 16;
450 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
451 } else {
452 /* We're in 32-bit mode. */
453 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
454 chip_id <<= 16;
455 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
456 }
457 bus_release_resource(dev, PCN_RES,
458 PCN_RID, sc->pcn_res);
459 PCN_UNLOCK(sc);
460 mtx_destroy(&sc->pcn_mtx);
461 chip_id >>= 12;
462 sc->pcn_type = chip_id & PART_MASK;
463 switch(sc->pcn_type) {
464 case Am79C971:
465 case Am79C972:
466 case Am79C973:
467 case Am79C975:
468 case Am79C976:
469 case Am79C978:
470 break;
471 default:
472 return(ENXIO);
473 }
474 device_set_desc(dev, t->pcn_name);
475 return(0);
476 }
477 t++;
478 }
479
480 return(ENXIO);
481 }
482
483 /*
484 * Attach the interface. Allocate softc structures, do ifmedia
485 * setup and ethernet/BPF attach.
486 */
487 static int
488 pcn_attach(dev)
489 device_t dev;
490 {
491 u_int32_t eaddr[2];
492 struct pcn_softc *sc;
493 struct ifnet *ifp;
494 int unit, error = 0, rid;
495
496 sc = device_get_softc(dev);
497 unit = device_get_unit(dev);
498
499 /* Initialize our mutex. */
500 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
501 MTX_DEF | MTX_RECURSE);
502 /*
503 * Map control/status registers.
504 */
505 pci_enable_busmaster(dev);
506
507 rid = PCN_RID;
508 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
509
510 if (sc->pcn_res == NULL) {
511 printf("pcn%d: couldn't map ports/memory\n", unit);
512 error = ENXIO;
513 goto fail;
514 }
515
516 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
517 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
518
519 /* Allocate interrupt */
520 rid = 0;
521 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
522 RF_SHAREABLE | RF_ACTIVE);
523
524 if (sc->pcn_irq == NULL) {
525 printf("pcn%d: couldn't map interrupt\n", unit);
526 error = ENXIO;
527 goto fail;
528 }
529
530 /* Reset the adapter. */
531 pcn_reset(sc);
532
533 /*
534 * Get station address from the EEPROM.
535 */
536 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00);
537 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01);
538 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
539
540 sc->pcn_unit = unit;
541 callout_handle_init(&sc->pcn_stat_ch);
542
543 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
544 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
545
546 if (sc->pcn_ldata == NULL) {
547 printf("pcn%d: no memory for list buffers!\n", unit);
548 error = ENXIO;
549 goto fail;
550 }
551 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
552
553 ifp = &sc->arpcom.ac_if;
554 ifp->if_softc = sc;
555 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
556 ifp->if_mtu = ETHERMTU;
557 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
558 IFF_NEEDSGIANT;
559 ifp->if_ioctl = pcn_ioctl;
560 ifp->if_start = pcn_start;
561 ifp->if_watchdog = pcn_watchdog;
562 ifp->if_init = pcn_init;
563 ifp->if_baudrate = 10000000;
564 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1;
565
566 /*
567 * Do MII setup.
568 */
569 if (mii_phy_probe(dev, &sc->pcn_miibus,
570 pcn_ifmedia_upd, pcn_ifmedia_sts)) {
571 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit);
572 error = ENXIO;
573 goto fail;
574 }
575
576 /*
577 * Call MI attach routine.
578 */
579 ether_ifattach(ifp, (u_int8_t *) eaddr);
580
581 /* Hook interrupt last to avoid having to lock softc */
582 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET,
583 pcn_intr, sc, &sc->pcn_intrhand);
584
585 if (error) {
586 printf("pcn%d: couldn't set up irq\n", unit);
587 ether_ifdetach(ifp);
588 goto fail;
589 }
590
591 fail:
592 if (error)
593 pcn_detach(dev);
594
595 return(error);
596 }
597
598 /*
599 * Shutdown hardware and free up resources. This can be called any
600 * time after the mutex has been initialized. It is called in both
601 * the error case in attach and the normal detach case so it needs
602 * to be careful about only freeing resources that have actually been
603 * allocated.
604 */
605 static int
606 pcn_detach(dev)
607 device_t dev;
608 {
609 struct pcn_softc *sc;
610 struct ifnet *ifp;
611
612 sc = device_get_softc(dev);
613 ifp = &sc->arpcom.ac_if;
614
615 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized"));
616 PCN_LOCK(sc);
617
618 /* These should only be active if attach succeeded */
619 if (device_is_attached(dev)) {
620 pcn_reset(sc);
621 pcn_stop(sc);
622 ether_ifdetach(ifp);
623 }
624 if (sc->pcn_miibus)
625 device_delete_child(dev, sc->pcn_miibus);
626 bus_generic_detach(dev);
627
628 if (sc->pcn_intrhand)
629 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
630 if (sc->pcn_irq)
631 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
632 if (sc->pcn_res)
633 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
634
635 if (sc->pcn_ldata) {
636 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
637 M_DEVBUF);
638 }
639 PCN_UNLOCK(sc);
640
641 mtx_destroy(&sc->pcn_mtx);
642
643 return(0);
644 }
645
646 /*
647 * Initialize the transmit descriptors.
648 */
649 static int
650 pcn_list_tx_init(sc)
651 struct pcn_softc *sc;
652 {
653 struct pcn_list_data *ld;
654 struct pcn_ring_data *cd;
655 int i;
656
657 cd = &sc->pcn_cdata;
658 ld = sc->pcn_ldata;
659
660 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
661 cd->pcn_tx_chain[i] = NULL;
662 ld->pcn_tx_list[i].pcn_tbaddr = 0;
663 ld->pcn_tx_list[i].pcn_txctl = 0;
664 ld->pcn_tx_list[i].pcn_txstat = 0;
665 }
666
667 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
668
669 return(0);
670 }
671
672
673 /*
674 * Initialize the RX descriptors and allocate mbufs for them.
675 */
676 static int
677 pcn_list_rx_init(sc)
678 struct pcn_softc *sc;
679 {
680 struct pcn_ring_data *cd;
681 int i;
682
683 cd = &sc->pcn_cdata;
684
685 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
686 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
687 return(ENOBUFS);
688 }
689
690 cd->pcn_rx_prod = 0;
691
692 return(0);
693 }
694
695 /*
696 * Initialize an RX descriptor and attach an MBUF cluster.
697 */
698 static int
699 pcn_newbuf(sc, idx, m)
700 struct pcn_softc *sc;
701 int idx;
702 struct mbuf *m;
703 {
704 struct mbuf *m_new = NULL;
705 struct pcn_rx_desc *c;
706
707 c = &sc->pcn_ldata->pcn_rx_list[idx];
708
709 if (m == NULL) {
710 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
711 if (m_new == NULL)
712 return(ENOBUFS);
713
714 MCLGET(m_new, M_DONTWAIT);
715 if (!(m_new->m_flags & M_EXT)) {
716 m_freem(m_new);
717 return(ENOBUFS);
718 }
719 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
720 } else {
721 m_new = m;
722 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
723 m_new->m_data = m_new->m_ext.ext_buf;
724 }
725
726 m_adj(m_new, ETHER_ALIGN);
727
728 sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
729 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
730 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
731 c->pcn_bufsz |= PCN_RXLEN_MBO;
732 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
733
734 return(0);
735 }
736
737 /*
738 * A frame has been uploaded: pass the resulting mbuf chain up to
739 * the higher level protocols.
740 */
741 static void
742 pcn_rxeof(sc)
743 struct pcn_softc *sc;
744 {
745 struct mbuf *m;
746 struct ifnet *ifp;
747 struct pcn_rx_desc *cur_rx;
748 int i;
749
750 PCN_LOCK_ASSERT(sc);
751
752 ifp = &sc->arpcom.ac_if;
753 i = sc->pcn_cdata.pcn_rx_prod;
754
755 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
756 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
757 m = sc->pcn_cdata.pcn_rx_chain[i];
758 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
759
760 /*
761 * If an error occurs, update stats, clear the
762 * status word and leave the mbuf cluster in place:
763 * it should simply get re-used next time this descriptor
764 * comes up in the ring.
765 */
766 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
767 ifp->if_ierrors++;
768 pcn_newbuf(sc, i, m);
769 PCN_INC(i, PCN_RX_LIST_CNT);
770 continue;
771 }
772
773 if (pcn_newbuf(sc, i, NULL)) {
774 /* Ran out of mbufs; recycle this one. */
775 pcn_newbuf(sc, i, m);
776 ifp->if_ierrors++;
777 PCN_INC(i, PCN_RX_LIST_CNT);
778 continue;
779 }
780
781 PCN_INC(i, PCN_RX_LIST_CNT);
782
783 /* No errors; receive the packet. */
784 ifp->if_ipackets++;
785 m->m_len = m->m_pkthdr.len =
786 cur_rx->pcn_rxlen - ETHER_CRC_LEN;
787 m->m_pkthdr.rcvif = ifp;
788
789 PCN_UNLOCK(sc);
790 (*ifp->if_input)(ifp, m);
791 PCN_LOCK(sc);
792 }
793
794 sc->pcn_cdata.pcn_rx_prod = i;
795
796 return;
797 }
798
799 /*
800 * A frame was downloaded to the chip. It's safe for us to clean up
801 * the list buffers.
802 */
803
804 static void
805 pcn_txeof(sc)
806 struct pcn_softc *sc;
807 {
808 struct pcn_tx_desc *cur_tx = NULL;
809 struct ifnet *ifp;
810 u_int32_t idx;
811
812 ifp = &sc->arpcom.ac_if;
813
814 /*
815 * Go through our tx list and free mbufs for those
816 * frames that have been transmitted.
817 */
818 idx = sc->pcn_cdata.pcn_tx_cons;
819 while (idx != sc->pcn_cdata.pcn_tx_prod) {
820 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
821
822 if (!PCN_OWN_TXDESC(cur_tx))
823 break;
824
825 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
826 sc->pcn_cdata.pcn_tx_cnt--;
827 PCN_INC(idx, PCN_TX_LIST_CNT);
828 continue;
829 }
830
831 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
832 ifp->if_oerrors++;
833 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
834 ifp->if_collisions++;
835 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
836 ifp->if_collisions++;
837 }
838
839 ifp->if_collisions +=
840 cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
841
842 ifp->if_opackets++;
843 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
844 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
845 sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
846 }
847
848 sc->pcn_cdata.pcn_tx_cnt--;
849 PCN_INC(idx, PCN_TX_LIST_CNT);
850 }
851
852 if (idx != sc->pcn_cdata.pcn_tx_cons) {
853 /* Some buffers have been freed. */
854 sc->pcn_cdata.pcn_tx_cons = idx;
855 ifp->if_flags &= ~IFF_OACTIVE;
856 }
857 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
858
859 return;
860 }
861
862 static void
863 pcn_tick(xsc)
864 void *xsc;
865 {
866 struct pcn_softc *sc;
867 struct mii_data *mii;
868 struct ifnet *ifp;
869
870 sc = xsc;
871 ifp = &sc->arpcom.ac_if;
872 PCN_LOCK(sc);
873
874 mii = device_get_softc(sc->pcn_miibus);
875 mii_tick(mii);
876
877 /* link just died */
878 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
879 sc->pcn_link = 0;
880
881 /* link just came up, restart */
882 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE &&
883 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
884 sc->pcn_link++;
885 if (ifp->if_snd.ifq_head != NULL)
886 pcn_start(ifp);
887 }
888
889 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz);
890
891 PCN_UNLOCK(sc);
892
893 return;
894 }
895
896 static void
897 pcn_intr(arg)
898 void *arg;
899 {
900 struct pcn_softc *sc;
901 struct ifnet *ifp;
902 u_int32_t status;
903
904 sc = arg;
905 ifp = &sc->arpcom.ac_if;
906
907 /* Suppress unwanted interrupts */
908 if (!(ifp->if_flags & IFF_UP)) {
909 pcn_stop(sc);
910 return;
911 }
912
913 PCN_LOCK(sc);
914
915 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
916
917 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
918 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
919
920 if (status & PCN_CSR_RINT)
921 pcn_rxeof(sc);
922
923 if (status & PCN_CSR_TINT)
924 pcn_txeof(sc);
925
926 if (status & PCN_CSR_ERR) {
927 pcn_init(sc);
928 break;
929 }
930 }
931
932 if (ifp->if_snd.ifq_head != NULL)
933 pcn_start(ifp);
934
935 PCN_UNLOCK(sc);
936 return;
937 }
938
939 /*
940 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
941 * pointers to the fragment pointers.
942 */
943 static int
944 pcn_encap(sc, m_head, txidx)
945 struct pcn_softc *sc;
946 struct mbuf *m_head;
947 u_int32_t *txidx;
948 {
949 struct pcn_tx_desc *f = NULL;
950 struct mbuf *m;
951 int frag, cur, cnt = 0;
952
953 /*
954 * Start packing the mbufs in this chain into
955 * the fragment pointers. Stop when we run out
956 * of fragments or hit the end of the mbuf chain.
957 */
958 m = m_head;
959 cur = frag = *txidx;
960
961 for (m = m_head; m != NULL; m = m->m_next) {
962 if (m->m_len != 0) {
963 if ((PCN_TX_LIST_CNT -
964 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
965 return(ENOBUFS);
966 f = &sc->pcn_ldata->pcn_tx_list[frag];
967 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
968 f->pcn_txctl |= PCN_TXCTL_MBO;
969 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
970 if (cnt == 0)
971 f->pcn_txctl |= PCN_TXCTL_STP;
972 else
973 f->pcn_txctl |= PCN_TXCTL_OWN;
974 cur = frag;
975 PCN_INC(frag, PCN_TX_LIST_CNT);
976 cnt++;
977 }
978 }
979
980 if (m != NULL)
981 return(ENOBUFS);
982
983 sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
984 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
985 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
986 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
987 sc->pcn_cdata.pcn_tx_cnt += cnt;
988 *txidx = frag;
989
990 return(0);
991 }
992
993 /*
994 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
995 * to the mbuf data regions directly in the transmit lists. We also save a
996 * copy of the pointers since the transmit list fragment pointers are
997 * physical addresses.
998 */
999 static void
1000 pcn_start(ifp)
1001 struct ifnet *ifp;
1002 {
1003 struct pcn_softc *sc;
1004 struct mbuf *m_head = NULL;
1005 u_int32_t idx;
1006
1007 sc = ifp->if_softc;
1008
1009 PCN_LOCK(sc);
1010
1011 if (!sc->pcn_link) {
1012 PCN_UNLOCK(sc);
1013 return;
1014 }
1015
1016 idx = sc->pcn_cdata.pcn_tx_prod;
1017
1018 if (ifp->if_flags & IFF_OACTIVE) {
1019 PCN_UNLOCK(sc);
1020 return;
1021 }
1022
1023 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
1024 IF_DEQUEUE(&ifp->if_snd, m_head);
1025 if (m_head == NULL)
1026 break;
1027
1028 if (pcn_encap(sc, m_head, &idx)) {
1029 IF_PREPEND(&ifp->if_snd, m_head);
1030 ifp->if_flags |= IFF_OACTIVE;
1031 break;
1032 }
1033
1034 /*
1035 * If there's a BPF listener, bounce a copy of this frame
1036 * to him.
1037 */
1038 BPF_MTAP(ifp, m_head);
1039
1040 }
1041
1042 /* Transmit */
1043 sc->pcn_cdata.pcn_tx_prod = idx;
1044 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
1045
1046 /*
1047 * Set a timeout in case the chip goes out to lunch.
1048 */
1049 ifp->if_timer = 5;
1050
1051 PCN_UNLOCK(sc);
1052
1053 return;
1054 }
1055
1056 static void
1057 pcn_setfilt(ifp)
1058 struct ifnet *ifp;
1059 {
1060 struct pcn_softc *sc;
1061
1062 sc = ifp->if_softc;
1063
1064 /* If we want promiscuous mode, set the allframes bit. */
1065 if (ifp->if_flags & IFF_PROMISC) {
1066 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1067 } else {
1068 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1069 }
1070
1071 /* Set the capture broadcast bit to capture broadcast frames. */
1072 if (ifp->if_flags & IFF_BROADCAST) {
1073 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1074 } else {
1075 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1076 }
1077
1078 return;
1079 }
1080
1081 static void
1082 pcn_init(xsc)
1083 void *xsc;
1084 {
1085 struct pcn_softc *sc = xsc;
1086 struct ifnet *ifp = &sc->arpcom.ac_if;
1087 struct mii_data *mii = NULL;
1088
1089 PCN_LOCK(sc);
1090
1091 /*
1092 * Cancel pending I/O and free all RX/TX buffers.
1093 */
1094 pcn_stop(sc);
1095 pcn_reset(sc);
1096
1097 mii = device_get_softc(sc->pcn_miibus);
1098
1099 /* Set MAC address */
1100 pcn_csr_write(sc, PCN_CSR_PAR0,
1101 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
1102 pcn_csr_write(sc, PCN_CSR_PAR1,
1103 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
1104 pcn_csr_write(sc, PCN_CSR_PAR2,
1105 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
1106
1107 /* Init circular RX list. */
1108 if (pcn_list_rx_init(sc) == ENOBUFS) {
1109 printf("pcn%d: initialization failed: no "
1110 "memory for rx buffers\n", sc->pcn_unit);
1111 pcn_stop(sc);
1112 PCN_UNLOCK(sc);
1113 return;
1114 }
1115
1116 /*
1117 * Init tx descriptors.
1118 */
1119 pcn_list_tx_init(sc);
1120
1121 /* Set up the mode register. */
1122 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
1123
1124 /* Set up RX filter. */
1125 pcn_setfilt(ifp);
1126
1127 /*
1128 * Load the multicast filter.
1129 */
1130 pcn_setmulti(sc);
1131
1132 /*
1133 * Load the addresses of the RX and TX lists.
1134 */
1135 pcn_csr_write(sc, PCN_CSR_RXADDR0,
1136 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
1137 pcn_csr_write(sc, PCN_CSR_RXADDR1,
1138 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
1139 pcn_csr_write(sc, PCN_CSR_TXADDR0,
1140 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
1141 pcn_csr_write(sc, PCN_CSR_TXADDR1,
1142 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
1143
1144 /* Set the RX and TX ring sizes. */
1145 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
1146 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
1147
1148 /* We're not using the initialization block. */
1149 pcn_csr_write(sc, PCN_CSR_IAB1, 0);
1150
1151 /* Enable fast suspend mode. */
1152 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1153
1154 /*
1155 * Enable burst read and write. Also set the no underflow
1156 * bit. This will avoid transmit underruns in certain
1157 * conditions while still providing decent performance.
1158 */
1159 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
1160 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
1161
1162 /* Enable graceful recovery from underflow. */
1163 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1164
1165 /* Enable auto-padding of short TX frames. */
1166 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1167
1168 /* Disable MII autoneg (we handle this ourselves). */
1169 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
1170
1171 if (sc->pcn_type == Am79C978)
1172 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
1173 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
1174
1175 /* Enable interrupts and start the controller running. */
1176 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
1177
1178 mii_mediachg(mii);
1179
1180 ifp->if_flags |= IFF_RUNNING;
1181 ifp->if_flags &= ~IFF_OACTIVE;
1182
1183 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz);
1184 PCN_UNLOCK(sc);
1185
1186 return;
1187 }
1188
1189 /*
1190 * Set media options.
1191 */
1192 static int
1193 pcn_ifmedia_upd(ifp)
1194 struct ifnet *ifp;
1195 {
1196 struct pcn_softc *sc;
1197 struct mii_data *mii;
1198
1199 sc = ifp->if_softc;
1200 mii = device_get_softc(sc->pcn_miibus);
1201
1202 sc->pcn_link = 0;
1203 if (mii->mii_instance) {
1204 struct mii_softc *miisc;
1205 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1206 mii_phy_reset(miisc);
1207 }
1208 mii_mediachg(mii);
1209
1210 return(0);
1211 }
1212
1213 /*
1214 * Report current media status.
1215 */
1216 static void
1217 pcn_ifmedia_sts(ifp, ifmr)
1218 struct ifnet *ifp;
1219 struct ifmediareq *ifmr;
1220 {
1221 struct pcn_softc *sc;
1222 struct mii_data *mii;
1223
1224 sc = ifp->if_softc;
1225
1226 mii = device_get_softc(sc->pcn_miibus);
1227 mii_pollstat(mii);
1228 ifmr->ifm_active = mii->mii_media_active;
1229 ifmr->ifm_status = mii->mii_media_status;
1230
1231 return;
1232 }
1233
1234 static int
1235 pcn_ioctl(ifp, command, data)
1236 struct ifnet *ifp;
1237 u_long command;
1238 caddr_t data;
1239 {
1240 struct pcn_softc *sc = ifp->if_softc;
1241 struct ifreq *ifr = (struct ifreq *) data;
1242 struct mii_data *mii = NULL;
1243 int error = 0;
1244
1245 PCN_LOCK(sc);
1246
1247 switch(command) {
1248 case SIOCSIFFLAGS:
1249 if (ifp->if_flags & IFF_UP) {
1250 if (ifp->if_flags & IFF_RUNNING &&
1251 ifp->if_flags & IFF_PROMISC &&
1252 !(sc->pcn_if_flags & IFF_PROMISC)) {
1253 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1254 PCN_EXTCTL1_SPND);
1255 pcn_setfilt(ifp);
1256 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1257 PCN_EXTCTL1_SPND);
1258 pcn_csr_write(sc, PCN_CSR_CSR,
1259 PCN_CSR_INTEN|PCN_CSR_START);
1260 } else if (ifp->if_flags & IFF_RUNNING &&
1261 !(ifp->if_flags & IFF_PROMISC) &&
1262 sc->pcn_if_flags & IFF_PROMISC) {
1263 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1264 PCN_EXTCTL1_SPND);
1265 pcn_setfilt(ifp);
1266 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1267 PCN_EXTCTL1_SPND);
1268 pcn_csr_write(sc, PCN_CSR_CSR,
1269 PCN_CSR_INTEN|PCN_CSR_START);
1270 } else if (!(ifp->if_flags & IFF_RUNNING))
1271 pcn_init(sc);
1272 } else {
1273 if (ifp->if_flags & IFF_RUNNING)
1274 pcn_stop(sc);
1275 }
1276 sc->pcn_if_flags = ifp->if_flags;
1277 error = 0;
1278 break;
1279 case SIOCADDMULTI:
1280 case SIOCDELMULTI:
1281 pcn_setmulti(sc);
1282 error = 0;
1283 break;
1284 case SIOCGIFMEDIA:
1285 case SIOCSIFMEDIA:
1286 mii = device_get_softc(sc->pcn_miibus);
1287 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1288 break;
1289 default:
1290 error = ether_ioctl(ifp, command, data);
1291 break;
1292 }
1293
1294 PCN_UNLOCK(sc);
1295
1296 return(error);
1297 }
1298
1299 static void
1300 pcn_watchdog(ifp)
1301 struct ifnet *ifp;
1302 {
1303 struct pcn_softc *sc;
1304
1305 sc = ifp->if_softc;
1306
1307 PCN_LOCK(sc);
1308
1309 ifp->if_oerrors++;
1310 printf("pcn%d: watchdog timeout\n", sc->pcn_unit);
1311
1312 pcn_stop(sc);
1313 pcn_reset(sc);
1314 pcn_init(sc);
1315
1316 if (ifp->if_snd.ifq_head != NULL)
1317 pcn_start(ifp);
1318
1319 PCN_UNLOCK(sc);
1320
1321 return;
1322 }
1323
1324 /*
1325 * Stop the adapter and free any mbufs allocated to the
1326 * RX and TX lists.
1327 */
1328 static void
1329 pcn_stop(sc)
1330 struct pcn_softc *sc;
1331 {
1332 register int i;
1333 struct ifnet *ifp;
1334
1335 ifp = &sc->arpcom.ac_if;
1336 PCN_LOCK(sc);
1337 ifp->if_timer = 0;
1338
1339 untimeout(pcn_tick, sc, sc->pcn_stat_ch);
1340
1341 /* Turn off interrupts */
1342 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
1343 /* Stop adapter */
1344 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
1345 sc->pcn_link = 0;
1346
1347 /*
1348 * Free data in the RX lists.
1349 */
1350 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
1351 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
1352 m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
1353 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
1354 }
1355 }
1356 bzero((char *)&sc->pcn_ldata->pcn_rx_list,
1357 sizeof(sc->pcn_ldata->pcn_rx_list));
1358
1359 /*
1360 * Free the TX list buffers.
1361 */
1362 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
1363 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
1364 m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
1365 sc->pcn_cdata.pcn_tx_chain[i] = NULL;
1366 }
1367 }
1368
1369 bzero((char *)&sc->pcn_ldata->pcn_tx_list,
1370 sizeof(sc->pcn_ldata->pcn_tx_list));
1371
1372 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1373 PCN_UNLOCK(sc);
1374
1375 return;
1376 }
1377
1378 /*
1379 * Stop all chip I/O so that the kernel's probe routines don't
1380 * get confused by errant DMAs when rebooting.
1381 */
1382 static void
1383 pcn_shutdown(dev)
1384 device_t dev;
1385 {
1386 struct pcn_softc *sc;
1387
1388 sc = device_get_softc(dev);
1389
1390 PCN_LOCK(sc);
1391 pcn_reset(sc);
1392 pcn_stop(sc);
1393 PCN_UNLOCK(sc);
1394
1395 return;
1396 }
Cache object: d34f343077819f214efa2806c9aeca22
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