FreeBSD/Linux Kernel Cross Reference
sys/pci/if_pcn.c
1 /*-
2 * Copyright (c) 2000 Berkeley Software Design, Inc.
3 * Copyright (c) 1997, 1998, 1999, 2000
4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: releng/6.0/sys/pci/if_pcn.c 151140 2005-10-09 04:11:20Z delphij $");
36
37 /*
38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available
39 * from http://www.amd.com.
40 *
41 * The AMD PCnet/PCI controllers are more advanced and functional
42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
43 * backwards compatibility with the LANCE and thus can be made
44 * to work with older LANCE drivers. This is in fact how the
45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble
46 * is that the PCnet/PCI devices offer several performance enhancements
47 * which can't be exploited in LANCE compatibility mode. Chief among
48 * these enhancements is the ability to perform PCI DMA operations
49 * using 32-bit addressing (which eliminates the need for ISA
50 * bounce-buffering), and special receive buffer alignment (which
51 * allows the receive handler to pass packets to the upper protocol
52 * layers without copying on both the x86 and alpha platforms).
53 */
54
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/sockio.h>
58 #include <sys/mbuf.h>
59 #include <sys/malloc.h>
60 #include <sys/kernel.h>
61 #include <sys/module.h>
62 #include <sys/socket.h>
63
64 #include <net/if.h>
65 #include <net/if_arp.h>
66 #include <net/ethernet.h>
67 #include <net/if_dl.h>
68 #include <net/if_media.h>
69 #include <net/if_types.h>
70
71 #include <net/bpf.h>
72
73 #include <vm/vm.h> /* for vtophys */
74 #include <vm/pmap.h> /* for vtophys */
75 #include <machine/bus.h>
76 #include <machine/resource.h>
77 #include <sys/bus.h>
78 #include <sys/rman.h>
79
80 #include <dev/mii/mii.h>
81 #include <dev/mii/miivar.h>
82
83 #include <dev/pci/pcireg.h>
84 #include <dev/pci/pcivar.h>
85
86 #define PCN_USEIOSPACE
87
88 #include <pci/if_pcnreg.h>
89
90 MODULE_DEPEND(pcn, pci, 1, 1, 1);
91 MODULE_DEPEND(pcn, ether, 1, 1, 1);
92 MODULE_DEPEND(pcn, miibus, 1, 1, 1);
93
94 /* "controller miibus0" required. See GENERIC if you get errors here. */
95 #include "miibus_if.h"
96
97 /*
98 * Various supported device vendors/types and their names.
99 */
100 static struct pcn_type pcn_devs[] = {
101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
103 { 0, 0, NULL }
104 };
105
106 static struct pcn_chipid {
107 u_int32_t id;
108 char * name;
109 } pcn_chipid[] = {
110 { Am79C960, "Am79C960" },
111 { Am79C961, "Am79C961" },
112 { Am79C961A, "Am79C961A" },
113 { Am79C965, "Am79C965" },
114 { Am79C970, "Am79C970" },
115 { Am79C970A, "Am79C970A" },
116 { Am79C971, "Am79C971" },
117 { Am79C972, "Am79C972" },
118 { Am79C973, "Am79C973" },
119 { Am79C978, "Am79C978" },
120 { Am79C975, "Am79C975" },
121 { Am79C976, "Am79C976" },
122 { 0, NULL },
123 };
124
125 static char * pcn_chipid_name(u_int32_t);
126 static u_int32_t pcn_chip_id(device_t);
127
128 static u_int32_t pcn_csr_read(struct pcn_softc *, int);
129 static u_int16_t pcn_csr_read16(struct pcn_softc *, int);
130 static u_int16_t pcn_bcr_read16(struct pcn_softc *, int);
131 static void pcn_csr_write(struct pcn_softc *, int, int);
132 static u_int32_t pcn_bcr_read(struct pcn_softc *, int);
133 static void pcn_bcr_write(struct pcn_softc *, int, int);
134
135 static int pcn_probe(device_t);
136 static int pcn_attach(device_t);
137 static int pcn_detach(device_t);
138
139 static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *);
140 static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *);
141 static void pcn_rxeof(struct pcn_softc *);
142 static void pcn_txeof(struct pcn_softc *);
143 static void pcn_intr(void *);
144 static void pcn_tick(void *);
145 static void pcn_start(struct ifnet *);
146 static void pcn_start_locked(struct ifnet *);
147 static int pcn_ioctl(struct ifnet *, u_long, caddr_t);
148 static void pcn_init(void *);
149 static void pcn_init_locked(struct pcn_softc *);
150 static void pcn_stop(struct pcn_softc *);
151 static void pcn_watchdog(struct ifnet *);
152 static void pcn_shutdown(device_t);
153 static int pcn_ifmedia_upd(struct ifnet *);
154 static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *);
155
156 static int pcn_miibus_readreg(device_t, int, int);
157 static int pcn_miibus_writereg(device_t, int, int, int);
158 static void pcn_miibus_statchg(device_t);
159
160 static void pcn_setfilt(struct ifnet *);
161 static void pcn_setmulti(struct pcn_softc *);
162 static void pcn_reset(struct pcn_softc *);
163 static int pcn_list_rx_init(struct pcn_softc *);
164 static int pcn_list_tx_init(struct pcn_softc *);
165
166 #ifdef PCN_USEIOSPACE
167 #define PCN_RES SYS_RES_IOPORT
168 #define PCN_RID PCN_PCI_LOIO
169 #else
170 #define PCN_RES SYS_RES_MEMORY
171 #define PCN_RID PCN_PCI_LOMEM
172 #endif
173
174 static device_method_t pcn_methods[] = {
175 /* Device interface */
176 DEVMETHOD(device_probe, pcn_probe),
177 DEVMETHOD(device_attach, pcn_attach),
178 DEVMETHOD(device_detach, pcn_detach),
179 DEVMETHOD(device_shutdown, pcn_shutdown),
180
181 /* bus interface */
182 DEVMETHOD(bus_print_child, bus_generic_print_child),
183 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
184
185 /* MII interface */
186 DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
187 DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
188 DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
189
190 { 0, 0 }
191 };
192
193 static driver_t pcn_driver = {
194 "pcn",
195 pcn_methods,
196 sizeof(struct pcn_softc)
197 };
198
199 static devclass_t pcn_devclass;
200
201 DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0);
202 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
203
204 #define PCN_CSR_SETBIT(sc, reg, x) \
205 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
206
207 #define PCN_CSR_CLRBIT(sc, reg, x) \
208 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
209
210 #define PCN_BCR_SETBIT(sc, reg, x) \
211 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
212
213 #define PCN_BCR_CLRBIT(sc, reg, x) \
214 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
215
216 static u_int32_t
217 pcn_csr_read(sc, reg)
218 struct pcn_softc *sc;
219 int reg;
220 {
221 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
222 return(CSR_READ_4(sc, PCN_IO32_RDP));
223 }
224
225 static u_int16_t
226 pcn_csr_read16(sc, reg)
227 struct pcn_softc *sc;
228 int reg;
229 {
230 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
231 return(CSR_READ_2(sc, PCN_IO16_RDP));
232 }
233
234 static void
235 pcn_csr_write(sc, reg, val)
236 struct pcn_softc *sc;
237 int reg;
238 int val;
239 {
240 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
241 CSR_WRITE_4(sc, PCN_IO32_RDP, val);
242 return;
243 }
244
245 static u_int32_t
246 pcn_bcr_read(sc, reg)
247 struct pcn_softc *sc;
248 int reg;
249 {
250 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
251 return(CSR_READ_4(sc, PCN_IO32_BDP));
252 }
253
254 static u_int16_t
255 pcn_bcr_read16(sc, reg)
256 struct pcn_softc *sc;
257 int reg;
258 {
259 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
260 return(CSR_READ_2(sc, PCN_IO16_BDP));
261 }
262
263 static void
264 pcn_bcr_write(sc, reg, val)
265 struct pcn_softc *sc;
266 int reg;
267 int val;
268 {
269 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
270 CSR_WRITE_4(sc, PCN_IO32_BDP, val);
271 return;
272 }
273
274 static int
275 pcn_miibus_readreg(dev, phy, reg)
276 device_t dev;
277 int phy, reg;
278 {
279 struct pcn_softc *sc;
280 int val;
281
282 sc = device_get_softc(dev);
283
284 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr)
285 return(0);
286
287 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
288 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
289 if (val == 0xFFFF)
290 return(0);
291
292 sc->pcn_phyaddr = phy;
293
294 return(val);
295 }
296
297 static int
298 pcn_miibus_writereg(dev, phy, reg, data)
299 device_t dev;
300 int phy, reg, data;
301 {
302 struct pcn_softc *sc;
303
304 sc = device_get_softc(dev);
305
306 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
307 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
308
309 return(0);
310 }
311
312 static void
313 pcn_miibus_statchg(dev)
314 device_t dev;
315 {
316 struct pcn_softc *sc;
317 struct mii_data *mii;
318
319 sc = device_get_softc(dev);
320 mii = device_get_softc(sc->pcn_miibus);
321
322 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
323 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
324 } else {
325 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
326 }
327
328 return;
329 }
330
331 static void
332 pcn_setmulti(sc)
333 struct pcn_softc *sc;
334 {
335 struct ifnet *ifp;
336 struct ifmultiaddr *ifma;
337 u_int32_t h, i;
338 u_int16_t hashes[4] = { 0, 0, 0, 0 };
339
340 ifp = sc->pcn_ifp;
341
342 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
343
344 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
345 for (i = 0; i < 4; i++)
346 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
347 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
348 return;
349 }
350
351 /* first, zot all the existing hash bits */
352 for (i = 0; i < 4; i++)
353 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
354
355 /* now program new ones */
356 IF_ADDR_LOCK(ifp);
357 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
358 if (ifma->ifma_addr->sa_family != AF_LINK)
359 continue;
360 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
361 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
362 hashes[h >> 4] |= 1 << (h & 0xF);
363 }
364 IF_ADDR_UNLOCK(ifp);
365
366 for (i = 0; i < 4; i++)
367 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
368
369 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
370
371 return;
372 }
373
374 static void
375 pcn_reset(sc)
376 struct pcn_softc *sc;
377 {
378 /*
379 * Issue a reset by reading from the RESET register.
380 * Note that we don't know if the chip is operating in
381 * 16-bit or 32-bit mode at this point, so we attempt
382 * to reset the chip both ways. If one fails, the other
383 * will succeed.
384 */
385 CSR_READ_2(sc, PCN_IO16_RESET);
386 CSR_READ_4(sc, PCN_IO32_RESET);
387
388 /* Wait a little while for the chip to get its brains in order. */
389 DELAY(1000);
390
391 /* Select 32-bit (DWIO) mode */
392 CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
393
394 /* Select software style 3. */
395 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
396
397 return;
398 }
399
400 static char *
401 pcn_chipid_name (u_int32_t id)
402 {
403 struct pcn_chipid *p = pcn_chipid;
404
405 while (p->name) {
406 if (id == p->id)
407 return (p->name);
408 p++;
409 }
410 return ("Unknown");
411 }
412
413 static u_int32_t
414 pcn_chip_id (device_t dev)
415 {
416 struct pcn_softc *sc;
417 u_int32_t chip_id;
418
419 sc = device_get_softc(dev);
420 /*
421 * Note: we can *NOT* put the chip into
422 * 32-bit mode yet. The lnc driver will only
423 * work in 16-bit mode, and once the chip
424 * goes into 32-bit mode, the only way to
425 * get it out again is with a hardware reset.
426 * So if pcn_probe() is called before the
427 * lnc driver's probe routine, the chip will
428 * be locked into 32-bit operation and the lnc
429 * driver will be unable to attach to it.
430 * Note II: if the chip happens to already
431 * be in 32-bit mode, we still need to check
432 * the chip ID, but first we have to detect
433 * 32-bit mode using only 16-bit operations.
434 * The safest way to do this is to read the
435 * PCI subsystem ID from BCR23/24 and compare
436 * that with the value read from PCI config
437 * space.
438 */
439 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
440 chip_id <<= 16;
441 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
442 /*
443 * Note III: the test for 0x10001000 is a hack to
444 * pacify VMware, who's pseudo-PCnet interface is
445 * broken. Reading the subsystem register from PCI
446 * config space yields 0x00000000 while reading the
447 * same value from I/O space yields 0x10001000. It's
448 * not supposed to be that way.
449 */
450 if (chip_id == pci_read_config(dev,
451 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
452 /* We're in 16-bit mode. */
453 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
454 chip_id <<= 16;
455 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
456 } else {
457 /* We're in 32-bit mode. */
458 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
459 chip_id <<= 16;
460 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
461 }
462
463 return (chip_id);
464 }
465
466 static struct pcn_type *
467 pcn_match (u_int16_t vid, u_int16_t did)
468 {
469 struct pcn_type *t;
470 t = pcn_devs;
471
472 while(t->pcn_name != NULL) {
473 if ((vid == t->pcn_vid) && (did == t->pcn_did))
474 return (t);
475 t++;
476 }
477 return (NULL);
478 }
479
480 /*
481 * Probe for an AMD chip. Check the PCI vendor and device
482 * IDs against our list and return a device name if we find a match.
483 */
484 static int
485 pcn_probe(dev)
486 device_t dev;
487 {
488 struct pcn_type *t;
489 struct pcn_softc *sc;
490 int rid;
491 u_int32_t chip_id;
492
493 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev));
494 if (t == NULL)
495 return (ENXIO);
496 sc = device_get_softc(dev);
497
498 /*
499 * Temporarily map the I/O space so we can read the chip ID register.
500 */
501 rid = PCN_RID;
502 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
503 if (sc->pcn_res == NULL) {
504 device_printf(dev, "couldn't map ports/memory\n");
505 return(ENXIO);
506 }
507 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
508 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
509
510 chip_id = pcn_chip_id(dev);
511
512 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
513
514 switch((chip_id >> 12) & PART_MASK) {
515 case Am79C971:
516 case Am79C972:
517 case Am79C973:
518 case Am79C975:
519 case Am79C976:
520 case Am79C978:
521 break;
522 default:
523 return(ENXIO);
524 }
525 device_set_desc(dev, t->pcn_name);
526 return(BUS_PROBE_DEFAULT);
527 }
528
529 /*
530 * Attach the interface. Allocate softc structures, do ifmedia
531 * setup and ethernet/BPF attach.
532 */
533 static int
534 pcn_attach(dev)
535 device_t dev;
536 {
537 u_int32_t eaddr[2];
538 struct pcn_softc *sc;
539 struct ifnet *ifp;
540 int unit, error = 0, rid;
541
542 sc = device_get_softc(dev);
543 unit = device_get_unit(dev);
544
545 /* Initialize our mutex. */
546 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
547 MTX_DEF);
548 /*
549 * Map control/status registers.
550 */
551 pci_enable_busmaster(dev);
552
553 /* Retrieve the chip ID */
554 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK;
555 device_printf(dev, "Chip ID %04x (%s)\n",
556 sc->pcn_type, pcn_chipid_name(sc->pcn_type));
557
558 rid = PCN_RID;
559 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
560
561 if (sc->pcn_res == NULL) {
562 printf("pcn%d: couldn't map ports/memory\n", unit);
563 error = ENXIO;
564 goto fail;
565 }
566
567 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
568 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
569
570 /* Allocate interrupt */
571 rid = 0;
572 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
573 RF_SHAREABLE | RF_ACTIVE);
574
575 if (sc->pcn_irq == NULL) {
576 printf("pcn%d: couldn't map interrupt\n", unit);
577 error = ENXIO;
578 goto fail;
579 }
580
581 /* Reset the adapter. */
582 pcn_reset(sc);
583
584 /*
585 * Get station address from the EEPROM.
586 */
587 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00);
588 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01);
589
590 sc->pcn_unit = unit;
591 callout_init_mtx(&sc->pcn_stat_callout, &sc->pcn_mtx, 0);
592
593 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
594 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
595
596 if (sc->pcn_ldata == NULL) {
597 printf("pcn%d: no memory for list buffers!\n", unit);
598 error = ENXIO;
599 goto fail;
600 }
601 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
602
603 ifp = sc->pcn_ifp = if_alloc(IFT_ETHER);
604 if (ifp == NULL) {
605 printf("pcn%d: can not if_alloc()\n", unit);
606 error = ENOSPC;
607 goto fail;
608 }
609 ifp->if_softc = sc;
610 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
611 ifp->if_mtu = ETHERMTU;
612 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
613 ifp->if_ioctl = pcn_ioctl;
614 ifp->if_start = pcn_start;
615 ifp->if_watchdog = pcn_watchdog;
616 ifp->if_init = pcn_init;
617 ifp->if_baudrate = 10000000;
618 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1;
619
620 /*
621 * Do MII setup.
622 */
623 if (mii_phy_probe(dev, &sc->pcn_miibus,
624 pcn_ifmedia_upd, pcn_ifmedia_sts)) {
625 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit);
626 error = ENXIO;
627 goto fail;
628 }
629
630 /*
631 * Call MI attach routine.
632 */
633 ether_ifattach(ifp, (u_int8_t *) eaddr);
634
635 /* Hook interrupt last to avoid having to lock softc */
636 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET | INTR_MPSAFE,
637 pcn_intr, sc, &sc->pcn_intrhand);
638
639 if (error) {
640 printf("pcn%d: couldn't set up irq\n", unit);
641 ether_ifdetach(ifp);
642 goto fail;
643 }
644
645 fail:
646 if (error)
647 pcn_detach(dev);
648
649 return(error);
650 }
651
652 /*
653 * Shutdown hardware and free up resources. This can be called any
654 * time after the mutex has been initialized. It is called in both
655 * the error case in attach and the normal detach case so it needs
656 * to be careful about only freeing resources that have actually been
657 * allocated.
658 */
659 static int
660 pcn_detach(dev)
661 device_t dev;
662 {
663 struct pcn_softc *sc;
664 struct ifnet *ifp;
665
666 sc = device_get_softc(dev);
667 ifp = sc->pcn_ifp;
668
669 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized"));
670
671 /* These should only be active if attach succeeded */
672 if (device_is_attached(dev)) {
673 PCN_LOCK(sc);
674 pcn_reset(sc);
675 pcn_stop(sc);
676 PCN_UNLOCK(sc);
677 callout_drain(&sc->pcn_stat_callout);
678 ether_ifdetach(ifp);
679 }
680 if (ifp)
681 if_free(ifp);
682 if (sc->pcn_miibus)
683 device_delete_child(dev, sc->pcn_miibus);
684 bus_generic_detach(dev);
685
686 if (sc->pcn_intrhand)
687 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
688 if (sc->pcn_irq)
689 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
690 if (sc->pcn_res)
691 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
692
693 if (sc->pcn_ldata) {
694 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
695 M_DEVBUF);
696 }
697
698 mtx_destroy(&sc->pcn_mtx);
699
700 return(0);
701 }
702
703 /*
704 * Initialize the transmit descriptors.
705 */
706 static int
707 pcn_list_tx_init(sc)
708 struct pcn_softc *sc;
709 {
710 struct pcn_list_data *ld;
711 struct pcn_ring_data *cd;
712 int i;
713
714 cd = &sc->pcn_cdata;
715 ld = sc->pcn_ldata;
716
717 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
718 cd->pcn_tx_chain[i] = NULL;
719 ld->pcn_tx_list[i].pcn_tbaddr = 0;
720 ld->pcn_tx_list[i].pcn_txctl = 0;
721 ld->pcn_tx_list[i].pcn_txstat = 0;
722 }
723
724 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
725
726 return(0);
727 }
728
729
730 /*
731 * Initialize the RX descriptors and allocate mbufs for them.
732 */
733 static int
734 pcn_list_rx_init(sc)
735 struct pcn_softc *sc;
736 {
737 struct pcn_ring_data *cd;
738 int i;
739
740 cd = &sc->pcn_cdata;
741
742 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
743 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
744 return(ENOBUFS);
745 }
746
747 cd->pcn_rx_prod = 0;
748
749 return(0);
750 }
751
752 /*
753 * Initialize an RX descriptor and attach an MBUF cluster.
754 */
755 static int
756 pcn_newbuf(sc, idx, m)
757 struct pcn_softc *sc;
758 int idx;
759 struct mbuf *m;
760 {
761 struct mbuf *m_new = NULL;
762 struct pcn_rx_desc *c;
763
764 c = &sc->pcn_ldata->pcn_rx_list[idx];
765
766 if (m == NULL) {
767 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
768 if (m_new == NULL)
769 return(ENOBUFS);
770
771 MCLGET(m_new, M_DONTWAIT);
772 if (!(m_new->m_flags & M_EXT)) {
773 m_freem(m_new);
774 return(ENOBUFS);
775 }
776 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
777 } else {
778 m_new = m;
779 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
780 m_new->m_data = m_new->m_ext.ext_buf;
781 }
782
783 m_adj(m_new, ETHER_ALIGN);
784
785 sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
786 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
787 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
788 c->pcn_bufsz |= PCN_RXLEN_MBO;
789 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
790
791 return(0);
792 }
793
794 /*
795 * A frame has been uploaded: pass the resulting mbuf chain up to
796 * the higher level protocols.
797 */
798 static void
799 pcn_rxeof(sc)
800 struct pcn_softc *sc;
801 {
802 struct mbuf *m;
803 struct ifnet *ifp;
804 struct pcn_rx_desc *cur_rx;
805 int i;
806
807 PCN_LOCK_ASSERT(sc);
808
809 ifp = sc->pcn_ifp;
810 i = sc->pcn_cdata.pcn_rx_prod;
811
812 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
813 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
814 m = sc->pcn_cdata.pcn_rx_chain[i];
815 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
816
817 /*
818 * If an error occurs, update stats, clear the
819 * status word and leave the mbuf cluster in place:
820 * it should simply get re-used next time this descriptor
821 * comes up in the ring.
822 */
823 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
824 ifp->if_ierrors++;
825 pcn_newbuf(sc, i, m);
826 PCN_INC(i, PCN_RX_LIST_CNT);
827 continue;
828 }
829
830 if (pcn_newbuf(sc, i, NULL)) {
831 /* Ran out of mbufs; recycle this one. */
832 pcn_newbuf(sc, i, m);
833 ifp->if_ierrors++;
834 PCN_INC(i, PCN_RX_LIST_CNT);
835 continue;
836 }
837
838 PCN_INC(i, PCN_RX_LIST_CNT);
839
840 /* No errors; receive the packet. */
841 ifp->if_ipackets++;
842 m->m_len = m->m_pkthdr.len =
843 cur_rx->pcn_rxlen - ETHER_CRC_LEN;
844 m->m_pkthdr.rcvif = ifp;
845
846 PCN_UNLOCK(sc);
847 (*ifp->if_input)(ifp, m);
848 PCN_LOCK(sc);
849 }
850
851 sc->pcn_cdata.pcn_rx_prod = i;
852
853 return;
854 }
855
856 /*
857 * A frame was downloaded to the chip. It's safe for us to clean up
858 * the list buffers.
859 */
860
861 static void
862 pcn_txeof(sc)
863 struct pcn_softc *sc;
864 {
865 struct pcn_tx_desc *cur_tx = NULL;
866 struct ifnet *ifp;
867 u_int32_t idx;
868
869 ifp = sc->pcn_ifp;
870
871 /*
872 * Go through our tx list and free mbufs for those
873 * frames that have been transmitted.
874 */
875 idx = sc->pcn_cdata.pcn_tx_cons;
876 while (idx != sc->pcn_cdata.pcn_tx_prod) {
877 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
878
879 if (!PCN_OWN_TXDESC(cur_tx))
880 break;
881
882 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
883 sc->pcn_cdata.pcn_tx_cnt--;
884 PCN_INC(idx, PCN_TX_LIST_CNT);
885 continue;
886 }
887
888 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
889 ifp->if_oerrors++;
890 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
891 ifp->if_collisions++;
892 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
893 ifp->if_collisions++;
894 }
895
896 ifp->if_collisions +=
897 cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
898
899 ifp->if_opackets++;
900 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
901 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
902 sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
903 }
904
905 sc->pcn_cdata.pcn_tx_cnt--;
906 PCN_INC(idx, PCN_TX_LIST_CNT);
907 }
908
909 if (idx != sc->pcn_cdata.pcn_tx_cons) {
910 /* Some buffers have been freed. */
911 sc->pcn_cdata.pcn_tx_cons = idx;
912 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
913 }
914 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
915
916 return;
917 }
918
919 static void
920 pcn_tick(xsc)
921 void *xsc;
922 {
923 struct pcn_softc *sc;
924 struct mii_data *mii;
925 struct ifnet *ifp;
926
927 sc = xsc;
928 ifp = sc->pcn_ifp;
929 PCN_LOCK_ASSERT(sc);
930
931 mii = device_get_softc(sc->pcn_miibus);
932 mii_tick(mii);
933
934 /* link just died */
935 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
936 sc->pcn_link = 0;
937
938 /* link just came up, restart */
939 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE &&
940 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
941 sc->pcn_link++;
942 if (ifp->if_snd.ifq_head != NULL)
943 pcn_start_locked(ifp);
944 }
945
946 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc);
947
948 return;
949 }
950
951 static void
952 pcn_intr(arg)
953 void *arg;
954 {
955 struct pcn_softc *sc;
956 struct ifnet *ifp;
957 u_int32_t status;
958
959 sc = arg;
960 ifp = sc->pcn_ifp;
961
962 PCN_LOCK(sc);
963
964 /* Suppress unwanted interrupts */
965 if (!(ifp->if_flags & IFF_UP)) {
966 pcn_stop(sc);
967 PCN_UNLOCK(sc);
968 return;
969 }
970
971 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
972
973 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
974 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
975
976 if (status & PCN_CSR_RINT)
977 pcn_rxeof(sc);
978
979 if (status & PCN_CSR_TINT)
980 pcn_txeof(sc);
981
982 if (status & PCN_CSR_ERR) {
983 pcn_init_locked(sc);
984 break;
985 }
986 }
987
988 if (ifp->if_snd.ifq_head != NULL)
989 pcn_start_locked(ifp);
990
991 PCN_UNLOCK(sc);
992 return;
993 }
994
995 /*
996 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
997 * pointers to the fragment pointers.
998 */
999 static int
1000 pcn_encap(sc, m_head, txidx)
1001 struct pcn_softc *sc;
1002 struct mbuf *m_head;
1003 u_int32_t *txidx;
1004 {
1005 struct pcn_tx_desc *f = NULL;
1006 struct mbuf *m;
1007 int frag, cur, cnt = 0;
1008
1009 /*
1010 * Start packing the mbufs in this chain into
1011 * the fragment pointers. Stop when we run out
1012 * of fragments or hit the end of the mbuf chain.
1013 */
1014 m = m_head;
1015 cur = frag = *txidx;
1016
1017 for (m = m_head; m != NULL; m = m->m_next) {
1018 if (m->m_len == 0)
1019 continue;
1020
1021 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
1022 return(ENOBUFS);
1023 f = &sc->pcn_ldata->pcn_tx_list[frag];
1024 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
1025 f->pcn_txctl |= PCN_TXCTL_MBO;
1026 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
1027 if (cnt == 0)
1028 f->pcn_txctl |= PCN_TXCTL_STP;
1029 else
1030 f->pcn_txctl |= PCN_TXCTL_OWN;
1031 cur = frag;
1032 PCN_INC(frag, PCN_TX_LIST_CNT);
1033 cnt++;
1034 }
1035
1036 if (m != NULL)
1037 return(ENOBUFS);
1038
1039 sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
1040 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
1041 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
1042 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
1043 sc->pcn_cdata.pcn_tx_cnt += cnt;
1044 *txidx = frag;
1045
1046 return(0);
1047 }
1048
1049 /*
1050 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1051 * to the mbuf data regions directly in the transmit lists. We also save a
1052 * copy of the pointers since the transmit list fragment pointers are
1053 * physical addresses.
1054 */
1055 static void
1056 pcn_start(ifp)
1057 struct ifnet *ifp;
1058 {
1059 struct pcn_softc *sc;
1060
1061 sc = ifp->if_softc;
1062 PCN_LOCK(sc);
1063 pcn_start_locked(ifp);
1064 PCN_UNLOCK(sc);
1065 }
1066
1067 static void
1068 pcn_start_locked(ifp)
1069 struct ifnet *ifp;
1070 {
1071 struct pcn_softc *sc;
1072 struct mbuf *m_head = NULL;
1073 u_int32_t idx;
1074
1075 sc = ifp->if_softc;
1076
1077 PCN_LOCK_ASSERT(sc);
1078
1079 if (!sc->pcn_link)
1080 return;
1081
1082 idx = sc->pcn_cdata.pcn_tx_prod;
1083
1084 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1085 return;
1086
1087 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
1088 IF_DEQUEUE(&ifp->if_snd, m_head);
1089 if (m_head == NULL)
1090 break;
1091
1092 if (pcn_encap(sc, m_head, &idx)) {
1093 IF_PREPEND(&ifp->if_snd, m_head);
1094 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1095 break;
1096 }
1097
1098 /*
1099 * If there's a BPF listener, bounce a copy of this frame
1100 * to him.
1101 */
1102 BPF_MTAP(ifp, m_head);
1103
1104 }
1105
1106 /* Transmit */
1107 sc->pcn_cdata.pcn_tx_prod = idx;
1108 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
1109
1110 /*
1111 * Set a timeout in case the chip goes out to lunch.
1112 */
1113 ifp->if_timer = 5;
1114
1115 return;
1116 }
1117
1118 static void
1119 pcn_setfilt(ifp)
1120 struct ifnet *ifp;
1121 {
1122 struct pcn_softc *sc;
1123
1124 sc = ifp->if_softc;
1125
1126 /* If we want promiscuous mode, set the allframes bit. */
1127 if (ifp->if_flags & IFF_PROMISC) {
1128 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1129 } else {
1130 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1131 }
1132
1133 /* Set the capture broadcast bit to capture broadcast frames. */
1134 if (ifp->if_flags & IFF_BROADCAST) {
1135 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1136 } else {
1137 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1138 }
1139
1140 return;
1141 }
1142
1143 static void
1144 pcn_init(xsc)
1145 void *xsc;
1146 {
1147 struct pcn_softc *sc = xsc;
1148
1149 PCN_LOCK(sc);
1150 pcn_init_locked(sc);
1151 PCN_UNLOCK(sc);
1152 }
1153
1154 static void
1155 pcn_init_locked(sc)
1156 struct pcn_softc *sc;
1157 {
1158 struct ifnet *ifp = sc->pcn_ifp;
1159 struct mii_data *mii = NULL;
1160
1161 PCN_LOCK_ASSERT(sc);
1162
1163 /*
1164 * Cancel pending I/O and free all RX/TX buffers.
1165 */
1166 pcn_stop(sc);
1167 pcn_reset(sc);
1168
1169 mii = device_get_softc(sc->pcn_miibus);
1170
1171 /* Set MAC address */
1172 pcn_csr_write(sc, PCN_CSR_PAR0,
1173 ((u_int16_t *)IFP2ENADDR(sc->pcn_ifp))[0]);
1174 pcn_csr_write(sc, PCN_CSR_PAR1,
1175 ((u_int16_t *)IFP2ENADDR(sc->pcn_ifp))[1]);
1176 pcn_csr_write(sc, PCN_CSR_PAR2,
1177 ((u_int16_t *)IFP2ENADDR(sc->pcn_ifp))[2]);
1178
1179 /* Init circular RX list. */
1180 if (pcn_list_rx_init(sc) == ENOBUFS) {
1181 printf("pcn%d: initialization failed: no "
1182 "memory for rx buffers\n", sc->pcn_unit);
1183 pcn_stop(sc);
1184 return;
1185 }
1186
1187 /*
1188 * Init tx descriptors.
1189 */
1190 pcn_list_tx_init(sc);
1191
1192 /* Set up the mode register. */
1193 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
1194
1195 /* Set up RX filter. */
1196 pcn_setfilt(ifp);
1197
1198 /*
1199 * Load the multicast filter.
1200 */
1201 pcn_setmulti(sc);
1202
1203 /*
1204 * Load the addresses of the RX and TX lists.
1205 */
1206 pcn_csr_write(sc, PCN_CSR_RXADDR0,
1207 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
1208 pcn_csr_write(sc, PCN_CSR_RXADDR1,
1209 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
1210 pcn_csr_write(sc, PCN_CSR_TXADDR0,
1211 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
1212 pcn_csr_write(sc, PCN_CSR_TXADDR1,
1213 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
1214
1215 /* Set the RX and TX ring sizes. */
1216 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
1217 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
1218
1219 /* We're not using the initialization block. */
1220 pcn_csr_write(sc, PCN_CSR_IAB1, 0);
1221
1222 /* Enable fast suspend mode. */
1223 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1224
1225 /*
1226 * Enable burst read and write. Also set the no underflow
1227 * bit. This will avoid transmit underruns in certain
1228 * conditions while still providing decent performance.
1229 */
1230 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
1231 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
1232
1233 /* Enable graceful recovery from underflow. */
1234 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1235
1236 /* Enable auto-padding of short TX frames. */
1237 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1238
1239 /* Disable MII autoneg (we handle this ourselves). */
1240 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
1241
1242 if (sc->pcn_type == Am79C978)
1243 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
1244 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
1245
1246 /* Enable interrupts and start the controller running. */
1247 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
1248
1249 mii_mediachg(mii);
1250
1251 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1252 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1253
1254 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc);
1255
1256 return;
1257 }
1258
1259 /*
1260 * Set media options.
1261 */
1262 static int
1263 pcn_ifmedia_upd(ifp)
1264 struct ifnet *ifp;
1265 {
1266 struct pcn_softc *sc;
1267 struct mii_data *mii;
1268
1269 sc = ifp->if_softc;
1270 mii = device_get_softc(sc->pcn_miibus);
1271
1272 PCN_LOCK(sc);
1273 sc->pcn_link = 0;
1274 if (mii->mii_instance) {
1275 struct mii_softc *miisc;
1276 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1277 mii_phy_reset(miisc);
1278 }
1279 mii_mediachg(mii);
1280 PCN_UNLOCK(sc);
1281
1282 return(0);
1283 }
1284
1285 /*
1286 * Report current media status.
1287 */
1288 static void
1289 pcn_ifmedia_sts(ifp, ifmr)
1290 struct ifnet *ifp;
1291 struct ifmediareq *ifmr;
1292 {
1293 struct pcn_softc *sc;
1294 struct mii_data *mii;
1295
1296 sc = ifp->if_softc;
1297
1298 mii = device_get_softc(sc->pcn_miibus);
1299 PCN_LOCK(sc);
1300 mii_pollstat(mii);
1301 ifmr->ifm_active = mii->mii_media_active;
1302 ifmr->ifm_status = mii->mii_media_status;
1303 PCN_UNLOCK(sc);
1304
1305 return;
1306 }
1307
1308 static int
1309 pcn_ioctl(ifp, command, data)
1310 struct ifnet *ifp;
1311 u_long command;
1312 caddr_t data;
1313 {
1314 struct pcn_softc *sc = ifp->if_softc;
1315 struct ifreq *ifr = (struct ifreq *) data;
1316 struct mii_data *mii = NULL;
1317 int error = 0;
1318
1319 switch(command) {
1320 case SIOCSIFFLAGS:
1321 PCN_LOCK(sc);
1322 if (ifp->if_flags & IFF_UP) {
1323 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1324 ifp->if_flags & IFF_PROMISC &&
1325 !(sc->pcn_if_flags & IFF_PROMISC)) {
1326 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1327 PCN_EXTCTL1_SPND);
1328 pcn_setfilt(ifp);
1329 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1330 PCN_EXTCTL1_SPND);
1331 pcn_csr_write(sc, PCN_CSR_CSR,
1332 PCN_CSR_INTEN|PCN_CSR_START);
1333 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1334 !(ifp->if_flags & IFF_PROMISC) &&
1335 sc->pcn_if_flags & IFF_PROMISC) {
1336 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1337 PCN_EXTCTL1_SPND);
1338 pcn_setfilt(ifp);
1339 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1340 PCN_EXTCTL1_SPND);
1341 pcn_csr_write(sc, PCN_CSR_CSR,
1342 PCN_CSR_INTEN|PCN_CSR_START);
1343 } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1344 pcn_init_locked(sc);
1345 } else {
1346 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1347 pcn_stop(sc);
1348 }
1349 sc->pcn_if_flags = ifp->if_flags;
1350 PCN_UNLOCK(sc);
1351 error = 0;
1352 break;
1353 case SIOCADDMULTI:
1354 case SIOCDELMULTI:
1355 PCN_LOCK(sc);
1356 pcn_setmulti(sc);
1357 PCN_UNLOCK(sc);
1358 error = 0;
1359 break;
1360 case SIOCGIFMEDIA:
1361 case SIOCSIFMEDIA:
1362 mii = device_get_softc(sc->pcn_miibus);
1363 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1364 break;
1365 default:
1366 error = ether_ioctl(ifp, command, data);
1367 break;
1368 }
1369
1370 return(error);
1371 }
1372
1373 static void
1374 pcn_watchdog(ifp)
1375 struct ifnet *ifp;
1376 {
1377 struct pcn_softc *sc;
1378
1379 sc = ifp->if_softc;
1380
1381 PCN_LOCK(sc);
1382
1383 ifp->if_oerrors++;
1384 printf("pcn%d: watchdog timeout\n", sc->pcn_unit);
1385
1386 pcn_stop(sc);
1387 pcn_reset(sc);
1388 pcn_init_locked(sc);
1389
1390 if (ifp->if_snd.ifq_head != NULL)
1391 pcn_start(ifp);
1392
1393 PCN_UNLOCK(sc);
1394
1395 return;
1396 }
1397
1398 /*
1399 * Stop the adapter and free any mbufs allocated to the
1400 * RX and TX lists.
1401 */
1402 static void
1403 pcn_stop(sc)
1404 struct pcn_softc *sc;
1405 {
1406 register int i;
1407 struct ifnet *ifp;
1408
1409 PCN_LOCK_ASSERT(sc);
1410 ifp = sc->pcn_ifp;
1411 ifp->if_timer = 0;
1412
1413 callout_stop(&sc->pcn_stat_callout);
1414
1415 /* Turn off interrupts */
1416 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
1417 /* Stop adapter */
1418 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
1419 sc->pcn_link = 0;
1420
1421 /*
1422 * Free data in the RX lists.
1423 */
1424 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
1425 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
1426 m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
1427 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
1428 }
1429 }
1430 bzero((char *)&sc->pcn_ldata->pcn_rx_list,
1431 sizeof(sc->pcn_ldata->pcn_rx_list));
1432
1433 /*
1434 * Free the TX list buffers.
1435 */
1436 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
1437 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
1438 m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
1439 sc->pcn_cdata.pcn_tx_chain[i] = NULL;
1440 }
1441 }
1442
1443 bzero((char *)&sc->pcn_ldata->pcn_tx_list,
1444 sizeof(sc->pcn_ldata->pcn_tx_list));
1445
1446 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1447
1448 return;
1449 }
1450
1451 /*
1452 * Stop all chip I/O so that the kernel's probe routines don't
1453 * get confused by errant DMAs when rebooting.
1454 */
1455 static void
1456 pcn_shutdown(dev)
1457 device_t dev;
1458 {
1459 struct pcn_softc *sc;
1460
1461 sc = device_get_softc(dev);
1462
1463 PCN_LOCK(sc);
1464 pcn_reset(sc);
1465 pcn_stop(sc);
1466 PCN_UNLOCK(sc);
1467
1468 return;
1469 }
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