FreeBSD/Linux Kernel Cross Reference
sys/pci/if_pcn.c
1 /*-
2 * Copyright (c) 2000 Berkeley Software Design, Inc.
3 * Copyright (c) 1997, 1998, 1999, 2000
4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: releng/6.2/sys/pci/if_pcn.c 156820 2006-03-17 21:30:57Z glebius $");
36
37 /*
38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available
39 * from http://www.amd.com.
40 *
41 * The AMD PCnet/PCI controllers are more advanced and functional
42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
43 * backwards compatibility with the LANCE and thus can be made
44 * to work with older LANCE drivers. This is in fact how the
45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble
46 * is that the PCnet/PCI devices offer several performance enhancements
47 * which can't be exploited in LANCE compatibility mode. Chief among
48 * these enhancements is the ability to perform PCI DMA operations
49 * using 32-bit addressing (which eliminates the need for ISA
50 * bounce-buffering), and special receive buffer alignment (which
51 * allows the receive handler to pass packets to the upper protocol
52 * layers without copying on both the x86 and alpha platforms).
53 */
54
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/sockio.h>
58 #include <sys/mbuf.h>
59 #include <sys/malloc.h>
60 #include <sys/kernel.h>
61 #include <sys/module.h>
62 #include <sys/socket.h>
63
64 #include <net/if.h>
65 #include <net/if_arp.h>
66 #include <net/ethernet.h>
67 #include <net/if_dl.h>
68 #include <net/if_media.h>
69 #include <net/if_types.h>
70
71 #include <net/bpf.h>
72
73 #include <vm/vm.h> /* for vtophys */
74 #include <vm/pmap.h> /* for vtophys */
75 #include <machine/bus.h>
76 #include <machine/resource.h>
77 #include <sys/bus.h>
78 #include <sys/rman.h>
79
80 #include <dev/mii/mii.h>
81 #include <dev/mii/miivar.h>
82
83 #include <dev/pci/pcireg.h>
84 #include <dev/pci/pcivar.h>
85
86 #define PCN_USEIOSPACE
87
88 #include <pci/if_pcnreg.h>
89
90 MODULE_DEPEND(pcn, pci, 1, 1, 1);
91 MODULE_DEPEND(pcn, ether, 1, 1, 1);
92 MODULE_DEPEND(pcn, miibus, 1, 1, 1);
93
94 /* "controller miibus0" required. See GENERIC if you get errors here. */
95 #include "miibus_if.h"
96
97 /*
98 * Various supported device vendors/types and their names.
99 */
100 static struct pcn_type pcn_devs[] = {
101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
103 { 0, 0, NULL }
104 };
105
106 static struct pcn_chipid {
107 u_int32_t id;
108 char * name;
109 } pcn_chipid[] = {
110 { Am79C960, "Am79C960" },
111 { Am79C961, "Am79C961" },
112 { Am79C961A, "Am79C961A" },
113 { Am79C965, "Am79C965" },
114 { Am79C970, "Am79C970" },
115 { Am79C970A, "Am79C970A" },
116 { Am79C971, "Am79C971" },
117 { Am79C972, "Am79C972" },
118 { Am79C973, "Am79C973" },
119 { Am79C978, "Am79C978" },
120 { Am79C975, "Am79C975" },
121 { Am79C976, "Am79C976" },
122 { 0, NULL },
123 };
124
125 static char * pcn_chipid_name(u_int32_t);
126 static u_int32_t pcn_chip_id(device_t);
127
128 static u_int32_t pcn_csr_read(struct pcn_softc *, int);
129 static u_int16_t pcn_csr_read16(struct pcn_softc *, int);
130 static u_int16_t pcn_bcr_read16(struct pcn_softc *, int);
131 static void pcn_csr_write(struct pcn_softc *, int, int);
132 static u_int32_t pcn_bcr_read(struct pcn_softc *, int);
133 static void pcn_bcr_write(struct pcn_softc *, int, int);
134
135 static int pcn_probe(device_t);
136 static int pcn_attach(device_t);
137 static int pcn_detach(device_t);
138
139 static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *);
140 static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *);
141 static void pcn_rxeof(struct pcn_softc *);
142 static void pcn_txeof(struct pcn_softc *);
143 static void pcn_intr(void *);
144 static void pcn_tick(void *);
145 static void pcn_start(struct ifnet *);
146 static void pcn_start_locked(struct ifnet *);
147 static int pcn_ioctl(struct ifnet *, u_long, caddr_t);
148 static void pcn_init(void *);
149 static void pcn_init_locked(struct pcn_softc *);
150 static void pcn_stop(struct pcn_softc *);
151 static void pcn_watchdog(struct ifnet *);
152 static void pcn_shutdown(device_t);
153 static int pcn_ifmedia_upd(struct ifnet *);
154 static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *);
155
156 static int pcn_miibus_readreg(device_t, int, int);
157 static int pcn_miibus_writereg(device_t, int, int, int);
158 static void pcn_miibus_statchg(device_t);
159
160 static void pcn_setfilt(struct ifnet *);
161 static void pcn_setmulti(struct pcn_softc *);
162 static void pcn_reset(struct pcn_softc *);
163 static int pcn_list_rx_init(struct pcn_softc *);
164 static int pcn_list_tx_init(struct pcn_softc *);
165
166 #ifdef PCN_USEIOSPACE
167 #define PCN_RES SYS_RES_IOPORT
168 #define PCN_RID PCN_PCI_LOIO
169 #else
170 #define PCN_RES SYS_RES_MEMORY
171 #define PCN_RID PCN_PCI_LOMEM
172 #endif
173
174 static device_method_t pcn_methods[] = {
175 /* Device interface */
176 DEVMETHOD(device_probe, pcn_probe),
177 DEVMETHOD(device_attach, pcn_attach),
178 DEVMETHOD(device_detach, pcn_detach),
179 DEVMETHOD(device_shutdown, pcn_shutdown),
180
181 /* bus interface */
182 DEVMETHOD(bus_print_child, bus_generic_print_child),
183 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
184
185 /* MII interface */
186 DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
187 DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
188 DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
189
190 { 0, 0 }
191 };
192
193 static driver_t pcn_driver = {
194 "pcn",
195 pcn_methods,
196 sizeof(struct pcn_softc)
197 };
198
199 static devclass_t pcn_devclass;
200
201 DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0);
202 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
203
204 #define PCN_CSR_SETBIT(sc, reg, x) \
205 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
206
207 #define PCN_CSR_CLRBIT(sc, reg, x) \
208 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
209
210 #define PCN_BCR_SETBIT(sc, reg, x) \
211 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
212
213 #define PCN_BCR_CLRBIT(sc, reg, x) \
214 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
215
216 static u_int32_t
217 pcn_csr_read(sc, reg)
218 struct pcn_softc *sc;
219 int reg;
220 {
221 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
222 return(CSR_READ_4(sc, PCN_IO32_RDP));
223 }
224
225 static u_int16_t
226 pcn_csr_read16(sc, reg)
227 struct pcn_softc *sc;
228 int reg;
229 {
230 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
231 return(CSR_READ_2(sc, PCN_IO16_RDP));
232 }
233
234 static void
235 pcn_csr_write(sc, reg, val)
236 struct pcn_softc *sc;
237 int reg;
238 int val;
239 {
240 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
241 CSR_WRITE_4(sc, PCN_IO32_RDP, val);
242 return;
243 }
244
245 static u_int32_t
246 pcn_bcr_read(sc, reg)
247 struct pcn_softc *sc;
248 int reg;
249 {
250 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
251 return(CSR_READ_4(sc, PCN_IO32_BDP));
252 }
253
254 static u_int16_t
255 pcn_bcr_read16(sc, reg)
256 struct pcn_softc *sc;
257 int reg;
258 {
259 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
260 return(CSR_READ_2(sc, PCN_IO16_BDP));
261 }
262
263 static void
264 pcn_bcr_write(sc, reg, val)
265 struct pcn_softc *sc;
266 int reg;
267 int val;
268 {
269 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
270 CSR_WRITE_4(sc, PCN_IO32_BDP, val);
271 return;
272 }
273
274 static int
275 pcn_miibus_readreg(dev, phy, reg)
276 device_t dev;
277 int phy, reg;
278 {
279 struct pcn_softc *sc;
280 int val;
281
282 sc = device_get_softc(dev);
283
284 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr)
285 return(0);
286
287 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
288 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
289 if (val == 0xFFFF)
290 return(0);
291
292 sc->pcn_phyaddr = phy;
293
294 return(val);
295 }
296
297 static int
298 pcn_miibus_writereg(dev, phy, reg, data)
299 device_t dev;
300 int phy, reg, data;
301 {
302 struct pcn_softc *sc;
303
304 sc = device_get_softc(dev);
305
306 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
307 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
308
309 return(0);
310 }
311
312 static void
313 pcn_miibus_statchg(dev)
314 device_t dev;
315 {
316 struct pcn_softc *sc;
317 struct mii_data *mii;
318
319 sc = device_get_softc(dev);
320 mii = device_get_softc(sc->pcn_miibus);
321
322 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
323 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
324 } else {
325 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
326 }
327
328 return;
329 }
330
331 static void
332 pcn_setmulti(sc)
333 struct pcn_softc *sc;
334 {
335 struct ifnet *ifp;
336 struct ifmultiaddr *ifma;
337 u_int32_t h, i;
338 u_int16_t hashes[4] = { 0, 0, 0, 0 };
339
340 ifp = sc->pcn_ifp;
341
342 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
343
344 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
345 for (i = 0; i < 4; i++)
346 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
347 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
348 return;
349 }
350
351 /* first, zot all the existing hash bits */
352 for (i = 0; i < 4; i++)
353 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
354
355 /* now program new ones */
356 IF_ADDR_LOCK(ifp);
357 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
358 if (ifma->ifma_addr->sa_family != AF_LINK)
359 continue;
360 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
361 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
362 hashes[h >> 4] |= 1 << (h & 0xF);
363 }
364 IF_ADDR_UNLOCK(ifp);
365
366 for (i = 0; i < 4; i++)
367 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
368
369 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
370
371 return;
372 }
373
374 static void
375 pcn_reset(sc)
376 struct pcn_softc *sc;
377 {
378 /*
379 * Issue a reset by reading from the RESET register.
380 * Note that we don't know if the chip is operating in
381 * 16-bit or 32-bit mode at this point, so we attempt
382 * to reset the chip both ways. If one fails, the other
383 * will succeed.
384 */
385 CSR_READ_2(sc, PCN_IO16_RESET);
386 CSR_READ_4(sc, PCN_IO32_RESET);
387
388 /* Wait a little while for the chip to get its brains in order. */
389 DELAY(1000);
390
391 /* Select 32-bit (DWIO) mode */
392 CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
393
394 /* Select software style 3. */
395 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
396
397 return;
398 }
399
400 static char *
401 pcn_chipid_name (u_int32_t id)
402 {
403 struct pcn_chipid *p = pcn_chipid;
404
405 while (p->name) {
406 if (id == p->id)
407 return (p->name);
408 p++;
409 }
410 return ("Unknown");
411 }
412
413 static u_int32_t
414 pcn_chip_id (device_t dev)
415 {
416 struct pcn_softc *sc;
417 u_int32_t chip_id;
418
419 sc = device_get_softc(dev);
420 /*
421 * Note: we can *NOT* put the chip into
422 * 32-bit mode yet. The lnc driver will only
423 * work in 16-bit mode, and once the chip
424 * goes into 32-bit mode, the only way to
425 * get it out again is with a hardware reset.
426 * So if pcn_probe() is called before the
427 * lnc driver's probe routine, the chip will
428 * be locked into 32-bit operation and the lnc
429 * driver will be unable to attach to it.
430 * Note II: if the chip happens to already
431 * be in 32-bit mode, we still need to check
432 * the chip ID, but first we have to detect
433 * 32-bit mode using only 16-bit operations.
434 * The safest way to do this is to read the
435 * PCI subsystem ID from BCR23/24 and compare
436 * that with the value read from PCI config
437 * space.
438 */
439 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
440 chip_id <<= 16;
441 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
442 /*
443 * Note III: the test for 0x10001000 is a hack to
444 * pacify VMware, who's pseudo-PCnet interface is
445 * broken. Reading the subsystem register from PCI
446 * config space yields 0x00000000 while reading the
447 * same value from I/O space yields 0x10001000. It's
448 * not supposed to be that way.
449 */
450 if (chip_id == pci_read_config(dev,
451 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
452 /* We're in 16-bit mode. */
453 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
454 chip_id <<= 16;
455 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
456 } else {
457 /* We're in 32-bit mode. */
458 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
459 chip_id <<= 16;
460 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
461 }
462
463 return (chip_id);
464 }
465
466 static struct pcn_type *
467 pcn_match (u_int16_t vid, u_int16_t did)
468 {
469 struct pcn_type *t;
470 t = pcn_devs;
471
472 while(t->pcn_name != NULL) {
473 if ((vid == t->pcn_vid) && (did == t->pcn_did))
474 return (t);
475 t++;
476 }
477 return (NULL);
478 }
479
480 /*
481 * Probe for an AMD chip. Check the PCI vendor and device
482 * IDs against our list and return a device name if we find a match.
483 */
484 static int
485 pcn_probe(dev)
486 device_t dev;
487 {
488 struct pcn_type *t;
489 struct pcn_softc *sc;
490 int rid;
491 u_int32_t chip_id;
492
493 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev));
494 if (t == NULL)
495 return (ENXIO);
496 sc = device_get_softc(dev);
497
498 /*
499 * Temporarily map the I/O space so we can read the chip ID register.
500 */
501 rid = PCN_RID;
502 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
503 if (sc->pcn_res == NULL) {
504 device_printf(dev, "couldn't map ports/memory\n");
505 return(ENXIO);
506 }
507 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
508 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
509
510 chip_id = pcn_chip_id(dev);
511
512 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
513
514 switch((chip_id >> 12) & PART_MASK) {
515 case Am79C971:
516 case Am79C972:
517 case Am79C973:
518 case Am79C975:
519 case Am79C976:
520 case Am79C978:
521 break;
522 default:
523 return(ENXIO);
524 }
525 device_set_desc(dev, t->pcn_name);
526 return(BUS_PROBE_DEFAULT);
527 }
528
529 /*
530 * Attach the interface. Allocate softc structures, do ifmedia
531 * setup and ethernet/BPF attach.
532 */
533 static int
534 pcn_attach(dev)
535 device_t dev;
536 {
537 u_int32_t eaddr[2];
538 struct pcn_softc *sc;
539 struct ifnet *ifp;
540 int unit, error = 0, rid;
541
542 sc = device_get_softc(dev);
543 unit = device_get_unit(dev);
544
545 /* Initialize our mutex. */
546 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
547 MTX_DEF);
548 /*
549 * Map control/status registers.
550 */
551 pci_enable_busmaster(dev);
552
553 /* Retrieve the chip ID */
554 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK;
555 device_printf(dev, "Chip ID %04x (%s)\n",
556 sc->pcn_type, pcn_chipid_name(sc->pcn_type));
557
558 rid = PCN_RID;
559 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
560
561 if (sc->pcn_res == NULL) {
562 printf("pcn%d: couldn't map ports/memory\n", unit);
563 error = ENXIO;
564 goto fail;
565 }
566
567 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
568 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
569
570 /* Allocate interrupt */
571 rid = 0;
572 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
573 RF_SHAREABLE | RF_ACTIVE);
574
575 if (sc->pcn_irq == NULL) {
576 printf("pcn%d: couldn't map interrupt\n", unit);
577 error = ENXIO;
578 goto fail;
579 }
580
581 /* Reset the adapter. */
582 pcn_reset(sc);
583
584 /*
585 * Get station address from the EEPROM.
586 */
587 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00);
588 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01);
589
590 sc->pcn_unit = unit;
591 callout_init_mtx(&sc->pcn_stat_callout, &sc->pcn_mtx, 0);
592
593 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
594 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
595
596 if (sc->pcn_ldata == NULL) {
597 printf("pcn%d: no memory for list buffers!\n", unit);
598 error = ENXIO;
599 goto fail;
600 }
601 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
602
603 ifp = sc->pcn_ifp = if_alloc(IFT_ETHER);
604 if (ifp == NULL) {
605 printf("pcn%d: can not if_alloc()\n", unit);
606 error = ENOSPC;
607 goto fail;
608 }
609 ifp->if_softc = sc;
610 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
611 ifp->if_mtu = ETHERMTU;
612 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
613 ifp->if_ioctl = pcn_ioctl;
614 ifp->if_start = pcn_start;
615 ifp->if_watchdog = pcn_watchdog;
616 ifp->if_init = pcn_init;
617 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1;
618
619 /*
620 * Do MII setup.
621 */
622 if (mii_phy_probe(dev, &sc->pcn_miibus,
623 pcn_ifmedia_upd, pcn_ifmedia_sts)) {
624 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit);
625 error = ENXIO;
626 goto fail;
627 }
628
629 /*
630 * Call MI attach routine.
631 */
632 ether_ifattach(ifp, (u_int8_t *) eaddr);
633
634 /* Hook interrupt last to avoid having to lock softc */
635 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET | INTR_MPSAFE,
636 pcn_intr, sc, &sc->pcn_intrhand);
637
638 if (error) {
639 printf("pcn%d: couldn't set up irq\n", unit);
640 ether_ifdetach(ifp);
641 goto fail;
642 }
643
644 fail:
645 if (error)
646 pcn_detach(dev);
647
648 return(error);
649 }
650
651 /*
652 * Shutdown hardware and free up resources. This can be called any
653 * time after the mutex has been initialized. It is called in both
654 * the error case in attach and the normal detach case so it needs
655 * to be careful about only freeing resources that have actually been
656 * allocated.
657 */
658 static int
659 pcn_detach(dev)
660 device_t dev;
661 {
662 struct pcn_softc *sc;
663 struct ifnet *ifp;
664
665 sc = device_get_softc(dev);
666 ifp = sc->pcn_ifp;
667
668 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized"));
669
670 /* These should only be active if attach succeeded */
671 if (device_is_attached(dev)) {
672 PCN_LOCK(sc);
673 pcn_reset(sc);
674 pcn_stop(sc);
675 PCN_UNLOCK(sc);
676 callout_drain(&sc->pcn_stat_callout);
677 ether_ifdetach(ifp);
678 }
679 if (ifp)
680 if_free(ifp);
681 if (sc->pcn_miibus)
682 device_delete_child(dev, sc->pcn_miibus);
683 bus_generic_detach(dev);
684
685 if (sc->pcn_intrhand)
686 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
687 if (sc->pcn_irq)
688 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
689 if (sc->pcn_res)
690 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
691
692 if (sc->pcn_ldata) {
693 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
694 M_DEVBUF);
695 }
696
697 mtx_destroy(&sc->pcn_mtx);
698
699 return(0);
700 }
701
702 /*
703 * Initialize the transmit descriptors.
704 */
705 static int
706 pcn_list_tx_init(sc)
707 struct pcn_softc *sc;
708 {
709 struct pcn_list_data *ld;
710 struct pcn_ring_data *cd;
711 int i;
712
713 cd = &sc->pcn_cdata;
714 ld = sc->pcn_ldata;
715
716 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
717 cd->pcn_tx_chain[i] = NULL;
718 ld->pcn_tx_list[i].pcn_tbaddr = 0;
719 ld->pcn_tx_list[i].pcn_txctl = 0;
720 ld->pcn_tx_list[i].pcn_txstat = 0;
721 }
722
723 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
724
725 return(0);
726 }
727
728
729 /*
730 * Initialize the RX descriptors and allocate mbufs for them.
731 */
732 static int
733 pcn_list_rx_init(sc)
734 struct pcn_softc *sc;
735 {
736 struct pcn_ring_data *cd;
737 int i;
738
739 cd = &sc->pcn_cdata;
740
741 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
742 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
743 return(ENOBUFS);
744 }
745
746 cd->pcn_rx_prod = 0;
747
748 return(0);
749 }
750
751 /*
752 * Initialize an RX descriptor and attach an MBUF cluster.
753 */
754 static int
755 pcn_newbuf(sc, idx, m)
756 struct pcn_softc *sc;
757 int idx;
758 struct mbuf *m;
759 {
760 struct mbuf *m_new = NULL;
761 struct pcn_rx_desc *c;
762
763 c = &sc->pcn_ldata->pcn_rx_list[idx];
764
765 if (m == NULL) {
766 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
767 if (m_new == NULL)
768 return(ENOBUFS);
769
770 MCLGET(m_new, M_DONTWAIT);
771 if (!(m_new->m_flags & M_EXT)) {
772 m_freem(m_new);
773 return(ENOBUFS);
774 }
775 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
776 } else {
777 m_new = m;
778 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
779 m_new->m_data = m_new->m_ext.ext_buf;
780 }
781
782 m_adj(m_new, ETHER_ALIGN);
783
784 sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
785 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
786 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
787 c->pcn_bufsz |= PCN_RXLEN_MBO;
788 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
789
790 return(0);
791 }
792
793 /*
794 * A frame has been uploaded: pass the resulting mbuf chain up to
795 * the higher level protocols.
796 */
797 static void
798 pcn_rxeof(sc)
799 struct pcn_softc *sc;
800 {
801 struct mbuf *m;
802 struct ifnet *ifp;
803 struct pcn_rx_desc *cur_rx;
804 int i;
805
806 PCN_LOCK_ASSERT(sc);
807
808 ifp = sc->pcn_ifp;
809 i = sc->pcn_cdata.pcn_rx_prod;
810
811 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
812 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
813 m = sc->pcn_cdata.pcn_rx_chain[i];
814 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
815
816 /*
817 * If an error occurs, update stats, clear the
818 * status word and leave the mbuf cluster in place:
819 * it should simply get re-used next time this descriptor
820 * comes up in the ring.
821 */
822 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
823 ifp->if_ierrors++;
824 pcn_newbuf(sc, i, m);
825 PCN_INC(i, PCN_RX_LIST_CNT);
826 continue;
827 }
828
829 if (pcn_newbuf(sc, i, NULL)) {
830 /* Ran out of mbufs; recycle this one. */
831 pcn_newbuf(sc, i, m);
832 ifp->if_ierrors++;
833 PCN_INC(i, PCN_RX_LIST_CNT);
834 continue;
835 }
836
837 PCN_INC(i, PCN_RX_LIST_CNT);
838
839 /* No errors; receive the packet. */
840 ifp->if_ipackets++;
841 m->m_len = m->m_pkthdr.len =
842 cur_rx->pcn_rxlen - ETHER_CRC_LEN;
843 m->m_pkthdr.rcvif = ifp;
844
845 PCN_UNLOCK(sc);
846 (*ifp->if_input)(ifp, m);
847 PCN_LOCK(sc);
848 }
849
850 sc->pcn_cdata.pcn_rx_prod = i;
851
852 return;
853 }
854
855 /*
856 * A frame was downloaded to the chip. It's safe for us to clean up
857 * the list buffers.
858 */
859
860 static void
861 pcn_txeof(sc)
862 struct pcn_softc *sc;
863 {
864 struct pcn_tx_desc *cur_tx = NULL;
865 struct ifnet *ifp;
866 u_int32_t idx;
867
868 ifp = sc->pcn_ifp;
869
870 /*
871 * Go through our tx list and free mbufs for those
872 * frames that have been transmitted.
873 */
874 idx = sc->pcn_cdata.pcn_tx_cons;
875 while (idx != sc->pcn_cdata.pcn_tx_prod) {
876 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
877
878 if (!PCN_OWN_TXDESC(cur_tx))
879 break;
880
881 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
882 sc->pcn_cdata.pcn_tx_cnt--;
883 PCN_INC(idx, PCN_TX_LIST_CNT);
884 continue;
885 }
886
887 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
888 ifp->if_oerrors++;
889 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
890 ifp->if_collisions++;
891 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
892 ifp->if_collisions++;
893 }
894
895 ifp->if_collisions +=
896 cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
897
898 ifp->if_opackets++;
899 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
900 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
901 sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
902 }
903
904 sc->pcn_cdata.pcn_tx_cnt--;
905 PCN_INC(idx, PCN_TX_LIST_CNT);
906 }
907
908 if (idx != sc->pcn_cdata.pcn_tx_cons) {
909 /* Some buffers have been freed. */
910 sc->pcn_cdata.pcn_tx_cons = idx;
911 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
912 }
913 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
914
915 return;
916 }
917
918 static void
919 pcn_tick(xsc)
920 void *xsc;
921 {
922 struct pcn_softc *sc;
923 struct mii_data *mii;
924 struct ifnet *ifp;
925
926 sc = xsc;
927 ifp = sc->pcn_ifp;
928 PCN_LOCK_ASSERT(sc);
929
930 mii = device_get_softc(sc->pcn_miibus);
931 mii_tick(mii);
932
933 /* link just died */
934 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
935 sc->pcn_link = 0;
936
937 /* link just came up, restart */
938 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE &&
939 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
940 sc->pcn_link++;
941 if (ifp->if_snd.ifq_head != NULL)
942 pcn_start_locked(ifp);
943 }
944
945 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc);
946
947 return;
948 }
949
950 static void
951 pcn_intr(arg)
952 void *arg;
953 {
954 struct pcn_softc *sc;
955 struct ifnet *ifp;
956 u_int32_t status;
957
958 sc = arg;
959 ifp = sc->pcn_ifp;
960
961 PCN_LOCK(sc);
962
963 /* Suppress unwanted interrupts */
964 if (!(ifp->if_flags & IFF_UP)) {
965 pcn_stop(sc);
966 PCN_UNLOCK(sc);
967 return;
968 }
969
970 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
971
972 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
973 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
974
975 if (status & PCN_CSR_RINT)
976 pcn_rxeof(sc);
977
978 if (status & PCN_CSR_TINT)
979 pcn_txeof(sc);
980
981 if (status & PCN_CSR_ERR) {
982 pcn_init_locked(sc);
983 break;
984 }
985 }
986
987 if (ifp->if_snd.ifq_head != NULL)
988 pcn_start_locked(ifp);
989
990 PCN_UNLOCK(sc);
991 return;
992 }
993
994 /*
995 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
996 * pointers to the fragment pointers.
997 */
998 static int
999 pcn_encap(sc, m_head, txidx)
1000 struct pcn_softc *sc;
1001 struct mbuf *m_head;
1002 u_int32_t *txidx;
1003 {
1004 struct pcn_tx_desc *f = NULL;
1005 struct mbuf *m;
1006 int frag, cur, cnt = 0;
1007
1008 /*
1009 * Start packing the mbufs in this chain into
1010 * the fragment pointers. Stop when we run out
1011 * of fragments or hit the end of the mbuf chain.
1012 */
1013 m = m_head;
1014 cur = frag = *txidx;
1015
1016 for (m = m_head; m != NULL; m = m->m_next) {
1017 if (m->m_len == 0)
1018 continue;
1019
1020 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
1021 return(ENOBUFS);
1022 f = &sc->pcn_ldata->pcn_tx_list[frag];
1023 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
1024 f->pcn_txctl |= PCN_TXCTL_MBO;
1025 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
1026 if (cnt == 0)
1027 f->pcn_txctl |= PCN_TXCTL_STP;
1028 else
1029 f->pcn_txctl |= PCN_TXCTL_OWN;
1030 cur = frag;
1031 PCN_INC(frag, PCN_TX_LIST_CNT);
1032 cnt++;
1033 }
1034
1035 if (m != NULL)
1036 return(ENOBUFS);
1037
1038 sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
1039 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
1040 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
1041 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
1042 sc->pcn_cdata.pcn_tx_cnt += cnt;
1043 *txidx = frag;
1044
1045 return(0);
1046 }
1047
1048 /*
1049 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1050 * to the mbuf data regions directly in the transmit lists. We also save a
1051 * copy of the pointers since the transmit list fragment pointers are
1052 * physical addresses.
1053 */
1054 static void
1055 pcn_start(ifp)
1056 struct ifnet *ifp;
1057 {
1058 struct pcn_softc *sc;
1059
1060 sc = ifp->if_softc;
1061 PCN_LOCK(sc);
1062 pcn_start_locked(ifp);
1063 PCN_UNLOCK(sc);
1064 }
1065
1066 static void
1067 pcn_start_locked(ifp)
1068 struct ifnet *ifp;
1069 {
1070 struct pcn_softc *sc;
1071 struct mbuf *m_head = NULL;
1072 u_int32_t idx;
1073
1074 sc = ifp->if_softc;
1075
1076 PCN_LOCK_ASSERT(sc);
1077
1078 if (!sc->pcn_link)
1079 return;
1080
1081 idx = sc->pcn_cdata.pcn_tx_prod;
1082
1083 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1084 return;
1085
1086 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
1087 IF_DEQUEUE(&ifp->if_snd, m_head);
1088 if (m_head == NULL)
1089 break;
1090
1091 if (pcn_encap(sc, m_head, &idx)) {
1092 IF_PREPEND(&ifp->if_snd, m_head);
1093 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1094 break;
1095 }
1096
1097 /*
1098 * If there's a BPF listener, bounce a copy of this frame
1099 * to him.
1100 */
1101 BPF_MTAP(ifp, m_head);
1102
1103 }
1104
1105 /* Transmit */
1106 sc->pcn_cdata.pcn_tx_prod = idx;
1107 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
1108
1109 /*
1110 * Set a timeout in case the chip goes out to lunch.
1111 */
1112 ifp->if_timer = 5;
1113
1114 return;
1115 }
1116
1117 static void
1118 pcn_setfilt(ifp)
1119 struct ifnet *ifp;
1120 {
1121 struct pcn_softc *sc;
1122
1123 sc = ifp->if_softc;
1124
1125 /* If we want promiscuous mode, set the allframes bit. */
1126 if (ifp->if_flags & IFF_PROMISC) {
1127 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1128 } else {
1129 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1130 }
1131
1132 /* Set the capture broadcast bit to capture broadcast frames. */
1133 if (ifp->if_flags & IFF_BROADCAST) {
1134 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1135 } else {
1136 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1137 }
1138
1139 return;
1140 }
1141
1142 static void
1143 pcn_init(xsc)
1144 void *xsc;
1145 {
1146 struct pcn_softc *sc = xsc;
1147
1148 PCN_LOCK(sc);
1149 pcn_init_locked(sc);
1150 PCN_UNLOCK(sc);
1151 }
1152
1153 static void
1154 pcn_init_locked(sc)
1155 struct pcn_softc *sc;
1156 {
1157 struct ifnet *ifp = sc->pcn_ifp;
1158 struct mii_data *mii = NULL;
1159
1160 PCN_LOCK_ASSERT(sc);
1161
1162 /*
1163 * Cancel pending I/O and free all RX/TX buffers.
1164 */
1165 pcn_stop(sc);
1166 pcn_reset(sc);
1167
1168 mii = device_get_softc(sc->pcn_miibus);
1169
1170 /* Set MAC address */
1171 pcn_csr_write(sc, PCN_CSR_PAR0,
1172 ((u_int16_t *)IFP2ENADDR(sc->pcn_ifp))[0]);
1173 pcn_csr_write(sc, PCN_CSR_PAR1,
1174 ((u_int16_t *)IFP2ENADDR(sc->pcn_ifp))[1]);
1175 pcn_csr_write(sc, PCN_CSR_PAR2,
1176 ((u_int16_t *)IFP2ENADDR(sc->pcn_ifp))[2]);
1177
1178 /* Init circular RX list. */
1179 if (pcn_list_rx_init(sc) == ENOBUFS) {
1180 printf("pcn%d: initialization failed: no "
1181 "memory for rx buffers\n", sc->pcn_unit);
1182 pcn_stop(sc);
1183 return;
1184 }
1185
1186 /*
1187 * Init tx descriptors.
1188 */
1189 pcn_list_tx_init(sc);
1190
1191 /* Set up the mode register. */
1192 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
1193
1194 /* Set up RX filter. */
1195 pcn_setfilt(ifp);
1196
1197 /*
1198 * Load the multicast filter.
1199 */
1200 pcn_setmulti(sc);
1201
1202 /*
1203 * Load the addresses of the RX and TX lists.
1204 */
1205 pcn_csr_write(sc, PCN_CSR_RXADDR0,
1206 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
1207 pcn_csr_write(sc, PCN_CSR_RXADDR1,
1208 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
1209 pcn_csr_write(sc, PCN_CSR_TXADDR0,
1210 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
1211 pcn_csr_write(sc, PCN_CSR_TXADDR1,
1212 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
1213
1214 /* Set the RX and TX ring sizes. */
1215 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
1216 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
1217
1218 /* We're not using the initialization block. */
1219 pcn_csr_write(sc, PCN_CSR_IAB1, 0);
1220
1221 /* Enable fast suspend mode. */
1222 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1223
1224 /*
1225 * Enable burst read and write. Also set the no underflow
1226 * bit. This will avoid transmit underruns in certain
1227 * conditions while still providing decent performance.
1228 */
1229 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
1230 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
1231
1232 /* Enable graceful recovery from underflow. */
1233 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1234
1235 /* Enable auto-padding of short TX frames. */
1236 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1237
1238 /* Disable MII autoneg (we handle this ourselves). */
1239 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
1240
1241 if (sc->pcn_type == Am79C978)
1242 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
1243 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
1244
1245 /* Enable interrupts and start the controller running. */
1246 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
1247
1248 mii_mediachg(mii);
1249
1250 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1251 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1252
1253 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc);
1254
1255 return;
1256 }
1257
1258 /*
1259 * Set media options.
1260 */
1261 static int
1262 pcn_ifmedia_upd(ifp)
1263 struct ifnet *ifp;
1264 {
1265 struct pcn_softc *sc;
1266 struct mii_data *mii;
1267
1268 sc = ifp->if_softc;
1269 mii = device_get_softc(sc->pcn_miibus);
1270
1271 PCN_LOCK(sc);
1272 sc->pcn_link = 0;
1273 if (mii->mii_instance) {
1274 struct mii_softc *miisc;
1275 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1276 mii_phy_reset(miisc);
1277 }
1278 mii_mediachg(mii);
1279 PCN_UNLOCK(sc);
1280
1281 return(0);
1282 }
1283
1284 /*
1285 * Report current media status.
1286 */
1287 static void
1288 pcn_ifmedia_sts(ifp, ifmr)
1289 struct ifnet *ifp;
1290 struct ifmediareq *ifmr;
1291 {
1292 struct pcn_softc *sc;
1293 struct mii_data *mii;
1294
1295 sc = ifp->if_softc;
1296
1297 mii = device_get_softc(sc->pcn_miibus);
1298 PCN_LOCK(sc);
1299 mii_pollstat(mii);
1300 ifmr->ifm_active = mii->mii_media_active;
1301 ifmr->ifm_status = mii->mii_media_status;
1302 PCN_UNLOCK(sc);
1303
1304 return;
1305 }
1306
1307 static int
1308 pcn_ioctl(ifp, command, data)
1309 struct ifnet *ifp;
1310 u_long command;
1311 caddr_t data;
1312 {
1313 struct pcn_softc *sc = ifp->if_softc;
1314 struct ifreq *ifr = (struct ifreq *) data;
1315 struct mii_data *mii = NULL;
1316 int error = 0;
1317
1318 switch(command) {
1319 case SIOCSIFFLAGS:
1320 PCN_LOCK(sc);
1321 if (ifp->if_flags & IFF_UP) {
1322 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1323 ifp->if_flags & IFF_PROMISC &&
1324 !(sc->pcn_if_flags & IFF_PROMISC)) {
1325 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1326 PCN_EXTCTL1_SPND);
1327 pcn_setfilt(ifp);
1328 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1329 PCN_EXTCTL1_SPND);
1330 pcn_csr_write(sc, PCN_CSR_CSR,
1331 PCN_CSR_INTEN|PCN_CSR_START);
1332 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1333 !(ifp->if_flags & IFF_PROMISC) &&
1334 sc->pcn_if_flags & IFF_PROMISC) {
1335 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1336 PCN_EXTCTL1_SPND);
1337 pcn_setfilt(ifp);
1338 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1339 PCN_EXTCTL1_SPND);
1340 pcn_csr_write(sc, PCN_CSR_CSR,
1341 PCN_CSR_INTEN|PCN_CSR_START);
1342 } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1343 pcn_init_locked(sc);
1344 } else {
1345 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1346 pcn_stop(sc);
1347 }
1348 sc->pcn_if_flags = ifp->if_flags;
1349 PCN_UNLOCK(sc);
1350 error = 0;
1351 break;
1352 case SIOCADDMULTI:
1353 case SIOCDELMULTI:
1354 PCN_LOCK(sc);
1355 pcn_setmulti(sc);
1356 PCN_UNLOCK(sc);
1357 error = 0;
1358 break;
1359 case SIOCGIFMEDIA:
1360 case SIOCSIFMEDIA:
1361 mii = device_get_softc(sc->pcn_miibus);
1362 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1363 break;
1364 default:
1365 error = ether_ioctl(ifp, command, data);
1366 break;
1367 }
1368
1369 return(error);
1370 }
1371
1372 static void
1373 pcn_watchdog(ifp)
1374 struct ifnet *ifp;
1375 {
1376 struct pcn_softc *sc;
1377
1378 sc = ifp->if_softc;
1379
1380 PCN_LOCK(sc);
1381
1382 ifp->if_oerrors++;
1383 printf("pcn%d: watchdog timeout\n", sc->pcn_unit);
1384
1385 pcn_stop(sc);
1386 pcn_reset(sc);
1387 pcn_init_locked(sc);
1388
1389 if (ifp->if_snd.ifq_head != NULL)
1390 pcn_start(ifp);
1391
1392 PCN_UNLOCK(sc);
1393
1394 return;
1395 }
1396
1397 /*
1398 * Stop the adapter and free any mbufs allocated to the
1399 * RX and TX lists.
1400 */
1401 static void
1402 pcn_stop(sc)
1403 struct pcn_softc *sc;
1404 {
1405 register int i;
1406 struct ifnet *ifp;
1407
1408 PCN_LOCK_ASSERT(sc);
1409 ifp = sc->pcn_ifp;
1410 ifp->if_timer = 0;
1411
1412 callout_stop(&sc->pcn_stat_callout);
1413
1414 /* Turn off interrupts */
1415 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
1416 /* Stop adapter */
1417 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
1418 sc->pcn_link = 0;
1419
1420 /*
1421 * Free data in the RX lists.
1422 */
1423 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
1424 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
1425 m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
1426 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
1427 }
1428 }
1429 bzero((char *)&sc->pcn_ldata->pcn_rx_list,
1430 sizeof(sc->pcn_ldata->pcn_rx_list));
1431
1432 /*
1433 * Free the TX list buffers.
1434 */
1435 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
1436 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
1437 m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
1438 sc->pcn_cdata.pcn_tx_chain[i] = NULL;
1439 }
1440 }
1441
1442 bzero((char *)&sc->pcn_ldata->pcn_tx_list,
1443 sizeof(sc->pcn_ldata->pcn_tx_list));
1444
1445 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1446
1447 return;
1448 }
1449
1450 /*
1451 * Stop all chip I/O so that the kernel's probe routines don't
1452 * get confused by errant DMAs when rebooting.
1453 */
1454 static void
1455 pcn_shutdown(dev)
1456 device_t dev;
1457 {
1458 struct pcn_softc *sc;
1459
1460 sc = device_get_softc(dev);
1461
1462 PCN_LOCK(sc);
1463 pcn_reset(sc);
1464 pcn_stop(sc);
1465 PCN_UNLOCK(sc);
1466
1467 return;
1468 }
Cache object: 7595a6b49b1bed657561bcc0946e6263
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