FreeBSD/Linux Kernel Cross Reference
sys/pci/if_pcn.c
1 /*-
2 * Copyright (c) 2000 Berkeley Software Design, Inc.
3 * Copyright (c) 1997, 1998, 1999, 2000
4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36
37 /*
38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available
39 * from http://www.amd.com.
40 *
41 * The AMD PCnet/PCI controllers are more advanced and functional
42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
43 * backwards compatibility with the LANCE and thus can be made
44 * to work with older LANCE drivers. This is in fact how the
45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble
46 * is that the PCnet/PCI devices offer several performance enhancements
47 * which can't be exploited in LANCE compatibility mode. Chief among
48 * these enhancements is the ability to perform PCI DMA operations
49 * using 32-bit addressing (which eliminates the need for ISA
50 * bounce-buffering), and special receive buffer alignment (which
51 * allows the receive handler to pass packets to the upper protocol
52 * layers without copying on both the x86 and alpha platforms).
53 */
54
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/sockio.h>
58 #include <sys/mbuf.h>
59 #include <sys/malloc.h>
60 #include <sys/kernel.h>
61 #include <sys/module.h>
62 #include <sys/socket.h>
63
64 #include <net/if.h>
65 #include <net/if_arp.h>
66 #include <net/ethernet.h>
67 #include <net/if_dl.h>
68 #include <net/if_media.h>
69 #include <net/if_types.h>
70
71 #include <net/bpf.h>
72
73 #include <vm/vm.h> /* for vtophys */
74 #include <vm/pmap.h> /* for vtophys */
75 #include <machine/bus.h>
76 #include <machine/resource.h>
77 #include <sys/bus.h>
78 #include <sys/rman.h>
79
80 #include <dev/mii/mii.h>
81 #include <dev/mii/miivar.h>
82
83 #include <dev/pci/pcireg.h>
84 #include <dev/pci/pcivar.h>
85
86 #define PCN_USEIOSPACE
87
88 #include <pci/if_pcnreg.h>
89
90 MODULE_DEPEND(pcn, pci, 1, 1, 1);
91 MODULE_DEPEND(pcn, ether, 1, 1, 1);
92 MODULE_DEPEND(pcn, miibus, 1, 1, 1);
93
94 /* "device miibus" required. See GENERIC if you get errors here. */
95 #include "miibus_if.h"
96
97 /*
98 * Various supported device vendors/types and their names.
99 */
100 static const struct pcn_type pcn_devs[] = {
101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
103 { 0, 0, NULL }
104 };
105
106 static const struct pcn_chipid {
107 u_int32_t id;
108 const char *name;
109 } pcn_chipid[] = {
110 { Am79C971, "Am79C971" },
111 { Am79C972, "Am79C972" },
112 { Am79C973, "Am79C973" },
113 { Am79C978, "Am79C978" },
114 { Am79C975, "Am79C975" },
115 { Am79C976, "Am79C976" },
116 { 0, NULL },
117 };
118
119 static const char *pcn_chipid_name(u_int32_t);
120 static u_int32_t pcn_chip_id(device_t);
121 static const struct pcn_type *pcn_match(u_int16_t, u_int16_t);
122
123 static u_int32_t pcn_csr_read(struct pcn_softc *, int);
124 static u_int16_t pcn_csr_read16(struct pcn_softc *, int);
125 static u_int16_t pcn_bcr_read16(struct pcn_softc *, int);
126 static void pcn_csr_write(struct pcn_softc *, int, int);
127 static u_int32_t pcn_bcr_read(struct pcn_softc *, int);
128 static void pcn_bcr_write(struct pcn_softc *, int, int);
129
130 static int pcn_probe(device_t);
131 static int pcn_attach(device_t);
132 static int pcn_detach(device_t);
133
134 static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *);
135 static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *);
136 static void pcn_rxeof(struct pcn_softc *);
137 static void pcn_txeof(struct pcn_softc *);
138 static void pcn_intr(void *);
139 static void pcn_tick(void *);
140 static void pcn_start(struct ifnet *);
141 static void pcn_start_locked(struct ifnet *);
142 static int pcn_ioctl(struct ifnet *, u_long, caddr_t);
143 static void pcn_init(void *);
144 static void pcn_init_locked(struct pcn_softc *);
145 static void pcn_stop(struct pcn_softc *);
146 static void pcn_watchdog(struct ifnet *);
147 static void pcn_shutdown(device_t);
148 static int pcn_ifmedia_upd(struct ifnet *);
149 static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *);
150
151 static int pcn_miibus_readreg(device_t, int, int);
152 static int pcn_miibus_writereg(device_t, int, int, int);
153 static void pcn_miibus_statchg(device_t);
154
155 static void pcn_setfilt(struct ifnet *);
156 static void pcn_setmulti(struct pcn_softc *);
157 static void pcn_reset(struct pcn_softc *);
158 static int pcn_list_rx_init(struct pcn_softc *);
159 static int pcn_list_tx_init(struct pcn_softc *);
160
161 #ifdef PCN_USEIOSPACE
162 #define PCN_RES SYS_RES_IOPORT
163 #define PCN_RID PCN_PCI_LOIO
164 #else
165 #define PCN_RES SYS_RES_MEMORY
166 #define PCN_RID PCN_PCI_LOMEM
167 #endif
168
169 static device_method_t pcn_methods[] = {
170 /* Device interface */
171 DEVMETHOD(device_probe, pcn_probe),
172 DEVMETHOD(device_attach, pcn_attach),
173 DEVMETHOD(device_detach, pcn_detach),
174 DEVMETHOD(device_shutdown, pcn_shutdown),
175
176 /* bus interface */
177 DEVMETHOD(bus_print_child, bus_generic_print_child),
178 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
179
180 /* MII interface */
181 DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
182 DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
183 DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
184
185 { 0, 0 }
186 };
187
188 static driver_t pcn_driver = {
189 "pcn",
190 pcn_methods,
191 sizeof(struct pcn_softc)
192 };
193
194 static devclass_t pcn_devclass;
195
196 DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0);
197 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
198
199 #define PCN_CSR_SETBIT(sc, reg, x) \
200 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
201
202 #define PCN_CSR_CLRBIT(sc, reg, x) \
203 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
204
205 #define PCN_BCR_SETBIT(sc, reg, x) \
206 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
207
208 #define PCN_BCR_CLRBIT(sc, reg, x) \
209 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
210
211 static u_int32_t
212 pcn_csr_read(sc, reg)
213 struct pcn_softc *sc;
214 int reg;
215 {
216 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
217 return(CSR_READ_4(sc, PCN_IO32_RDP));
218 }
219
220 static u_int16_t
221 pcn_csr_read16(sc, reg)
222 struct pcn_softc *sc;
223 int reg;
224 {
225 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
226 return(CSR_READ_2(sc, PCN_IO16_RDP));
227 }
228
229 static void
230 pcn_csr_write(sc, reg, val)
231 struct pcn_softc *sc;
232 int reg;
233 int val;
234 {
235 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
236 CSR_WRITE_4(sc, PCN_IO32_RDP, val);
237 return;
238 }
239
240 static u_int32_t
241 pcn_bcr_read(sc, reg)
242 struct pcn_softc *sc;
243 int reg;
244 {
245 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
246 return(CSR_READ_4(sc, PCN_IO32_BDP));
247 }
248
249 static u_int16_t
250 pcn_bcr_read16(sc, reg)
251 struct pcn_softc *sc;
252 int reg;
253 {
254 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
255 return(CSR_READ_2(sc, PCN_IO16_BDP));
256 }
257
258 static void
259 pcn_bcr_write(sc, reg, val)
260 struct pcn_softc *sc;
261 int reg;
262 int val;
263 {
264 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
265 CSR_WRITE_4(sc, PCN_IO32_BDP, val);
266 return;
267 }
268
269 static int
270 pcn_miibus_readreg(dev, phy, reg)
271 device_t dev;
272 int phy, reg;
273 {
274 struct pcn_softc *sc;
275 int val;
276
277 sc = device_get_softc(dev);
278
279 /*
280 * At least Am79C971 with DP83840A wedge when isolating the
281 * external PHY so we can't allow multiple external PHYs.
282 * There are cards that use Am79C971 with both the internal
283 * and an external PHY though.
284 * For internal PHYs it doesn't really matter whether we can
285 * isolate the remaining internal and the external ones in
286 * the PHY drivers as the internal PHYs have to be enabled
287 * individually in PCN_BCR_PHYSEL, PCN_CSR_MODE, etc.
288 * With Am79C97{3,5,8} we don't support switching beetween
289 * the internal and external PHYs, yet, so we can't allow
290 * multiple PHYs with these either.
291 * Am79C97{2,6} actually only support external PHYs (not
292 * connectable internal ones respond at the usual addresses,
293 * which don't hurt if we let them show up on the bus) and
294 * isolating them works.
295 */
296 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) ||
297 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 ||
298 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr != -1 &&
299 phy != sc->pcn_extphyaddr)
300 return(0);
301
302 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
303 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
304 if (val == 0xFFFF)
305 return(0);
306
307 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) ||
308 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 ||
309 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr == -1)
310 sc->pcn_extphyaddr = phy;
311
312 return(val);
313 }
314
315 static int
316 pcn_miibus_writereg(dev, phy, reg, data)
317 device_t dev;
318 int phy, reg, data;
319 {
320 struct pcn_softc *sc;
321
322 sc = device_get_softc(dev);
323
324 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
325 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
326
327 return(0);
328 }
329
330 static void
331 pcn_miibus_statchg(dev)
332 device_t dev;
333 {
334 struct pcn_softc *sc;
335 struct mii_data *mii;
336
337 sc = device_get_softc(dev);
338 mii = device_get_softc(sc->pcn_miibus);
339
340 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
341 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
342 } else {
343 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
344 }
345
346 return;
347 }
348
349 static void
350 pcn_setmulti(sc)
351 struct pcn_softc *sc;
352 {
353 struct ifnet *ifp;
354 struct ifmultiaddr *ifma;
355 u_int32_t h, i;
356 u_int16_t hashes[4] = { 0, 0, 0, 0 };
357
358 ifp = sc->pcn_ifp;
359
360 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
361
362 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
363 for (i = 0; i < 4; i++)
364 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
365 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
366 return;
367 }
368
369 /* first, zot all the existing hash bits */
370 for (i = 0; i < 4; i++)
371 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
372
373 /* now program new ones */
374 IF_ADDR_LOCK(ifp);
375 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
376 if (ifma->ifma_addr->sa_family != AF_LINK)
377 continue;
378 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
379 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
380 hashes[h >> 4] |= 1 << (h & 0xF);
381 }
382 IF_ADDR_UNLOCK(ifp);
383
384 for (i = 0; i < 4; i++)
385 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
386
387 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
388
389 return;
390 }
391
392 static void
393 pcn_reset(sc)
394 struct pcn_softc *sc;
395 {
396 /*
397 * Issue a reset by reading from the RESET register.
398 * Note that we don't know if the chip is operating in
399 * 16-bit or 32-bit mode at this point, so we attempt
400 * to reset the chip both ways. If one fails, the other
401 * will succeed.
402 */
403 CSR_READ_2(sc, PCN_IO16_RESET);
404 CSR_READ_4(sc, PCN_IO32_RESET);
405
406 /* Wait a little while for the chip to get its brains in order. */
407 DELAY(1000);
408
409 /* Select 32-bit (DWIO) mode */
410 CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
411
412 /* Select software style 3. */
413 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
414
415 return;
416 }
417
418 static const char *
419 pcn_chipid_name(u_int32_t id)
420 {
421 const struct pcn_chipid *p;
422
423 p = pcn_chipid;
424 while (p->name) {
425 if (id == p->id)
426 return (p->name);
427 p++;
428 }
429 return ("Unknown");
430 }
431
432 static u_int32_t
433 pcn_chip_id(device_t dev)
434 {
435 struct pcn_softc *sc;
436 u_int32_t chip_id;
437
438 sc = device_get_softc(dev);
439 /*
440 * Note: we can *NOT* put the chip into
441 * 32-bit mode yet. The le(4) driver will only
442 * work in 16-bit mode, and once the chip
443 * goes into 32-bit mode, the only way to
444 * get it out again is with a hardware reset.
445 * So if pcn_probe() is called before the
446 * le(4) driver's probe routine, the chip will
447 * be locked into 32-bit operation and the
448 * le(4) driver will be unable to attach to it.
449 * Note II: if the chip happens to already
450 * be in 32-bit mode, we still need to check
451 * the chip ID, but first we have to detect
452 * 32-bit mode using only 16-bit operations.
453 * The safest way to do this is to read the
454 * PCI subsystem ID from BCR23/24 and compare
455 * that with the value read from PCI config
456 * space.
457 */
458 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
459 chip_id <<= 16;
460 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
461 /*
462 * Note III: the test for 0x10001000 is a hack to
463 * pacify VMware, who's pseudo-PCnet interface is
464 * broken. Reading the subsystem register from PCI
465 * config space yields 0x00000000 while reading the
466 * same value from I/O space yields 0x10001000. It's
467 * not supposed to be that way.
468 */
469 if (chip_id == pci_read_config(dev,
470 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
471 /* We're in 16-bit mode. */
472 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
473 chip_id <<= 16;
474 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
475 } else {
476 /* We're in 32-bit mode. */
477 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
478 chip_id <<= 16;
479 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
480 }
481
482 return (chip_id);
483 }
484
485 static const struct pcn_type *
486 pcn_match(u_int16_t vid, u_int16_t did)
487 {
488 const struct pcn_type *t;
489
490 t = pcn_devs;
491 while (t->pcn_name != NULL) {
492 if ((vid == t->pcn_vid) && (did == t->pcn_did))
493 return (t);
494 t++;
495 }
496 return (NULL);
497 }
498
499 /*
500 * Probe for an AMD chip. Check the PCI vendor and device
501 * IDs against our list and return a device name if we find a match.
502 */
503 static int
504 pcn_probe(dev)
505 device_t dev;
506 {
507 const struct pcn_type *t;
508 struct pcn_softc *sc;
509 int rid;
510 u_int32_t chip_id;
511
512 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev));
513 if (t == NULL)
514 return (ENXIO);
515 sc = device_get_softc(dev);
516
517 /*
518 * Temporarily map the I/O space so we can read the chip ID register.
519 */
520 rid = PCN_RID;
521 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
522 if (sc->pcn_res == NULL) {
523 device_printf(dev, "couldn't map ports/memory\n");
524 return(ENXIO);
525 }
526 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
527 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
528
529 chip_id = pcn_chip_id(dev);
530
531 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
532
533 switch((chip_id >> 12) & PART_MASK) {
534 case Am79C971:
535 case Am79C972:
536 case Am79C973:
537 case Am79C975:
538 case Am79C976:
539 case Am79C978:
540 break;
541 default:
542 return(ENXIO);
543 }
544 device_set_desc(dev, t->pcn_name);
545 return(BUS_PROBE_DEFAULT);
546 }
547
548 /*
549 * Attach the interface. Allocate softc structures, do ifmedia
550 * setup and ethernet/BPF attach.
551 */
552 static int
553 pcn_attach(dev)
554 device_t dev;
555 {
556 u_int32_t eaddr[2];
557 struct pcn_softc *sc;
558 struct mii_data *mii;
559 struct mii_softc *miisc;
560 struct ifnet *ifp;
561 int error = 0, rid;
562
563 sc = device_get_softc(dev);
564
565 /* Initialize our mutex. */
566 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
567 MTX_DEF);
568 /*
569 * Map control/status registers.
570 */
571 pci_enable_busmaster(dev);
572
573 /* Retrieve the chip ID */
574 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK;
575 device_printf(dev, "Chip ID %04x (%s)\n",
576 sc->pcn_type, pcn_chipid_name(sc->pcn_type));
577
578 rid = PCN_RID;
579 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
580
581 if (sc->pcn_res == NULL) {
582 device_printf(dev, "couldn't map ports/memory\n");
583 error = ENXIO;
584 goto fail;
585 }
586
587 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
588 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
589
590 /* Allocate interrupt */
591 rid = 0;
592 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
593 RF_SHAREABLE | RF_ACTIVE);
594
595 if (sc->pcn_irq == NULL) {
596 device_printf(dev, "couldn't map interrupt\n");
597 error = ENXIO;
598 goto fail;
599 }
600
601 /* Reset the adapter. */
602 pcn_reset(sc);
603
604 /*
605 * Get station address from the EEPROM.
606 */
607 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00);
608 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01);
609
610 callout_init_mtx(&sc->pcn_stat_callout, &sc->pcn_mtx, 0);
611
612 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
613 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
614
615 if (sc->pcn_ldata == NULL) {
616 device_printf(dev, "no memory for list buffers!\n");
617 error = ENXIO;
618 goto fail;
619 }
620 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
621
622 ifp = sc->pcn_ifp = if_alloc(IFT_ETHER);
623 if (ifp == NULL) {
624 device_printf(dev, "can not if_alloc()\n");
625 error = ENOSPC;
626 goto fail;
627 }
628 ifp->if_softc = sc;
629 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
630 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
631 ifp->if_ioctl = pcn_ioctl;
632 ifp->if_start = pcn_start;
633 ifp->if_watchdog = pcn_watchdog;
634 ifp->if_init = pcn_init;
635 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1;
636
637 /*
638 * Do MII setup.
639 */
640 sc->pcn_extphyaddr = -1;
641 if (mii_phy_probe(dev, &sc->pcn_miibus,
642 pcn_ifmedia_upd, pcn_ifmedia_sts)) {
643 device_printf(dev, "MII without any PHY!\n");
644 error = ENXIO;
645 goto fail;
646 }
647 /*
648 * Record the media instances of internal PHYs, which map the
649 * built-in interfaces to the MII, so we can set the active
650 * PHY/port based on the currently selected media.
651 */
652 sc->pcn_inst_10bt = -1;
653 mii = device_get_softc(sc->pcn_miibus);
654 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
655 switch (miisc->mii_phy) {
656 case PCN_PHYAD_10BT:
657 sc->pcn_inst_10bt = miisc->mii_inst;
658 break;
659 /*
660 * XXX deal with the Am79C97{3,5} internal 100baseT
661 * and the Am79C978 internal HomePNA PHYs.
662 */
663 }
664 }
665
666 /*
667 * Call MI attach routine.
668 */
669 ether_ifattach(ifp, (u_int8_t *) eaddr);
670
671 /* Hook interrupt last to avoid having to lock softc */
672 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET | INTR_MPSAFE,
673 NULL, pcn_intr, sc, &sc->pcn_intrhand);
674
675 if (error) {
676 device_printf(dev, "couldn't set up irq\n");
677 ether_ifdetach(ifp);
678 goto fail;
679 }
680
681 fail:
682 if (error)
683 pcn_detach(dev);
684
685 return(error);
686 }
687
688 /*
689 * Shutdown hardware and free up resources. This can be called any
690 * time after the mutex has been initialized. It is called in both
691 * the error case in attach and the normal detach case so it needs
692 * to be careful about only freeing resources that have actually been
693 * allocated.
694 */
695 static int
696 pcn_detach(dev)
697 device_t dev;
698 {
699 struct pcn_softc *sc;
700 struct ifnet *ifp;
701
702 sc = device_get_softc(dev);
703 ifp = sc->pcn_ifp;
704
705 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized"));
706
707 /* These should only be active if attach succeeded */
708 if (device_is_attached(dev)) {
709 PCN_LOCK(sc);
710 pcn_reset(sc);
711 pcn_stop(sc);
712 PCN_UNLOCK(sc);
713 callout_drain(&sc->pcn_stat_callout);
714 ether_ifdetach(ifp);
715 }
716 if (sc->pcn_miibus)
717 device_delete_child(dev, sc->pcn_miibus);
718 bus_generic_detach(dev);
719
720 if (sc->pcn_intrhand)
721 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
722 if (sc->pcn_irq)
723 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
724 if (sc->pcn_res)
725 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
726
727 if (ifp)
728 if_free(ifp);
729
730 if (sc->pcn_ldata) {
731 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
732 M_DEVBUF);
733 }
734
735 mtx_destroy(&sc->pcn_mtx);
736
737 return(0);
738 }
739
740 /*
741 * Initialize the transmit descriptors.
742 */
743 static int
744 pcn_list_tx_init(sc)
745 struct pcn_softc *sc;
746 {
747 struct pcn_list_data *ld;
748 struct pcn_ring_data *cd;
749 int i;
750
751 cd = &sc->pcn_cdata;
752 ld = sc->pcn_ldata;
753
754 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
755 cd->pcn_tx_chain[i] = NULL;
756 ld->pcn_tx_list[i].pcn_tbaddr = 0;
757 ld->pcn_tx_list[i].pcn_txctl = 0;
758 ld->pcn_tx_list[i].pcn_txstat = 0;
759 }
760
761 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
762
763 return(0);
764 }
765
766
767 /*
768 * Initialize the RX descriptors and allocate mbufs for them.
769 */
770 static int
771 pcn_list_rx_init(sc)
772 struct pcn_softc *sc;
773 {
774 struct pcn_ring_data *cd;
775 int i;
776
777 cd = &sc->pcn_cdata;
778
779 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
780 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
781 return(ENOBUFS);
782 }
783
784 cd->pcn_rx_prod = 0;
785
786 return(0);
787 }
788
789 /*
790 * Initialize an RX descriptor and attach an MBUF cluster.
791 */
792 static int
793 pcn_newbuf(sc, idx, m)
794 struct pcn_softc *sc;
795 int idx;
796 struct mbuf *m;
797 {
798 struct mbuf *m_new = NULL;
799 struct pcn_rx_desc *c;
800
801 c = &sc->pcn_ldata->pcn_rx_list[idx];
802
803 if (m == NULL) {
804 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
805 if (m_new == NULL)
806 return(ENOBUFS);
807
808 MCLGET(m_new, M_DONTWAIT);
809 if (!(m_new->m_flags & M_EXT)) {
810 m_freem(m_new);
811 return(ENOBUFS);
812 }
813 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
814 } else {
815 m_new = m;
816 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
817 m_new->m_data = m_new->m_ext.ext_buf;
818 }
819
820 m_adj(m_new, ETHER_ALIGN);
821
822 sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
823 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
824 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
825 c->pcn_bufsz |= PCN_RXLEN_MBO;
826 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
827
828 return(0);
829 }
830
831 /*
832 * A frame has been uploaded: pass the resulting mbuf chain up to
833 * the higher level protocols.
834 */
835 static void
836 pcn_rxeof(sc)
837 struct pcn_softc *sc;
838 {
839 struct mbuf *m;
840 struct ifnet *ifp;
841 struct pcn_rx_desc *cur_rx;
842 int i;
843
844 PCN_LOCK_ASSERT(sc);
845
846 ifp = sc->pcn_ifp;
847 i = sc->pcn_cdata.pcn_rx_prod;
848
849 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
850 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
851 m = sc->pcn_cdata.pcn_rx_chain[i];
852 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
853
854 /*
855 * If an error occurs, update stats, clear the
856 * status word and leave the mbuf cluster in place:
857 * it should simply get re-used next time this descriptor
858 * comes up in the ring.
859 */
860 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
861 ifp->if_ierrors++;
862 pcn_newbuf(sc, i, m);
863 PCN_INC(i, PCN_RX_LIST_CNT);
864 continue;
865 }
866
867 if (pcn_newbuf(sc, i, NULL)) {
868 /* Ran out of mbufs; recycle this one. */
869 pcn_newbuf(sc, i, m);
870 ifp->if_ierrors++;
871 PCN_INC(i, PCN_RX_LIST_CNT);
872 continue;
873 }
874
875 PCN_INC(i, PCN_RX_LIST_CNT);
876
877 /* No errors; receive the packet. */
878 ifp->if_ipackets++;
879 m->m_len = m->m_pkthdr.len =
880 cur_rx->pcn_rxlen - ETHER_CRC_LEN;
881 m->m_pkthdr.rcvif = ifp;
882
883 PCN_UNLOCK(sc);
884 (*ifp->if_input)(ifp, m);
885 PCN_LOCK(sc);
886 }
887
888 sc->pcn_cdata.pcn_rx_prod = i;
889
890 return;
891 }
892
893 /*
894 * A frame was downloaded to the chip. It's safe for us to clean up
895 * the list buffers.
896 */
897
898 static void
899 pcn_txeof(sc)
900 struct pcn_softc *sc;
901 {
902 struct pcn_tx_desc *cur_tx = NULL;
903 struct ifnet *ifp;
904 u_int32_t idx;
905
906 ifp = sc->pcn_ifp;
907
908 /*
909 * Go through our tx list and free mbufs for those
910 * frames that have been transmitted.
911 */
912 idx = sc->pcn_cdata.pcn_tx_cons;
913 while (idx != sc->pcn_cdata.pcn_tx_prod) {
914 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
915
916 if (!PCN_OWN_TXDESC(cur_tx))
917 break;
918
919 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
920 sc->pcn_cdata.pcn_tx_cnt--;
921 PCN_INC(idx, PCN_TX_LIST_CNT);
922 continue;
923 }
924
925 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
926 ifp->if_oerrors++;
927 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
928 ifp->if_collisions++;
929 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
930 ifp->if_collisions++;
931 }
932
933 ifp->if_collisions +=
934 cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
935
936 ifp->if_opackets++;
937 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
938 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
939 sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
940 }
941
942 sc->pcn_cdata.pcn_tx_cnt--;
943 PCN_INC(idx, PCN_TX_LIST_CNT);
944 }
945
946 if (idx != sc->pcn_cdata.pcn_tx_cons) {
947 /* Some buffers have been freed. */
948 sc->pcn_cdata.pcn_tx_cons = idx;
949 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
950 }
951 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
952
953 return;
954 }
955
956 static void
957 pcn_tick(xsc)
958 void *xsc;
959 {
960 struct pcn_softc *sc;
961 struct mii_data *mii;
962 struct ifnet *ifp;
963
964 sc = xsc;
965 ifp = sc->pcn_ifp;
966 PCN_LOCK_ASSERT(sc);
967
968 mii = device_get_softc(sc->pcn_miibus);
969 mii_tick(mii);
970
971 /* link just died */
972 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
973 sc->pcn_link = 0;
974
975 /* link just came up, restart */
976 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE &&
977 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
978 sc->pcn_link++;
979 if (ifp->if_snd.ifq_head != NULL)
980 pcn_start_locked(ifp);
981 }
982
983 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc);
984
985 return;
986 }
987
988 static void
989 pcn_intr(arg)
990 void *arg;
991 {
992 struct pcn_softc *sc;
993 struct ifnet *ifp;
994 u_int32_t status;
995
996 sc = arg;
997 ifp = sc->pcn_ifp;
998
999 PCN_LOCK(sc);
1000
1001 /* Suppress unwanted interrupts */
1002 if (!(ifp->if_flags & IFF_UP)) {
1003 pcn_stop(sc);
1004 PCN_UNLOCK(sc);
1005 return;
1006 }
1007
1008 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
1009
1010 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
1011 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
1012
1013 if (status & PCN_CSR_RINT)
1014 pcn_rxeof(sc);
1015
1016 if (status & PCN_CSR_TINT)
1017 pcn_txeof(sc);
1018
1019 if (status & PCN_CSR_ERR) {
1020 pcn_init_locked(sc);
1021 break;
1022 }
1023 }
1024
1025 if (ifp->if_snd.ifq_head != NULL)
1026 pcn_start_locked(ifp);
1027
1028 PCN_UNLOCK(sc);
1029 return;
1030 }
1031
1032 /*
1033 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1034 * pointers to the fragment pointers.
1035 */
1036 static int
1037 pcn_encap(sc, m_head, txidx)
1038 struct pcn_softc *sc;
1039 struct mbuf *m_head;
1040 u_int32_t *txidx;
1041 {
1042 struct pcn_tx_desc *f = NULL;
1043 struct mbuf *m;
1044 int frag, cur, cnt = 0;
1045
1046 /*
1047 * Start packing the mbufs in this chain into
1048 * the fragment pointers. Stop when we run out
1049 * of fragments or hit the end of the mbuf chain.
1050 */
1051 m = m_head;
1052 cur = frag = *txidx;
1053
1054 for (m = m_head; m != NULL; m = m->m_next) {
1055 if (m->m_len == 0)
1056 continue;
1057
1058 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
1059 return(ENOBUFS);
1060 f = &sc->pcn_ldata->pcn_tx_list[frag];
1061 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
1062 f->pcn_txctl |= PCN_TXCTL_MBO;
1063 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
1064 if (cnt == 0)
1065 f->pcn_txctl |= PCN_TXCTL_STP;
1066 else
1067 f->pcn_txctl |= PCN_TXCTL_OWN;
1068 cur = frag;
1069 PCN_INC(frag, PCN_TX_LIST_CNT);
1070 cnt++;
1071 }
1072
1073 if (m != NULL)
1074 return(ENOBUFS);
1075
1076 sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
1077 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
1078 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
1079 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
1080 sc->pcn_cdata.pcn_tx_cnt += cnt;
1081 *txidx = frag;
1082
1083 return(0);
1084 }
1085
1086 /*
1087 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1088 * to the mbuf data regions directly in the transmit lists. We also save a
1089 * copy of the pointers since the transmit list fragment pointers are
1090 * physical addresses.
1091 */
1092 static void
1093 pcn_start(ifp)
1094 struct ifnet *ifp;
1095 {
1096 struct pcn_softc *sc;
1097
1098 sc = ifp->if_softc;
1099 PCN_LOCK(sc);
1100 pcn_start_locked(ifp);
1101 PCN_UNLOCK(sc);
1102 }
1103
1104 static void
1105 pcn_start_locked(ifp)
1106 struct ifnet *ifp;
1107 {
1108 struct pcn_softc *sc;
1109 struct mbuf *m_head = NULL;
1110 u_int32_t idx;
1111
1112 sc = ifp->if_softc;
1113
1114 PCN_LOCK_ASSERT(sc);
1115
1116 if (!sc->pcn_link)
1117 return;
1118
1119 idx = sc->pcn_cdata.pcn_tx_prod;
1120
1121 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1122 return;
1123
1124 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
1125 IF_DEQUEUE(&ifp->if_snd, m_head);
1126 if (m_head == NULL)
1127 break;
1128
1129 if (pcn_encap(sc, m_head, &idx)) {
1130 IF_PREPEND(&ifp->if_snd, m_head);
1131 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1132 break;
1133 }
1134
1135 /*
1136 * If there's a BPF listener, bounce a copy of this frame
1137 * to him.
1138 */
1139 BPF_MTAP(ifp, m_head);
1140
1141 }
1142
1143 /* Transmit */
1144 sc->pcn_cdata.pcn_tx_prod = idx;
1145 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
1146
1147 /*
1148 * Set a timeout in case the chip goes out to lunch.
1149 */
1150 ifp->if_timer = 5;
1151
1152 return;
1153 }
1154
1155 static void
1156 pcn_setfilt(ifp)
1157 struct ifnet *ifp;
1158 {
1159 struct pcn_softc *sc;
1160
1161 sc = ifp->if_softc;
1162
1163 /* If we want promiscuous mode, set the allframes bit. */
1164 if (ifp->if_flags & IFF_PROMISC) {
1165 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1166 } else {
1167 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1168 }
1169
1170 /* Set the capture broadcast bit to capture broadcast frames. */
1171 if (ifp->if_flags & IFF_BROADCAST) {
1172 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1173 } else {
1174 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1175 }
1176
1177 return;
1178 }
1179
1180 static void
1181 pcn_init(xsc)
1182 void *xsc;
1183 {
1184 struct pcn_softc *sc = xsc;
1185
1186 PCN_LOCK(sc);
1187 pcn_init_locked(sc);
1188 PCN_UNLOCK(sc);
1189 }
1190
1191 static void
1192 pcn_init_locked(sc)
1193 struct pcn_softc *sc;
1194 {
1195 struct ifnet *ifp = sc->pcn_ifp;
1196 struct mii_data *mii = NULL;
1197 struct ifmedia_entry *ife;
1198
1199 PCN_LOCK_ASSERT(sc);
1200
1201 /*
1202 * Cancel pending I/O and free all RX/TX buffers.
1203 */
1204 pcn_stop(sc);
1205 pcn_reset(sc);
1206
1207 mii = device_get_softc(sc->pcn_miibus);
1208 ife = mii->mii_media.ifm_cur;
1209
1210 /* Set MAC address */
1211 pcn_csr_write(sc, PCN_CSR_PAR0,
1212 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[0]);
1213 pcn_csr_write(sc, PCN_CSR_PAR1,
1214 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[1]);
1215 pcn_csr_write(sc, PCN_CSR_PAR2,
1216 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[2]);
1217
1218 /* Init circular RX list. */
1219 if (pcn_list_rx_init(sc) == ENOBUFS) {
1220 if_printf(ifp, "initialization failed: no "
1221 "memory for rx buffers\n");
1222 pcn_stop(sc);
1223 return;
1224 }
1225
1226 /*
1227 * Init tx descriptors.
1228 */
1229 pcn_list_tx_init(sc);
1230
1231 /* Clear PCN_MISC_ASEL so we can set the port via PCN_CSR_MODE. */
1232 PCN_BCR_CLRBIT(sc, PCN_BCR_MISCCFG, PCN_MISC_ASEL);
1233
1234 /*
1235 * Set up the port based on the currently selected media.
1236 * For Am79C978 we've to unconditionally set PCN_PORT_MII and
1237 * set the PHY in PCN_BCR_PHYSEL instead.
1238 */
1239 if (sc->pcn_type != Am79C978 &&
1240 IFM_INST(ife->ifm_media) == sc->pcn_inst_10bt)
1241 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_10BASET);
1242 else
1243 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
1244
1245 /* Set up RX filter. */
1246 pcn_setfilt(ifp);
1247
1248 /*
1249 * Load the multicast filter.
1250 */
1251 pcn_setmulti(sc);
1252
1253 /*
1254 * Load the addresses of the RX and TX lists.
1255 */
1256 pcn_csr_write(sc, PCN_CSR_RXADDR0,
1257 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
1258 pcn_csr_write(sc, PCN_CSR_RXADDR1,
1259 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
1260 pcn_csr_write(sc, PCN_CSR_TXADDR0,
1261 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
1262 pcn_csr_write(sc, PCN_CSR_TXADDR1,
1263 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
1264
1265 /* Set the RX and TX ring sizes. */
1266 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
1267 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
1268
1269 /* We're not using the initialization block. */
1270 pcn_csr_write(sc, PCN_CSR_IAB1, 0);
1271
1272 /* Enable fast suspend mode. */
1273 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1274
1275 /*
1276 * Enable burst read and write. Also set the no underflow
1277 * bit. This will avoid transmit underruns in certain
1278 * conditions while still providing decent performance.
1279 */
1280 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
1281 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
1282
1283 /* Enable graceful recovery from underflow. */
1284 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1285
1286 /* Enable auto-padding of short TX frames. */
1287 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1288
1289 /* Disable MII autoneg (we handle this ourselves). */
1290 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
1291
1292 if (sc->pcn_type == Am79C978)
1293 /* XXX support other PHYs? */
1294 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
1295 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
1296
1297 /* Enable interrupts and start the controller running. */
1298 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
1299
1300 mii_mediachg(mii);
1301
1302 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1303 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1304
1305 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc);
1306
1307 return;
1308 }
1309
1310 /*
1311 * Set media options.
1312 */
1313 static int
1314 pcn_ifmedia_upd(ifp)
1315 struct ifnet *ifp;
1316 {
1317 struct pcn_softc *sc;
1318
1319 sc = ifp->if_softc;
1320
1321 PCN_LOCK(sc);
1322
1323 /*
1324 * At least Am79C971 with DP83840A can wedge when switching
1325 * from the internal 10baseT PHY to the external PHY without
1326 * issuing pcn_reset(). For setting the port in PCN_CSR_MODE
1327 * the PCnet chip has to be powered down or stopped anyway
1328 * and although documented otherwise it doesn't take effect
1329 * until the next initialization.
1330 */
1331 sc->pcn_link = 0;
1332 pcn_stop(sc);
1333 pcn_reset(sc);
1334 pcn_init_locked(sc);
1335 if (ifp->if_snd.ifq_head != NULL)
1336 pcn_start_locked(ifp);
1337
1338 PCN_UNLOCK(sc);
1339
1340 return(0);
1341 }
1342
1343 /*
1344 * Report current media status.
1345 */
1346 static void
1347 pcn_ifmedia_sts(ifp, ifmr)
1348 struct ifnet *ifp;
1349 struct ifmediareq *ifmr;
1350 {
1351 struct pcn_softc *sc;
1352 struct mii_data *mii;
1353
1354 sc = ifp->if_softc;
1355
1356 mii = device_get_softc(sc->pcn_miibus);
1357 PCN_LOCK(sc);
1358 mii_pollstat(mii);
1359 ifmr->ifm_active = mii->mii_media_active;
1360 ifmr->ifm_status = mii->mii_media_status;
1361 PCN_UNLOCK(sc);
1362
1363 return;
1364 }
1365
1366 static int
1367 pcn_ioctl(ifp, command, data)
1368 struct ifnet *ifp;
1369 u_long command;
1370 caddr_t data;
1371 {
1372 struct pcn_softc *sc = ifp->if_softc;
1373 struct ifreq *ifr = (struct ifreq *) data;
1374 struct mii_data *mii = NULL;
1375 int error = 0;
1376
1377 switch(command) {
1378 case SIOCSIFFLAGS:
1379 PCN_LOCK(sc);
1380 if (ifp->if_flags & IFF_UP) {
1381 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1382 ifp->if_flags & IFF_PROMISC &&
1383 !(sc->pcn_if_flags & IFF_PROMISC)) {
1384 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1385 PCN_EXTCTL1_SPND);
1386 pcn_setfilt(ifp);
1387 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1388 PCN_EXTCTL1_SPND);
1389 pcn_csr_write(sc, PCN_CSR_CSR,
1390 PCN_CSR_INTEN|PCN_CSR_START);
1391 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1392 !(ifp->if_flags & IFF_PROMISC) &&
1393 sc->pcn_if_flags & IFF_PROMISC) {
1394 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1395 PCN_EXTCTL1_SPND);
1396 pcn_setfilt(ifp);
1397 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1398 PCN_EXTCTL1_SPND);
1399 pcn_csr_write(sc, PCN_CSR_CSR,
1400 PCN_CSR_INTEN|PCN_CSR_START);
1401 } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1402 pcn_init_locked(sc);
1403 } else {
1404 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1405 pcn_stop(sc);
1406 }
1407 sc->pcn_if_flags = ifp->if_flags;
1408 PCN_UNLOCK(sc);
1409 error = 0;
1410 break;
1411 case SIOCADDMULTI:
1412 case SIOCDELMULTI:
1413 PCN_LOCK(sc);
1414 pcn_setmulti(sc);
1415 PCN_UNLOCK(sc);
1416 error = 0;
1417 break;
1418 case SIOCGIFMEDIA:
1419 case SIOCSIFMEDIA:
1420 mii = device_get_softc(sc->pcn_miibus);
1421 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1422 break;
1423 default:
1424 error = ether_ioctl(ifp, command, data);
1425 break;
1426 }
1427
1428 return(error);
1429 }
1430
1431 static void
1432 pcn_watchdog(ifp)
1433 struct ifnet *ifp;
1434 {
1435 struct pcn_softc *sc;
1436
1437 sc = ifp->if_softc;
1438
1439 PCN_LOCK(sc);
1440
1441 ifp->if_oerrors++;
1442 if_printf(ifp, "watchdog timeout\n");
1443
1444 pcn_stop(sc);
1445 pcn_reset(sc);
1446 pcn_init_locked(sc);
1447
1448 if (ifp->if_snd.ifq_head != NULL)
1449 pcn_start(ifp);
1450
1451 PCN_UNLOCK(sc);
1452
1453 return;
1454 }
1455
1456 /*
1457 * Stop the adapter and free any mbufs allocated to the
1458 * RX and TX lists.
1459 */
1460 static void
1461 pcn_stop(sc)
1462 struct pcn_softc *sc;
1463 {
1464 register int i;
1465 struct ifnet *ifp;
1466
1467 PCN_LOCK_ASSERT(sc);
1468 ifp = sc->pcn_ifp;
1469 ifp->if_timer = 0;
1470
1471 callout_stop(&sc->pcn_stat_callout);
1472
1473 /* Turn off interrupts */
1474 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
1475 /* Stop adapter */
1476 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
1477 sc->pcn_link = 0;
1478
1479 /*
1480 * Free data in the RX lists.
1481 */
1482 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
1483 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
1484 m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
1485 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
1486 }
1487 }
1488 bzero((char *)&sc->pcn_ldata->pcn_rx_list,
1489 sizeof(sc->pcn_ldata->pcn_rx_list));
1490
1491 /*
1492 * Free the TX list buffers.
1493 */
1494 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
1495 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
1496 m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
1497 sc->pcn_cdata.pcn_tx_chain[i] = NULL;
1498 }
1499 }
1500
1501 bzero((char *)&sc->pcn_ldata->pcn_tx_list,
1502 sizeof(sc->pcn_ldata->pcn_tx_list));
1503
1504 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1505
1506 return;
1507 }
1508
1509 /*
1510 * Stop all chip I/O so that the kernel's probe routines don't
1511 * get confused by errant DMAs when rebooting.
1512 */
1513 static void
1514 pcn_shutdown(dev)
1515 device_t dev;
1516 {
1517 struct pcn_softc *sc;
1518
1519 sc = device_get_softc(dev);
1520
1521 PCN_LOCK(sc);
1522 pcn_reset(sc);
1523 pcn_stop(sc);
1524 PCN_UNLOCK(sc);
1525
1526 return;
1527 }
Cache object: cb510fbe731c4d37ae7b102a774942f1
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