FreeBSD/Linux Kernel Cross Reference
sys/pci/if_rl.c
1 /*-
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: src/sys/pci/if_rl.c,v 1.183 2008/11/02 16:50:57 imp Exp $");
35
36 /*
37 * RealTek 8129/8139 PCI NIC driver
38 *
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
41 * www.realtek.com.tw.
42 *
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
46 */
47 /*
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
53 *
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
62 *
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
68 * levels.
69 *
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
73 *
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
78 * filter.
79 *
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
84 */
85
86 #ifdef HAVE_KERNEL_OPTION_HEADERS
87 #include "opt_device_polling.h"
88 #endif
89
90 #include <sys/param.h>
91 #include <sys/endian.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
94 #include <sys/mbuf.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/module.h>
98 #include <sys/socket.h>
99 #include <sys/sysctl.h>
100
101 #include <net/if.h>
102 #include <net/if_arp.h>
103 #include <net/ethernet.h>
104 #include <net/if_dl.h>
105 #include <net/if_media.h>
106 #include <net/if_types.h>
107
108 #include <net/bpf.h>
109
110 #include <machine/bus.h>
111 #include <machine/resource.h>
112 #include <sys/bus.h>
113 #include <sys/rman.h>
114
115 #include <dev/mii/mii.h>
116 #include <dev/mii/miivar.h>
117
118 #include <dev/pci/pcireg.h>
119 #include <dev/pci/pcivar.h>
120
121 MODULE_DEPEND(rl, pci, 1, 1, 1);
122 MODULE_DEPEND(rl, ether, 1, 1, 1);
123 MODULE_DEPEND(rl, miibus, 1, 1, 1);
124
125 /* "device miibus" required. See GENERIC if you get errors here. */
126 #include "miibus_if.h"
127
128 /*
129 * Default to using PIO access for this driver. On SMP systems,
130 * there appear to be problems with memory mapped mode: it looks like
131 * doing too many memory mapped access back to back in rapid succession
132 * can hang the bus. I'm inclined to blame this on crummy design/construction
133 * on the part of RealTek. Memory mapped mode does appear to work on
134 * uniprocessor systems though.
135 */
136 #define RL_USEIOSPACE
137
138 #include <pci/if_rlreg.h>
139
140 /*
141 * Various supported device vendors/types and their names.
142 */
143 static struct rl_type rl_devs[] = {
144 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
145 "RealTek 8129 10/100BaseTX" },
146 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
147 "RealTek 8139 10/100BaseTX" },
148 { RT_VENDORID, RT_DEVICEID_8139D, RL_8139,
149 "RealTek 8139 10/100BaseTX" },
150 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
151 "RealTek 8139 10/100BaseTX CardBus" },
152 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
153 "RealTek 8100 10/100BaseTX" },
154 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
155 "Accton MPX 5030/5038 10/100BaseTX" },
156 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
157 "Delta Electronics 8139 10/100BaseTX" },
158 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
159 "Addtron Technology 8139 10/100BaseTX" },
160 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
161 "D-Link DFE-530TX+ 10/100BaseTX" },
162 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
163 "D-Link DFE-690TXD 10/100BaseTX" },
164 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
165 "Nortel Networks 10/100BaseTX" },
166 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
167 "Corega FEther CB-TXD" },
168 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
169 "Corega FEtherII CB-TXD" },
170 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
171 "Peppercon AG ROL-F" },
172 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
173 "Planex FNW-3603-TX" },
174 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
175 "Planex FNW-3800-TX" },
176 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
177 "Compaq HNE-300" },
178 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
179 "LevelOne FPC-0106TX" },
180 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
181 "Edimax EP-4103DL CardBus" }
182 };
183
184 static int rl_attach(device_t);
185 static int rl_detach(device_t);
186 static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int);
187 static int rl_dma_alloc(struct rl_softc *);
188 static void rl_dma_free(struct rl_softc *);
189 static void rl_eeprom_putbyte(struct rl_softc *, int);
190 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
191 static int rl_encap(struct rl_softc *, struct mbuf **);
192 static int rl_list_tx_init(struct rl_softc *);
193 static int rl_list_rx_init(struct rl_softc *);
194 static int rl_ifmedia_upd(struct ifnet *);
195 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
196 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
197 static void rl_intr(void *);
198 static void rl_init(void *);
199 static void rl_init_locked(struct rl_softc *sc);
200 static void rl_mii_send(struct rl_softc *, uint32_t, int);
201 static void rl_mii_sync(struct rl_softc *);
202 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
203 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
204 static int rl_miibus_readreg(device_t, int, int);
205 static void rl_miibus_statchg(device_t);
206 static int rl_miibus_writereg(device_t, int, int, int);
207 #ifdef DEVICE_POLLING
208 static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
209 static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
210 #endif
211 static int rl_probe(device_t);
212 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
213 static void rl_reset(struct rl_softc *);
214 static int rl_resume(device_t);
215 static void rl_rxeof(struct rl_softc *);
216 static void rl_setmulti(struct rl_softc *);
217 static int rl_shutdown(device_t);
218 static void rl_start(struct ifnet *);
219 static void rl_start_locked(struct ifnet *);
220 static void rl_stop(struct rl_softc *);
221 static int rl_suspend(device_t);
222 static void rl_tick(void *);
223 static void rl_txeof(struct rl_softc *);
224 static void rl_watchdog(struct rl_softc *);
225
226 #ifdef RL_USEIOSPACE
227 #define RL_RES SYS_RES_IOPORT
228 #define RL_RID RL_PCI_LOIO
229 #else
230 #define RL_RES SYS_RES_MEMORY
231 #define RL_RID RL_PCI_LOMEM
232 #endif
233
234 static device_method_t rl_methods[] = {
235 /* Device interface */
236 DEVMETHOD(device_probe, rl_probe),
237 DEVMETHOD(device_attach, rl_attach),
238 DEVMETHOD(device_detach, rl_detach),
239 DEVMETHOD(device_suspend, rl_suspend),
240 DEVMETHOD(device_resume, rl_resume),
241 DEVMETHOD(device_shutdown, rl_shutdown),
242
243 /* bus interface */
244 DEVMETHOD(bus_print_child, bus_generic_print_child),
245 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
246
247 /* MII interface */
248 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
249 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
250 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
251
252 { 0, 0 }
253 };
254
255 static driver_t rl_driver = {
256 "rl",
257 rl_methods,
258 sizeof(struct rl_softc)
259 };
260
261 static devclass_t rl_devclass;
262
263 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
264 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
265 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
266
267 #define EE_SET(x) \
268 CSR_WRITE_1(sc, RL_EECMD, \
269 CSR_READ_1(sc, RL_EECMD) | x)
270
271 #define EE_CLR(x) \
272 CSR_WRITE_1(sc, RL_EECMD, \
273 CSR_READ_1(sc, RL_EECMD) & ~x)
274
275 /*
276 * Send a read command and address to the EEPROM, check for ACK.
277 */
278 static void
279 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
280 {
281 register int d, i;
282
283 d = addr | sc->rl_eecmd_read;
284
285 /*
286 * Feed in each bit and strobe the clock.
287 */
288 for (i = 0x400; i; i >>= 1) {
289 if (d & i) {
290 EE_SET(RL_EE_DATAIN);
291 } else {
292 EE_CLR(RL_EE_DATAIN);
293 }
294 DELAY(100);
295 EE_SET(RL_EE_CLK);
296 DELAY(150);
297 EE_CLR(RL_EE_CLK);
298 DELAY(100);
299 }
300 }
301
302 /*
303 * Read a word of data stored in the EEPROM at address 'addr.'
304 */
305 static void
306 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
307 {
308 register int i;
309 uint16_t word = 0;
310
311 /* Enter EEPROM access mode. */
312 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
313
314 /*
315 * Send address of word we want to read.
316 */
317 rl_eeprom_putbyte(sc, addr);
318
319 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
320
321 /*
322 * Start reading bits from EEPROM.
323 */
324 for (i = 0x8000; i; i >>= 1) {
325 EE_SET(RL_EE_CLK);
326 DELAY(100);
327 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
328 word |= i;
329 EE_CLR(RL_EE_CLK);
330 DELAY(100);
331 }
332
333 /* Turn off EEPROM access mode. */
334 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
335
336 *dest = word;
337 }
338
339 /*
340 * Read a sequence of words from the EEPROM.
341 */
342 static void
343 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
344 {
345 int i;
346 uint16_t word = 0, *ptr;
347
348 for (i = 0; i < cnt; i++) {
349 rl_eeprom_getword(sc, off + i, &word);
350 ptr = (uint16_t *)(dest + (i * 2));
351 if (swap)
352 *ptr = ntohs(word);
353 else
354 *ptr = word;
355 }
356 }
357
358 /*
359 * MII access routines are provided for the 8129, which
360 * doesn't have a built-in PHY. For the 8139, we fake things
361 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
362 * direct access PHY registers.
363 */
364 #define MII_SET(x) \
365 CSR_WRITE_1(sc, RL_MII, \
366 CSR_READ_1(sc, RL_MII) | (x))
367
368 #define MII_CLR(x) \
369 CSR_WRITE_1(sc, RL_MII, \
370 CSR_READ_1(sc, RL_MII) & ~(x))
371
372 /*
373 * Sync the PHYs by setting data bit and strobing the clock 32 times.
374 */
375 static void
376 rl_mii_sync(struct rl_softc *sc)
377 {
378 register int i;
379
380 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
381
382 for (i = 0; i < 32; i++) {
383 MII_SET(RL_MII_CLK);
384 DELAY(1);
385 MII_CLR(RL_MII_CLK);
386 DELAY(1);
387 }
388 }
389
390 /*
391 * Clock a series of bits through the MII.
392 */
393 static void
394 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
395 {
396 int i;
397
398 MII_CLR(RL_MII_CLK);
399
400 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
401 if (bits & i) {
402 MII_SET(RL_MII_DATAOUT);
403 } else {
404 MII_CLR(RL_MII_DATAOUT);
405 }
406 DELAY(1);
407 MII_CLR(RL_MII_CLK);
408 DELAY(1);
409 MII_SET(RL_MII_CLK);
410 }
411 }
412
413 /*
414 * Read an PHY register through the MII.
415 */
416 static int
417 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
418 {
419 int i, ack;
420
421 /* Set up frame for RX. */
422 frame->mii_stdelim = RL_MII_STARTDELIM;
423 frame->mii_opcode = RL_MII_READOP;
424 frame->mii_turnaround = 0;
425 frame->mii_data = 0;
426
427 CSR_WRITE_2(sc, RL_MII, 0);
428
429 /* Turn on data xmit. */
430 MII_SET(RL_MII_DIR);
431
432 rl_mii_sync(sc);
433
434 /* Send command/address info. */
435 rl_mii_send(sc, frame->mii_stdelim, 2);
436 rl_mii_send(sc, frame->mii_opcode, 2);
437 rl_mii_send(sc, frame->mii_phyaddr, 5);
438 rl_mii_send(sc, frame->mii_regaddr, 5);
439
440 /* Idle bit */
441 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
442 DELAY(1);
443 MII_SET(RL_MII_CLK);
444 DELAY(1);
445
446 /* Turn off xmit. */
447 MII_CLR(RL_MII_DIR);
448
449 /* Check for ack */
450 MII_CLR(RL_MII_CLK);
451 DELAY(1);
452 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
453 MII_SET(RL_MII_CLK);
454 DELAY(1);
455
456 /*
457 * Now try reading data bits. If the ack failed, we still
458 * need to clock through 16 cycles to keep the PHY(s) in sync.
459 */
460 if (ack) {
461 for(i = 0; i < 16; i++) {
462 MII_CLR(RL_MII_CLK);
463 DELAY(1);
464 MII_SET(RL_MII_CLK);
465 DELAY(1);
466 }
467 goto fail;
468 }
469
470 for (i = 0x8000; i; i >>= 1) {
471 MII_CLR(RL_MII_CLK);
472 DELAY(1);
473 if (!ack) {
474 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
475 frame->mii_data |= i;
476 DELAY(1);
477 }
478 MII_SET(RL_MII_CLK);
479 DELAY(1);
480 }
481
482 fail:
483 MII_CLR(RL_MII_CLK);
484 DELAY(1);
485 MII_SET(RL_MII_CLK);
486 DELAY(1);
487
488 return (ack ? 1 : 0);
489 }
490
491 /*
492 * Write to a PHY register through the MII.
493 */
494 static int
495 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
496 {
497
498 /* Set up frame for TX. */
499 frame->mii_stdelim = RL_MII_STARTDELIM;
500 frame->mii_opcode = RL_MII_WRITEOP;
501 frame->mii_turnaround = RL_MII_TURNAROUND;
502
503 /* Turn on data output. */
504 MII_SET(RL_MII_DIR);
505
506 rl_mii_sync(sc);
507
508 rl_mii_send(sc, frame->mii_stdelim, 2);
509 rl_mii_send(sc, frame->mii_opcode, 2);
510 rl_mii_send(sc, frame->mii_phyaddr, 5);
511 rl_mii_send(sc, frame->mii_regaddr, 5);
512 rl_mii_send(sc, frame->mii_turnaround, 2);
513 rl_mii_send(sc, frame->mii_data, 16);
514
515 /* Idle bit. */
516 MII_SET(RL_MII_CLK);
517 DELAY(1);
518 MII_CLR(RL_MII_CLK);
519 DELAY(1);
520
521 /* Turn off xmit. */
522 MII_CLR(RL_MII_DIR);
523
524 return (0);
525 }
526
527 static int
528 rl_miibus_readreg(device_t dev, int phy, int reg)
529 {
530 struct rl_softc *sc;
531 struct rl_mii_frame frame;
532 uint16_t rval = 0;
533 uint16_t rl8139_reg = 0;
534
535 sc = device_get_softc(dev);
536
537 if (sc->rl_type == RL_8139) {
538 /* Pretend the internal PHY is only at address 0 */
539 if (phy) {
540 return (0);
541 }
542 switch (reg) {
543 case MII_BMCR:
544 rl8139_reg = RL_BMCR;
545 break;
546 case MII_BMSR:
547 rl8139_reg = RL_BMSR;
548 break;
549 case MII_ANAR:
550 rl8139_reg = RL_ANAR;
551 break;
552 case MII_ANER:
553 rl8139_reg = RL_ANER;
554 break;
555 case MII_ANLPAR:
556 rl8139_reg = RL_LPAR;
557 break;
558 case MII_PHYIDR1:
559 case MII_PHYIDR2:
560 return (0);
561 /*
562 * Allow the rlphy driver to read the media status
563 * register. If we have a link partner which does not
564 * support NWAY, this is the register which will tell
565 * us the results of parallel detection.
566 */
567 case RL_MEDIASTAT:
568 rval = CSR_READ_1(sc, RL_MEDIASTAT);
569 return (rval);
570 default:
571 device_printf(sc->rl_dev, "bad phy register\n");
572 return (0);
573 }
574 rval = CSR_READ_2(sc, rl8139_reg);
575 return (rval);
576 }
577
578 bzero((char *)&frame, sizeof(frame));
579 frame.mii_phyaddr = phy;
580 frame.mii_regaddr = reg;
581 rl_mii_readreg(sc, &frame);
582
583 return (frame.mii_data);
584 }
585
586 static int
587 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
588 {
589 struct rl_softc *sc;
590 struct rl_mii_frame frame;
591 uint16_t rl8139_reg = 0;
592
593 sc = device_get_softc(dev);
594
595 if (sc->rl_type == RL_8139) {
596 /* Pretend the internal PHY is only at address 0 */
597 if (phy) {
598 return (0);
599 }
600 switch (reg) {
601 case MII_BMCR:
602 rl8139_reg = RL_BMCR;
603 break;
604 case MII_BMSR:
605 rl8139_reg = RL_BMSR;
606 break;
607 case MII_ANAR:
608 rl8139_reg = RL_ANAR;
609 break;
610 case MII_ANER:
611 rl8139_reg = RL_ANER;
612 break;
613 case MII_ANLPAR:
614 rl8139_reg = RL_LPAR;
615 break;
616 case MII_PHYIDR1:
617 case MII_PHYIDR2:
618 return (0);
619 break;
620 default:
621 device_printf(sc->rl_dev, "bad phy register\n");
622 return (0);
623 }
624 CSR_WRITE_2(sc, rl8139_reg, data);
625 return (0);
626 }
627
628 bzero((char *)&frame, sizeof(frame));
629 frame.mii_phyaddr = phy;
630 frame.mii_regaddr = reg;
631 frame.mii_data = data;
632 rl_mii_writereg(sc, &frame);
633
634 return (0);
635 }
636
637 static void
638 rl_miibus_statchg(device_t dev)
639 {
640 struct rl_softc *sc;
641 struct ifnet *ifp;
642 struct mii_data *mii;
643
644 sc = device_get_softc(dev);
645 mii = device_get_softc(sc->rl_miibus);
646 ifp = sc->rl_ifp;
647 if (mii == NULL || ifp == NULL ||
648 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
649 return;
650
651 sc->rl_flags &= ~RL_FLAG_LINK;
652 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
653 (IFM_ACTIVE | IFM_AVALID)) {
654 switch (IFM_SUBTYPE(mii->mii_media_active)) {
655 case IFM_10_T:
656 case IFM_100_TX:
657 sc->rl_flags |= RL_FLAG_LINK;
658 break;
659 default:
660 break;
661 }
662 }
663 /*
664 * RealTek controllers do not provide any interface to
665 * Tx/Rx MACs for resolved speed, duplex and flow-control
666 * parameters.
667 */
668 }
669
670 /*
671 * Program the 64-bit multicast hash filter.
672 */
673 static void
674 rl_setmulti(struct rl_softc *sc)
675 {
676 struct ifnet *ifp = sc->rl_ifp;
677 int h = 0;
678 uint32_t hashes[2] = { 0, 0 };
679 struct ifmultiaddr *ifma;
680 uint32_t rxfilt;
681 int mcnt = 0;
682
683 RL_LOCK_ASSERT(sc);
684
685 rxfilt = CSR_READ_4(sc, RL_RXCFG);
686
687 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
688 rxfilt |= RL_RXCFG_RX_MULTI;
689 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
690 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
691 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
692 return;
693 }
694
695 /* first, zot all the existing hash bits */
696 CSR_WRITE_4(sc, RL_MAR0, 0);
697 CSR_WRITE_4(sc, RL_MAR4, 0);
698
699 /* now program new ones */
700 IF_ADDR_LOCK(ifp);
701 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
702 if (ifma->ifma_addr->sa_family != AF_LINK)
703 continue;
704 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
705 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
706 if (h < 32)
707 hashes[0] |= (1 << h);
708 else
709 hashes[1] |= (1 << (h - 32));
710 mcnt++;
711 }
712 IF_ADDR_UNLOCK(ifp);
713
714 if (mcnt)
715 rxfilt |= RL_RXCFG_RX_MULTI;
716 else
717 rxfilt &= ~RL_RXCFG_RX_MULTI;
718
719 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
720 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
721 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
722 }
723
724 static void
725 rl_reset(struct rl_softc *sc)
726 {
727 register int i;
728
729 RL_LOCK_ASSERT(sc);
730
731 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
732
733 for (i = 0; i < RL_TIMEOUT; i++) {
734 DELAY(10);
735 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
736 break;
737 }
738 if (i == RL_TIMEOUT)
739 device_printf(sc->rl_dev, "reset never completed!\n");
740 }
741
742 /*
743 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
744 * IDs against our list and return a device name if we find a match.
745 */
746 static int
747 rl_probe(device_t dev)
748 {
749 struct rl_type *t;
750 uint16_t devid, revid, vendor;
751 int i;
752
753 vendor = pci_get_vendor(dev);
754 devid = pci_get_device(dev);
755 revid = pci_get_revid(dev);
756
757 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
758 if (revid == 0x20) {
759 /* 8139C+, let re(4) take care of this device. */
760 return (ENXIO);
761 }
762 }
763 t = rl_devs;
764 for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) {
765 if (vendor == t->rl_vid && devid == t->rl_did) {
766 device_set_desc(dev, t->rl_name);
767 return (BUS_PROBE_DEFAULT);
768 }
769 }
770
771 return (ENXIO);
772 }
773
774 struct rl_dmamap_arg {
775 bus_addr_t rl_busaddr;
776 };
777
778 static void
779 rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
780 {
781 struct rl_dmamap_arg *ctx;
782
783 if (error != 0)
784 return;
785
786 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
787
788 ctx = (struct rl_dmamap_arg *)arg;
789 ctx->rl_busaddr = segs[0].ds_addr;
790 }
791
792 /*
793 * Attach the interface. Allocate softc structures, do ifmedia
794 * setup and ethernet/BPF attach.
795 */
796 static int
797 rl_attach(device_t dev)
798 {
799 uint8_t eaddr[ETHER_ADDR_LEN];
800 uint16_t as[3];
801 struct ifnet *ifp;
802 struct rl_softc *sc;
803 struct rl_type *t;
804 struct sysctl_ctx_list *ctx;
805 struct sysctl_oid_list *children;
806 int error = 0, i, rid;
807 int unit;
808 uint16_t rl_did = 0;
809 char tn[32];
810
811 sc = device_get_softc(dev);
812 unit = device_get_unit(dev);
813 sc->rl_dev = dev;
814
815 sc->rl_twister_enable = 0;
816 snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit);
817 TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable);
818 ctx = device_get_sysctl_ctx(sc->rl_dev);
819 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
820 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD,
821 &sc->rl_twister_enable, 0, "");
822
823 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
824 MTX_DEF);
825 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
826
827 pci_enable_busmaster(dev);
828
829 /* Map control/status registers. */
830 rid = RL_RID;
831 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
832
833 if (sc->rl_res == NULL) {
834 device_printf(dev, "couldn't map ports/memory\n");
835 error = ENXIO;
836 goto fail;
837 }
838
839 #ifdef notdef
840 /*
841 * Detect the Realtek 8139B. For some reason, this chip is very
842 * unstable when left to autoselect the media
843 * The best workaround is to set the device to the required
844 * media type or to set it to the 10 Meg speed.
845 */
846 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
847 device_printf(dev,
848 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
849 #endif
850
851 sc->rl_btag = rman_get_bustag(sc->rl_res);
852 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
853
854 /* Allocate interrupt */
855 rid = 0;
856 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
857 RF_SHAREABLE | RF_ACTIVE);
858
859 if (sc->rl_irq[0] == NULL) {
860 device_printf(dev, "couldn't map interrupt\n");
861 error = ENXIO;
862 goto fail;
863 }
864
865 /*
866 * Reset the adapter. Only take the lock here as it's needed in
867 * order to call rl_reset().
868 */
869 RL_LOCK(sc);
870 rl_reset(sc);
871 RL_UNLOCK(sc);
872
873 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
874 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
875 if (rl_did != 0x8129)
876 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
877
878 /*
879 * Get station address from the EEPROM.
880 */
881 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
882 for (i = 0; i < 3; i++) {
883 eaddr[(i * 2) + 0] = as[i] & 0xff;
884 eaddr[(i * 2) + 1] = as[i] >> 8;
885 }
886
887 /*
888 * Now read the exact device type from the EEPROM to find
889 * out if it's an 8129 or 8139.
890 */
891 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
892
893 t = rl_devs;
894 sc->rl_type = 0;
895 while(t->rl_name != NULL) {
896 if (rl_did == t->rl_did) {
897 sc->rl_type = t->rl_basetype;
898 break;
899 }
900 t++;
901 }
902
903 if (sc->rl_type == 0) {
904 device_printf(dev, "unknown device ID: %x\n", rl_did);
905 error = ENXIO;
906 goto fail;
907 }
908
909 if ((error = rl_dma_alloc(sc)) != 0)
910 goto fail;
911
912 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
913 if (ifp == NULL) {
914 device_printf(dev, "can not if_alloc()\n");
915 error = ENOSPC;
916 goto fail;
917 }
918
919 /* Do MII setup */
920 if (mii_phy_probe(dev, &sc->rl_miibus,
921 rl_ifmedia_upd, rl_ifmedia_sts)) {
922 device_printf(dev, "MII without any phy!\n");
923 error = ENXIO;
924 goto fail;
925 }
926
927 ifp->if_softc = sc;
928 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
929 ifp->if_mtu = ETHERMTU;
930 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
931 ifp->if_ioctl = rl_ioctl;
932 ifp->if_start = rl_start;
933 ifp->if_init = rl_init;
934 ifp->if_capabilities = IFCAP_VLAN_MTU;
935 ifp->if_capenable = ifp->if_capabilities;
936 #ifdef DEVICE_POLLING
937 ifp->if_capabilities |= IFCAP_POLLING;
938 #endif
939 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
940 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
941 IFQ_SET_READY(&ifp->if_snd);
942
943 /*
944 * Call MI attach routine.
945 */
946 ether_ifattach(ifp, eaddr);
947
948 /* Hook interrupt last to avoid having to lock softc */
949 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
950 NULL, rl_intr, sc, &sc->rl_intrhand[0]);
951 if (error) {
952 device_printf(sc->rl_dev, "couldn't set up irq\n");
953 ether_ifdetach(ifp);
954 }
955
956 fail:
957 if (error)
958 rl_detach(dev);
959
960 return (error);
961 }
962
963 /*
964 * Shutdown hardware and free up resources. This can be called any
965 * time after the mutex has been initialized. It is called in both
966 * the error case in attach and the normal detach case so it needs
967 * to be careful about only freeing resources that have actually been
968 * allocated.
969 */
970 static int
971 rl_detach(device_t dev)
972 {
973 struct rl_softc *sc;
974 struct ifnet *ifp;
975
976 sc = device_get_softc(dev);
977 ifp = sc->rl_ifp;
978
979 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
980
981 #ifdef DEVICE_POLLING
982 if (ifp->if_capenable & IFCAP_POLLING)
983 ether_poll_deregister(ifp);
984 #endif
985 /* These should only be active if attach succeeded */
986 if (device_is_attached(dev)) {
987 RL_LOCK(sc);
988 rl_stop(sc);
989 RL_UNLOCK(sc);
990 callout_drain(&sc->rl_stat_callout);
991 ether_ifdetach(ifp);
992 }
993 #if 0
994 sc->suspended = 1;
995 #endif
996 if (sc->rl_miibus)
997 device_delete_child(dev, sc->rl_miibus);
998 bus_generic_detach(dev);
999
1000 if (sc->rl_intrhand[0])
1001 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1002 if (sc->rl_irq[0])
1003 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
1004 if (sc->rl_res)
1005 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1006
1007 if (ifp)
1008 if_free(ifp);
1009
1010 rl_dma_free(sc);
1011
1012 mtx_destroy(&sc->rl_mtx);
1013
1014 return (0);
1015 }
1016
1017 static int
1018 rl_dma_alloc(struct rl_softc *sc)
1019 {
1020 struct rl_dmamap_arg ctx;
1021 int error, i;
1022
1023 /*
1024 * Allocate the parent bus DMA tag appropriate for PCI.
1025 */
1026 error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */
1027 1, 0, /* alignment, boundary */
1028 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1029 BUS_SPACE_MAXADDR, /* highaddr */
1030 NULL, NULL, /* filter, filterarg */
1031 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */
1032 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1033 0, /* flags */
1034 NULL, NULL, /* lockfunc, lockarg */
1035 &sc->rl_parent_tag);
1036 if (error) {
1037 device_printf(sc->rl_dev,
1038 "failed to create parent DMA tag.\n");
1039 goto fail;
1040 }
1041 /* Create DMA tag for Rx memory block. */
1042 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
1043 RL_RX_8139_BUF_ALIGN, 0, /* alignment, boundary */
1044 BUS_SPACE_MAXADDR, /* lowaddr */
1045 BUS_SPACE_MAXADDR, /* highaddr */
1046 NULL, NULL, /* filter, filterarg */
1047 |