Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_rl.c
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1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86 #include "bpfilter.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 96 #include <net/if.h> 97 #include <net/if_arp.h> 98 #include <net/ethernet.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 102 #if NBPFILTER > 0 103 #include <net/bpf.h> 104 #endif 105 106 #include "opt_bdg.h" 107 #ifdef BRIDGE 108 #include <net/if_types.h> 109 #include <net/bridge.h> 110 #endif 111 112 #include <vm/vm.h> /* for vtophys */ 113 #include <vm/pmap.h> /* for vtophys */ 114 #include <machine/clock.h> /* for DELAY */ 115 #include <machine/bus_pio.h> 116 #include <machine/bus_memio.h> 117 #include <machine/bus.h> 118 119 #include <pci/pcireg.h> 120 #include <pci/pcivar.h> 121 122 /* 123 * Default to using PIO access for this driver. On SMP systems, 124 * there appear to be problems with memory mapped mode: it looks like 125 * doing too many memory mapped access back to back in rapid succession 126 * can hang the bus. I'm inclined to blame this on crummy design/construction 127 * on the part of RealTek. Memory mapped mode does appear to work on 128 * uniprocessor systems though. 129 */ 130 #define RL_USEIOSPACE 131 132 #include <pci/if_rlreg.h> 133 134 #ifndef lint 135 static const char rcsid[] = 136 "$FreeBSD$"; 137 #endif 138 139 /* 140 * Various supported device vendors/types and their names. 141 */ 142 static struct rl_type rl_devs[] = { 143 { RT_VENDORID, RT_DEVICEID_8129, 144 "RealTek 8129 10/100BaseTX" }, 145 { RT_VENDORID, RT_DEVICEID_8139, 146 "RealTek 8139 10/100BaseTX" }, 147 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 148 "Accton MPX 5030/5038 10/100BaseTX" }, 149 { DELTA_VENDORID, DELTA_DEVICEID_8139, 150 "Delta Electronics 8139 10/100BaseTX" }, 151 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 152 "Addtron Technolgy 8139 10/100BaseTX" }, 153 { 0, 0, NULL } 154 }; 155 156 /* 157 * Various supported PHY vendors/types and their names. Note that 158 * this driver will work with pretty much any MII-compliant PHY, 159 * so failure to positively identify the chip is not a fatal error. 160 */ 161 162 static struct rl_type rl_phys[] = { 163 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" }, 164 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" }, 165 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"}, 166 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 167 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" }, 168 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" }, 169 { 0, 0, "<MII-compliant physical interface>" } 170 }; 171 172 static unsigned long rl_count = 0; 173 static const char *rl_probe __P((pcici_t, pcidi_t)); 174 static void rl_attach __P((pcici_t, int)); 175 176 static int rl_encap __P((struct rl_softc *, struct mbuf * )); 177 178 static void rl_rxeof __P((struct rl_softc *)); 179 static void rl_txeof __P((struct rl_softc *)); 180 static void rl_intr __P((void *)); 181 static void rl_start __P((struct ifnet *)); 182 static int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 183 static void rl_init __P((void *)); 184 static void rl_stop __P((struct rl_softc *)); 185 static void rl_watchdog __P((struct ifnet *)); 186 static void rl_shutdown __P((int, void *)); 187 static int rl_ifmedia_upd __P((struct ifnet *)); 188 static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 189 190 static void rl_eeprom_putbyte __P((struct rl_softc *, int)); 191 static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *)); 192 static void rl_read_eeprom __P((struct rl_softc *, caddr_t, 193 int, int, int)); 194 static void rl_mii_sync __P((struct rl_softc *)); 195 static void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 196 static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 197 static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 198 199 static u_int16_t rl_phy_readreg __P((struct rl_softc *, int)); 200 static void rl_phy_writereg __P((struct rl_softc *, int, int)); 201 202 static void rl_autoneg_xmit __P((struct rl_softc *)); 203 static void rl_autoneg_mii __P((struct rl_softc *, int, int)); 204 static void rl_setmode_mii __P((struct rl_softc *, int)); 205 static void rl_getmode_mii __P((struct rl_softc *)); 206 static u_int8_t rl_calchash __P((caddr_t)); 207 static void rl_setmulti __P((struct rl_softc *)); 208 static void rl_reset __P((struct rl_softc *)); 209 static int rl_list_tx_init __P((struct rl_softc *)); 210 211 #define EE_SET(x) \ 212 CSR_WRITE_1(sc, RL_EECMD, \ 213 CSR_READ_1(sc, RL_EECMD) | x) 214 215 #define EE_CLR(x) \ 216 CSR_WRITE_1(sc, RL_EECMD, \ 217 CSR_READ_1(sc, RL_EECMD) & ~x) 218 219 /* 220 * Send a read command and address to the EEPROM, check for ACK. 221 */ 222 static void rl_eeprom_putbyte(sc, addr) 223 struct rl_softc *sc; 224 int addr; 225 { 226 register int d, i; 227 228 d = addr | RL_EECMD_READ; 229 230 /* 231 * Feed in each bit and stobe the clock. 232 */ 233 for (i = 0x400; i; i >>= 1) { 234 if (d & i) { 235 EE_SET(RL_EE_DATAIN); 236 } else { 237 EE_CLR(RL_EE_DATAIN); 238 } 239 DELAY(100); 240 EE_SET(RL_EE_CLK); 241 DELAY(150); 242 EE_CLR(RL_EE_CLK); 243 DELAY(100); 244 } 245 246 return; 247 } 248 249 /* 250 * Read a word of data stored in the EEPROM at address 'addr.' 251 */ 252 static void rl_eeprom_getword(sc, addr, dest) 253 struct rl_softc *sc; 254 int addr; 255 u_int16_t *dest; 256 { 257 register int i; 258 u_int16_t word = 0; 259 260 /* Enter EEPROM access mode. */ 261 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 262 263 /* 264 * Send address of word we want to read. 265 */ 266 rl_eeprom_putbyte(sc, addr); 267 268 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 269 270 /* 271 * Start reading bits from EEPROM. 272 */ 273 for (i = 0x8000; i; i >>= 1) { 274 EE_SET(RL_EE_CLK); 275 DELAY(100); 276 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 277 word |= i; 278 EE_CLR(RL_EE_CLK); 279 DELAY(100); 280 } 281 282 /* Turn off EEPROM access mode. */ 283 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 284 285 *dest = word; 286 287 return; 288 } 289 290 /* 291 * Read a sequence of words from the EEPROM. 292 */ 293 static void rl_read_eeprom(sc, dest, off, cnt, swap) 294 struct rl_softc *sc; 295 caddr_t dest; 296 int off; 297 int cnt; 298 int swap; 299 { 300 int i; 301 u_int16_t word = 0, *ptr; 302 303 for (i = 0; i < cnt; i++) { 304 rl_eeprom_getword(sc, off + i, &word); 305 ptr = (u_int16_t *)(dest + (i * 2)); 306 if (swap) 307 *ptr = ntohs(word); 308 else 309 *ptr = word; 310 } 311 312 return; 313 } 314 315 316 /* 317 * MII access routines are provided for the 8129, which 318 * doesn't have a built-in PHY. For the 8139, we fake things 319 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 320 * direct access PHY registers. 321 */ 322 #define MII_SET(x) \ 323 CSR_WRITE_1(sc, RL_MII, \ 324 CSR_READ_1(sc, RL_MII) | x) 325 326 #define MII_CLR(x) \ 327 CSR_WRITE_1(sc, RL_MII, \ 328 CSR_READ_1(sc, RL_MII) & ~x) 329 330 /* 331 * Sync the PHYs by setting data bit and strobing the clock 32 times. 332 */ 333 static void rl_mii_sync(sc) 334 struct rl_softc *sc; 335 { 336 register int i; 337 338 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 339 340 for (i = 0; i < 32; i++) { 341 MII_SET(RL_MII_CLK); 342 DELAY(1); 343 MII_CLR(RL_MII_CLK); 344 DELAY(1); 345 } 346 347 return; 348 } 349 350 /* 351 * Clock a series of bits through the MII. 352 */ 353 static void rl_mii_send(sc, bits, cnt) 354 struct rl_softc *sc; 355 u_int32_t bits; 356 int cnt; 357 { 358 int i; 359 360 MII_CLR(RL_MII_CLK); 361 362 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 363 if (bits & i) { 364 MII_SET(RL_MII_DATAOUT); 365 } else { 366 MII_CLR(RL_MII_DATAOUT); 367 } 368 DELAY(1); 369 MII_CLR(RL_MII_CLK); 370 DELAY(1); 371 MII_SET(RL_MII_CLK); 372 } 373 } 374 375 /* 376 * Read an PHY register through the MII. 377 */ 378 static int rl_mii_readreg(sc, frame) 379 struct rl_softc *sc; 380 struct rl_mii_frame *frame; 381 382 { 383 int i, ack, s; 384 385 s = splimp(); 386 387 /* 388 * Set up frame for RX. 389 */ 390 frame->mii_stdelim = RL_MII_STARTDELIM; 391 frame->mii_opcode = RL_MII_READOP; 392 frame->mii_turnaround = 0; 393 frame->mii_data = 0; 394 395 CSR_WRITE_2(sc, RL_MII, 0); 396 397 /* 398 * Turn on data xmit. 399 */ 400 MII_SET(RL_MII_DIR); 401 402 rl_mii_sync(sc); 403 404 /* 405 * Send command/address info. 406 */ 407 rl_mii_send(sc, frame->mii_stdelim, 2); 408 rl_mii_send(sc, frame->mii_opcode, 2); 409 rl_mii_send(sc, frame->mii_phyaddr, 5); 410 rl_mii_send(sc, frame->mii_regaddr, 5); 411 412 /* Idle bit */ 413 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 414 DELAY(1); 415 MII_SET(RL_MII_CLK); 416 DELAY(1); 417 418 /* Turn off xmit. */ 419 MII_CLR(RL_MII_DIR); 420 421 /* Check for ack */ 422 MII_CLR(RL_MII_CLK); 423 DELAY(1); 424 MII_SET(RL_MII_CLK); 425 DELAY(1); 426 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 427 428 /* 429 * Now try reading data bits. If the ack failed, we still 430 * need to clock through 16 cycles to keep the PHY(s) in sync. 431 */ 432 if (ack) { 433 for(i = 0; i < 16; i++) { 434 MII_CLR(RL_MII_CLK); 435 DELAY(1); 436 MII_SET(RL_MII_CLK); 437 DELAY(1); 438 } 439 goto fail; 440 } 441 442 for (i = 0x8000; i; i >>= 1) { 443 MII_CLR(RL_MII_CLK); 444 DELAY(1); 445 if (!ack) { 446 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 447 frame->mii_data |= i; 448 DELAY(1); 449 } 450 MII_SET(RL_MII_CLK); 451 DELAY(1); 452 } 453 454 fail: 455 456 MII_CLR(RL_MII_CLK); 457 DELAY(1); 458 MII_SET(RL_MII_CLK); 459 DELAY(1); 460 461 splx(s); 462 463 if (ack) 464 return(1); 465 return(0); 466 } 467 468 /* 469 * Write to a PHY register through the MII. 470 */ 471 static int rl_mii_writereg(sc, frame) 472 struct rl_softc *sc; 473 struct rl_mii_frame *frame; 474 475 { 476 int s; 477 478 s = splimp(); 479 /* 480 * Set up frame for TX. 481 */ 482 483 frame->mii_stdelim = RL_MII_STARTDELIM; 484 frame->mii_opcode = RL_MII_WRITEOP; 485 frame->mii_turnaround = RL_MII_TURNAROUND; 486 487 /* 488 * Turn on data output. 489 */ 490 MII_SET(RL_MII_DIR); 491 492 rl_mii_sync(sc); 493 494 rl_mii_send(sc, frame->mii_stdelim, 2); 495 rl_mii_send(sc, frame->mii_opcode, 2); 496 rl_mii_send(sc, frame->mii_phyaddr, 5); 497 rl_mii_send(sc, frame->mii_regaddr, 5); 498 rl_mii_send(sc, frame->mii_turnaround, 2); 499 rl_mii_send(sc, frame->mii_data, 16); 500 501 /* Idle bit. */ 502 MII_SET(RL_MII_CLK); 503 DELAY(1); 504 MII_CLR(RL_MII_CLK); 505 DELAY(1); 506 507 /* 508 * Turn off xmit. 509 */ 510 MII_CLR(RL_MII_DIR); 511 512 splx(s); 513 514 return(0); 515 } 516 517 static u_int16_t rl_phy_readreg(sc, reg) 518 struct rl_softc *sc; 519 int reg; 520 { 521 struct rl_mii_frame frame; 522 u_int16_t rval = 0; 523 u_int16_t rl8139_reg = 0; 524 525 if (sc->rl_type == RL_8139) { 526 switch(reg) { 527 case PHY_BMCR: 528 rl8139_reg = RL_BMCR; 529 break; 530 case PHY_BMSR: 531 rl8139_reg = RL_BMSR; 532 break; 533 case PHY_ANAR: 534 rl8139_reg = RL_ANAR; 535 break; 536 case PHY_LPAR: 537 rl8139_reg = RL_LPAR; 538 break; 539 default: 540 printf("rl%d: bad phy register\n", sc->rl_unit); 541 return(0); 542 } 543 rval = CSR_READ_2(sc, rl8139_reg); 544 return(rval); 545 } 546 547 bzero((char *)&frame, sizeof(frame)); 548 549 frame.mii_phyaddr = sc->rl_phy_addr; 550 frame.mii_regaddr = reg; 551 rl_mii_readreg(sc, &frame); 552 553 return(frame.mii_data); 554 } 555 556 static void rl_phy_writereg(sc, reg, data) 557 struct rl_softc *sc; 558 int reg; 559 int data; 560 { 561 struct rl_mii_frame frame; 562 u_int16_t rl8139_reg = 0; 563 564 if (sc->rl_type == RL_8139) { 565 switch(reg) { 566 case PHY_BMCR: 567 rl8139_reg = RL_BMCR; 568 break; 569 case PHY_BMSR: 570 rl8139_reg = RL_BMSR; 571 break; 572 case PHY_ANAR: 573 rl8139_reg = RL_ANAR; 574 break; 575 case PHY_LPAR: 576 rl8139_reg = RL_LPAR; 577 break; 578 default: 579 printf("rl%d: bad phy register\n", sc->rl_unit); 580 return; 581 } 582 CSR_WRITE_2(sc, rl8139_reg, data); 583 return; 584 } 585 586 bzero((char *)&frame, sizeof(frame)); 587 588 frame.mii_phyaddr = sc->rl_phy_addr; 589 frame.mii_regaddr = reg; 590 frame.mii_data = data; 591 592 rl_mii_writereg(sc, &frame); 593 594 return; 595 } 596 597 /* 598 * Calculate CRC of a multicast group address, return the upper 6 bits. 599 */ 600 static u_int8_t rl_calchash(addr) 601 caddr_t addr; 602 { 603 u_int32_t crc, carry; 604 int i, j; 605 u_int8_t c; 606 607 /* Compute CRC for the address value. */ 608 crc = 0xFFFFFFFF; /* initial value */ 609 610 for (i = 0; i < 6; i++) { 611 c = *(addr + i); 612 for (j = 0; j < 8; j++) { 613 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 614 crc <<= 1; 615 c >>= 1; 616 if (carry) 617 crc = (crc ^ 0x04c11db6) | carry; 618 } 619 } 620 621 /* return the filter bit position */ 622 return(crc >> 26); 623 } 624 625 /* 626 * Program the 64-bit multicast hash filter. 627 */ 628 static void rl_setmulti(sc) 629 struct rl_softc *sc; 630 { 631 struct ifnet *ifp; 632 int h = 0; 633 u_int32_t hashes[2] = { 0, 0 }; 634 struct ifmultiaddr *ifma; 635 u_int32_t rxfilt; 636 int mcnt = 0; 637 638 ifp = &sc->arpcom.ac_if; 639 640 rxfilt = CSR_READ_4(sc, RL_RXCFG); 641 642 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 643 rxfilt |= RL_RXCFG_RX_MULTI; 644 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 645 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 646 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 647 return; 648 } 649 650 /* first, zot all the existing hash bits */ 651 CSR_WRITE_4(sc, RL_MAR0, 0); 652 CSR_WRITE_4(sc, RL_MAR4, 0); 653 654 /* now program new ones */ 655 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 656 ifma = ifma->ifma_link.le_next) { 657 if (ifma->ifma_addr->sa_family != AF_LINK) 658 continue; 659 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 660 if (h < 32) 661 hashes[0] |= (1 << h); 662 else 663 hashes[1] |= (1 << (h - 32)); 664 mcnt++; 665 } 666 667 if (mcnt) 668 rxfilt |= RL_RXCFG_RX_MULTI; 669 else 670 rxfilt &= ~RL_RXCFG_RX_MULTI; 671 672 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 673 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 674 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 675 676 return; 677 } 678 679 /* 680 * Initiate an autonegotiation session. 681 */ 682 static void rl_autoneg_xmit(sc) 683 struct rl_softc *sc; 684 { 685 u_int16_t phy_sts; 686 687 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 688 DELAY(500); 689 while(rl_phy_readreg(sc, PHY_BMCR) 690 & PHY_BMCR_RESET); 691 692 phy_sts = rl_phy_readreg(sc, PHY_BMCR); 693 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 694 rl_phy_writereg(sc, PHY_BMCR, phy_sts); 695 696 return; 697 } 698 699 /* 700 * Invoke autonegotiation on a PHY. Also used with the 8139 internal 701 * transceiver. 702 */ 703 static void rl_autoneg_mii(sc, flag, verbose) 704 struct rl_softc *sc; 705 int flag; 706 int verbose; 707 { 708 u_int16_t phy_sts = 0, media, advert, ability; 709 struct ifnet *ifp; 710 struct ifmedia *ifm; 711 712 ifm = &sc->ifmedia; 713 ifp = &sc->arpcom.ac_if; 714 715 /* 716 * The 100baseT4 PHY sometimes has the 'autoneg supported' 717 * bit cleared in the status register, but has the 'autoneg enabled' 718 * bit set in the control register. This is a contradiction, and 719 * I'm not sure how to handle it. If you want to force an attempt 720 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR 721 * and see what happens. 722 */ 723 #ifndef FORCE_AUTONEG_TFOUR 724 /* 725 * First, see if autoneg is supported. If not, there's 726 * no point in continuing. 727 */ 728 phy_sts = rl_phy_readreg(sc, PHY_BMSR); 729 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 730 if (verbose) 731 printf("rl%d: autonegotiation not supported\n", 732 sc->rl_unit); 733 return; 734 } 735 #endif 736 737 switch (flag) { 738 case RL_FLAG_FORCEDELAY: 739 /* 740 * XXX Never use this option anywhere but in the probe 741 * routine: making the kernel stop dead in its tracks 742 * for three whole seconds after we've gone multi-user 743 * is really bad manners. 744 */ 745 rl_autoneg_xmit(sc); 746 DELAY(5000000); 747 break; 748 case RL_FLAG_SCHEDDELAY: 749 /* 750 * Wait for the transmitter to go idle before starting 751 * an autoneg session, otherwise rl_start() may clobber 752 * our timeout, and we don't want to allow transmission 753 * during an autoneg session since that can screw it up. 754 */ 755 if (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx) { 756 sc->rl_want_auto = 1; 757 return; 758 } 759 rl_autoneg_xmit(sc); 760 ifp->if_timer = 5; 761 sc->rl_autoneg = 1; 762 sc->rl_want_auto = 0; 763 return; 764 break; 765 case RL_FLAG_DELAYTIMEO: 766 ifp->if_timer = 0; 767 sc->rl_autoneg = 0; 768 break; 769 default: 770 printf("rl%d: invalid autoneg flag: %d\n", sc->rl_unit, flag); 771 return; 772 } 773 774 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 775 if (verbose) 776 printf("rl%d: autoneg complete, ", sc->rl_unit); 777 phy_sts = rl_phy_readreg(sc, PHY_BMSR); 778 } else { 779 if (verbose) 780 printf("rl%d: autoneg not complete, ", sc->rl_unit); 781 } 782 783 media = rl_phy_readreg(sc, PHY_BMCR); 784 785 /* Link is good. Report modes and set duplex mode. */ 786 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 787 if (verbose) 788 printf("link status good "); 789 advert = rl_phy_readreg(sc, PHY_ANAR); 790 ability = rl_phy_readreg(sc, PHY_LPAR); 791 792 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 793 ifm->ifm_media = IFM_ETHER|IFM_100_T4; 794 media |= PHY_BMCR_SPEEDSEL; 795 media &= ~PHY_BMCR_DUPLEX; 796 printf("(100baseT4)\n"); 797 } else if (advert & PHY_ANAR_100BTXFULL && 798 ability & PHY_ANAR_100BTXFULL) { 799 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 800 media |= PHY_BMCR_SPEEDSEL; 801 media |= PHY_BMCR_DUPLEX; 802 printf("(full-duplex, 100Mbps)\n"); 803 } else if (advert & PHY_ANAR_100BTXHALF && 804 ability & PHY_ANAR_100BTXHALF) { 805 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 806 media |= PHY_BMCR_SPEEDSEL; 807 media &= ~PHY_BMCR_DUPLEX; 808 printf("(half-duplex, 100Mbps)\n"); 809 } else if (advert & PHY_ANAR_10BTFULL && 810 ability & PHY_ANAR_10BTFULL) { 811 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 812 media &= ~PHY_BMCR_SPEEDSEL; 813 media |= PHY_BMCR_DUPLEX; 814 printf("(full-duplex, 10Mbps)\n"); 815 } else { 816 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 817 media &= ~PHY_BMCR_SPEEDSEL; 818 media &= ~PHY_BMCR_DUPLEX; 819 printf("(half-duplex, 10Mbps)\n"); 820 } 821 822 /* Set ASIC's duplex mode to match the PHY. */ 823 rl_phy_writereg(sc, PHY_BMCR, media); 824 } else { 825 if (verbose) 826 printf("no carrier\n"); 827 } 828 829 rl_init(sc); 830 831 if (sc->rl_tx_pend) { 832 sc->rl_autoneg = 0; 833 sc->rl_tx_pend = 0; 834 rl_start(ifp); 835 } 836 837 return; 838 } 839 840 static void rl_getmode_mii(sc) 841 struct rl_softc *sc; 842 { 843 u_int16_t bmsr; 844 struct ifnet *ifp; 845 846 ifp = &sc->arpcom.ac_if; 847 848 bmsr = rl_phy_readreg(sc, PHY_BMSR); 849 if (bootverbose) 850 printf("rl%d: PHY status word: %x\n", sc->rl_unit, bmsr); 851 852 /* fallback */ 853 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 854 855 if (bmsr & PHY_BMSR_10BTHALF) { 856 if (bootverbose) 857 printf("rl%d: 10Mbps half-duplex mode supported\n", 858 sc->rl_unit); 859 ifmedia_add(&sc->ifmedia, 860 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 861 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 862 } 863 864 if (bmsr & PHY_BMSR_10BTFULL) { 865 if (bootverbose) 866 printf("rl%d: 10Mbps full-duplex mode supported\n", 867 sc->rl_unit); 868 ifmedia_add(&sc->ifmedia, 869 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 870 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 871 } 872 873 if (bmsr & PHY_BMSR_100BTXHALF) { 874 if (bootverbose) 875 printf("rl%d: 100Mbps half-duplex mode supported\n", 876 sc->rl_unit); 877 ifp->if_baudrate = 100000000; 878 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 879 ifmedia_add(&sc->ifmedia, 880 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 881 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 882 } 883 884 if (bmsr & PHY_BMSR_100BTXFULL) { 885 if (bootverbose) 886 printf("rl%d: 100Mbps full-duplex mode supported\n", 887 sc->rl_unit); 888 ifp->if_baudrate = 100000000; 889 ifmedia_add(&sc->ifmedia, 890 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 891 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 892 } 893 894 /* Some also support 100BaseT4. */ 895 if (bmsr & PHY_BMSR_100BT4) { 896 if (bootverbose) 897 printf("rl%d: 100baseT4 mode supported\n", sc->rl_unit); 898 ifp->if_baudrate = 100000000; 899 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); 900 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4; 901 #ifdef FORCE_AUTONEG_TFOUR 902 if (bootverbose) 903 printf("rl%d: forcing on autoneg support for BT4\n", 904 sc->rl_unit); 905 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL): 906 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 907 #endif 908 } 909 910 if (bmsr & PHY_BMSR_CANAUTONEG) { 911 if (bootverbose) 912 printf("rl%d: autoneg supported\n", sc->rl_unit); 913 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 914 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 915 } 916 917 return; 918 } 919 920 /* 921 * Set speed and duplex mode. 922 */ 923 static void rl_setmode_mii(sc, media) 924 struct rl_softc *sc; 925 int media; 926 { 927 u_int16_t bmcr; 928 929 printf("rl%d: selecting MII, ", sc->rl_unit); 930 931 bmcr = rl_phy_readreg(sc, PHY_BMCR); 932 933 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL| 934 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK); 935 936 if (IFM_SUBTYPE(media) == IFM_100_T4) { 937 printf("100Mbps/T4, half-duplex\n"); 938 bmcr |= PHY_BMCR_SPEEDSEL; 939 bmcr &= ~PHY_BMCR_DUPLEX; 940 } 941 942 if (IFM_SUBTYPE(media) == IFM_100_TX) { 943 printf("100Mbps, "); 944 bmcr |= PHY_BMCR_SPEEDSEL; 945 } 946 947 if (IFM_SUBTYPE(media) == IFM_10_T) { 948 printf("10Mbps, "); 949 bmcr &= ~PHY_BMCR_SPEEDSEL; 950 } 951 952 if ((media & IFM_GMASK) == IFM_FDX) { 953 printf("full duplex\n"); 954 bmcr |= PHY_BMCR_DUPLEX; 955 } else { 956 printf("half duplex\n"); 957 bmcr &= ~PHY_BMCR_DUPLEX; 958 } 959 960 rl_phy_writereg(sc, PHY_BMCR, bmcr); 961 962 return; 963 } 964 965 static void rl_reset(sc) 966 struct rl_softc *sc; 967 { 968 register int i; 969 970 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 971 972 for (i = 0; i < RL_TIMEOUT; i++) { 973 DELAY(10); 974 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 975 break; 976 } 977 if (i == RL_TIMEOUT) 978 printf("rl%d: reset never completed!\n", sc->rl_unit); 979 980 return; 981 } 982 983 /* 984 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 985 * IDs against our list and return a device name if we find a match. 986 */ 987 static const char * 988 rl_probe(config_id, device_id) 989 pcici_t config_id; 990 pcidi_t device_id; 991 { 992 struct rl_type *t; 993 994 t = rl_devs; 995 996 while(t->rl_name != NULL) { 997 if ((device_id & 0xFFFF) == t->rl_vid && 998 ((device_id >> 16) & 0xFFFF) == t->rl_did) { 999 return(t->rl_name); 1000 } 1001 t++; 1002 } 1003 1004 return(NULL); 1005 } 1006 1007 /* 1008 * Attach the interface. Allocate softc structures, do ifmedia 1009 * setup and ethernet/BPF attach. 1010 */ 1011 static void 1012 rl_attach(config_id, unit) 1013 pcici_t config_id; 1014 int unit; 1015 { 1016 int s, i; 1017 #ifndef RL_USEIOSPACE 1018 vm_offset_t pbase, vbase; 1019 #endif 1020 u_char eaddr[ETHER_ADDR_LEN]; 1021 u_int32_t command; 1022 struct rl_softc *sc; 1023 struct ifnet *ifp; 1024 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1025 struct rl_type *p; 1026 u_int16_t phy_vid, phy_did, phy_sts; 1027 u_int16_t rl_did = 0; 1028 1029 s = splimp(); 1030 1031 sc = malloc(sizeof(struct rl_softc), M_DEVBUF, M_NOWAIT); 1032 if (sc == NULL) { 1033 printf("rl%d: no memory for softc struct!\n", unit); 1034 goto fail; 1035 } 1036 bzero(sc, sizeof(struct rl_softc)); 1037 1038 /* 1039 * Handle power management nonsense. 1040 */ 1041 1042 command = pci_conf_read(config_id, RL_PCI_CAPID) & 0x000000FF; 1043 if (command == 0x01) { 1044 1045 command = pci_conf_read(config_id, RL_PCI_PWRMGMTCTRL); 1046 if (command & RL_PSTATE_MASK) { 1047 u_int32_t iobase, membase, irq; 1048 1049 /* Save important PCI config data. */ 1050 iobase = pci_conf_read(config_id, RL_PCI_LOIO); 1051 membase = pci_conf_read(config_id, RL_PCI_LOMEM); 1052 irq = pci_conf_read(config_id, RL_PCI_INTLINE); 1053 1054 /* Reset the power state. */ 1055 printf("rl%d: chip is is in D%d power mode " 1056 "-- setting to D0\n", unit, command & RL_PSTATE_MASK); 1057 command &= 0xFFFFFFFC; 1058 pci_conf_write(config_id, RL_PCI_PWRMGMTCTRL, command); 1059 1060 /* Restore PCI config data. */ 1061 pci_conf_write(config_id, RL_PCI_LOIO, iobase); 1062 pci_conf_write(config_id, RL_PCI_LOMEM, membase); 1063 pci_conf_write(config_id, RL_PCI_INTLINE, irq); 1064 } 1065 } 1066 1067 /* 1068 * Map control/status registers. 1069 */ 1070 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1071 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1072 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); 1073 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1074 1075 #ifdef RL_USEIOSPACE 1076 if (!(command & PCIM_CMD_PORTEN)) { 1077 printf("rl%d: failed to enable I/O ports!\n", unit); 1078 free(sc, M_DEVBUF); 1079 goto fail; 1080 } 1081 1082 if (!pci_map_port(config_id, RL_PCI_LOIO, 1083 (u_int16_t *)&(sc->rl_bhandle))) { 1084 printf ("rl%d: couldn't map ports\n", unit); 1085 goto fail; 1086 } 1087 #ifdef __i386__ 1088 sc->rl_btag = I386_BUS_SPACE_IO; 1089 #endif 1090 #ifdef __alpha__ 1091 sc->rl_btag = ALPHA_BUS_SPACE_IO; 1092 #endif 1093 #else 1094 if (!(command & PCIM_CMD_MEMEN)) { 1095 printf("rl%d: failed to enable memory mapping!\n", unit); 1096 goto fail; 1097 } 1098 1099 if (!pci_map_mem(config_id, RL_PCI_LOMEM, &vbase, &pbase)) { 1100 printf ("rl%d: couldn't map memory\n", unit); 1101 goto fail; 1102 } 1103 #ifdef __i386__ 1104 sc->rl_btag = I386_BUS_SPACE_MEM; 1105 #endif 1106 #ifdef __alpha__ 1107 sc->rl_btag = ALPHA_BUS_SPACE_MEM; 1108 #endif 1109 sc->rl_bhandle = vbase; 1110 #endif 1111 1112 /* Allocate interrupt */ 1113 if (!pci_map_int(config_id, rl_intr, sc, &net_imask)) { 1114 printf("rl%d: couldn't map interrupt\n", unit); 1115 goto fail; 1116 } 1117 1118 /* Reset the adapter. */ 1119 rl_reset(sc); 1120 1121 /* 1122 * Get station address from the EEPROM. 1123 */ 1124 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 1125 1126 /* 1127 * A RealTek chip was detected. Inform the world. 1128 */ 1129 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1130 1131 sc->rl_unit = unit; 1132 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1133 1134 /* 1135 * Now read the exact device type from the EEPROM to find 1136 * out if it's an 8129 or 8139. 1137 */ 1138 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 1139 1140 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 1141 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139) 1142 sc->rl_type = RL_8139; 1143 else if (rl_did == RT_DEVICEID_8129) 1144 sc->rl_type = RL_8129; 1145 else { 1146 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 1147 free(sc, M_DEVBUF); 1148 goto fail; 1149 } 1150 1151 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 32, M_DEVBUF, 1152 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 1153 1154 if (sc->rl_cdata.rl_rx_buf == NULL) { 1155 free(sc, M_DEVBUF); 1156 printf("rl%d: no memory for list buffers!\n", unit); 1157 goto fail; 1158 } 1159 1160 /* Leave a few bytes before the start of the RX ring buffer. */ 1161 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1162 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1163 1164 ifp = &sc->arpcom.ac_if; 1165 ifp->if_softc = sc; 1166 ifp->if_unit = unit; 1167 ifp->if_name = "rl"; 1168 ifp->if_mtu = ETHERMTU; 1169 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1170 ifp->if_ioctl = rl_ioctl; 1171 ifp->if_output = ether_output; 1172 ifp->if_start = rl_start; 1173 ifp->if_watchdog = rl_watchdog; 1174 ifp->if_init = rl_init; 1175 ifp->if_baudrate = 10000000; 1176 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1177 1178 if (sc->rl_type == RL_8129) { 1179 if (bootverbose) 1180 printf("rl%d: probing for a PHY\n", sc->rl_unit); 1181 for (i = RL_PHYADDR_MIN; i < RL_PHYADDR_MAX + 1; i++) { 1182 if (bootverbose) 1183 printf("rl%d: checking address: %d\n", 1184 sc->rl_unit, i); 1185 sc->rl_phy_addr = i; 1186 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 1187 DELAY(500); 1188 while(rl_phy_readreg(sc, PHY_BMCR) 1189 & PHY_BMCR_RESET); 1190 if ((phy_sts = rl_phy_readreg(sc, PHY_BMSR))) 1191 break; 1192 } 1193 if (phy_sts) { 1194 phy_vid = rl_phy_readreg(sc, PHY_VENID); 1195 phy_did = rl_phy_readreg(sc, PHY_DEVID); 1196 if (bootverbose) 1197 printf("rl%d: found PHY at address %d, ", 1198 sc->rl_unit, sc->rl_phy_addr); 1199 if (bootverbose) 1200 printf("vendor id: %x device id: %x\n", 1201 phy_vid, phy_did); 1202 p = rl_phys; 1203 while(p->rl_vid) { 1204 if (phy_vid == p->rl_vid && 1205 (phy_did | 0x000F) == p->rl_did) { 1206 sc->rl_pinfo = p; 1207 break; 1208 } 1209 p++; 1210 } 1211 if (sc->rl_pinfo == NULL) 1212 sc->rl_pinfo = &rl_phys[PHY_UNKNOWN]; 1213 if (bootverbose) 1214 printf("rl%d: PHY type: %s\n", 1215 sc->rl_unit, sc->rl_pinfo->rl_name); 1216 } else { 1217 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1218 } 1219 } 1220 1221 /* 1222 * Do ifmedia setup. 1223 */ 1224 ifmedia_init(&sc->ifmedia, 0, rl_ifmedia_upd, rl_ifmedia_sts); 1225 1226 rl_getmode_mii(sc); 1227 1228 /* Choose a default media. */ 1229 media = IFM_ETHER|IFM_AUTO; 1230 ifmedia_set(&sc->ifmedia, media); 1231 1232 rl_autoneg_mii(sc, RL_FLAG_FORCEDELAY, 1); 1233 1234 /* 1235 * Call MI attach routines. 1236 */ 1237 if_attach(ifp); 1238 ether_ifattach(ifp); 1239 1240 #if NBPFILTER > 0 1241 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1242 #endif 1243 at_shutdown(rl_shutdown, sc, SHUTDOWN_POST_SYNC); 1244 1245 fail: 1246 splx(s); 1247 return; 1248 } 1249 1250 /* 1251 * Initialize the transmit descriptors. 1252 */ 1253 static int rl_list_tx_init(sc) 1254 struct rl_softc *sc; 1255 { 1256 struct rl_chain_data *cd; 1257 int i; 1258 1259 cd = &sc->rl_cdata; 1260 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1261 cd->rl_tx_chain[i] = NULL; 1262 CSR_WRITE_4(sc, 1263 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1264 } 1265 1266 sc->rl_cdata.cur_tx = 0; 1267 sc->rl_cdata.last_tx = 0; 1268 1269 return(0); 1270 } 1271 1272 /* 1273 * A frame has been uploaded: pass the resulting mbuf chain up to 1274 * the higher level protocols. 1275 * 1276 * You know there's something wrong with a PCI bus-master chip design 1277 * when you have to use m_devget(). 1278 * 1279 * The receive operation is badly documented in the datasheet, so I'll 1280 * attempt to document it here. The driver provides a buffer area and 1281 * places its base address in the RX buffer start address register. 1282 * The chip then begins copying frames into the RX buffer. Each frame 1283 * is preceeded by a 32-bit RX status word which specifies the length 1284 * of the frame and certain other status bits. Each frame (starting with 1285 * the status word) is also 32-bit aligned. The frame length is in the 1286 * first 16 bits of the status word; the lower 15 bits correspond with 1287 * the 'rx status register' mentioned in the datasheet. 1288 * 1289 * Note: to make the Alpha happy, the frame payload needs to be aligned 1290 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 1291 * the ring buffer starting at an address two bytes before the actual 1292 * data location. We can then shave off the first two bytes using m_adj(). 1293 * The reason we do this is because m_devget() doesn't let us specify an 1294 * offset into the mbuf storage space, so we have to artificially create 1295 * one. The ring is allocated in such a way that there are a few unused 1296 * bytes of space preceecing it so that it will be safe for us to do the 1297 * 2-byte backstep even if reading from the ring at offset 0. 1298 */ 1299 static void rl_rxeof(sc) 1300 struct rl_softc *sc; 1301 { 1302 struct ether_header *eh; 1303 struct mbuf *m; 1304 struct ifnet *ifp; 1305 int total_len = 0; 1306 u_int32_t rxstat; 1307 caddr_t rxbufpos; 1308 int wrap = 0; 1309 u_int16_t cur_rx; 1310 u_int16_t limit; 1311 u_int16_t rx_bytes = 0, max_bytes; 1312 1313 ifp = &sc->arpcom.ac_if; 1314 1315 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1316 1317 /* Do not try to read past this point. */ 1318 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1319 1320 if (limit < cur_rx) 1321 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1322 else 1323 max_bytes = limit - cur_rx; 1324 1325 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1326 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1327 rxstat = *(u_int32_t *)rxbufpos; 1328 1329 /* 1330 * Here's a totally undocumented fact for you. When the 1331 * RealTek chip is in the process of copying a packet into 1332 * RAM for you, the length will be 0xfff0. If you spot a 1333 * packet header with this value, you need to stop. The 1334 * datasheet makes absolutely no mention of this and 1335 * RealTek should be shot for this. 1336 */ 1337 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1338 break; 1339 1340 if (!(rxstat & RL_RXSTAT_RXOK)) { 1341 ifp->if_ierrors++; 1342 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT| 1343 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR| 1344 RL_RXSTAT_ALIGNERR)) { 1345 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB); 1346 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB| 1347 RL_CMD_RX_ENB); 1348 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1349 CSR_WRITE_4(sc, RL_RXADDR, 1350 vtophys(sc->rl_cdata.rl_rx_buf)); 1351 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1352 cur_rx = 0; 1353 } 1354 break; 1355 } 1356 1357 /* No errors; receive the packet. */ 1358 total_len = rxstat >> 16; 1359 rx_bytes += total_len + 4; 1360 1361 /* 1362 * XXX The RealTek chip includes the CRC with every 1363 * received frame, and there's no way to turn this 1364 * behavior off (at least, I can't find anything in 1365 * the manual that explains how to do it) so we have 1366 * to trim off the CRC manually. 1367 */ 1368 total_len -= ETHER_CRC_LEN; 1369 1370 /* 1371 * Avoid trying to read more bytes than we know 1372 * the chip has prepared for us. 1373 */ 1374 if (rx_bytes > max_bytes) 1375 break; 1376 1377 rxbufpos = sc->rl_cdata.rl_rx_buf + 1378 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1379 1380 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1381 rxbufpos = sc->rl_cdata.rl_rx_buf; 1382 1383 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1384 1385 if (total_len > wrap) { 1386 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1387 wrap + RL_ETHER_ALIGN, 0, ifp, NULL); 1388 if (m == NULL) { 1389 ifp->if_ierrors++; 1390 printf("rl%d: out of mbufs, tried to " 1391 "copy %d bytes\n", sc->rl_unit, wrap); 1392 } else { 1393 m_adj(m, RL_ETHER_ALIGN); 1394 m_copyback(m, wrap, total_len - wrap, 1395 sc->rl_cdata.rl_rx_buf); 1396 m = m_pullup(m, MHLEN - RL_ETHER_ALIGN); 1397 } 1398 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1399 } else { 1400 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1401 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1402 if (m == NULL) { 1403 ifp->if_ierrors++; 1404 printf("rl%d: out of mbufs, tried to " 1405 "copy %d bytes\n", sc->rl_unit, total_len); 1406 } else 1407 m_adj(m, RL_ETHER_ALIGN); 1408 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1409 } 1410 1411 /* 1412 * Round up to 32-bit boundary. 1413 */ 1414 cur_rx = (cur_rx + 3) & ~3; 1415 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1416 1417 if (m == NULL) 1418 continue; 1419 1420 eh = mtod(m, struct ether_header *); 1421 ifp->if_ipackets++; 1422 1423 #if NBPFILTER > 0 1424 /* 1425 * Handle BPF listeners. Let the BPF user see the packet, but 1426 * don't pass it up to the ether_input() layer unless it's 1427 * a broadcast packet, multicast packet, matches our ethernet 1428 * address or the interface is in promiscuous mode. 1429 */ 1430 if (ifp->if_bpf) 1431 bpf_mtap(ifp, m); 1432 #endif 1433 #ifdef BRIDGE 1434 if (do_bridge) { 1435 struct ifnet *bdg_ifp = bridge_in(m); 1436 if (bdg_ifp == BDG_DROP) 1437 goto dropit ; 1438 if (bdg_ifp != BDG_LOCAL) { 1439 bdg_forward(&m, bdg_ifp); 1440 if (m == NULL) 1441 goto dropit; 1442 eh = mtod(m, struct ether_header *); 1443 } 1444 if (bdg_ifp != BDG_LOCAL && 1445 bdg_ifp != BDG_BCAST && bdg_ifp != BDG_MCAST) 1446 goto dropit; 1447 /* ok, get it */ 1448 } else 1449 #endif 1450 if (ifp->if_flags & IFF_PROMISC && 1451 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1452 ETHER_ADDR_LEN) && 1453 (eh->ether_dhost[0] & 1) == 0)) { 1454 #ifdef BRIDGE 1455 dropit: 1456 if (m) 1457 #endif 1458 m_freem(m); 1459 continue; 1460 } 1461 /* Remove header from mbuf and pass it on. */ 1462 m_adj(m, sizeof(struct ether_header)); 1463 ether_input(ifp, eh, m); 1464 } 1465 1466 return; 1467 } 1468 1469 /* 1470 * A frame was downloaded to the chip. It's safe for us to clean up 1471 * the list buffers. 1472 */ 1473 static void rl_txeof(sc) 1474 struct rl_softc *sc; 1475 { 1476 struct ifnet *ifp; 1477 u_int32_t txstat; 1478 1479 ifp = &sc->arpcom.ac_if; 1480 1481 /* Clear the timeout timer. */ 1482 ifp->if_timer = 0; 1483 1484 /* 1485 * Go through our tx list and free mbufs for those 1486 * frames that have been uploaded. 1487 */ 1488 do { 1489 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1490 if (!(txstat & (RL_TXSTAT_TX_OK| 1491 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1492 break; 1493 1494 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1495 1496 if (RL_LAST_TXMBUF(sc) != NULL) { 1497 m_freem(RL_LAST_TXMBUF(sc)); 1498 RL_LAST_TXMBUF(sc) = NULL; 1499 } 1500 if (txstat & RL_TXSTAT_TX_OK) 1501 ifp->if_opackets++; 1502 else { 1503 int oldthresh; 1504 ifp->if_oerrors++; 1505 if ((txstat & RL_TXSTAT_TXABRT) || 1506 (txstat & RL_TXSTAT_OUTOFWIN)) 1507 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1508 oldthresh = sc->rl_txthresh; 1509 /* error recovery */ 1510 rl_reset(sc); 1511 rl_init(sc); 1512 /* 1513 * If there was a transmit underrun, 1514 * bump the TX threshold. 1515 */ 1516 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1517 sc->rl_txthresh = oldthresh + 32; 1518 return; 1519 } 1520 RL_INC(sc->rl_cdata.last_tx); 1521 ifp->if_flags &= ~IFF_OACTIVE; 1522 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1523 1524 if (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) { 1525 if (sc->rl_want_auto) 1526 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1); 1527 } 1528 1529 return; 1530 } 1531 1532 static void rl_intr(arg) 1533 void *arg; 1534 { 1535 struct rl_softc *sc; 1536 struct ifnet *ifp; 1537 u_int16_t status; 1538 1539 sc = arg; 1540 ifp = &sc->arpcom.ac_if; 1541 1542 /* Disable interrupts. */ 1543 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1544 1545 for (;;) { 1546 1547 status = CSR_READ_2(sc, RL_ISR); 1548 if (status) 1549 CSR_WRITE_2(sc, RL_ISR, status); 1550 1551 if ((status & RL_INTRS) == 0) 1552 break; 1553 1554 if (status & RL_ISR_RX_OK) 1555 rl_rxeof(sc); 1556 1557 if (status & RL_ISR_RX_ERR) 1558 rl_rxeof(sc); 1559 1560 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1561 rl_txeof(sc); 1562 1563 if (status & RL_ISR_SYSTEM_ERR) { 1564 rl_reset(sc); 1565 rl_init(sc); 1566 } 1567 1568 } 1569 1570 /* Re-enable interrupts. */ 1571 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1572 1573 if (ifp->if_snd.ifq_head != NULL) 1574 rl_start(ifp); 1575 1576 return; 1577 } 1578 1579 /* 1580 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1581 * pointers to the fragment pointers. 1582 */ 1583 static int rl_encap(sc, m_head) 1584 struct rl_softc *sc; 1585 struct mbuf *m_head; 1586 { 1587 struct mbuf *m_new = NULL; 1588 1589 /* 1590 * The RealTek is brain damaged and wants longword-aligned 1591 * TX buffers, plus we can only have one fragment buffer 1592 * per packet. We have to copy pretty much all the time. 1593 */ 1594 1595 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1596 if (m_new == NULL) { 1597 printf("rl%d: no memory for tx list", sc->rl_unit); 1598 return(1); 1599 } 1600 if (m_head->m_pkthdr.len > MHLEN) { 1601 MCLGET(m_new, M_DONTWAIT); 1602 if (!(m_new->m_flags & M_EXT)) { 1603 m_freem(m_new); 1604 printf("rl%d: no memory for tx list", 1605 sc->rl_unit); 1606 return(1); 1607 } 1608 } 1609 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1610 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1611 m_freem(m_head); 1612 m_head = m_new; 1613 1614 /* Pad frames to at least 60 bytes. */ 1615 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1616 m_head->m_pkthdr.len += 1617 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1618 m_head->m_len = m_head->m_pkthdr.len; 1619 } 1620 1621 RL_CUR_TXMBUF(sc) = m_head; 1622 1623 return(0); 1624 } 1625 1626 /* 1627 * Main transmit routine. 1628 */ 1629 1630 static void rl_start(ifp) 1631 struct ifnet *ifp; 1632 { 1633 struct rl_softc *sc; 1634 struct mbuf *m_head = NULL; 1635 1636 sc = ifp->if_softc; 1637 1638 if (sc->rl_autoneg) { 1639 sc->rl_tx_pend = 1; 1640 return; 1641 } 1642 1643 while(RL_CUR_TXMBUF(sc) == NULL) { 1644 IF_DEQUEUE(&ifp->if_snd, m_head); 1645 if (m_head == NULL) 1646 break; 1647 1648 rl_encap(sc, m_head); 1649 1650 #if NBPFILTER > 0 1651 /* 1652 * If there's a BPF listener, bounce a copy of this frame 1653 * to him. 1654 */ 1655 if (ifp->if_bpf) 1656 bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 1657 #endif 1658 /* 1659 * Transmit the frame. 1660 */ 1661 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 1662 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t))); 1663 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1664 RL_TXTHRESH(sc->rl_txthresh) | 1665 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1666 1667 RL_INC(sc->rl_cdata.cur_tx); 1668 } 1669 1670 /* 1671 * We broke out of the loop because all our TX slots are 1672 * full. Mark the NIC as busy until it drains some of the 1673 * packets from the queue. 1674 */ 1675 if (RL_CUR_TXMBUF(sc) != NULL) 1676 ifp->if_flags |= IFF_OACTIVE; 1677 1678 /* 1679 * Set a timeout in case the chip goes out to lunch. 1680 */ 1681 ifp->if_timer = 5; 1682 1683 return; 1684 } 1685 1686 static void rl_init(xsc) 1687 void *xsc; 1688 { 1689 struct rl_softc *sc = xsc; 1690 struct ifnet *ifp = &sc->arpcom.ac_if; 1691 int s, i; 1692 u_int32_t rxcfg = 0; 1693 u_int16_t phy_bmcr = 0; 1694 1695 if (sc->rl_autoneg) 1696 return; 1697 1698 s = splimp(); 1699 1700 /* 1701 * XXX Hack for the 8139: the built-in autoneg logic's state 1702 * gets reset by rl_init() when we don't want it to. Try 1703 * to preserve it. (For 8129 cards with real external PHYs, 1704 * the BMCR register doesn't change, but this doesn't hurt.) 1705 */ 1706 if (sc->rl_type == RL_8139) 1707 phy_bmcr = rl_phy_readreg(sc, PHY_BMCR); 1708 1709 /* 1710 * Cancel pending I/O and free all RX/TX buffers. 1711 */ 1712 rl_stop(sc); 1713 1714 /* Init our MAC address */ 1715 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1716 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1717 } 1718 1719 /* Init the RX buffer pointer register. */ 1720 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); 1721 1722 /* Init TX descriptors. */ 1723 rl_list_tx_init(sc); 1724 1725 /* 1726 * Enable transmit and receive. 1727 */ 1728 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1729 1730 /* 1731 * Set the initial TX and RX configuration. 1732 */ 1733 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1734 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1735 1736 /* Set the individual bit to receive frames for this host only. */ 1737 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1738 rxcfg |= RL_RXCFG_RX_INDIV; 1739 1740 /* If we want promiscuous mode, set the allframes bit. */ 1741 if (ifp->if_flags & IFF_PROMISC) { 1742 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1743 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1744 } else { 1745 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1746 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1747 } 1748 1749 /* 1750 * Set capture broadcast bit to capture broadcast frames. 1751 */ 1752 if (ifp->if_flags & IFF_BROADCAST) { 1753 rxcfg |= RL_RXCFG_RX_BROAD; 1754 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1755 } else { 1756 rxcfg &= ~RL_RXCFG_RX_BROAD; 1757 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1758 } 1759 1760 /* 1761 * Program the multicast filter, if necessary. 1762 */ 1763 rl_setmulti(sc); 1764 1765 /* 1766 * Enable interrupts. 1767 */ 1768 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1769 1770 /* Set initial TX threshold */ 1771 sc->rl_txthresh = RL_TX_THRESH_INIT; 1772 1773 /* Start RX/TX process. */ 1774 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1775 1776 /* Enable receiver and transmitter. */ 1777 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1778 1779 /* Restore state of BMCR */ 1780 if (sc->rl_pinfo != NULL) 1781 rl_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1782 1783 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1784 1785 ifp->if_flags |= IFF_RUNNING; 1786 ifp->if_flags &= ~IFF_OACTIVE; 1787 1788 (void)splx(s); 1789 1790 return; 1791 } 1792 1793 /* 1794 * Set media options. 1795 */ 1796 static int rl_ifmedia_upd(ifp) 1797 struct ifnet *ifp; 1798 { 1799 struct rl_softc *sc; 1800 struct ifmedia *ifm; 1801 1802 sc = ifp->if_softc; 1803 ifm = &sc->ifmedia; 1804 1805 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1806 return(EINVAL); 1807 1808 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1809 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1); 1810 else 1811 rl_setmode_mii(sc, ifm->ifm_media); 1812 1813 return(0); 1814 } 1815 1816 /* 1817 * Report current media status. 1818 */ 1819 static void rl_ifmedia_sts(ifp, ifmr) 1820 struct ifnet *ifp; 1821 struct ifmediareq *ifmr; 1822 { 1823 struct rl_softc *sc; 1824 u_int16_t advert = 0, ability = 0; 1825 1826 sc = ifp->if_softc; 1827 1828 if (!(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1829 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1830 ifmr->ifm_active = IFM_ETHER|IFM_100_TX; 1831 else 1832 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 1833 1834 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1835 ifmr->ifm_active |= IFM_FDX; 1836 else 1837 ifmr->ifm_active |= IFM_HDX; 1838 return; 1839 } 1840 1841 ability = rl_phy_readreg(sc, PHY_LPAR); 1842 advert = rl_phy_readreg(sc, PHY_ANAR); 1843 if (advert & PHY_ANAR_100BT4 && 1844 ability & PHY_ANAR_100BT4) { 1845 ifmr->ifm_active = IFM_ETHER|IFM_100_T4; 1846 } else if (advert & PHY_ANAR_100BTXFULL && 1847 ability & PHY_ANAR_100BTXFULL) { 1848 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX; 1849 } else if (advert & PHY_ANAR_100BTXHALF && 1850 ability & PHY_ANAR_100BTXHALF) { 1851 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX; 1852 } else if (advert & PHY_ANAR_10BTFULL && 1853 ability & PHY_ANAR_10BTFULL) { 1854 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX; 1855 } else if (advert & PHY_ANAR_10BTHALF && 1856 ability & PHY_ANAR_10BTHALF) { 1857 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX; 1858 } 1859 1860 return; 1861 } 1862 1863 static int rl_ioctl(ifp, command, data) 1864 struct ifnet *ifp; 1865 u_long command; 1866 caddr_t data; 1867 { 1868 struct rl_softc *sc = ifp->if_softc; 1869 struct ifreq *ifr = (struct ifreq *) data; 1870 int s, error = 0; 1871 1872 s = splimp(); 1873 1874 switch(command) { 1875 case SIOCSIFADDR: 1876 case SIOCGIFADDR: 1877 case SIOCSIFMTU: 1878 error = ether_ioctl(ifp, command, data); 1879 break; 1880 case SIOCSIFFLAGS: 1881 if (ifp->if_flags & IFF_UP) { 1882 rl_init(sc); 1883 } else { 1884 if (ifp->if_flags & IFF_RUNNING) 1885 rl_stop(sc); 1886 } 1887 error = 0; 1888 break; 1889 case SIOCADDMULTI: 1890 case SIOCDELMULTI: 1891 rl_setmulti(sc); 1892 error = 0; 1893 break; 1894 case SIOCGIFMEDIA: 1895 case SIOCSIFMEDIA: 1896 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1897 break; 1898 default: 1899 error = EINVAL; 1900 break; 1901 } 1902 1903 (void)splx(s); 1904 1905 return(error); 1906 } 1907 1908 static void rl_watchdog(ifp) 1909 struct ifnet *ifp; 1910 { 1911 struct rl_softc *sc; 1912 1913 sc = ifp->if_softc; 1914 1915 if (sc->rl_autoneg) { 1916 rl_autoneg_mii(sc, RL_FLAG_DELAYTIMEO, 1); 1917 return; 1918 } 1919 1920 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1921 ifp->if_oerrors++; 1922 if (!(rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1923 printf("rl%d: no carrier - transceiver cable problem?\n", 1924 sc->rl_unit); 1925 rl_txeof(sc); 1926 rl_rxeof(sc); 1927 rl_init(sc); 1928 1929 return; 1930 } 1931 1932 /* 1933 * Stop the adapter and free any mbufs allocated to the 1934 * RX and TX lists. 1935 */ 1936 static void rl_stop(sc) 1937 struct rl_softc *sc; 1938 { 1939 register int i; 1940 struct ifnet *ifp; 1941 1942 ifp = &sc->arpcom.ac_if; 1943 ifp->if_timer = 0; 1944 1945 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1946 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1947 1948 /* 1949 * Free the TX list buffers. 1950 */ 1951 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1952 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1953 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1954 sc->rl_cdata.rl_tx_chain[i] = NULL; 1955 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1956 } 1957 } 1958 1959 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1960 1961 return; 1962 } 1963 1964 /* 1965 * Stop all chip I/O so that the kernel's probe routines don't 1966 * get confused by errant DMAs when rebooting. 1967 */ 1968 static void rl_shutdown(howto, arg) 1969 int howto; 1970 void *arg; 1971 { 1972 struct rl_softc *sc = (struct rl_softc *)arg; 1973 1974 rl_stop(sc); 1975 1976 return; 1977 } 1978 1979 1980 static struct pci_device rl_device = { 1981 "rl", 1982 rl_probe, 1983 rl_attach, 1984 &rl_count, 1985 NULL 1986 }; 1987 DATA_SET(pcidevice_set, rl_device);
Cache object: c78025c4911fbb408227f786f63b7e71
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