Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_rl.c
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1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/sockio.h> 89 #include <sys/mbuf.h> 90 #include <sys/malloc.h> 91 #include <sys/kernel.h> 92 #include <sys/socket.h> 93 94 #include <net/if.h> 95 #include <net/if_arp.h> 96 #include <net/ethernet.h> 97 #include <net/if_dl.h> 98 #include <net/if_media.h> 99 100 #include <net/bpf.h> 101 102 #include <vm/vm.h> /* for vtophys */ 103 #include <vm/pmap.h> /* for vtophys */ 104 #include <machine/clock.h> /* for DELAY */ 105 #include <machine/bus_pio.h> 106 #include <machine/bus_memio.h> 107 #include <machine/bus.h> 108 #include <machine/resource.h> 109 #include <sys/bus.h> 110 #include <sys/rman.h> 111 112 #include <dev/mii/mii.h> 113 #include <dev/mii/miivar.h> 114 115 #include <pci/pcireg.h> 116 #include <pci/pcivar.h> 117 118 /* "controller miibus0" required. See GENERIC if you get errors here. */ 119 #include "miibus_if.h" 120 121 /* 122 * Default to using PIO access for this driver. On SMP systems, 123 * there appear to be problems with memory mapped mode: it looks like 124 * doing too many memory mapped access back to back in rapid succession 125 * can hang the bus. I'm inclined to blame this on crummy design/construction 126 * on the part of RealTek. Memory mapped mode does appear to work on 127 * uniprocessor systems though. 128 */ 129 #define RL_USEIOSPACE 130 131 #include <pci/if_rlreg.h> 132 133 #ifndef lint 134 static const char rcsid[] = 135 "$FreeBSD$"; 136 #endif 137 138 /* 139 * Various supported device vendors/types and their names. 140 */ 141 static struct rl_type rl_devs[] = { 142 { RT_VENDORID, RT_DEVICEID_8129, 143 "RealTek 8129 10/100BaseTX" }, 144 { RT_VENDORID, RT_DEVICEID_8139, 145 "RealTek 8139 10/100BaseTX" }, 146 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 147 "Accton MPX 5030/5038 10/100BaseTX" }, 148 { DELTA_VENDORID, DELTA_DEVICEID_8139, 149 "Delta Electronics 8139 10/100BaseTX" }, 150 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 151 "Addtron Technolgy 8139 10/100BaseTX" }, 152 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 153 "D-Link DFE-530TX+ 10/100BaseTX" }, 154 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 155 "Nortel Networks 10/100BaseTX" }, 156 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, 157 "Peppercon AG ROL/F" }, 158 { 0, 0, NULL } 159 }; 160 161 static int rl_probe __P((device_t)); 162 static int rl_attach __P((device_t)); 163 static int rl_detach __P((device_t)); 164 165 static int rl_encap __P((struct rl_softc *, struct mbuf * )); 166 167 static void rl_rxeof __P((struct rl_softc *)); 168 static void rl_txeof __P((struct rl_softc *)); 169 static void rl_intr __P((void *)); 170 static void rl_tick __P((void *)); 171 static void rl_start __P((struct ifnet *)); 172 static int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 173 static void rl_init __P((void *)); 174 static void rl_stop __P((struct rl_softc *)); 175 static void rl_watchdog __P((struct ifnet *)); 176 static int rl_suspend __P((device_t)); 177 static int rl_resume __P((device_t)); 178 static void rl_shutdown __P((device_t)); 179 static int rl_ifmedia_upd __P((struct ifnet *)); 180 static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 181 182 static void rl_eeprom_putbyte __P((struct rl_softc *, int)); 183 static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *)); 184 static void rl_read_eeprom __P((struct rl_softc *, caddr_t, 185 int, int, int)); 186 static void rl_mii_sync __P((struct rl_softc *)); 187 static void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 188 static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 189 static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 190 191 static int rl_miibus_readreg __P((device_t, int, int)); 192 static int rl_miibus_writereg __P((device_t, int, int, int)); 193 static void rl_miibus_statchg __P((device_t)); 194 195 static u_int8_t rl_calchash __P((caddr_t)); 196 static void rl_setmulti __P((struct rl_softc *)); 197 static void rl_reset __P((struct rl_softc *)); 198 static int rl_list_tx_init __P((struct rl_softc *)); 199 200 #ifdef RL_USEIOSPACE 201 #define RL_RES SYS_RES_IOPORT 202 #define RL_RID RL_PCI_LOIO 203 #else 204 #define RL_RES SYS_RES_MEMORY 205 #define RL_RID RL_PCI_LOMEM 206 #endif 207 208 static device_method_t rl_methods[] = { 209 /* Device interface */ 210 DEVMETHOD(device_probe, rl_probe), 211 DEVMETHOD(device_attach, rl_attach), 212 DEVMETHOD(device_detach, rl_detach), 213 DEVMETHOD(device_suspend, rl_suspend), 214 DEVMETHOD(device_resume, rl_resume), 215 DEVMETHOD(device_shutdown, rl_shutdown), 216 217 /* bus interface */ 218 DEVMETHOD(bus_print_child, bus_generic_print_child), 219 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 220 221 /* MII interface */ 222 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 223 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 224 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 225 226 { 0, 0 } 227 }; 228 229 static driver_t rl_driver = { 230 "rl", 231 rl_methods, 232 sizeof(struct rl_softc) 233 }; 234 235 static devclass_t rl_devclass; 236 237 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 238 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 239 240 #define EE_SET(x) \ 241 CSR_WRITE_1(sc, RL_EECMD, \ 242 CSR_READ_1(sc, RL_EECMD) | x) 243 244 #define EE_CLR(x) \ 245 CSR_WRITE_1(sc, RL_EECMD, \ 246 CSR_READ_1(sc, RL_EECMD) & ~x) 247 248 /* 249 * Send a read command and address to the EEPROM, check for ACK. 250 */ 251 static void rl_eeprom_putbyte(sc, addr) 252 struct rl_softc *sc; 253 int addr; 254 { 255 register int d, i; 256 257 d = addr | RL_EECMD_READ; 258 259 /* 260 * Feed in each bit and strobe the clock. 261 */ 262 for (i = 0x400; i; i >>= 1) { 263 if (d & i) { 264 EE_SET(RL_EE_DATAIN); 265 } else { 266 EE_CLR(RL_EE_DATAIN); 267 } 268 DELAY(100); 269 EE_SET(RL_EE_CLK); 270 DELAY(150); 271 EE_CLR(RL_EE_CLK); 272 DELAY(100); 273 } 274 275 return; 276 } 277 278 /* 279 * Read a word of data stored in the EEPROM at address 'addr.' 280 */ 281 static void rl_eeprom_getword(sc, addr, dest) 282 struct rl_softc *sc; 283 int addr; 284 u_int16_t *dest; 285 { 286 register int i; 287 u_int16_t word = 0; 288 289 /* Enter EEPROM access mode. */ 290 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 291 292 /* 293 * Send address of word we want to read. 294 */ 295 rl_eeprom_putbyte(sc, addr); 296 297 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 298 299 /* 300 * Start reading bits from EEPROM. 301 */ 302 for (i = 0x8000; i; i >>= 1) { 303 EE_SET(RL_EE_CLK); 304 DELAY(100); 305 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 306 word |= i; 307 EE_CLR(RL_EE_CLK); 308 DELAY(100); 309 } 310 311 /* Turn off EEPROM access mode. */ 312 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 313 314 *dest = word; 315 316 return; 317 } 318 319 /* 320 * Read a sequence of words from the EEPROM. 321 */ 322 static void rl_read_eeprom(sc, dest, off, cnt, swap) 323 struct rl_softc *sc; 324 caddr_t dest; 325 int off; 326 int cnt; 327 int swap; 328 { 329 int i; 330 u_int16_t word = 0, *ptr; 331 332 for (i = 0; i < cnt; i++) { 333 rl_eeprom_getword(sc, off + i, &word); 334 ptr = (u_int16_t *)(dest + (i * 2)); 335 if (swap) 336 *ptr = ntohs(word); 337 else 338 *ptr = word; 339 } 340 341 return; 342 } 343 344 345 /* 346 * MII access routines are provided for the 8129, which 347 * doesn't have a built-in PHY. For the 8139, we fake things 348 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 349 * direct access PHY registers. 350 */ 351 #define MII_SET(x) \ 352 CSR_WRITE_1(sc, RL_MII, \ 353 CSR_READ_1(sc, RL_MII) | x) 354 355 #define MII_CLR(x) \ 356 CSR_WRITE_1(sc, RL_MII, \ 357 CSR_READ_1(sc, RL_MII) & ~x) 358 359 /* 360 * Sync the PHYs by setting data bit and strobing the clock 32 times. 361 */ 362 static void rl_mii_sync(sc) 363 struct rl_softc *sc; 364 { 365 register int i; 366 367 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 368 369 for (i = 0; i < 32; i++) { 370 MII_SET(RL_MII_CLK); 371 DELAY(1); 372 MII_CLR(RL_MII_CLK); 373 DELAY(1); 374 } 375 376 return; 377 } 378 379 /* 380 * Clock a series of bits through the MII. 381 */ 382 static void rl_mii_send(sc, bits, cnt) 383 struct rl_softc *sc; 384 u_int32_t bits; 385 int cnt; 386 { 387 int i; 388 389 MII_CLR(RL_MII_CLK); 390 391 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 392 if (bits & i) { 393 MII_SET(RL_MII_DATAOUT); 394 } else { 395 MII_CLR(RL_MII_DATAOUT); 396 } 397 DELAY(1); 398 MII_CLR(RL_MII_CLK); 399 DELAY(1); 400 MII_SET(RL_MII_CLK); 401 } 402 } 403 404 /* 405 * Read an PHY register through the MII. 406 */ 407 static int rl_mii_readreg(sc, frame) 408 struct rl_softc *sc; 409 struct rl_mii_frame *frame; 410 411 { 412 int i, ack, s; 413 414 s = splimp(); 415 416 /* 417 * Set up frame for RX. 418 */ 419 frame->mii_stdelim = RL_MII_STARTDELIM; 420 frame->mii_opcode = RL_MII_READOP; 421 frame->mii_turnaround = 0; 422 frame->mii_data = 0; 423 424 CSR_WRITE_2(sc, RL_MII, 0); 425 426 /* 427 * Turn on data xmit. 428 */ 429 MII_SET(RL_MII_DIR); 430 431 rl_mii_sync(sc); 432 433 /* 434 * Send command/address info. 435 */ 436 rl_mii_send(sc, frame->mii_stdelim, 2); 437 rl_mii_send(sc, frame->mii_opcode, 2); 438 rl_mii_send(sc, frame->mii_phyaddr, 5); 439 rl_mii_send(sc, frame->mii_regaddr, 5); 440 441 /* Idle bit */ 442 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 443 DELAY(1); 444 MII_SET(RL_MII_CLK); 445 DELAY(1); 446 447 /* Turn off xmit. */ 448 MII_CLR(RL_MII_DIR); 449 450 /* Check for ack */ 451 MII_CLR(RL_MII_CLK); 452 DELAY(1); 453 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 454 MII_SET(RL_MII_CLK); 455 DELAY(1); 456 457 /* 458 * Now try reading data bits. If the ack failed, we still 459 * need to clock through 16 cycles to keep the PHY(s) in sync. 460 */ 461 if (ack) { 462 for(i = 0; i < 16; i++) { 463 MII_CLR(RL_MII_CLK); 464 DELAY(1); 465 MII_SET(RL_MII_CLK); 466 DELAY(1); 467 } 468 goto fail; 469 } 470 471 for (i = 0x8000; i; i >>= 1) { 472 MII_CLR(RL_MII_CLK); 473 DELAY(1); 474 if (!ack) { 475 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 476 frame->mii_data |= i; 477 DELAY(1); 478 } 479 MII_SET(RL_MII_CLK); 480 DELAY(1); 481 } 482 483 fail: 484 485 MII_CLR(RL_MII_CLK); 486 DELAY(1); 487 MII_SET(RL_MII_CLK); 488 DELAY(1); 489 490 splx(s); 491 492 if (ack) 493 return(1); 494 return(0); 495 } 496 497 /* 498 * Write to a PHY register through the MII. 499 */ 500 static int rl_mii_writereg(sc, frame) 501 struct rl_softc *sc; 502 struct rl_mii_frame *frame; 503 504 { 505 int s; 506 507 s = splimp(); 508 /* 509 * Set up frame for TX. 510 */ 511 512 frame->mii_stdelim = RL_MII_STARTDELIM; 513 frame->mii_opcode = RL_MII_WRITEOP; 514 frame->mii_turnaround = RL_MII_TURNAROUND; 515 516 /* 517 * Turn on data output. 518 */ 519 MII_SET(RL_MII_DIR); 520 521 rl_mii_sync(sc); 522 523 rl_mii_send(sc, frame->mii_stdelim, 2); 524 rl_mii_send(sc, frame->mii_opcode, 2); 525 rl_mii_send(sc, frame->mii_phyaddr, 5); 526 rl_mii_send(sc, frame->mii_regaddr, 5); 527 rl_mii_send(sc, frame->mii_turnaround, 2); 528 rl_mii_send(sc, frame->mii_data, 16); 529 530 /* Idle bit. */ 531 MII_SET(RL_MII_CLK); 532 DELAY(1); 533 MII_CLR(RL_MII_CLK); 534 DELAY(1); 535 536 /* 537 * Turn off xmit. 538 */ 539 MII_CLR(RL_MII_DIR); 540 541 splx(s); 542 543 return(0); 544 } 545 546 static int rl_miibus_readreg(dev, phy, reg) 547 device_t dev; 548 int phy, reg; 549 { 550 struct rl_softc *sc; 551 struct rl_mii_frame frame; 552 u_int16_t rval = 0; 553 u_int16_t rl8139_reg = 0; 554 555 sc = device_get_softc(dev); 556 557 if (sc->rl_type == RL_8139) { 558 /* Pretend the internal PHY is only at address 0 */ 559 if (phy) 560 return(0); 561 switch(reg) { 562 case MII_BMCR: 563 rl8139_reg = RL_BMCR; 564 break; 565 case MII_BMSR: 566 rl8139_reg = RL_BMSR; 567 break; 568 case MII_ANAR: 569 rl8139_reg = RL_ANAR; 570 break; 571 case MII_ANER: 572 rl8139_reg = RL_ANER; 573 break; 574 case MII_ANLPAR: 575 rl8139_reg = RL_LPAR; 576 break; 577 case MII_PHYIDR1: 578 case MII_PHYIDR2: 579 return(0); 580 break; 581 /* 582 * Allow the rlphy driver to read the media status 583 * register. If we have a link partner which does not 584 * support NWAY, this is the register which will tell 585 * us the results of parallel detection. 586 */ 587 case RL_MEDIASTAT: 588 rval = CSR_READ_1(sc, RL_MEDIASTAT); 589 return(rval); 590 break; 591 default: 592 printf("rl%d: bad phy register\n", sc->rl_unit); 593 return(0); 594 } 595 rval = CSR_READ_2(sc, rl8139_reg); 596 return(rval); 597 } 598 599 bzero((char *)&frame, sizeof(frame)); 600 601 frame.mii_phyaddr = phy; 602 frame.mii_regaddr = reg; 603 rl_mii_readreg(sc, &frame); 604 605 return(frame.mii_data); 606 } 607 608 static int rl_miibus_writereg(dev, phy, reg, data) 609 device_t dev; 610 int phy, reg, data; 611 { 612 struct rl_softc *sc; 613 struct rl_mii_frame frame; 614 u_int16_t rl8139_reg = 0; 615 616 sc = device_get_softc(dev); 617 618 if (sc->rl_type == RL_8139) { 619 /* Pretend the internal PHY is only at address 0 */ 620 if (phy) 621 return(0); 622 switch(reg) { 623 case MII_BMCR: 624 rl8139_reg = RL_BMCR; 625 break; 626 case MII_BMSR: 627 rl8139_reg = RL_BMSR; 628 break; 629 case MII_ANAR: 630 rl8139_reg = RL_ANAR; 631 break; 632 case MII_ANER: 633 rl8139_reg = RL_ANER; 634 break; 635 case MII_ANLPAR: 636 rl8139_reg = RL_LPAR; 637 break; 638 case MII_PHYIDR1: 639 case MII_PHYIDR2: 640 return(0); 641 break; 642 default: 643 printf("rl%d: bad phy register\n", sc->rl_unit); 644 return(0); 645 } 646 CSR_WRITE_2(sc, rl8139_reg, data); 647 return(0); 648 } 649 650 bzero((char *)&frame, sizeof(frame)); 651 652 frame.mii_phyaddr = phy; 653 frame.mii_regaddr = reg; 654 frame.mii_data = data; 655 656 rl_mii_writereg(sc, &frame); 657 658 return(0); 659 } 660 661 static void rl_miibus_statchg(dev) 662 device_t dev; 663 { 664 return; 665 } 666 667 /* 668 * Calculate CRC of a multicast group address, return the upper 6 bits. 669 */ 670 static u_int8_t rl_calchash(addr) 671 caddr_t addr; 672 { 673 u_int32_t crc, carry; 674 int i, j; 675 u_int8_t c; 676 677 /* Compute CRC for the address value. */ 678 crc = 0xFFFFFFFF; /* initial value */ 679 680 for (i = 0; i < 6; i++) { 681 c = *(addr + i); 682 for (j = 0; j < 8; j++) { 683 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 684 crc <<= 1; 685 c >>= 1; 686 if (carry) 687 crc = (crc ^ 0x04c11db6) | carry; 688 } 689 } 690 691 /* return the filter bit position */ 692 return(crc >> 26); 693 } 694 695 /* 696 * Program the 64-bit multicast hash filter. 697 */ 698 static void rl_setmulti(sc) 699 struct rl_softc *sc; 700 { 701 struct ifnet *ifp; 702 int h = 0; 703 u_int32_t hashes[2] = { 0, 0 }; 704 struct ifmultiaddr *ifma; 705 u_int32_t rxfilt; 706 int mcnt = 0; 707 708 ifp = &sc->arpcom.ac_if; 709 710 rxfilt = CSR_READ_4(sc, RL_RXCFG); 711 712 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 713 rxfilt |= RL_RXCFG_RX_MULTI; 714 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 715 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 716 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 717 return; 718 } 719 720 /* first, zot all the existing hash bits */ 721 CSR_WRITE_4(sc, RL_MAR0, 0); 722 CSR_WRITE_4(sc, RL_MAR4, 0); 723 724 /* now program new ones */ 725 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 726 ifma = ifma->ifma_link.le_next) { 727 if (ifma->ifma_addr->sa_family != AF_LINK) 728 continue; 729 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 730 if (h < 32) 731 hashes[0] |= (1 << h); 732 else 733 hashes[1] |= (1 << (h - 32)); 734 mcnt++; 735 } 736 737 if (mcnt) 738 rxfilt |= RL_RXCFG_RX_MULTI; 739 else 740 rxfilt &= ~RL_RXCFG_RX_MULTI; 741 742 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 743 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 744 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 745 746 return; 747 } 748 749 static void rl_reset(sc) 750 struct rl_softc *sc; 751 { 752 register int i; 753 754 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 755 756 for (i = 0; i < RL_TIMEOUT; i++) { 757 DELAY(10); 758 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 759 break; 760 } 761 if (i == RL_TIMEOUT) 762 printf("rl%d: reset never completed!\n", sc->rl_unit); 763 764 return; 765 } 766 767 /* 768 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 769 * IDs against our list and return a device name if we find a match. 770 */ 771 static int rl_probe(dev) 772 device_t dev; 773 { 774 struct rl_type *t; 775 776 t = rl_devs; 777 778 while(t->rl_name != NULL) { 779 if ((pci_get_vendor(dev) == t->rl_vid) && 780 (pci_get_device(dev) == t->rl_did)) { 781 device_set_desc(dev, t->rl_name); 782 return(0); 783 } 784 t++; 785 } 786 787 return(ENXIO); 788 } 789 790 /* 791 * Attach the interface. Allocate softc structures, do ifmedia 792 * setup and ethernet/BPF attach. 793 */ 794 static int rl_attach(dev) 795 device_t dev; 796 { 797 int s; 798 u_char eaddr[ETHER_ADDR_LEN]; 799 u_int32_t command; 800 struct rl_softc *sc; 801 struct ifnet *ifp; 802 u_int16_t rl_did = 0; 803 int unit, error = 0, rid; 804 805 s = splimp(); 806 807 sc = device_get_softc(dev); 808 unit = device_get_unit(dev); 809 bzero(sc, sizeof(struct rl_softc)); 810 811 /* 812 * Handle power management nonsense. 813 */ 814 815 command = pci_read_config(dev, RL_PCI_CAPID, 4) & 0x000000FF; 816 if (command == 0x01) { 817 818 command = pci_read_config(dev, RL_PCI_PWRMGMTCTRL, 4); 819 if (command & RL_PSTATE_MASK) { 820 u_int32_t iobase, membase, irq; 821 822 /* Save important PCI config data. */ 823 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 824 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 825 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 826 827 /* Reset the power state. */ 828 printf("rl%d: chip is is in D%d power mode " 829 "-- setting to D0\n", unit, command & RL_PSTATE_MASK); 830 command &= 0xFFFFFFFC; 831 pci_write_config(dev, RL_PCI_PWRMGMTCTRL, command, 4); 832 833 /* Restore PCI config data. */ 834 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 835 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 836 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 837 } 838 } 839 840 /* 841 * Map control/status registers. 842 */ 843 command = pci_read_config(dev, PCIR_COMMAND, 4); 844 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 845 pci_write_config(dev, PCIR_COMMAND, command, 4); 846 command = pci_read_config(dev, PCIR_COMMAND, 4); 847 848 #ifdef RL_USEIOSPACE 849 if (!(command & PCIM_CMD_PORTEN)) { 850 printf("rl%d: failed to enable I/O ports!\n", unit); 851 error = ENXIO; 852 goto fail; 853 } 854 #else 855 if (!(command & PCIM_CMD_MEMEN)) { 856 printf("rl%d: failed to enable memory mapping!\n", unit); 857 error = ENXIO; 858 goto fail; 859 } 860 #endif 861 862 rid = RL_RID; 863 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 864 0, ~0, 1, RF_ACTIVE); 865 866 if (sc->rl_res == NULL) { 867 printf ("rl%d: couldn't map ports/memory\n", unit); 868 error = ENXIO; 869 goto fail; 870 } 871 872 sc->rl_btag = rman_get_bustag(sc->rl_res); 873 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 874 875 rid = 0; 876 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 877 RF_SHAREABLE | RF_ACTIVE); 878 879 if (sc->rl_irq == NULL) { 880 printf("rl%d: couldn't map interrupt\n", unit); 881 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 882 error = ENXIO; 883 goto fail; 884 } 885 886 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 887 rl_intr, sc, &sc->rl_intrhand); 888 889 if (error) { 890 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 891 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 892 printf("rl%d: couldn't set up irq\n", unit); 893 goto fail; 894 } 895 896 callout_handle_init(&sc->rl_stat_ch); 897 898 /* Reset the adapter. */ 899 rl_reset(sc); 900 901 /* 902 * Get station address from the EEPROM. 903 */ 904 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 905 906 /* 907 * A RealTek chip was detected. Inform the world. 908 */ 909 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 910 911 sc->rl_unit = unit; 912 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 913 914 /* 915 * Now read the exact device type from the EEPROM to find 916 * out if it's an 8129 or 8139. 917 */ 918 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 919 920 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 921 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 922 rl_did == DLINK_DEVICEID_530TXPLUS) 923 sc->rl_type = RL_8139; 924 else if (rl_did == RT_DEVICEID_8129) 925 sc->rl_type = RL_8129; 926 else { 927 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 928 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 929 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 930 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 931 error = ENXIO; 932 goto fail; 933 } 934 935 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 1518, M_DEVBUF, 936 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 937 938 if (sc->rl_cdata.rl_rx_buf == NULL) { 939 printf("rl%d: no memory for list buffers!\n", unit); 940 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 941 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 942 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 943 error = ENXIO; 944 goto fail; 945 } 946 947 /* Leave a few bytes before the start of the RX ring buffer. */ 948 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 949 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 950 951 /* Do MII setup */ 952 if (mii_phy_probe(dev, &sc->rl_miibus, 953 rl_ifmedia_upd, rl_ifmedia_sts)) { 954 printf("rl%d: MII without any phy!\n", sc->rl_unit); 955 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 1518, 956 M_DEVBUF); 957 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 958 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 959 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 960 free(sc->rl_cdata.rl_rx_buf, M_DEVBUF); 961 error = ENXIO; 962 goto fail; 963 } 964 965 ifp = &sc->arpcom.ac_if; 966 ifp->if_softc = sc; 967 ifp->if_unit = unit; 968 ifp->if_name = "rl"; 969 ifp->if_mtu = ETHERMTU; 970 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 971 ifp->if_ioctl = rl_ioctl; 972 ifp->if_output = ether_output; 973 ifp->if_start = rl_start; 974 ifp->if_watchdog = rl_watchdog; 975 ifp->if_init = rl_init; 976 ifp->if_baudrate = 10000000; 977 #ifdef DEVICE_POLLING 978 ifp->if_capabilities |= IFCAP_POLLING; 979 #endif 980 ifp->if_capenable = ifp->if_capabilities; 981 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 982 983 /* 984 * Call MI attach routine. 985 */ 986 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 987 988 fail: 989 splx(s); 990 return(error); 991 } 992 993 static int rl_detach(dev) 994 device_t dev; 995 { 996 struct rl_softc *sc; 997 struct ifnet *ifp; 998 int s; 999 1000 s = splimp(); 1001 1002 sc = device_get_softc(dev); 1003 ifp = &sc->arpcom.ac_if; 1004 1005 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1006 rl_stop(sc); 1007 1008 bus_generic_detach(dev); 1009 device_delete_child(dev, sc->rl_miibus); 1010 1011 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1012 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1013 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1014 1015 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 1518, M_DEVBUF); 1016 1017 splx(s); 1018 1019 return(0); 1020 } 1021 1022 /* 1023 * Initialize the transmit descriptors. 1024 */ 1025 static int rl_list_tx_init(sc) 1026 struct rl_softc *sc; 1027 { 1028 struct rl_chain_data *cd; 1029 int i; 1030 1031 cd = &sc->rl_cdata; 1032 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1033 cd->rl_tx_chain[i] = NULL; 1034 CSR_WRITE_4(sc, 1035 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1036 } 1037 1038 sc->rl_cdata.cur_tx = 0; 1039 sc->rl_cdata.last_tx = 0; 1040 1041 return(0); 1042 } 1043 1044 /* 1045 * A frame has been uploaded: pass the resulting mbuf chain up to 1046 * the higher level protocols. 1047 * 1048 * You know there's something wrong with a PCI bus-master chip design 1049 * when you have to use m_devget(). 1050 * 1051 * The receive operation is badly documented in the datasheet, so I'll 1052 * attempt to document it here. The driver provides a buffer area and 1053 * places its base address in the RX buffer start address register. 1054 * The chip then begins copying frames into the RX buffer. Each frame 1055 * is preceeded by a 32-bit RX status word which specifies the length 1056 * of the frame and certain other status bits. Each frame (starting with 1057 * the status word) is also 32-bit aligned. The frame length is in the 1058 * first 16 bits of the status word; the lower 15 bits correspond with 1059 * the 'rx status register' mentioned in the datasheet. 1060 * 1061 * Note: to make the Alpha happy, the frame payload needs to be aligned 1062 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 1063 * the ring buffer starting at an address two bytes before the actual 1064 * data location. We can then shave off the first two bytes using m_adj(). 1065 * The reason we do this is because m_devget() doesn't let us specify an 1066 * offset into the mbuf storage space, so we have to artificially create 1067 * one. The ring is allocated in such a way that there are a few unused 1068 * bytes of space preceecing it so that it will be safe for us to do the 1069 * 2-byte backstep even if reading from the ring at offset 0. 1070 */ 1071 static void rl_rxeof(sc) 1072 struct rl_softc *sc; 1073 { 1074 struct ether_header *eh; 1075 struct mbuf *m; 1076 struct ifnet *ifp; 1077 int total_len = 0; 1078 u_int32_t rxstat; 1079 caddr_t rxbufpos; 1080 int wrap = 0; 1081 u_int16_t cur_rx; 1082 u_int16_t limit; 1083 u_int16_t rx_bytes = 0, max_bytes; 1084 1085 ifp = &sc->arpcom.ac_if; 1086 1087 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1088 1089 /* Do not try to read past this point. */ 1090 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1091 1092 if (limit < cur_rx) 1093 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1094 else 1095 max_bytes = limit - cur_rx; 1096 1097 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1098 #ifdef DEVICE_POLLING 1099 if (ifp->if_ipending & IFF_POLLING) { 1100 if (sc->rxcycles <= 0) 1101 break; 1102 sc->rxcycles--; 1103 } 1104 #endif /* DEVICE_POLLING */ 1105 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1106 rxstat = *(u_int32_t *)rxbufpos; 1107 1108 /* 1109 * Here's a totally undocumented fact for you. When the 1110 * RealTek chip is in the process of copying a packet into 1111 * RAM for you, the length will be 0xfff0. If you spot a 1112 * packet header with this value, you need to stop. The 1113 * datasheet makes absolutely no mention of this and 1114 * RealTek should be shot for this. 1115 */ 1116 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1117 break; 1118 1119 if (!(rxstat & RL_RXSTAT_RXOK)) { 1120 ifp->if_ierrors++; 1121 rl_init(sc); 1122 return; 1123 } 1124 1125 /* No errors; receive the packet. */ 1126 total_len = rxstat >> 16; 1127 rx_bytes += total_len + 4; 1128 1129 /* 1130 * XXX The RealTek chip includes the CRC with every 1131 * received frame, and there's no way to turn this 1132 * behavior off (at least, I can't find anything in 1133 * the manual that explains how to do it) so we have 1134 * to trim off the CRC manually. 1135 */ 1136 total_len -= ETHER_CRC_LEN; 1137 1138 /* 1139 * Avoid trying to read more bytes than we know 1140 * the chip has prepared for us. 1141 */ 1142 if (rx_bytes > max_bytes) 1143 break; 1144 1145 rxbufpos = sc->rl_cdata.rl_rx_buf + 1146 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1147 1148 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1149 rxbufpos = sc->rl_cdata.rl_rx_buf; 1150 1151 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1152 1153 if (total_len > wrap) { 1154 /* 1155 * Fool m_devget() into thinking we want to copy 1156 * the whole buffer so we don't end up fragmenting 1157 * the data. 1158 */ 1159 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1160 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1161 if (m == NULL) { 1162 ifp->if_ierrors++; 1163 } else { 1164 m_adj(m, RL_ETHER_ALIGN); 1165 m_copyback(m, wrap, total_len - wrap, 1166 sc->rl_cdata.rl_rx_buf); 1167 } 1168 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1169 } else { 1170 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1171 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1172 if (m == NULL) { 1173 ifp->if_ierrors++; 1174 } else 1175 m_adj(m, RL_ETHER_ALIGN); 1176 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1177 } 1178 1179 /* 1180 * Round up to 32-bit boundary. 1181 */ 1182 cur_rx = (cur_rx + 3) & ~3; 1183 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1184 1185 if (m == NULL) 1186 continue; 1187 1188 eh = mtod(m, struct ether_header *); 1189 ifp->if_ipackets++; 1190 1191 /* Remove header from mbuf and pass it on. */ 1192 m_adj(m, sizeof(struct ether_header)); 1193 ether_input(ifp, eh, m); 1194 } 1195 1196 return; 1197 } 1198 1199 /* 1200 * A frame was downloaded to the chip. It's safe for us to clean up 1201 * the list buffers. 1202 */ 1203 static void rl_txeof(sc) 1204 struct rl_softc *sc; 1205 { 1206 struct ifnet *ifp; 1207 u_int32_t txstat; 1208 1209 ifp = &sc->arpcom.ac_if; 1210 1211 /* 1212 * Go through our tx list and free mbufs for those 1213 * frames that have been uploaded. 1214 */ 1215 do { 1216 if (RL_LAST_TXMBUF(sc) == NULL) 1217 break; 1218 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1219 if (!(txstat & (RL_TXSTAT_TX_OK| 1220 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1221 break; 1222 1223 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1224 1225 m_freem(RL_LAST_TXMBUF(sc)); 1226 RL_LAST_TXMBUF(sc) = NULL; 1227 if (txstat & RL_TXSTAT_TX_OK) 1228 ifp->if_opackets++; 1229 else { 1230 int oldthresh; 1231 ifp->if_oerrors++; 1232 if ((txstat & RL_TXSTAT_TXABRT) || 1233 (txstat & RL_TXSTAT_OUTOFWIN)) 1234 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1235 oldthresh = sc->rl_txthresh; 1236 /* error recovery */ 1237 rl_reset(sc); 1238 rl_init(sc); 1239 /* 1240 * If there was a transmit underrun, 1241 * bump the TX threshold. 1242 */ 1243 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1244 sc->rl_txthresh = oldthresh + 32; 1245 return; 1246 } 1247 RL_INC(sc->rl_cdata.last_tx); 1248 ifp->if_flags &= ~IFF_OACTIVE; 1249 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1250 1251 if (RL_LAST_TXMBUF(sc) == NULL) 1252 ifp->if_timer = 0; 1253 else if (ifp->if_timer == 0) 1254 ifp->if_timer = 5; 1255 1256 return; 1257 } 1258 1259 static void rl_tick(xsc) 1260 void *xsc; 1261 { 1262 struct rl_softc *sc; 1263 struct mii_data *mii; 1264 int s; 1265 1266 s = splimp(); 1267 1268 sc = xsc; 1269 mii = device_get_softc(sc->rl_miibus); 1270 1271 mii_tick(mii); 1272 1273 splx(s); 1274 1275 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1276 1277 return; 1278 } 1279 1280 #ifdef DEVICE_POLLING 1281 static poll_handler_t rl_poll; 1282 1283 static void 1284 rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1285 { 1286 struct rl_softc *sc = ifp->if_softc; 1287 1288 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1289 ether_poll_deregister(ifp); 1290 cmd = POLL_DEREGISTER; 1291 } 1292 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1293 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1294 return; 1295 } 1296 1297 sc->rxcycles = count; 1298 rl_rxeof(sc); 1299 rl_txeof(sc); 1300 if (ifp->if_snd.ifq_head != NULL) 1301 rl_start(ifp); 1302 1303 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1304 u_int16_t status; 1305 1306 status = CSR_READ_2(sc, RL_ISR); 1307 if (status) 1308 CSR_WRITE_2(sc, RL_ISR, status); 1309 1310 /* 1311 * XXX check behaviour on receiver stalls. 1312 */ 1313 1314 if (status & RL_ISR_SYSTEM_ERR) { 1315 rl_reset(sc); 1316 rl_init(sc); 1317 } 1318 } 1319 } 1320 #endif /* DEVICE_POLLING */ 1321 1322 static void rl_intr(arg) 1323 void *arg; 1324 { 1325 struct rl_softc *sc; 1326 struct ifnet *ifp; 1327 u_int16_t status; 1328 1329 sc = arg; 1330 1331 if (sc->suspended) { 1332 return; 1333 } 1334 1335 ifp = &sc->arpcom.ac_if; 1336 #ifdef DEVICE_POLLING 1337 if (ifp->if_ipending & IFF_POLLING) 1338 return; 1339 if ((ifp->if_capenable & IFCAP_POLLING) && 1340 ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 1341 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1342 rl_poll(ifp, 0, 1); 1343 return; 1344 } 1345 #endif /* DEVICE_POLLING */ 1346 1347 for (;;) { 1348 1349 status = CSR_READ_2(sc, RL_ISR); 1350 if (status) 1351 CSR_WRITE_2(sc, RL_ISR, status); 1352 1353 if ((status & RL_INTRS) == 0) 1354 break; 1355 1356 if (status & RL_ISR_RX_OK) 1357 rl_rxeof(sc); 1358 1359 if (status & RL_ISR_RX_ERR) 1360 rl_rxeof(sc); 1361 1362 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1363 rl_txeof(sc); 1364 1365 if (status & RL_ISR_SYSTEM_ERR) { 1366 rl_reset(sc); 1367 rl_init(sc); 1368 } 1369 1370 } 1371 if (ifp->if_snd.ifq_head != NULL) 1372 rl_start(ifp); 1373 1374 return; 1375 } 1376 1377 /* 1378 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1379 * pointers to the fragment pointers. 1380 */ 1381 static int rl_encap(sc, m_head) 1382 struct rl_softc *sc; 1383 struct mbuf *m_head; 1384 { 1385 struct mbuf *m_new = NULL; 1386 1387 /* 1388 * The RealTek is brain damaged and wants longword-aligned 1389 * TX buffers, plus we can only have one fragment buffer 1390 * per packet. We have to copy pretty much all the time. 1391 */ 1392 1393 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1394 if (m_new == NULL) 1395 return(1); 1396 if (m_head->m_pkthdr.len > MHLEN) { 1397 MCLGET(m_new, M_DONTWAIT); 1398 if (!(m_new->m_flags & M_EXT)) { 1399 m_freem(m_new); 1400 return(1); 1401 } 1402 } 1403 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1404 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1405 m_freem(m_head); 1406 m_head = m_new; 1407 1408 /* Pad frames to at least 60 bytes. */ 1409 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1410 /* 1411 * Make security concious people happy: zero out the 1412 * bytes in the pad area, since we don't know what 1413 * this mbuf cluster buffer's previous user might 1414 * have left in it. 1415 */ 1416 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1417 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1418 m_head->m_pkthdr.len += 1419 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1420 m_head->m_len = m_head->m_pkthdr.len; 1421 } 1422 1423 RL_CUR_TXMBUF(sc) = m_head; 1424 1425 return(0); 1426 } 1427 1428 /* 1429 * Main transmit routine. 1430 */ 1431 1432 static void rl_start(ifp) 1433 struct ifnet *ifp; 1434 { 1435 struct rl_softc *sc; 1436 struct mbuf *m_head = NULL; 1437 1438 sc = ifp->if_softc; 1439 1440 while(RL_CUR_TXMBUF(sc) == NULL) { 1441 IF_DEQUEUE(&ifp->if_snd, m_head); 1442 if (m_head == NULL) 1443 break; 1444 1445 if (rl_encap(sc, m_head)) { 1446 IF_PREPEND(&ifp->if_snd, m_head); 1447 ifp->if_flags |= IFF_OACTIVE; 1448 break; 1449 } 1450 1451 /* 1452 * If there's a BPF listener, bounce a copy of this frame 1453 * to him. 1454 */ 1455 if (ifp->if_bpf) 1456 bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 1457 1458 /* 1459 * Transmit the frame. 1460 */ 1461 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 1462 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t))); 1463 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1464 RL_TXTHRESH(sc->rl_txthresh) | 1465 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1466 1467 RL_INC(sc->rl_cdata.cur_tx); 1468 } 1469 1470 /* 1471 * We broke out of the loop because all our TX slots are 1472 * full. Mark the NIC as busy until it drains some of the 1473 * packets from the queue. 1474 */ 1475 if (RL_CUR_TXMBUF(sc) != NULL) 1476 ifp->if_flags |= IFF_OACTIVE; 1477 1478 /* 1479 * Set a timeout in case the chip goes out to lunch. 1480 */ 1481 ifp->if_timer = 5; 1482 1483 return; 1484 } 1485 1486 static void rl_init(xsc) 1487 void *xsc; 1488 { 1489 struct rl_softc *sc = xsc; 1490 struct ifnet *ifp = &sc->arpcom.ac_if; 1491 struct mii_data *mii; 1492 int s, i; 1493 u_int32_t rxcfg = 0; 1494 1495 s = splimp(); 1496 1497 mii = device_get_softc(sc->rl_miibus); 1498 1499 /* 1500 * Cancel pending I/O and free all RX/TX buffers. 1501 */ 1502 rl_stop(sc); 1503 1504 /* Init our MAC address */ 1505 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1506 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1507 } 1508 1509 /* Init the RX buffer pointer register. */ 1510 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); 1511 1512 /* Init TX descriptors. */ 1513 rl_list_tx_init(sc); 1514 1515 /* 1516 * Enable transmit and receive. 1517 */ 1518 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1519 1520 /* 1521 * Set the initial TX and RX configuration. 1522 */ 1523 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1524 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1525 1526 /* Set the individual bit to receive frames for this host only. */ 1527 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1528 rxcfg |= RL_RXCFG_RX_INDIV; 1529 1530 /* If we want promiscuous mode, set the allframes bit. */ 1531 if (ifp->if_flags & IFF_PROMISC) { 1532 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1533 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1534 } else { 1535 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1536 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1537 } 1538 1539 /* 1540 * Set capture broadcast bit to capture broadcast frames. 1541 */ 1542 if (ifp->if_flags & IFF_BROADCAST) { 1543 rxcfg |= RL_RXCFG_RX_BROAD; 1544 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1545 } else { 1546 rxcfg &= ~RL_RXCFG_RX_BROAD; 1547 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1548 } 1549 1550 /* 1551 * Program the multicast filter, if necessary. 1552 */ 1553 rl_setmulti(sc); 1554 1555 #ifdef DEVICE_POLLING 1556 /* 1557 * Disable interrupts if we are polling. 1558 */ 1559 if (ifp->if_ipending & IFF_POLLING) 1560 CSR_WRITE_2(sc, RL_IMR, 0); 1561 else 1562 #endif /* DEVICE_POLLING */ 1563 /* 1564 * Enable interrupts. 1565 */ 1566 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1567 1568 /* Set initial TX threshold */ 1569 sc->rl_txthresh = RL_TX_THRESH_INIT; 1570 1571 /* Start RX/TX process. */ 1572 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1573 1574 /* Enable receiver and transmitter. */ 1575 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1576 1577 mii_mediachg(mii); 1578 1579 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1580 1581 ifp->if_flags |= IFF_RUNNING; 1582 ifp->if_flags &= ~IFF_OACTIVE; 1583 1584 (void)splx(s); 1585 1586 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1587 1588 return; 1589 } 1590 1591 /* 1592 * Set media options. 1593 */ 1594 static int rl_ifmedia_upd(ifp) 1595 struct ifnet *ifp; 1596 { 1597 struct rl_softc *sc; 1598 struct mii_data *mii; 1599 1600 sc = ifp->if_softc; 1601 mii = device_get_softc(sc->rl_miibus); 1602 mii_mediachg(mii); 1603 1604 return(0); 1605 } 1606 1607 /* 1608 * Report current media status. 1609 */ 1610 static void rl_ifmedia_sts(ifp, ifmr) 1611 struct ifnet *ifp; 1612 struct ifmediareq *ifmr; 1613 { 1614 struct rl_softc *sc; 1615 struct mii_data *mii; 1616 1617 sc = ifp->if_softc; 1618 mii = device_get_softc(sc->rl_miibus); 1619 1620 mii_pollstat(mii); 1621 ifmr->ifm_active = mii->mii_media_active; 1622 ifmr->ifm_status = mii->mii_media_status; 1623 1624 return; 1625 } 1626 1627 static int rl_ioctl(ifp, command, data) 1628 struct ifnet *ifp; 1629 u_long command; 1630 caddr_t data; 1631 { 1632 struct rl_softc *sc = ifp->if_softc; 1633 struct ifreq *ifr = (struct ifreq *) data; 1634 struct mii_data *mii; 1635 int s, error = 0; 1636 1637 s = splimp(); 1638 1639 switch(command) { 1640 case SIOCSIFADDR: 1641 case SIOCGIFADDR: 1642 case SIOCSIFMTU: 1643 error = ether_ioctl(ifp, command, data); 1644 break; 1645 case SIOCSIFFLAGS: 1646 if (ifp->if_flags & IFF_UP) { 1647 rl_init(sc); 1648 } else { 1649 if (ifp->if_flags & IFF_RUNNING) 1650 rl_stop(sc); 1651 } 1652 error = 0; 1653 break; 1654 case SIOCADDMULTI: 1655 case SIOCDELMULTI: 1656 rl_setmulti(sc); 1657 error = 0; 1658 break; 1659 case SIOCGIFMEDIA: 1660 case SIOCSIFMEDIA: 1661 mii = device_get_softc(sc->rl_miibus); 1662 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1663 break; 1664 case SIOCSIFCAP: 1665 ifp->if_capenable = ifr->ifr_reqcap; 1666 break; 1667 default: 1668 error = EINVAL; 1669 break; 1670 } 1671 1672 (void)splx(s); 1673 1674 return(error); 1675 } 1676 1677 static void rl_watchdog(ifp) 1678 struct ifnet *ifp; 1679 { 1680 struct rl_softc *sc; 1681 1682 sc = ifp->if_softc; 1683 1684 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1685 ifp->if_oerrors++; 1686 1687 rl_txeof(sc); 1688 rl_rxeof(sc); 1689 rl_init(sc); 1690 1691 return; 1692 } 1693 1694 /* 1695 * Stop the adapter and free any mbufs allocated to the 1696 * RX and TX lists. 1697 */ 1698 static void rl_stop(sc) 1699 struct rl_softc *sc; 1700 { 1701 register int i; 1702 struct ifnet *ifp; 1703 1704 ifp = &sc->arpcom.ac_if; 1705 ifp->if_timer = 0; 1706 1707 untimeout(rl_tick, sc, sc->rl_stat_ch); 1708 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1709 #ifdef DEVICE_POLLING 1710 ether_poll_deregister(ifp); 1711 #endif /* DEVICE_POLLING */ 1712 1713 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1714 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1715 1716 /* 1717 * Free the TX list buffers. 1718 */ 1719 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1720 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1721 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1722 sc->rl_cdata.rl_tx_chain[i] = NULL; 1723 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1724 } 1725 } 1726 1727 1728 return; 1729 } 1730 1731 /* 1732 * Stop all chip I/O so that the kernel's probe routines don't 1733 * get confused by errant DMAs when rebooting. 1734 */ 1735 static void rl_shutdown(dev) 1736 device_t dev; 1737 { 1738 struct rl_softc *sc; 1739 1740 sc = device_get_softc(dev); 1741 1742 rl_stop(sc); 1743 1744 return; 1745 } 1746 1747 /* 1748 * Device suspend routine. Stop the interface and save some PCI 1749 * settings in case the BIOS doesn't restore them properly on 1750 * resume. 1751 */ 1752 static int rl_suspend(dev) 1753 device_t dev; 1754 { 1755 register int i; 1756 struct rl_softc *sc; 1757 1758 sc = device_get_softc(dev); 1759 1760 rl_stop(sc); 1761 1762 for (i = 0; i < 5; i++) 1763 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1764 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1765 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1766 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1767 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1768 1769 sc->suspended = 1; 1770 1771 return (0); 1772 } 1773 1774 /* 1775 * Device resume routine. Restore some PCI settings in case the BIOS 1776 * doesn't, re-enable busmastering, and restart the interface if 1777 * appropriate. 1778 */ 1779 static int rl_resume(dev) 1780 device_t dev; 1781 { 1782 register int i; 1783 struct rl_softc *sc; 1784 struct ifnet *ifp; 1785 1786 sc = device_get_softc(dev); 1787 ifp = &sc->arpcom.ac_if; 1788 1789 /* better way to do this? */ 1790 for (i = 0; i < 5; i++) 1791 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1792 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1793 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1794 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1795 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1796 1797 /* reenable busmastering */ 1798 pci_enable_busmaster(dev); 1799 pci_enable_io(dev, RL_RES); 1800 1801 /* reinitialize interface if necessary */ 1802 if (ifp->if_flags & IFF_UP) 1803 rl_init(sc); 1804 1805 sc->suspended = 0; 1806 1807 return (0); 1808 }
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