The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_rl.c

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    1 /*
    2  * Copyright (c) 1997, 1998
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD: releng/5.0/sys/pci/if_rl.c 106936 2002-11-14 23:49:09Z sam $
   33  */
   34 
   35 /*
   36  * RealTek 8129/8139 PCI NIC driver
   37  *
   38  * Supports several extremely cheap PCI 10/100 adapters based on
   39  * the RealTek chipset. Datasheets can be obtained from
   40  * www.realtek.com.tw.
   41  *
   42  * Written by Bill Paul <wpaul@ctr.columbia.edu>
   43  * Electrical Engineering Department
   44  * Columbia University, New York City
   45  */
   46 
   47 /*
   48  * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
   49  * probably the worst PCI ethernet controller ever made, with the possible
   50  * exception of the FEAST chip made by SMC. The 8139 supports bus-master
   51  * DMA, but it has a terrible interface that nullifies any performance
   52  * gains that bus-master DMA usually offers.
   53  *
   54  * For transmission, the chip offers a series of four TX descriptor
   55  * registers. Each transmit frame must be in a contiguous buffer, aligned
   56  * on a longword (32-bit) boundary. This means we almost always have to
   57  * do mbuf copies in order to transmit a frame, except in the unlikely
   58  * case where a) the packet fits into a single mbuf, and b) the packet
   59  * is 32-bit aligned within the mbuf's data area. The presence of only
   60  * four descriptor registers means that we can never have more than four
   61  * packets queued for transmission at any one time.
   62  *
   63  * Reception is not much better. The driver has to allocate a single large
   64  * buffer area (up to 64K in size) into which the chip will DMA received
   65  * frames. Because we don't know where within this region received packets
   66  * will begin or end, we have no choice but to copy data from the buffer
   67  * area into mbufs in order to pass the packets up to the higher protocol
   68  * levels.
   69  *
   70  * It's impossible given this rotten design to really achieve decent
   71  * performance at 100Mbps, unless you happen to have a 400Mhz PII or
   72  * some equally overmuscled CPU to drive it.
   73  *
   74  * On the bright side, the 8139 does have a built-in PHY, although
   75  * rather than using an MDIO serial interface like most other NICs, the
   76  * PHY registers are directly accessible through the 8139's register
   77  * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
   78  * filter.
   79  *
   80  * The 8129 chip is an older version of the 8139 that uses an external PHY
   81  * chip. The 8129 has a serial MDIO interface for accessing the MII where
   82  * the 8139 lets you directly access the on-board PHY registers. We need
   83  * to select which interface to use depending on the chip type.
   84  */
   85 
   86 #include <sys/param.h>
   87 #include <sys/systm.h>
   88 #include <sys/sockio.h>
   89 #include <sys/mbuf.h>
   90 #include <sys/malloc.h>
   91 #include <sys/kernel.h>
   92 #include <sys/socket.h>
   93 
   94 #include <net/if.h>
   95 #include <net/if_arp.h>
   96 #include <net/ethernet.h>
   97 #include <net/if_dl.h>
   98 #include <net/if_media.h>
   99 
  100 #include <net/bpf.h>
  101 
  102 #include <machine/bus_pio.h>
  103 #include <machine/bus_memio.h>
  104 #include <machine/bus.h>
  105 #include <machine/resource.h>
  106 #include <sys/bus.h>
  107 #include <sys/rman.h>
  108 
  109 #include <dev/mii/mii.h>
  110 #include <dev/mii/miivar.h>
  111 
  112 #include <pci/pcireg.h>
  113 #include <pci/pcivar.h>
  114 
  115 MODULE_DEPEND(rl, miibus, 1, 1, 1);
  116 
  117 /* "controller miibus0" required.  See GENERIC if you get errors here. */
  118 #include "miibus_if.h"
  119 
  120 /*
  121  * Default to using PIO access for this driver. On SMP systems,
  122  * there appear to be problems with memory mapped mode: it looks like
  123  * doing too many memory mapped access back to back in rapid succession
  124  * can hang the bus. I'm inclined to blame this on crummy design/construction
  125  * on the part of RealTek. Memory mapped mode does appear to work on
  126  * uniprocessor systems though.
  127  */
  128 #define RL_USEIOSPACE
  129 
  130 #include <pci/if_rlreg.h>
  131 
  132 #ifndef lint
  133 static const char rcsid[] =
  134   "$FreeBSD: releng/5.0/sys/pci/if_rl.c 106936 2002-11-14 23:49:09Z sam $";
  135 #endif
  136 
  137 /*
  138  * Various supported device vendors/types and their names.
  139  */
  140 static struct rl_type rl_devs[] = {
  141         { RT_VENDORID, RT_DEVICEID_8129,
  142                 "RealTek 8129 10/100BaseTX" },
  143         { RT_VENDORID, RT_DEVICEID_8139,
  144                 "RealTek 8139 10/100BaseTX" },
  145         { RT_VENDORID, RT_DEVICEID_8138,
  146                 "RealTek 8139 10/100BaseTX CardBus" },
  147         { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
  148                 "Accton MPX 5030/5038 10/100BaseTX" },
  149         { DELTA_VENDORID, DELTA_DEVICEID_8139,
  150                 "Delta Electronics 8139 10/100BaseTX" },
  151         { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
  152                 "Addtron Technolgy 8139 10/100BaseTX" },
  153         { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS,
  154                 "D-Link DFE-530TX+ 10/100BaseTX" },
  155         { DLINK_VENDORID, DLINK_DEVICEID_690TXD,
  156                 "D-Link DFE-690TXD 10/100BaseTX" },
  157         { NORTEL_VENDORID, ACCTON_DEVICEID_5030,
  158                 "Nortel Networks 10/100BaseTX" },
  159         { COREGA_VENDORID, COREGA_DEVICEID_CBTXD,
  160                 "Corega FEther CB-TXD" },
  161         { 0, 0, NULL }
  162 };
  163 
  164 static int rl_probe             (device_t);
  165 static int rl_attach            (device_t);
  166 static int rl_detach            (device_t);
  167 
  168 static int rl_encap             (struct rl_softc *, struct mbuf * );
  169 
  170 static void rl_rxeof            (struct rl_softc *);
  171 static void rl_txeof            (struct rl_softc *);
  172 static void rl_intr             (void *);
  173 static void rl_tick             (void *);
  174 static void rl_start            (struct ifnet *);
  175 static int rl_ioctl             (struct ifnet *, u_long, caddr_t);
  176 static void rl_init             (void *);
  177 static void rl_stop             (struct rl_softc *);
  178 static void rl_watchdog         (struct ifnet *);
  179 static int rl_suspend           (device_t);
  180 static int rl_resume            (device_t);
  181 static void rl_shutdown         (device_t);
  182 static int rl_ifmedia_upd       (struct ifnet *);
  183 static void rl_ifmedia_sts      (struct ifnet *, struct ifmediareq *);
  184 
  185 static void rl_eeprom_putbyte   (struct rl_softc *, int);
  186 static void rl_eeprom_getword   (struct rl_softc *, int, u_int16_t *);
  187 static void rl_read_eeprom      (struct rl_softc *, caddr_t, int, int, int);
  188 static void rl_mii_sync         (struct rl_softc *);
  189 static void rl_mii_send         (struct rl_softc *, u_int32_t, int);
  190 static int rl_mii_readreg       (struct rl_softc *, struct rl_mii_frame *);
  191 static int rl_mii_writereg      (struct rl_softc *, struct rl_mii_frame *);
  192 
  193 static int rl_miibus_readreg    (device_t, int, int);
  194 static int rl_miibus_writereg   (device_t, int, int, int);
  195 static void rl_miibus_statchg   (device_t);
  196 
  197 static u_int8_t rl_calchash     (caddr_t);
  198 static void rl_setmulti         (struct rl_softc *);
  199 static void rl_reset            (struct rl_softc *);
  200 static int rl_list_tx_init      (struct rl_softc *);
  201 
  202 static void rl_dma_map_rxbuf    (void *, bus_dma_segment_t *, int, int);
  203 static void rl_dma_map_txbuf    (void *, bus_dma_segment_t *, int, int);
  204 
  205 #ifdef RL_USEIOSPACE
  206 #define RL_RES                  SYS_RES_IOPORT
  207 #define RL_RID                  RL_PCI_LOIO
  208 #else
  209 #define RL_RES                  SYS_RES_MEMORY
  210 #define RL_RID                  RL_PCI_LOMEM
  211 #endif
  212 
  213 static device_method_t rl_methods[] = {
  214         /* Device interface */
  215         DEVMETHOD(device_probe,         rl_probe),
  216         DEVMETHOD(device_attach,        rl_attach),
  217         DEVMETHOD(device_detach,        rl_detach),
  218         DEVMETHOD(device_suspend,       rl_suspend),
  219         DEVMETHOD(device_resume,        rl_resume),
  220         DEVMETHOD(device_shutdown,      rl_shutdown),
  221 
  222         /* bus interface */
  223         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  224         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
  225 
  226         /* MII interface */
  227         DEVMETHOD(miibus_readreg,       rl_miibus_readreg),
  228         DEVMETHOD(miibus_writereg,      rl_miibus_writereg),
  229         DEVMETHOD(miibus_statchg,       rl_miibus_statchg),
  230 
  231         { 0, 0 }
  232 };
  233 
  234 static driver_t rl_driver = {
  235         "rl",
  236         rl_methods,
  237         sizeof(struct rl_softc)
  238 };
  239 
  240 static devclass_t rl_devclass;
  241 
  242 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
  243 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0);
  244 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
  245 
  246 #define EE_SET(x)                                       \
  247         CSR_WRITE_1(sc, RL_EECMD,                       \
  248                 CSR_READ_1(sc, RL_EECMD) | x)
  249 
  250 #define EE_CLR(x)                                       \
  251         CSR_WRITE_1(sc, RL_EECMD,                       \
  252                 CSR_READ_1(sc, RL_EECMD) & ~x)
  253 
  254 static void
  255 rl_dma_map_rxbuf(arg, segs, nseg, error)
  256         void *arg;
  257         bus_dma_segment_t *segs;
  258         int nseg, error;
  259 {
  260         struct rl_softc *sc;
  261 
  262         sc = arg;
  263         CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
  264 
  265         return;
  266 }
  267 
  268 static void
  269 rl_dma_map_txbuf(arg, segs, nseg, error)
  270         void *arg;
  271         bus_dma_segment_t *segs;
  272         int nseg, error;
  273 {
  274         struct rl_softc *sc;
  275 
  276         sc = arg;
  277         CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
  278 
  279         return;
  280 }
  281 
  282 /*
  283  * Send a read command and address to the EEPROM, check for ACK.
  284  */
  285 static void
  286 rl_eeprom_putbyte(sc, addr)
  287         struct rl_softc         *sc;
  288         int                     addr;
  289 {
  290         register int            d, i;
  291 
  292         d = addr | sc->rl_eecmd_read;
  293 
  294         /*
  295          * Feed in each bit and strobe the clock.
  296          */
  297         for (i = 0x400; i; i >>= 1) {
  298                 if (d & i) {
  299                         EE_SET(RL_EE_DATAIN);
  300                 } else {
  301                         EE_CLR(RL_EE_DATAIN);
  302                 }
  303                 DELAY(100);
  304                 EE_SET(RL_EE_CLK);
  305                 DELAY(150);
  306                 EE_CLR(RL_EE_CLK);
  307                 DELAY(100);
  308         }
  309 
  310         return;
  311 }
  312 
  313 /*
  314  * Read a word of data stored in the EEPROM at address 'addr.'
  315  */
  316 static void
  317 rl_eeprom_getword(sc, addr, dest)
  318         struct rl_softc         *sc;
  319         int                     addr;
  320         u_int16_t               *dest;
  321 {
  322         register int            i;
  323         u_int16_t               word = 0;
  324 
  325         /* Enter EEPROM access mode. */
  326         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
  327 
  328         /*
  329          * Send address of word we want to read.
  330          */
  331         rl_eeprom_putbyte(sc, addr);
  332 
  333         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
  334 
  335         /*
  336          * Start reading bits from EEPROM.
  337          */
  338         for (i = 0x8000; i; i >>= 1) {
  339                 EE_SET(RL_EE_CLK);
  340                 DELAY(100);
  341                 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
  342                         word |= i;
  343                 EE_CLR(RL_EE_CLK);
  344                 DELAY(100);
  345         }
  346 
  347         /* Turn off EEPROM access mode. */
  348         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
  349 
  350         *dest = word;
  351 
  352         return;
  353 }
  354 
  355 /*
  356  * Read a sequence of words from the EEPROM.
  357  */
  358 static void
  359 rl_read_eeprom(sc, dest, off, cnt, swap)
  360         struct rl_softc         *sc;
  361         caddr_t                 dest;
  362         int                     off;
  363         int                     cnt;
  364         int                     swap;
  365 {
  366         int                     i;
  367         u_int16_t               word = 0, *ptr;
  368 
  369         for (i = 0; i < cnt; i++) {
  370                 rl_eeprom_getword(sc, off + i, &word);
  371                 ptr = (u_int16_t *)(dest + (i * 2));
  372                 if (swap)
  373                         *ptr = ntohs(word);
  374                 else
  375                         *ptr = word;
  376         }
  377 
  378         return;
  379 }
  380 
  381 
  382 /*
  383  * MII access routines are provided for the 8129, which
  384  * doesn't have a built-in PHY. For the 8139, we fake things
  385  * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
  386  * direct access PHY registers.
  387  */
  388 #define MII_SET(x)                                      \
  389         CSR_WRITE_1(sc, RL_MII,                         \
  390                 CSR_READ_1(sc, RL_MII) | (x))
  391 
  392 #define MII_CLR(x)                                      \
  393         CSR_WRITE_1(sc, RL_MII,                         \
  394                 CSR_READ_1(sc, RL_MII) & ~(x))
  395 
  396 /*
  397  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  398  */
  399 static void
  400 rl_mii_sync(sc)
  401         struct rl_softc         *sc;
  402 {
  403         register int            i;
  404 
  405         MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
  406 
  407         for (i = 0; i < 32; i++) {
  408                 MII_SET(RL_MII_CLK);
  409                 DELAY(1);
  410                 MII_CLR(RL_MII_CLK);
  411                 DELAY(1);
  412         }
  413 
  414         return;
  415 }
  416 
  417 /*
  418  * Clock a series of bits through the MII.
  419  */
  420 static void
  421 rl_mii_send(sc, bits, cnt)
  422         struct rl_softc         *sc;
  423         u_int32_t               bits;
  424         int                     cnt;
  425 {
  426         int                     i;
  427 
  428         MII_CLR(RL_MII_CLK);
  429 
  430         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  431                 if (bits & i) {
  432                         MII_SET(RL_MII_DATAOUT);
  433                 } else {
  434                         MII_CLR(RL_MII_DATAOUT);
  435                 }
  436                 DELAY(1);
  437                 MII_CLR(RL_MII_CLK);
  438                 DELAY(1);
  439                 MII_SET(RL_MII_CLK);
  440         }
  441 }
  442 
  443 /*
  444  * Read an PHY register through the MII.
  445  */
  446 static int
  447 rl_mii_readreg(sc, frame)
  448         struct rl_softc         *sc;
  449         struct rl_mii_frame     *frame;
  450         
  451 {
  452         int                     i, ack;
  453 
  454         RL_LOCK(sc);
  455 
  456         /*
  457          * Set up frame for RX.
  458          */
  459         frame->mii_stdelim = RL_MII_STARTDELIM;
  460         frame->mii_opcode = RL_MII_READOP;
  461         frame->mii_turnaround = 0;
  462         frame->mii_data = 0;
  463         
  464         CSR_WRITE_2(sc, RL_MII, 0);
  465 
  466         /*
  467          * Turn on data xmit.
  468          */
  469         MII_SET(RL_MII_DIR);
  470 
  471         rl_mii_sync(sc);
  472 
  473         /*
  474          * Send command/address info.
  475          */
  476         rl_mii_send(sc, frame->mii_stdelim, 2);
  477         rl_mii_send(sc, frame->mii_opcode, 2);
  478         rl_mii_send(sc, frame->mii_phyaddr, 5);
  479         rl_mii_send(sc, frame->mii_regaddr, 5);
  480 
  481         /* Idle bit */
  482         MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
  483         DELAY(1);
  484         MII_SET(RL_MII_CLK);
  485         DELAY(1);
  486 
  487         /* Turn off xmit. */
  488         MII_CLR(RL_MII_DIR);
  489 
  490         /* Check for ack */
  491         MII_CLR(RL_MII_CLK);
  492         DELAY(1);
  493         MII_SET(RL_MII_CLK);
  494         DELAY(1);
  495         ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
  496 
  497         /*
  498          * Now try reading data bits. If the ack failed, we still
  499          * need to clock through 16 cycles to keep the PHY(s) in sync.
  500          */
  501         if (ack) {
  502                 for(i = 0; i < 16; i++) {
  503                         MII_CLR(RL_MII_CLK);
  504                         DELAY(1);
  505                         MII_SET(RL_MII_CLK);
  506                         DELAY(1);
  507                 }
  508                 goto fail;
  509         }
  510 
  511         for (i = 0x8000; i; i >>= 1) {
  512                 MII_CLR(RL_MII_CLK);
  513                 DELAY(1);
  514                 if (!ack) {
  515                         if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
  516                                 frame->mii_data |= i;
  517                         DELAY(1);
  518                 }
  519                 MII_SET(RL_MII_CLK);
  520                 DELAY(1);
  521         }
  522 
  523 fail:
  524 
  525         MII_CLR(RL_MII_CLK);
  526         DELAY(1);
  527         MII_SET(RL_MII_CLK);
  528         DELAY(1);
  529 
  530         RL_UNLOCK(sc);
  531 
  532         if (ack)
  533                 return(1);
  534         return(0);
  535 }
  536 
  537 /*
  538  * Write to a PHY register through the MII.
  539  */
  540 static int
  541 rl_mii_writereg(sc, frame)
  542         struct rl_softc         *sc;
  543         struct rl_mii_frame     *frame;
  544         
  545 {
  546         RL_LOCK(sc);
  547 
  548         /*
  549          * Set up frame for TX.
  550          */
  551 
  552         frame->mii_stdelim = RL_MII_STARTDELIM;
  553         frame->mii_opcode = RL_MII_WRITEOP;
  554         frame->mii_turnaround = RL_MII_TURNAROUND;
  555         
  556         /*
  557          * Turn on data output.
  558          */
  559         MII_SET(RL_MII_DIR);
  560 
  561         rl_mii_sync(sc);
  562 
  563         rl_mii_send(sc, frame->mii_stdelim, 2);
  564         rl_mii_send(sc, frame->mii_opcode, 2);
  565         rl_mii_send(sc, frame->mii_phyaddr, 5);
  566         rl_mii_send(sc, frame->mii_regaddr, 5);
  567         rl_mii_send(sc, frame->mii_turnaround, 2);
  568         rl_mii_send(sc, frame->mii_data, 16);
  569 
  570         /* Idle bit. */
  571         MII_SET(RL_MII_CLK);
  572         DELAY(1);
  573         MII_CLR(RL_MII_CLK);
  574         DELAY(1);
  575 
  576         /*
  577          * Turn off xmit.
  578          */
  579         MII_CLR(RL_MII_DIR);
  580 
  581         RL_UNLOCK(sc);
  582 
  583         return(0);
  584 }
  585 
  586 static int
  587 rl_miibus_readreg(dev, phy, reg)
  588         device_t                dev;
  589         int                     phy, reg;
  590 {
  591         struct rl_softc         *sc;
  592         struct rl_mii_frame     frame;
  593         u_int16_t               rval = 0;
  594         u_int16_t               rl8139_reg = 0;
  595 
  596         sc = device_get_softc(dev);
  597         RL_LOCK(sc);
  598 
  599         if (sc->rl_type == RL_8139) {
  600                 /* Pretend the internal PHY is only at address 0 */
  601                 if (phy) {
  602                         RL_UNLOCK(sc);
  603                         return(0);
  604                 }
  605                 switch(reg) {
  606                 case MII_BMCR:
  607                         rl8139_reg = RL_BMCR;
  608                         break;
  609                 case MII_BMSR:
  610                         rl8139_reg = RL_BMSR;
  611                         break;
  612                 case MII_ANAR:
  613                         rl8139_reg = RL_ANAR;
  614                         break;
  615                 case MII_ANER:
  616                         rl8139_reg = RL_ANER;
  617                         break;
  618                 case MII_ANLPAR:
  619                         rl8139_reg = RL_LPAR;
  620                         break;
  621                 case MII_PHYIDR1:
  622                 case MII_PHYIDR2:
  623                         RL_UNLOCK(sc);
  624                         return(0);
  625                         break;
  626                 /*
  627                  * Allow the rlphy driver to read the media status
  628                  * register. If we have a link partner which does not
  629                  * support NWAY, this is the register which will tell
  630                  * us the results of parallel detection.
  631                  */
  632                 case RL_MEDIASTAT:
  633                         rval = CSR_READ_1(sc, RL_MEDIASTAT);
  634                         RL_UNLOCK(sc);
  635                         return(rval);
  636                         break;
  637                 default:
  638                         printf("rl%d: bad phy register\n", sc->rl_unit);
  639                         RL_UNLOCK(sc);
  640                         return(0);
  641                 }
  642                 rval = CSR_READ_2(sc, rl8139_reg);
  643                 RL_UNLOCK(sc);
  644                 return(rval);
  645         }
  646 
  647         bzero((char *)&frame, sizeof(frame));
  648 
  649         frame.mii_phyaddr = phy;
  650         frame.mii_regaddr = reg;
  651         rl_mii_readreg(sc, &frame);
  652         RL_UNLOCK(sc);
  653 
  654         return(frame.mii_data);
  655 }
  656 
  657 static int
  658 rl_miibus_writereg(dev, phy, reg, data)
  659         device_t                dev;
  660         int                     phy, reg, data;
  661 {
  662         struct rl_softc         *sc;
  663         struct rl_mii_frame     frame;
  664         u_int16_t               rl8139_reg = 0;
  665 
  666         sc = device_get_softc(dev);
  667         RL_LOCK(sc);
  668 
  669         if (sc->rl_type == RL_8139) {
  670                 /* Pretend the internal PHY is only at address 0 */
  671                 if (phy) {
  672                         RL_UNLOCK(sc);
  673                         return(0);
  674                 }
  675                 switch(reg) {
  676                 case MII_BMCR:
  677                         rl8139_reg = RL_BMCR;
  678                         break;
  679                 case MII_BMSR:
  680                         rl8139_reg = RL_BMSR;
  681                         break;
  682                 case MII_ANAR:
  683                         rl8139_reg = RL_ANAR;
  684                         break;
  685                 case MII_ANER:
  686                         rl8139_reg = RL_ANER;
  687                         break;
  688                 case MII_ANLPAR:
  689                         rl8139_reg = RL_LPAR;
  690                         break;
  691                 case MII_PHYIDR1:
  692                 case MII_PHYIDR2:
  693                         RL_UNLOCK(sc);
  694                         return(0);
  695                         break;
  696                 default:
  697                         printf("rl%d: bad phy register\n", sc->rl_unit);
  698                         RL_UNLOCK(sc);
  699                         return(0);
  700                 }
  701                 CSR_WRITE_2(sc, rl8139_reg, data);
  702                 RL_UNLOCK(sc);
  703                 return(0);
  704         }
  705 
  706         bzero((char *)&frame, sizeof(frame));
  707 
  708         frame.mii_phyaddr = phy;
  709         frame.mii_regaddr = reg;
  710         frame.mii_data = data;
  711 
  712         rl_mii_writereg(sc, &frame);
  713 
  714         RL_UNLOCK(sc);
  715         return(0);
  716 }
  717 
  718 static void
  719 rl_miibus_statchg(dev)
  720         device_t                dev;
  721 {
  722         return;
  723 }
  724 
  725 /*
  726  * Calculate CRC of a multicast group address, return the upper 6 bits.
  727  */
  728 static u_int8_t
  729 rl_calchash(addr)
  730         caddr_t                 addr;
  731 {
  732         u_int32_t               crc, carry;
  733         int                     i, j;
  734         u_int8_t                c;
  735 
  736         /* Compute CRC for the address value. */
  737         crc = 0xFFFFFFFF; /* initial value */
  738 
  739         for (i = 0; i < 6; i++) {
  740                 c = *(addr + i);
  741                 for (j = 0; j < 8; j++) {
  742                         carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
  743                         crc <<= 1;
  744                         c >>= 1;
  745                         if (carry)
  746                                 crc = (crc ^ 0x04c11db6) | carry;
  747                 }
  748         }
  749 
  750         /* return the filter bit position */
  751         return(crc >> 26);
  752 }
  753 
  754 /*
  755  * Program the 64-bit multicast hash filter.
  756  */
  757 static void
  758 rl_setmulti(sc)
  759         struct rl_softc         *sc;
  760 {
  761         struct ifnet            *ifp;
  762         int                     h = 0;
  763         u_int32_t               hashes[2] = { 0, 0 };
  764         struct ifmultiaddr      *ifma;
  765         u_int32_t               rxfilt;
  766         int                     mcnt = 0;
  767 
  768         ifp = &sc->arpcom.ac_if;
  769 
  770         rxfilt = CSR_READ_4(sc, RL_RXCFG);
  771 
  772         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
  773                 rxfilt |= RL_RXCFG_RX_MULTI;
  774                 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
  775                 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
  776                 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
  777                 return;
  778         }
  779 
  780         /* first, zot all the existing hash bits */
  781         CSR_WRITE_4(sc, RL_MAR0, 0);
  782         CSR_WRITE_4(sc, RL_MAR4, 0);
  783 
  784         /* now program new ones */
  785         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
  786                 if (ifma->ifma_addr->sa_family != AF_LINK)
  787                         continue;
  788                 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
  789                 if (h < 32)
  790                         hashes[0] |= (1 << h);
  791                 else
  792                         hashes[1] |= (1 << (h - 32));
  793                 mcnt++;
  794         }
  795 
  796         if (mcnt)
  797                 rxfilt |= RL_RXCFG_RX_MULTI;
  798         else
  799                 rxfilt &= ~RL_RXCFG_RX_MULTI;
  800 
  801         CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
  802         CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
  803         CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
  804 
  805         return;
  806 }
  807 
  808 static void
  809 rl_reset(sc)
  810         struct rl_softc         *sc;
  811 {
  812         register int            i;
  813 
  814         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
  815 
  816         for (i = 0; i < RL_TIMEOUT; i++) {
  817                 DELAY(10);
  818                 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
  819                         break;
  820         }
  821         if (i == RL_TIMEOUT)
  822                 printf("rl%d: reset never completed!\n", sc->rl_unit);
  823 
  824         return;
  825 }
  826 
  827 /*
  828  * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
  829  * IDs against our list and return a device name if we find a match.
  830  */
  831 static int
  832 rl_probe(dev)
  833         device_t                dev;
  834 {
  835         struct rl_type          *t;
  836 
  837         t = rl_devs;
  838 
  839         while(t->rl_name != NULL) {
  840                 if ((pci_get_vendor(dev) == t->rl_vid) &&
  841                     (pci_get_device(dev) == t->rl_did)) {
  842                         device_set_desc(dev, t->rl_name);
  843                         return(0);
  844                 }
  845                 t++;
  846         }
  847 
  848         return(ENXIO);
  849 }
  850 
  851 /*
  852  * Attach the interface. Allocate softc structures, do ifmedia
  853  * setup and ethernet/BPF attach.
  854  */
  855 static int
  856 rl_attach(dev)
  857         device_t                dev;
  858 {
  859         u_char                  eaddr[ETHER_ADDR_LEN];
  860         u_int32_t               command;
  861         struct rl_softc         *sc;
  862         struct ifnet            *ifp;
  863         u_int16_t               rl_did = 0;
  864         int                     unit, error = 0, rid;
  865 
  866         sc = device_get_softc(dev);
  867         unit = device_get_unit(dev);
  868         bzero(sc, sizeof(struct rl_softc));
  869 
  870         mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
  871             MTX_DEF | MTX_RECURSE);
  872 
  873         /*
  874          * Handle power management nonsense.
  875          */
  876 
  877         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
  878                 u_int32_t               iobase, membase, irq;
  879 
  880                 /* Save important PCI config data. */
  881                 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
  882                 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
  883                 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
  884 
  885                 /* Reset the power state. */
  886                 printf("rl%d: chip is is in D%d power mode "
  887                     "-- setting to D0\n", unit,
  888                     pci_get_powerstate(dev));
  889 
  890                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
  891 
  892                 /* Restore PCI config data. */
  893                 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
  894                 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
  895                 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
  896         }
  897 
  898         /*
  899          * Map control/status registers.
  900          */
  901         pci_enable_busmaster(dev);
  902         pci_enable_io(dev, SYS_RES_IOPORT);
  903         pci_enable_io(dev, SYS_RES_MEMORY);
  904         command = pci_read_config(dev, PCIR_COMMAND, 4);
  905 
  906 #ifdef RL_USEIOSPACE
  907         if (!(command & PCIM_CMD_PORTEN)) {
  908                 printf("rl%d: failed to enable I/O ports!\n", unit);
  909                 error = ENXIO;
  910                 goto fail;
  911         }
  912 #else
  913         if (!(command & PCIM_CMD_MEMEN)) {
  914                 printf("rl%d: failed to enable memory mapping!\n", unit);
  915                 error = ENXIO;
  916                 goto fail;
  917         }
  918 #endif
  919 
  920         rid = RL_RID; 
  921         sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
  922             0, ~0, 1, RF_ACTIVE);
  923 
  924         if (sc->rl_res == NULL) {
  925                 printf ("rl%d: couldn't map ports/memory\n", unit);
  926                 error = ENXIO;
  927                 goto fail;
  928         }
  929 
  930         /* Detect the Realtek 8139B. For some reason, this chip is very
  931          * unstable when left to autoselect the media
  932          * The best workaround is to set the device to the required
  933          * media type or to set it to the 10 Meg speed.
  934          */
  935 
  936         if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) {
  937                 printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit);
  938         }
  939 
  940         sc->rl_btag = rman_get_bustag(sc->rl_res);
  941         sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
  942 
  943         rid = 0;
  944         sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
  945             RF_SHAREABLE | RF_ACTIVE);
  946 
  947         if (sc->rl_irq == NULL) {
  948                 printf("rl%d: couldn't map interrupt\n", unit);
  949                 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
  950                 error = ENXIO;
  951                 goto fail;
  952         }
  953 
  954         /* Reset the adapter. */
  955         rl_reset(sc);
  956         sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
  957         rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0);
  958         if (rl_did != 0x8129)
  959                 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
  960 
  961         /*
  962          * Get station address from the EEPROM.
  963          */
  964         rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
  965 
  966         /*
  967          * A RealTek chip was detected. Inform the world.
  968          */
  969         printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
  970 
  971         sc->rl_unit = unit;
  972         bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
  973 
  974         /*
  975          * Now read the exact device type from the EEPROM to find
  976          * out if it's an 8129 or 8139.
  977          */
  978         rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
  979 
  980         if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
  981             rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
  982             rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS ||
  983             rl_did == DLINK_DEVICEID_690TXD || rl_did == COREGA_DEVICEID_CBTXD)
  984                 sc->rl_type = RL_8139;
  985         else if (rl_did == RT_DEVICEID_8129)
  986                 sc->rl_type = RL_8129;
  987         else {
  988                 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
  989                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
  990                 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
  991                 error = ENXIO;
  992                 goto fail;
  993         }
  994 
  995         /*
  996          * Allocate the parent bus DMA tag appropriate for PCI.
  997          */
  998 #define RL_NSEG_NEW 32
  999         error = bus_dma_tag_create(NULL,        /* parent */ 
 1000                         1, 0,                   /* alignment, boundary */
 1001                         BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
 1002                         BUS_SPACE_MAXADDR,      /* highaddr */
 1003                         NULL, NULL,             /* filter, filterarg */
 1004                         MAXBSIZE, RL_NSEG_NEW,  /* maxsize, nsegments */
 1005                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 
 1006                         BUS_DMA_ALLOCNOW,       /* flags */
 1007                         &sc->rl_parent_tag);
 1008 
 1009         /*
 1010          * Now allocate a tag for the DMA descriptor lists.
 1011          * All of our lists are allocated as a contiguous block
 1012          * of memory.
 1013          */
 1014         error = bus_dma_tag_create(sc->rl_parent_tag,   /* parent */
 1015                         1, 0,                   /* alignment, boundary */
 1016                         BUS_SPACE_MAXADDR,      /* lowaddr */
 1017                         BUS_SPACE_MAXADDR,      /* highaddr */
 1018                         NULL, NULL,             /* filter, filterarg */
 1019                         RL_RXBUFLEN + 1518, 1,  /* maxsize,nsegments */
 1020                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
 1021                         0,                      /* flags */
 1022                         &sc->rl_tag);
 1023 
 1024         /*
 1025          * Now allocate a chunk of DMA-able memory based on the
 1026          * tag we just created.
 1027          */
 1028         error = bus_dmamem_alloc(sc->rl_tag,
 1029             (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT,
 1030             &sc->rl_cdata.rl_rx_dmamap);
 1031 
 1032         if (sc->rl_cdata.rl_rx_buf == NULL) {
 1033                 printf("rl%d: no memory for list buffers!\n", unit);
 1034                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
 1035                 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
 1036                 bus_dma_tag_destroy(sc->rl_tag);
 1037                 error = ENXIO;
 1038                 goto fail;
 1039         }
 1040 
 1041         /* Leave a few bytes before the start of the RX ring buffer. */
 1042         sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
 1043         sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
 1044 
 1045         /* Do MII setup */
 1046         if (mii_phy_probe(dev, &sc->rl_miibus,
 1047             rl_ifmedia_upd, rl_ifmedia_sts)) {
 1048                 printf("rl%d: MII without any phy!\n", sc->rl_unit);
 1049                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
 1050                 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
 1051                 bus_dmamem_free(sc->rl_tag,
 1052                     sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap);
 1053                 bus_dma_tag_destroy(sc->rl_tag);
 1054                 error = ENXIO;
 1055                 goto fail;
 1056         }
 1057 
 1058         ifp = &sc->arpcom.ac_if;
 1059         ifp->if_softc = sc;
 1060         ifp->if_unit = unit;
 1061         ifp->if_name = "rl";
 1062         ifp->if_mtu = ETHERMTU;
 1063         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 1064         ifp->if_ioctl = rl_ioctl;
 1065         ifp->if_output = ether_output;
 1066         ifp->if_start = rl_start;
 1067         ifp->if_watchdog = rl_watchdog;
 1068         ifp->if_init = rl_init;
 1069         ifp->if_baudrate = 10000000;
 1070         ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
 1071 
 1072         /*
 1073          * Call MI attach routine.
 1074          */
 1075         ether_ifattach(ifp, eaddr);
 1076 
 1077         error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
 1078             rl_intr, sc, &sc->rl_intrhand);
 1079 
 1080         if (error) {
 1081                 printf("rl%d: couldn't set up irq\n", unit);
 1082                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
 1083                 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
 1084                 bus_dmamem_free(sc->rl_tag,
 1085                     sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap);
 1086                 bus_dma_tag_destroy(sc->rl_tag);
 1087                 goto fail;
 1088         }
 1089 
 1090         callout_handle_init(&sc->rl_stat_ch);
 1091         return(0);
 1092 fail:
 1093         mtx_destroy(&sc->rl_mtx);
 1094         return(error);
 1095 }
 1096 
 1097 static int
 1098 rl_detach(dev)
 1099         device_t                dev;
 1100 {
 1101         struct rl_softc         *sc;
 1102         struct ifnet            *ifp;
 1103 
 1104         sc = device_get_softc(dev);
 1105         RL_LOCK(sc);
 1106         ifp = &sc->arpcom.ac_if;
 1107 
 1108         ether_ifdetach(ifp);
 1109         rl_stop(sc);
 1110 
 1111         bus_generic_detach(dev);
 1112         device_delete_child(dev, sc->rl_miibus);
 1113 
 1114         bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
 1115         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
 1116         bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
 1117 
 1118         bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
 1119         bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
 1120             sc->rl_cdata.rl_rx_dmamap);
 1121         bus_dma_tag_destroy(sc->rl_tag);
 1122         bus_dma_tag_destroy(sc->rl_parent_tag);
 1123 
 1124         RL_UNLOCK(sc);
 1125         mtx_destroy(&sc->rl_mtx);
 1126 
 1127         return(0);
 1128 }
 1129 
 1130 /*
 1131  * Initialize the transmit descriptors.
 1132  */
 1133 static int
 1134 rl_list_tx_init(sc)
 1135         struct rl_softc         *sc;
 1136 {
 1137         struct rl_chain_data    *cd;
 1138         int                     i;
 1139 
 1140         cd = &sc->rl_cdata;
 1141         for (i = 0; i < RL_TX_LIST_CNT; i++) {
 1142                 cd->rl_tx_chain[i] = NULL;
 1143                 CSR_WRITE_4(sc,
 1144                     RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
 1145         }
 1146 
 1147         sc->rl_cdata.cur_tx = 0;
 1148         sc->rl_cdata.last_tx = 0;
 1149 
 1150         return(0);
 1151 }
 1152 
 1153 /*
 1154  * A frame has been uploaded: pass the resulting mbuf chain up to
 1155  * the higher level protocols.
 1156  *
 1157  * You know there's something wrong with a PCI bus-master chip design
 1158  * when you have to use m_devget().
 1159  *
 1160  * The receive operation is badly documented in the datasheet, so I'll
 1161  * attempt to document it here. The driver provides a buffer area and
 1162  * places its base address in the RX buffer start address register.
 1163  * The chip then begins copying frames into the RX buffer. Each frame
 1164  * is preceded by a 32-bit RX status word which specifies the length
 1165  * of the frame and certain other status bits. Each frame (starting with
 1166  * the status word) is also 32-bit aligned. The frame length is in the
 1167  * first 16 bits of the status word; the lower 15 bits correspond with
 1168  * the 'rx status register' mentioned in the datasheet.
 1169  *
 1170  * Note: to make the Alpha happy, the frame payload needs to be aligned
 1171  * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
 1172  * as the offset argument to m_devget(). 
 1173  */
 1174 static void
 1175 rl_rxeof(sc)
 1176         struct rl_softc         *sc;
 1177 {
 1178         struct mbuf             *m;
 1179         struct ifnet            *ifp;
 1180         int                     total_len = 0;
 1181         u_int32_t               rxstat;
 1182         caddr_t                 rxbufpos;
 1183         int                     wrap = 0;
 1184         u_int16_t               cur_rx;
 1185         u_int16_t               limit;
 1186         u_int16_t               rx_bytes = 0, max_bytes;
 1187 
 1188         ifp = &sc->arpcom.ac_if;
 1189 
 1190         bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
 1191             BUS_DMASYNC_POSTWRITE);
 1192 
 1193         cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
 1194 
 1195         /* Do not try to read past this point. */
 1196         limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
 1197 
 1198         if (limit < cur_rx)
 1199                 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
 1200         else
 1201                 max_bytes = limit - cur_rx;
 1202 
 1203         while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
 1204 #ifdef DEVICE_POLLING
 1205                 if (ifp->if_flags & IFF_POLLING) {
 1206                         if (sc->rxcycles <= 0)
 1207                                 break;
 1208                         sc->rxcycles--;
 1209                 }
 1210 #endif /* DEVICE_POLLING */
 1211                 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
 1212                 rxstat = *(u_int32_t *)rxbufpos;
 1213 
 1214                 /*
 1215                  * Here's a totally undocumented fact for you. When the
 1216                  * RealTek chip is in the process of copying a packet into
 1217                  * RAM for you, the length will be 0xfff0. If you spot a
 1218                  * packet header with this value, you need to stop. The
 1219                  * datasheet makes absolutely no mention of this and
 1220                  * RealTek should be shot for this.
 1221                  */
 1222                 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
 1223                         break;
 1224         
 1225                 if (!(rxstat & RL_RXSTAT_RXOK)) {
 1226                         ifp->if_ierrors++;
 1227                         rl_init(sc);
 1228                         return;
 1229                 }
 1230 
 1231                 /* No errors; receive the packet. */    
 1232                 total_len = rxstat >> 16;
 1233                 rx_bytes += total_len + 4;
 1234 
 1235                 /*
 1236                  * XXX The RealTek chip includes the CRC with every
 1237                  * received frame, and there's no way to turn this
 1238                  * behavior off (at least, I can't find anything in
 1239                  * the manual that explains how to do it) so we have
 1240                  * to trim off the CRC manually.
 1241                  */
 1242                 total_len -= ETHER_CRC_LEN;
 1243 
 1244                 /*
 1245                  * Avoid trying to read more bytes than we know
 1246                  * the chip has prepared for us.
 1247                  */
 1248                 if (rx_bytes > max_bytes)
 1249                         break;
 1250 
 1251                 rxbufpos = sc->rl_cdata.rl_rx_buf +
 1252                         ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
 1253 
 1254                 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
 1255                         rxbufpos = sc->rl_cdata.rl_rx_buf;
 1256 
 1257                 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
 1258 
 1259                 if (total_len > wrap) {
 1260                         m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
 1261                             NULL);
 1262                         if (m == NULL) {
 1263                                 ifp->if_ierrors++;
 1264                         } else {
 1265                                 m_copyback(m, wrap, total_len - wrap,
 1266                                         sc->rl_cdata.rl_rx_buf);
 1267                         }
 1268                         cur_rx = (total_len - wrap + ETHER_CRC_LEN);
 1269                 } else {
 1270                         m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
 1271                             NULL);
 1272                         if (m == NULL) {
 1273                                 ifp->if_ierrors++;
 1274                         }
 1275                         cur_rx += total_len + 4 + ETHER_CRC_LEN;
 1276                 }
 1277 
 1278                 /*
 1279                  * Round up to 32-bit boundary.
 1280                  */
 1281                 cur_rx = (cur_rx + 3) & ~3;
 1282                 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
 1283 
 1284                 if (m == NULL)
 1285                         continue;
 1286 
 1287                 ifp->if_ipackets++;
 1288                 (*ifp->if_input)(ifp, m);
 1289         }
 1290 
 1291         return;
 1292 }
 1293 
 1294 /*
 1295  * A frame was downloaded to the chip. It's safe for us to clean up
 1296  * the list buffers.
 1297  */
 1298 static void
 1299 rl_txeof(sc)
 1300         struct rl_softc         *sc;
 1301 {
 1302         struct ifnet            *ifp;
 1303         u_int32_t               txstat;
 1304 
 1305         ifp = &sc->arpcom.ac_if;
 1306 
 1307         /*
 1308          * Go through our tx list and free mbufs for those
 1309          * frames that have been uploaded.
 1310          */
 1311         do {
 1312                 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
 1313                 if (!(txstat & (RL_TXSTAT_TX_OK|
 1314                     RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
 1315                         break;
 1316 
 1317                 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
 1318 
 1319                 if (RL_LAST_TXMBUF(sc) != NULL) {
 1320                         bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
 1321                         bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
 1322                         m_freem(RL_LAST_TXMBUF(sc));
 1323                         RL_LAST_TXMBUF(sc) = NULL;
 1324                 }
 1325                 if (txstat & RL_TXSTAT_TX_OK)
 1326                         ifp->if_opackets++;
 1327                 else {
 1328                         int                     oldthresh;
 1329                         ifp->if_oerrors++;
 1330                         if ((txstat & RL_TXSTAT_TXABRT) ||
 1331                             (txstat & RL_TXSTAT_OUTOFWIN))
 1332                                 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
 1333                         oldthresh = sc->rl_txthresh;
 1334                         /* error recovery */
 1335                         rl_reset(sc);
 1336                         rl_init(sc);
 1337                         /*
 1338                          * If there was a transmit underrun,
 1339                          * bump the TX threshold.
 1340                          */
 1341                         if (txstat & RL_TXSTAT_TX_UNDERRUN)
 1342                                 sc->rl_txthresh = oldthresh + 32;
 1343                         return;
 1344                 }
 1345                 RL_INC(sc->rl_cdata.last_tx);
 1346                 ifp->if_flags &= ~IFF_OACTIVE;
 1347         } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
 1348 
 1349         ifp->if_timer =
 1350             (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5;
 1351 
 1352         return;
 1353 }
 1354 
 1355 static void
 1356 rl_tick(xsc)
 1357         void                    *xsc;
 1358 {
 1359         struct rl_softc         *sc;
 1360         struct mii_data         *mii;
 1361 
 1362         sc = xsc;
 1363         RL_LOCK(sc);
 1364         mii = device_get_softc(sc->rl_miibus);
 1365 
 1366         mii_tick(mii);
 1367 
 1368         sc->rl_stat_ch = timeout(rl_tick, sc, hz);
 1369         RL_UNLOCK(sc);
 1370 
 1371         return;
 1372 }
 1373 
 1374 #ifdef DEVICE_POLLING
 1375 static void
 1376 rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
 1377 {
 1378         struct rl_softc *sc = ifp->if_softc;
 1379 
 1380         RL_LOCK(sc);
 1381         if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
 1382                 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
 1383                 goto done;
 1384         }
 1385 
 1386         sc->rxcycles = count;
 1387         rl_rxeof(sc);
 1388         rl_txeof(sc);
 1389         if (ifp->if_snd.ifq_head != NULL)
 1390                 rl_start(ifp);
 1391 
 1392         if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
 1393                 u_int16_t       status;
 1394 
 1395                 status = CSR_READ_2(sc, RL_ISR);
 1396                 if (status == 0xffff)
 1397                         goto done;
 1398                 if (status)
 1399                         CSR_WRITE_2(sc, RL_ISR, status);
 1400 
 1401                 /*
 1402                  * XXX check behaviour on receiver stalls.
 1403                  */
 1404 
 1405                 if (status & RL_ISR_SYSTEM_ERR) {
 1406                         rl_reset(sc);
 1407                         rl_init(sc);
 1408                 }
 1409         }
 1410 done:
 1411         RL_UNLOCK(sc);
 1412 }
 1413 #endif /* DEVICE_POLLING */
 1414 
 1415 static void
 1416 rl_intr(arg)
 1417         void                    *arg;
 1418 {
 1419         struct rl_softc         *sc;
 1420         struct ifnet            *ifp;
 1421         u_int16_t               status;
 1422 
 1423         sc = arg;
 1424 
 1425         if (sc->suspended) {
 1426                 return;
 1427         }
 1428 
 1429         RL_LOCK(sc);
 1430         ifp = &sc->arpcom.ac_if;
 1431 
 1432 #ifdef DEVICE_POLLING
 1433         if  (ifp->if_flags & IFF_POLLING)
 1434                 goto done;
 1435         if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */
 1436                 CSR_WRITE_2(sc, RL_IMR, 0x0000);
 1437                 rl_poll(ifp, 0, 1);
 1438                 goto done;
 1439         }
 1440 #endif /* DEVICE_POLLING */
 1441 
 1442         for (;;) {
 1443 
 1444                 status = CSR_READ_2(sc, RL_ISR);
 1445                 /* If the card has gone away the read returns 0xffff. */
 1446                 if (status == 0xffff)
 1447                         break;
 1448                 if (status)
 1449                         CSR_WRITE_2(sc, RL_ISR, status);
 1450 
 1451                 if ((status & RL_INTRS) == 0)
 1452                         break;
 1453 
 1454                 if (status & RL_ISR_RX_OK)
 1455                         rl_rxeof(sc);
 1456 
 1457                 if (status & RL_ISR_RX_ERR)
 1458                         rl_rxeof(sc);
 1459 
 1460                 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
 1461                         rl_txeof(sc);
 1462 
 1463                 if (status & RL_ISR_SYSTEM_ERR) {
 1464                         rl_reset(sc);
 1465                         rl_init(sc);
 1466                 }
 1467 
 1468         }
 1469 
 1470         if (ifp->if_snd.ifq_head != NULL)
 1471                 rl_start(ifp);
 1472 
 1473 #ifdef DEVICE_POLLING
 1474 done:
 1475 #endif
 1476         RL_UNLOCK(sc);
 1477 
 1478         return;
 1479 }
 1480 
 1481 /*
 1482  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
 1483  * pointers to the fragment pointers.
 1484  */
 1485 static int
 1486 rl_encap(sc, m_head)
 1487         struct rl_softc         *sc;
 1488         struct mbuf             *m_head;
 1489 {
 1490         struct mbuf             *m_new = NULL;
 1491 
 1492         /*
 1493          * The RealTek is brain damaged and wants longword-aligned
 1494          * TX buffers, plus we can only have one fragment buffer
 1495          * per packet. We have to copy pretty much all the time.
 1496          */
 1497 
 1498         MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1499         if (m_new == NULL)
 1500                 return(1);
 1501         if (m_head->m_pkthdr.len > MHLEN) {
 1502                 MCLGET(m_new, M_DONTWAIT);
 1503                 if (!(m_new->m_flags & M_EXT)) {
 1504                         m_freem(m_new);
 1505                         return(1);
 1506                 }
 1507         }
 1508         m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
 1509         m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
 1510         m_freem(m_head);
 1511         m_head = m_new;
 1512 
 1513         /* Pad frames to at least 60 bytes. */
 1514         if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
 1515                 /*
 1516                  * Make security concious people happy: zero out the
 1517                  * bytes in the pad area, since we don't know what
 1518                  * this mbuf cluster buffer's previous user might
 1519                  * have left in it.
 1520                  */
 1521                 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
 1522                      RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
 1523                 m_head->m_pkthdr.len +=
 1524                     (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
 1525                 m_head->m_len = m_head->m_pkthdr.len;
 1526         }
 1527 
 1528         RL_CUR_TXMBUF(sc) = m_head;
 1529 
 1530         return(0);
 1531 }
 1532 
 1533 /*
 1534  * Main transmit routine.
 1535  */
 1536 
 1537 static void
 1538 rl_start(ifp)
 1539         struct ifnet            *ifp;
 1540 {
 1541         struct rl_softc         *sc;
 1542         struct mbuf             *m_head = NULL;
 1543 
 1544         sc = ifp->if_softc;
 1545         RL_LOCK(sc);
 1546 
 1547         while(RL_CUR_TXMBUF(sc) == NULL) {
 1548                 IF_DEQUEUE(&ifp->if_snd, m_head);
 1549                 if (m_head == NULL)
 1550                         break;
 1551 
 1552                 if (rl_encap(sc, m_head)) {
 1553                         IF_PREPEND(&ifp->if_snd, m_head);
 1554                         ifp->if_flags |= IFF_OACTIVE;
 1555                         break;
 1556                 }
 1557 
 1558                 /*
 1559                  * If there's a BPF listener, bounce a copy of this frame
 1560                  * to him.
 1561                  */
 1562                 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
 1563 
 1564                 /*
 1565                  * Transmit the frame.
 1566                  */
 1567                 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
 1568                 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
 1569                     mtod(RL_CUR_TXMBUF(sc), void *),
 1570                     RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
 1571                 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
 1572                     BUS_DMASYNC_PREREAD);
 1573                 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
 1574                     RL_TXTHRESH(sc->rl_txthresh) |
 1575                     RL_CUR_TXMBUF(sc)->m_pkthdr.len);
 1576 
 1577                 RL_INC(sc->rl_cdata.cur_tx);
 1578         }
 1579 
 1580         /*
 1581          * We broke out of the loop because all our TX slots are
 1582          * full. Mark the NIC as busy until it drains some of the
 1583          * packets from the queue.
 1584          */
 1585         if (RL_CUR_TXMBUF(sc) != NULL)
 1586                 ifp->if_flags |= IFF_OACTIVE;
 1587 
 1588         /*
 1589          * Set a timeout in case the chip goes out to lunch.
 1590          */
 1591         ifp->if_timer = 5;
 1592         RL_UNLOCK(sc);
 1593 
 1594         return;
 1595 }
 1596 
 1597 static void
 1598 rl_init(xsc)
 1599         void                    *xsc;
 1600 {
 1601         struct rl_softc         *sc = xsc;
 1602         struct ifnet            *ifp = &sc->arpcom.ac_if;
 1603         struct mii_data         *mii;
 1604         int                     i;
 1605         u_int32_t               rxcfg = 0;
 1606 
 1607         RL_LOCK(sc);
 1608         mii = device_get_softc(sc->rl_miibus);
 1609 
 1610         /*
 1611          * Cancel pending I/O and free all RX/TX buffers.
 1612          */
 1613         rl_stop(sc);
 1614 
 1615         /* Init our MAC address */
 1616         for (i = 0; i < ETHER_ADDR_LEN; i++) {
 1617                 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
 1618         }
 1619 
 1620         /* Init the RX buffer pointer register. */
 1621         bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
 1622             sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
 1623         bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
 1624             BUS_DMASYNC_PREWRITE);
 1625 
 1626         /* Init TX descriptors. */
 1627         rl_list_tx_init(sc);
 1628 
 1629         /*
 1630          * Enable transmit and receive.
 1631          */
 1632         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
 1633 
 1634         /*
 1635          * Set the initial TX and RX configuration.
 1636          */
 1637         CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
 1638         CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
 1639 
 1640         /* Set the individual bit to receive frames for this host only. */
 1641         rxcfg = CSR_READ_4(sc, RL_RXCFG);
 1642         rxcfg |= RL_RXCFG_RX_INDIV;
 1643 
 1644         /* If we want promiscuous mode, set the allframes bit. */
 1645         if (ifp->if_flags & IFF_PROMISC) {
 1646                 rxcfg |= RL_RXCFG_RX_ALLPHYS;
 1647                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
 1648         } else {
 1649                 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
 1650                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
 1651         }
 1652 
 1653         /*
 1654          * Set capture broadcast bit to capture broadcast frames.
 1655          */
 1656         if (ifp->if_flags & IFF_BROADCAST) {
 1657                 rxcfg |= RL_RXCFG_RX_BROAD;
 1658                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
 1659         } else {
 1660                 rxcfg &= ~RL_RXCFG_RX_BROAD;
 1661                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
 1662         }
 1663 
 1664         /*
 1665          * Program the multicast filter, if necessary.
 1666          */
 1667         rl_setmulti(sc);
 1668 
 1669 #ifdef DEVICE_POLLING
 1670         /*
 1671          * Disable interrupts if we are polling.
 1672          */
 1673         if (ifp->if_flags & IFF_POLLING)
 1674                 CSR_WRITE_2(sc, RL_IMR, 0);
 1675         else    /* otherwise ... */
 1676 #endif /* DEVICE_POLLING */
 1677         /*
 1678          * Enable interrupts.
 1679          */
 1680         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
 1681 
 1682         /* Set initial TX threshold */
 1683         sc->rl_txthresh = RL_TX_THRESH_INIT;
 1684 
 1685         /* Start RX/TX process. */
 1686         CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
 1687 
 1688         /* Enable receiver and transmitter. */
 1689         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
 1690 
 1691         mii_mediachg(mii);
 1692 
 1693         CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
 1694 
 1695         ifp->if_flags |= IFF_RUNNING;
 1696         ifp->if_flags &= ~IFF_OACTIVE;
 1697 
 1698         sc->rl_stat_ch = timeout(rl_tick, sc, hz);
 1699         RL_UNLOCK(sc);
 1700 
 1701         return;
 1702 }
 1703 
 1704 /*
 1705  * Set media options.
 1706  */
 1707 static int
 1708 rl_ifmedia_upd(ifp)
 1709         struct ifnet            *ifp;
 1710 {
 1711         struct rl_softc         *sc;
 1712         struct mii_data         *mii;
 1713 
 1714         sc = ifp->if_softc;
 1715         mii = device_get_softc(sc->rl_miibus);
 1716         mii_mediachg(mii);
 1717 
 1718         return(0);
 1719 }
 1720 
 1721 /*
 1722  * Report current media status.
 1723  */
 1724 static void
 1725 rl_ifmedia_sts(ifp, ifmr)
 1726         struct ifnet            *ifp;
 1727         struct ifmediareq       *ifmr;
 1728 {
 1729         struct rl_softc         *sc;
 1730         struct mii_data         *mii;
 1731 
 1732         sc = ifp->if_softc;
 1733         mii = device_get_softc(sc->rl_miibus);
 1734 
 1735         mii_pollstat(mii);
 1736         ifmr->ifm_active = mii->mii_media_active;
 1737         ifmr->ifm_status = mii->mii_media_status;
 1738 
 1739         return;
 1740 }
 1741 
 1742 static int
 1743 rl_ioctl(ifp, command, data)
 1744         struct ifnet            *ifp;
 1745         u_long                  command;
 1746         caddr_t                 data;
 1747 {
 1748         struct rl_softc         *sc = ifp->if_softc;
 1749         struct ifreq            *ifr = (struct ifreq *) data;
 1750         struct mii_data         *mii;
 1751         int                     error = 0;
 1752 
 1753         RL_LOCK(sc);
 1754 
 1755         switch(command) {
 1756         case SIOCSIFFLAGS:
 1757                 if (ifp->if_flags & IFF_UP) {
 1758                         rl_init(sc);
 1759                 } else {
 1760                         if (ifp->if_flags & IFF_RUNNING)
 1761                                 rl_stop(sc);
 1762                 }
 1763                 error = 0;
 1764                 break;
 1765         case SIOCADDMULTI:
 1766         case SIOCDELMULTI:
 1767                 rl_setmulti(sc);
 1768                 error = 0;
 1769                 break;
 1770         case SIOCGIFMEDIA:
 1771         case SIOCSIFMEDIA:
 1772                 mii = device_get_softc(sc->rl_miibus);
 1773                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 1774                 break;
 1775         default:
 1776                 error = ether_ioctl(ifp, command, data);
 1777                 break;
 1778         }
 1779 
 1780         RL_UNLOCK(sc);
 1781 
 1782         return(error);
 1783 }
 1784 
 1785 static void
 1786 rl_watchdog(ifp)
 1787         struct ifnet            *ifp;
 1788 {
 1789         struct rl_softc         *sc;
 1790 
 1791         sc = ifp->if_softc;
 1792         RL_LOCK(sc);
 1793         printf("rl%d: watchdog timeout\n", sc->rl_unit);
 1794         ifp->if_oerrors++;
 1795 
 1796         rl_txeof(sc);
 1797         rl_rxeof(sc);
 1798         rl_init(sc);
 1799         RL_UNLOCK(sc);
 1800 
 1801         return;
 1802 }
 1803 
 1804 /*
 1805  * Stop the adapter and free any mbufs allocated to the
 1806  * RX and TX lists.
 1807  */
 1808 static void
 1809 rl_stop(sc)
 1810         struct rl_softc         *sc;
 1811 {
 1812         register int            i;
 1813         struct ifnet            *ifp;
 1814 
 1815         RL_LOCK(sc);
 1816         ifp = &sc->arpcom.ac_if;
 1817         ifp->if_timer = 0;
 1818 
 1819         untimeout(rl_tick, sc, sc->rl_stat_ch);
 1820         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 1821 #ifdef DEVICE_POLLING
 1822         ether_poll_deregister(ifp);
 1823 #endif /* DEVICE_POLLING */
 1824 
 1825         CSR_WRITE_1(sc, RL_COMMAND, 0x00);
 1826         CSR_WRITE_2(sc, RL_IMR, 0x0000);
 1827         bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
 1828 
 1829         /*
 1830          * Free the TX list buffers.
 1831          */
 1832         for (i = 0; i < RL_TX_LIST_CNT; i++) {
 1833                 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
 1834                         bus_dmamap_unload(sc->rl_tag,
 1835                             sc->rl_cdata.rl_tx_dmamap[i]);
 1836                         bus_dmamap_destroy(sc->rl_tag,
 1837                             sc->rl_cdata.rl_tx_dmamap[i]);
 1838                         m_freem(sc->rl_cdata.rl_tx_chain[i]);
 1839                         sc->rl_cdata.rl_tx_chain[i] = NULL;
 1840                         CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
 1841                 }
 1842         }
 1843 
 1844         RL_UNLOCK(sc);
 1845         return;
 1846 }
 1847 
 1848 /*
 1849  * Device suspend routine.  Stop the interface and save some PCI
 1850  * settings in case the BIOS doesn't restore them properly on
 1851  * resume.
 1852  */
 1853 static int
 1854 rl_suspend(dev)
 1855         device_t                dev;
 1856 {
 1857         register int            i;
 1858         struct rl_softc         *sc;
 1859 
 1860         sc = device_get_softc(dev);
 1861 
 1862         rl_stop(sc);
 1863 
 1864         for (i = 0; i < 5; i++)
 1865                 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
 1866         sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
 1867         sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
 1868         sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
 1869         sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
 1870 
 1871         sc->suspended = 1;
 1872 
 1873         return (0);
 1874 }
 1875 
 1876 /*
 1877  * Device resume routine.  Restore some PCI settings in case the BIOS
 1878  * doesn't, re-enable busmastering, and restart the interface if
 1879  * appropriate.
 1880  */
 1881 static int
 1882 rl_resume(dev)
 1883         device_t                dev;
 1884 {
 1885         register int            i;
 1886         struct rl_softc         *sc;
 1887         struct ifnet            *ifp;
 1888 
 1889         sc = device_get_softc(dev);
 1890         ifp = &sc->arpcom.ac_if;
 1891 
 1892         /* better way to do this? */
 1893         for (i = 0; i < 5; i++)
 1894                 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
 1895         pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
 1896         pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
 1897         pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
 1898         pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
 1899 
 1900         /* reenable busmastering */
 1901         pci_enable_busmaster(dev);
 1902         pci_enable_io(dev, RL_RES);
 1903 
 1904         /* reinitialize interface if necessary */
 1905         if (ifp->if_flags & IFF_UP)
 1906                 rl_init(sc);
 1907 
 1908         sc->suspended = 0;
 1909 
 1910         return (0);
 1911 }
 1912 
 1913 /*
 1914  * Stop all chip I/O so that the kernel's probe routines don't
 1915  * get confused by errant DMAs when rebooting.
 1916  */
 1917 static void
 1918 rl_shutdown(dev)
 1919         device_t                dev;
 1920 {
 1921         struct rl_softc         *sc;
 1922 
 1923         sc = device_get_softc(dev);
 1924 
 1925         rl_stop(sc);
 1926 
 1927         return;
 1928 }

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