The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_rl.c

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    1 /*
    2  * Copyright (c) 1997, 1998
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD: releng/5.2/sys/pci/if_rl.c 123019 2003-11-28 05:28:29Z imp $");
   35 
   36 /*
   37  * RealTek 8129/8139 PCI NIC driver
   38  *
   39  * Supports several extremely cheap PCI 10/100 adapters based on
   40  * the RealTek chipset. Datasheets can be obtained from
   41  * www.realtek.com.tw.
   42  *
   43  * Written by Bill Paul <wpaul@ctr.columbia.edu>
   44  * Electrical Engineering Department
   45  * Columbia University, New York City
   46  */
   47 /*
   48  * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
   49  * probably the worst PCI ethernet controller ever made, with the possible
   50  * exception of the FEAST chip made by SMC. The 8139 supports bus-master
   51  * DMA, but it has a terrible interface that nullifies any performance
   52  * gains that bus-master DMA usually offers.
   53  *
   54  * For transmission, the chip offers a series of four TX descriptor
   55  * registers. Each transmit frame must be in a contiguous buffer, aligned
   56  * on a longword (32-bit) boundary. This means we almost always have to
   57  * do mbuf copies in order to transmit a frame, except in the unlikely
   58  * case where a) the packet fits into a single mbuf, and b) the packet
   59  * is 32-bit aligned within the mbuf's data area. The presence of only
   60  * four descriptor registers means that we can never have more than four
   61  * packets queued for transmission at any one time.
   62  *
   63  * Reception is not much better. The driver has to allocate a single large
   64  * buffer area (up to 64K in size) into which the chip will DMA received
   65  * frames. Because we don't know where within this region received packets
   66  * will begin or end, we have no choice but to copy data from the buffer
   67  * area into mbufs in order to pass the packets up to the higher protocol
   68  * levels.
   69  *
   70  * It's impossible given this rotten design to really achieve decent
   71  * performance at 100Mbps, unless you happen to have a 400Mhz PII or
   72  * some equally overmuscled CPU to drive it.
   73  *
   74  * On the bright side, the 8139 does have a built-in PHY, although
   75  * rather than using an MDIO serial interface like most other NICs, the
   76  * PHY registers are directly accessible through the 8139's register
   77  * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
   78  * filter.
   79  *
   80  * The 8129 chip is an older version of the 8139 that uses an external PHY
   81  * chip. The 8129 has a serial MDIO interface for accessing the MII where
   82  * the 8139 lets you directly access the on-board PHY registers. We need
   83  * to select which interface to use depending on the chip type.
   84  */
   85 
   86 #include <sys/param.h>
   87 #include <sys/endian.h>
   88 #include <sys/systm.h>
   89 #include <sys/sockio.h>
   90 #include <sys/mbuf.h>
   91 #include <sys/malloc.h>
   92 #include <sys/kernel.h>
   93 #include <sys/socket.h>
   94 
   95 #include <net/if.h>
   96 #include <net/if_arp.h>
   97 #include <net/ethernet.h>
   98 #include <net/if_dl.h>
   99 #include <net/if_media.h>
  100 
  101 #include <net/bpf.h>
  102 
  103 #include <machine/bus_pio.h>
  104 #include <machine/bus_memio.h>
  105 #include <machine/bus.h>
  106 #include <machine/resource.h>
  107 #include <sys/bus.h>
  108 #include <sys/rman.h>
  109 
  110 #include <dev/mii/mii.h>
  111 #include <dev/mii/miivar.h>
  112 
  113 #include <dev/pci/pcireg.h>
  114 #include <dev/pci/pcivar.h>
  115 
  116 MODULE_DEPEND(rl, pci, 1, 1, 1);
  117 MODULE_DEPEND(rl, ether, 1, 1, 1);
  118 MODULE_DEPEND(rl, miibus, 1, 1, 1);
  119 
  120 /* "controller miibus0" required.  See GENERIC if you get errors here. */
  121 #include "miibus_if.h"
  122 
  123 /*
  124  * Default to using PIO access for this driver. On SMP systems,
  125  * there appear to be problems with memory mapped mode: it looks like
  126  * doing too many memory mapped access back to back in rapid succession
  127  * can hang the bus. I'm inclined to blame this on crummy design/construction
  128  * on the part of RealTek. Memory mapped mode does appear to work on
  129  * uniprocessor systems though.
  130  */
  131 #define RL_USEIOSPACE
  132 
  133 #include <pci/if_rlreg.h>
  134 
  135 /*
  136  * Various supported device vendors/types and their names.
  137  */
  138 static struct rl_type rl_devs[] = {
  139         { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
  140                 "RealTek 8129 10/100BaseTX" },
  141         { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
  142                 "RealTek 8139 10/100BaseTX" },
  143         { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
  144                 "RealTek 8139 10/100BaseTX CardBus" },
  145         { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
  146                 "RealTek 8100 10/100BaseTX" },
  147         { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
  148                 "Accton MPX 5030/5038 10/100BaseTX" },
  149         { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
  150                 "Delta Electronics 8139 10/100BaseTX" },
  151         { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
  152                 "Addtron Technolgy 8139 10/100BaseTX" },
  153         { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
  154                 "D-Link DFE-530TX+ 10/100BaseTX" },
  155         { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
  156                 "D-Link DFE-690TXD 10/100BaseTX" },
  157         { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
  158                 "Nortel Networks 10/100BaseTX" },
  159         { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
  160                 "Corega FEther CB-TXD" },
  161         { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
  162                 "Corega FEtherII CB-TXD" },
  163         { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
  164                 "Peppercon AG ROL-F" },
  165         { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
  166                 "Planex FNW-3800-TX" },
  167         { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
  168                 "Compaq HNE-300" },
  169         { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
  170                 "LevelOne FPC-0106TX" },
  171         { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
  172                 "Edimax EP-4103DL CardBus" },
  173         { 0, 0, NULL }
  174 };
  175 
  176 static int rl_probe             (device_t);
  177 static int rl_attach            (device_t);
  178 static int rl_detach            (device_t);
  179 
  180 static int rl_encap             (struct rl_softc *, struct mbuf * );
  181 
  182 static void rl_rxeof            (struct rl_softc *);
  183 static void rl_txeof            (struct rl_softc *);
  184 static void rl_intr             (void *);
  185 static void rl_tick             (void *);
  186 static void rl_start            (struct ifnet *);
  187 static int rl_ioctl             (struct ifnet *, u_long, caddr_t);
  188 static void rl_init             (void *);
  189 static void rl_stop             (struct rl_softc *);
  190 static void rl_watchdog         (struct ifnet *);
  191 static int rl_suspend           (device_t);
  192 static int rl_resume            (device_t);
  193 static void rl_shutdown         (device_t);
  194 static int rl_ifmedia_upd       (struct ifnet *);
  195 static void rl_ifmedia_sts      (struct ifnet *, struct ifmediareq *);
  196 
  197 static void rl_eeprom_putbyte   (struct rl_softc *, int);
  198 static void rl_eeprom_getword   (struct rl_softc *, int, u_int16_t *);
  199 static void rl_read_eeprom      (struct rl_softc *, caddr_t, int, int, int);
  200 static void rl_mii_sync         (struct rl_softc *);
  201 static void rl_mii_send         (struct rl_softc *, u_int32_t, int);
  202 static int rl_mii_readreg       (struct rl_softc *, struct rl_mii_frame *);
  203 static int rl_mii_writereg      (struct rl_softc *, struct rl_mii_frame *);
  204 
  205 static int rl_miibus_readreg    (device_t, int, int);
  206 static int rl_miibus_writereg   (device_t, int, int, int);
  207 static void rl_miibus_statchg   (device_t);
  208 
  209 static u_int32_t rl_mchash      (caddr_t);
  210 static void rl_setmulti         (struct rl_softc *);
  211 static void rl_reset            (struct rl_softc *);
  212 static int rl_list_tx_init      (struct rl_softc *);
  213 
  214 static void rl_dma_map_rxbuf    (void *, bus_dma_segment_t *, int, int);
  215 static void rl_dma_map_txbuf    (void *, bus_dma_segment_t *, int, int);
  216 
  217 #ifdef RL_USEIOSPACE
  218 #define RL_RES                  SYS_RES_IOPORT
  219 #define RL_RID                  RL_PCI_LOIO
  220 #else
  221 #define RL_RES                  SYS_RES_MEMORY
  222 #define RL_RID                  RL_PCI_LOMEM
  223 #endif
  224 
  225 static device_method_t rl_methods[] = {
  226         /* Device interface */
  227         DEVMETHOD(device_probe,         rl_probe),
  228         DEVMETHOD(device_attach,        rl_attach),
  229         DEVMETHOD(device_detach,        rl_detach),
  230         DEVMETHOD(device_suspend,       rl_suspend),
  231         DEVMETHOD(device_resume,        rl_resume),
  232         DEVMETHOD(device_shutdown,      rl_shutdown),
  233 
  234         /* bus interface */
  235         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  236         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
  237 
  238         /* MII interface */
  239         DEVMETHOD(miibus_readreg,       rl_miibus_readreg),
  240         DEVMETHOD(miibus_writereg,      rl_miibus_writereg),
  241         DEVMETHOD(miibus_statchg,       rl_miibus_statchg),
  242 
  243         { 0, 0 }
  244 };
  245 
  246 static driver_t rl_driver = {
  247         "rl",
  248         rl_methods,
  249         sizeof(struct rl_softc)
  250 };
  251 
  252 static devclass_t rl_devclass;
  253 
  254 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
  255 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
  256 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
  257 
  258 #define EE_SET(x)                                       \
  259         CSR_WRITE_1(sc, RL_EECMD,                       \
  260                 CSR_READ_1(sc, RL_EECMD) | x)
  261 
  262 #define EE_CLR(x)                                       \
  263         CSR_WRITE_1(sc, RL_EECMD,                       \
  264                 CSR_READ_1(sc, RL_EECMD) & ~x)
  265 
  266 static void
  267 rl_dma_map_rxbuf(arg, segs, nseg, error)
  268         void *arg;
  269         bus_dma_segment_t *segs;
  270         int nseg, error;
  271 {
  272         struct rl_softc *sc;
  273 
  274         sc = arg;
  275         CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
  276 
  277         return;
  278 }
  279 
  280 static void
  281 rl_dma_map_txbuf(arg, segs, nseg, error)
  282         void *arg;
  283         bus_dma_segment_t *segs;
  284         int nseg, error;
  285 {
  286         struct rl_softc *sc;
  287 
  288         sc = arg;
  289         CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
  290 
  291         return;
  292 }
  293 
  294 /*
  295  * Send a read command and address to the EEPROM, check for ACK.
  296  */
  297 static void
  298 rl_eeprom_putbyte(sc, addr)
  299         struct rl_softc         *sc;
  300         int                     addr;
  301 {
  302         register int            d, i;
  303 
  304         d = addr | sc->rl_eecmd_read;
  305 
  306         /*
  307          * Feed in each bit and strobe the clock.
  308          */
  309         for (i = 0x400; i; i >>= 1) {
  310                 if (d & i) {
  311                         EE_SET(RL_EE_DATAIN);
  312                 } else {
  313                         EE_CLR(RL_EE_DATAIN);
  314                 }
  315                 DELAY(100);
  316                 EE_SET(RL_EE_CLK);
  317                 DELAY(150);
  318                 EE_CLR(RL_EE_CLK);
  319                 DELAY(100);
  320         }
  321 
  322         return;
  323 }
  324 
  325 /*
  326  * Read a word of data stored in the EEPROM at address 'addr.'
  327  */
  328 static void
  329 rl_eeprom_getword(sc, addr, dest)
  330         struct rl_softc         *sc;
  331         int                     addr;
  332         u_int16_t               *dest;
  333 {
  334         register int            i;
  335         u_int16_t               word = 0;
  336 
  337         /* Enter EEPROM access mode. */
  338         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
  339 
  340         /*
  341          * Send address of word we want to read.
  342          */
  343         rl_eeprom_putbyte(sc, addr);
  344 
  345         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
  346 
  347         /*
  348          * Start reading bits from EEPROM.
  349          */
  350         for (i = 0x8000; i; i >>= 1) {
  351                 EE_SET(RL_EE_CLK);
  352                 DELAY(100);
  353                 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
  354                         word |= i;
  355                 EE_CLR(RL_EE_CLK);
  356                 DELAY(100);
  357         }
  358 
  359         /* Turn off EEPROM access mode. */
  360         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
  361 
  362         *dest = word;
  363 
  364         return;
  365 }
  366 
  367 /*
  368  * Read a sequence of words from the EEPROM.
  369  */
  370 static void
  371 rl_read_eeprom(sc, dest, off, cnt, swap)
  372         struct rl_softc         *sc;
  373         caddr_t                 dest;
  374         int                     off;
  375         int                     cnt;
  376         int                     swap;
  377 {
  378         int                     i;
  379         u_int16_t               word = 0, *ptr;
  380 
  381         for (i = 0; i < cnt; i++) {
  382                 rl_eeprom_getword(sc, off + i, &word);
  383                 ptr = (u_int16_t *)(dest + (i * 2));
  384                 if (swap)
  385                         *ptr = ntohs(word);
  386                 else
  387                         *ptr = word;
  388         }
  389 
  390         return;
  391 }
  392 
  393 
  394 /*
  395  * MII access routines are provided for the 8129, which
  396  * doesn't have a built-in PHY. For the 8139, we fake things
  397  * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
  398  * direct access PHY registers.
  399  */
  400 #define MII_SET(x)                                      \
  401         CSR_WRITE_1(sc, RL_MII,                         \
  402                 CSR_READ_1(sc, RL_MII) | (x))
  403 
  404 #define MII_CLR(x)                                      \
  405         CSR_WRITE_1(sc, RL_MII,                         \
  406                 CSR_READ_1(sc, RL_MII) & ~(x))
  407 
  408 /*
  409  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  410  */
  411 static void
  412 rl_mii_sync(sc)
  413         struct rl_softc         *sc;
  414 {
  415         register int            i;
  416 
  417         MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
  418 
  419         for (i = 0; i < 32; i++) {
  420                 MII_SET(RL_MII_CLK);
  421                 DELAY(1);
  422                 MII_CLR(RL_MII_CLK);
  423                 DELAY(1);
  424         }
  425 
  426         return;
  427 }
  428 
  429 /*
  430  * Clock a series of bits through the MII.
  431  */
  432 static void
  433 rl_mii_send(sc, bits, cnt)
  434         struct rl_softc         *sc;
  435         u_int32_t               bits;
  436         int                     cnt;
  437 {
  438         int                     i;
  439 
  440         MII_CLR(RL_MII_CLK);
  441 
  442         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  443                 if (bits & i) {
  444                         MII_SET(RL_MII_DATAOUT);
  445                 } else {
  446                         MII_CLR(RL_MII_DATAOUT);
  447                 }
  448                 DELAY(1);
  449                 MII_CLR(RL_MII_CLK);
  450                 DELAY(1);
  451                 MII_SET(RL_MII_CLK);
  452         }
  453 }
  454 
  455 /*
  456  * Read an PHY register through the MII.
  457  */
  458 static int
  459 rl_mii_readreg(sc, frame)
  460         struct rl_softc         *sc;
  461         struct rl_mii_frame     *frame;
  462 
  463 {
  464         int                     i, ack;
  465 
  466         RL_LOCK(sc);
  467 
  468         /*
  469          * Set up frame for RX.
  470          */
  471         frame->mii_stdelim = RL_MII_STARTDELIM;
  472         frame->mii_opcode = RL_MII_READOP;
  473         frame->mii_turnaround = 0;
  474         frame->mii_data = 0;
  475 
  476         CSR_WRITE_2(sc, RL_MII, 0);
  477 
  478         /*
  479          * Turn on data xmit.
  480          */
  481         MII_SET(RL_MII_DIR);
  482 
  483         rl_mii_sync(sc);
  484 
  485         /*
  486          * Send command/address info.
  487          */
  488         rl_mii_send(sc, frame->mii_stdelim, 2);
  489         rl_mii_send(sc, frame->mii_opcode, 2);
  490         rl_mii_send(sc, frame->mii_phyaddr, 5);
  491         rl_mii_send(sc, frame->mii_regaddr, 5);
  492 
  493         /* Idle bit */
  494         MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
  495         DELAY(1);
  496         MII_SET(RL_MII_CLK);
  497         DELAY(1);
  498 
  499         /* Turn off xmit. */
  500         MII_CLR(RL_MII_DIR);
  501 
  502         /* Check for ack */
  503         MII_CLR(RL_MII_CLK);
  504         DELAY(1);
  505         ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
  506         MII_SET(RL_MII_CLK);
  507         DELAY(1);
  508 
  509         /*
  510          * Now try reading data bits. If the ack failed, we still
  511          * need to clock through 16 cycles to keep the PHY(s) in sync.
  512          */
  513         if (ack) {
  514                 for(i = 0; i < 16; i++) {
  515                         MII_CLR(RL_MII_CLK);
  516                         DELAY(1);
  517                         MII_SET(RL_MII_CLK);
  518                         DELAY(1);
  519                 }
  520                 goto fail;
  521         }
  522 
  523         for (i = 0x8000; i; i >>= 1) {
  524                 MII_CLR(RL_MII_CLK);
  525                 DELAY(1);
  526                 if (!ack) {
  527                         if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
  528                                 frame->mii_data |= i;
  529                         DELAY(1);
  530                 }
  531                 MII_SET(RL_MII_CLK);
  532                 DELAY(1);
  533         }
  534 
  535 fail:
  536 
  537         MII_CLR(RL_MII_CLK);
  538         DELAY(1);
  539         MII_SET(RL_MII_CLK);
  540         DELAY(1);
  541 
  542         RL_UNLOCK(sc);
  543 
  544         if (ack)
  545                 return(1);
  546         return(0);
  547 }
  548 
  549 /*
  550  * Write to a PHY register through the MII.
  551  */
  552 static int
  553 rl_mii_writereg(sc, frame)
  554         struct rl_softc         *sc;
  555         struct rl_mii_frame     *frame;
  556 
  557 {
  558         RL_LOCK(sc);
  559 
  560         /*
  561          * Set up frame for TX.
  562          */
  563 
  564         frame->mii_stdelim = RL_MII_STARTDELIM;
  565         frame->mii_opcode = RL_MII_WRITEOP;
  566         frame->mii_turnaround = RL_MII_TURNAROUND;
  567 
  568         /*
  569          * Turn on data output.
  570          */
  571         MII_SET(RL_MII_DIR);
  572 
  573         rl_mii_sync(sc);
  574 
  575         rl_mii_send(sc, frame->mii_stdelim, 2);
  576         rl_mii_send(sc, frame->mii_opcode, 2);
  577         rl_mii_send(sc, frame->mii_phyaddr, 5);
  578         rl_mii_send(sc, frame->mii_regaddr, 5);
  579         rl_mii_send(sc, frame->mii_turnaround, 2);
  580         rl_mii_send(sc, frame->mii_data, 16);
  581 
  582         /* Idle bit. */
  583         MII_SET(RL_MII_CLK);
  584         DELAY(1);
  585         MII_CLR(RL_MII_CLK);
  586         DELAY(1);
  587 
  588         /*
  589          * Turn off xmit.
  590          */
  591         MII_CLR(RL_MII_DIR);
  592 
  593         RL_UNLOCK(sc);
  594 
  595         return(0);
  596 }
  597 
  598 static int
  599 rl_miibus_readreg(dev, phy, reg)
  600         device_t                dev;
  601         int                     phy, reg;
  602 {
  603         struct rl_softc         *sc;
  604         struct rl_mii_frame     frame;
  605         u_int16_t               rval = 0;
  606         u_int16_t               rl8139_reg = 0;
  607 
  608         sc = device_get_softc(dev);
  609         RL_LOCK(sc);
  610 
  611         if (sc->rl_type == RL_8139) {
  612                 /* Pretend the internal PHY is only at address 0 */
  613                 if (phy) {
  614                         RL_UNLOCK(sc);
  615                         return(0);
  616                 }
  617                 switch(reg) {
  618                 case MII_BMCR:
  619                         rl8139_reg = RL_BMCR;
  620                         break;
  621                 case MII_BMSR:
  622                         rl8139_reg = RL_BMSR;
  623                         break;
  624                 case MII_ANAR:
  625                         rl8139_reg = RL_ANAR;
  626                         break;
  627                 case MII_ANER:
  628                         rl8139_reg = RL_ANER;
  629                         break;
  630                 case MII_ANLPAR:
  631                         rl8139_reg = RL_LPAR;
  632                         break;
  633                 case MII_PHYIDR1:
  634                 case MII_PHYIDR2:
  635                         RL_UNLOCK(sc);
  636                         return(0);
  637                 /*
  638                  * Allow the rlphy driver to read the media status
  639                  * register. If we have a link partner which does not
  640                  * support NWAY, this is the register which will tell
  641                  * us the results of parallel detection.
  642                  */
  643                 case RL_MEDIASTAT:
  644                         rval = CSR_READ_1(sc, RL_MEDIASTAT);
  645                         RL_UNLOCK(sc);
  646                         return(rval);
  647                 default:
  648                         printf("rl%d: bad phy register\n", sc->rl_unit);
  649                         RL_UNLOCK(sc);
  650                         return(0);
  651                 }
  652                 rval = CSR_READ_2(sc, rl8139_reg);
  653                 RL_UNLOCK(sc);
  654                 return(rval);
  655         }
  656 
  657         bzero((char *)&frame, sizeof(frame));
  658 
  659         frame.mii_phyaddr = phy;
  660         frame.mii_regaddr = reg;
  661         rl_mii_readreg(sc, &frame);
  662         RL_UNLOCK(sc);
  663 
  664         return(frame.mii_data);
  665 }
  666 
  667 static int
  668 rl_miibus_writereg(dev, phy, reg, data)
  669         device_t                dev;
  670         int                     phy, reg, data;
  671 {
  672         struct rl_softc         *sc;
  673         struct rl_mii_frame     frame;
  674         u_int16_t               rl8139_reg = 0;
  675 
  676         sc = device_get_softc(dev);
  677         RL_LOCK(sc);
  678 
  679         if (sc->rl_type == RL_8139) {
  680                 /* Pretend the internal PHY is only at address 0 */
  681                 if (phy) {
  682                         RL_UNLOCK(sc);
  683                         return(0);
  684                 }
  685                 switch(reg) {
  686                 case MII_BMCR:
  687                         rl8139_reg = RL_BMCR;
  688                         break;
  689                 case MII_BMSR:
  690                         rl8139_reg = RL_BMSR;
  691                         break;
  692                 case MII_ANAR:
  693                         rl8139_reg = RL_ANAR;
  694                         break;
  695                 case MII_ANER:
  696                         rl8139_reg = RL_ANER;
  697                         break;
  698                 case MII_ANLPAR:
  699                         rl8139_reg = RL_LPAR;
  700                         break;
  701                 case MII_PHYIDR1:
  702                 case MII_PHYIDR2:
  703                         RL_UNLOCK(sc);
  704                         return(0);
  705                         break;
  706                 default:
  707                         printf("rl%d: bad phy register\n", sc->rl_unit);
  708                         RL_UNLOCK(sc);
  709                         return(0);
  710                 }
  711                 CSR_WRITE_2(sc, rl8139_reg, data);
  712                 RL_UNLOCK(sc);
  713                 return(0);
  714         }
  715 
  716         bzero((char *)&frame, sizeof(frame));
  717 
  718         frame.mii_phyaddr = phy;
  719         frame.mii_regaddr = reg;
  720         frame.mii_data = data;
  721 
  722         rl_mii_writereg(sc, &frame);
  723 
  724         RL_UNLOCK(sc);
  725         return(0);
  726 }
  727 
  728 static void
  729 rl_miibus_statchg(dev)
  730         device_t                dev;
  731 {
  732         return;
  733 }
  734 
  735 /*
  736  * Calculate CRC of a multicast group address, return the upper 6 bits.
  737  */
  738 static u_int32_t
  739 rl_mchash(addr)
  740         caddr_t         addr;
  741 {
  742         u_int32_t       crc, carry;
  743         int             idx, bit;
  744         u_int8_t        data;
  745 
  746         /* Compute CRC for the address value. */
  747         crc = 0xFFFFFFFF; /* initial value */
  748 
  749         for (idx = 0; idx < 6; idx++) {
  750                 for (data = *addr++, bit = 0; bit < 8; bit++, data >>=1 ) {
  751                         carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
  752                         crc <<= 1;
  753                         if (carry)
  754                                 crc = (crc ^ 0x04c11db6) | carry;
  755                 }
  756         }
  757 
  758         /* return the filter bit position */
  759         return(crc >> 26);
  760 }
  761 
  762 /*
  763  * Program the 64-bit multicast hash filter.
  764  */
  765 static void
  766 rl_setmulti(sc)
  767         struct rl_softc         *sc;
  768 {
  769         struct ifnet            *ifp;
  770         int                     h = 0;
  771         u_int32_t               hashes[2] = { 0, 0 };
  772         struct ifmultiaddr      *ifma;
  773         u_int32_t               rxfilt;
  774         int                     mcnt = 0;
  775 
  776         ifp = &sc->arpcom.ac_if;
  777 
  778         rxfilt = CSR_READ_4(sc, RL_RXCFG);
  779 
  780         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
  781                 rxfilt |= RL_RXCFG_RX_MULTI;
  782                 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
  783                 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
  784                 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
  785                 return;
  786         }
  787 
  788         /* first, zot all the existing hash bits */
  789         CSR_WRITE_4(sc, RL_MAR0, 0);
  790         CSR_WRITE_4(sc, RL_MAR4, 0);
  791 
  792         /* now program new ones */
  793         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
  794                 if (ifma->ifma_addr->sa_family != AF_LINK)
  795                         continue;
  796                 h = rl_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
  797                 if (h < 32)
  798                         hashes[0] |= (1 << h);
  799                 else
  800                         hashes[1] |= (1 << (h - 32));
  801                 mcnt++;
  802         }
  803 
  804         if (mcnt)
  805                 rxfilt |= RL_RXCFG_RX_MULTI;
  806         else
  807                 rxfilt &= ~RL_RXCFG_RX_MULTI;
  808 
  809         CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
  810         CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
  811         CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
  812 
  813         return;
  814 }
  815 
  816 static void
  817 rl_reset(sc)
  818         struct rl_softc         *sc;
  819 {
  820         register int            i;
  821 
  822         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
  823 
  824         for (i = 0; i < RL_TIMEOUT; i++) {
  825                 DELAY(10);
  826                 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
  827                         break;
  828         }
  829         if (i == RL_TIMEOUT)
  830                 printf("rl%d: reset never completed!\n", sc->rl_unit);
  831 
  832         return;
  833 }
  834 
  835 /*
  836  * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
  837  * IDs against our list and return a device name if we find a match.
  838  */
  839 static int
  840 rl_probe(dev)
  841         device_t                dev;
  842 {
  843         struct rl_type          *t;
  844         struct rl_softc         *sc;
  845         int                     rid;
  846         u_int32_t               hwrev;
  847 
  848         t = rl_devs;
  849         sc = device_get_softc(dev);
  850 
  851         while(t->rl_name != NULL) {
  852                 if ((pci_get_vendor(dev) == t->rl_vid) &&
  853                     (pci_get_device(dev) == t->rl_did)) {
  854 
  855                         /*
  856                          * Temporarily map the I/O space
  857                          * so we can read the chip ID register.
  858                          */
  859                         rid = RL_RID;
  860                         sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
  861                             0, ~0, 1, RF_ACTIVE);
  862                         if (sc->rl_res == NULL) {
  863                                 device_printf(dev,
  864                                     "couldn't map ports/memory\n");
  865                                 return(ENXIO);
  866                         }
  867                         sc->rl_btag = rman_get_bustag(sc->rl_res);
  868                         sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
  869                         mtx_init(&sc->rl_mtx,
  870                             device_get_nameunit(dev),
  871                             MTX_NETWORK_LOCK, MTX_DEF);
  872                         RL_LOCK(sc);
  873                         hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
  874                         bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
  875                         RL_UNLOCK(sc);
  876                         mtx_destroy(&sc->rl_mtx);
  877 
  878                         /* Don't attach to 8139C+ or 8169/8110 chips. */
  879                         if (hwrev == RL_HWREV_8139CPLUS ||
  880                             hwrev == RL_HWREV_8169 ||
  881                             hwrev == RL_HWREV_8169S ||
  882                             hwrev == RL_HWREV_8110S) {
  883                                 t++;
  884                                 continue;
  885                         }
  886 
  887                         device_set_desc(dev, t->rl_name);
  888                         return(0);
  889                 }
  890                 t++;
  891         }
  892 
  893         return(ENXIO);
  894 }
  895 
  896 /*
  897  * Attach the interface. Allocate softc structures, do ifmedia
  898  * setup and ethernet/BPF attach.
  899  */
  900 static int
  901 rl_attach(dev)
  902         device_t                dev;
  903 {
  904         u_char                  eaddr[ETHER_ADDR_LEN];
  905         u_int16_t               as[3];
  906         struct rl_softc         *sc;
  907         struct ifnet            *ifp;
  908         u_int16_t               rl_did = 0;
  909         struct rl_type          *t;
  910         int                     unit, error = 0, rid, i;
  911 
  912         sc = device_get_softc(dev);
  913         unit = device_get_unit(dev);
  914 
  915         mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
  916             MTX_DEF | MTX_RECURSE);
  917 #ifndef BURN_BRIDGES
  918         /*
  919          * Handle power management nonsense.
  920          */
  921 
  922         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
  923                 u_int32_t               iobase, membase, irq;
  924 
  925                 /* Save important PCI config data. */
  926                 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
  927                 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
  928                 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
  929 
  930                 /* Reset the power state. */
  931                 printf("rl%d: chip is is in D%d power mode "
  932                     "-- setting to D0\n", unit,
  933                     pci_get_powerstate(dev));
  934 
  935                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
  936 
  937                 /* Restore PCI config data. */
  938                 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
  939                 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
  940                 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
  941         }
  942 #endif
  943         /*
  944          * Map control/status registers.
  945          */
  946         pci_enable_busmaster(dev);
  947 
  948         rid = RL_RID;
  949         sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
  950             0, ~0, 1, RF_ACTIVE);
  951 
  952         if (sc->rl_res == NULL) {
  953                 printf ("rl%d: couldn't map ports/memory\n", unit);
  954                 error = ENXIO;
  955                 goto fail;
  956         }
  957 
  958 #ifdef notdef
  959         /* Detect the Realtek 8139B. For some reason, this chip is very
  960          * unstable when left to autoselect the media
  961          * The best workaround is to set the device to the required
  962          * media type or to set it to the 10 Meg speed.
  963          */
  964 
  965         if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) {
  966                 printf("rl%d: Realtek 8139B detected. Warning, "
  967                     "this may be unstable in autoselect mode\n", unit);
  968         }
  969 #endif
  970 
  971         sc->rl_btag = rman_get_bustag(sc->rl_res);
  972         sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
  973 
  974         /* Allocate interrupt */
  975         rid = 0;
  976         sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
  977             RF_SHAREABLE | RF_ACTIVE);
  978 
  979         if (sc->rl_irq == NULL) {
  980                 printf("rl%d: couldn't map interrupt\n", unit);
  981                 error = ENXIO;
  982                 goto fail;
  983         }
  984 
  985         /* Reset the adapter. */
  986         rl_reset(sc);
  987         sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
  988         rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0);
  989         if (rl_did != 0x8129)
  990                 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
  991 
  992         /*
  993          * Get station address from the EEPROM.
  994          */
  995         rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
  996         for (i = 0; i < 3; i++) {
  997                 eaddr[(i * 2) + 0] = as[i] & 0xff;
  998                 eaddr[(i * 2) + 1] = as[i] >> 8;
  999         }
 1000 
 1001         /*
 1002          * A RealTek chip was detected. Inform the world.
 1003          */
 1004         printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
 1005 
 1006         sc->rl_unit = unit;
 1007         bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
 1008 
 1009         /*
 1010          * Now read the exact device type from the EEPROM to find
 1011          * out if it's an 8129 or 8139.
 1012          */
 1013         rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
 1014 
 1015         t = rl_devs;
 1016         sc->rl_type = 0;
 1017         while(t->rl_name != NULL) {
 1018                 if (rl_did == t->rl_did) {
 1019                         sc->rl_type = t->rl_basetype;
 1020                         break;
 1021                 }
 1022                 t++;
 1023         }
 1024 
 1025         if (sc->rl_type == 0) {
 1026                 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
 1027                 error = ENXIO;
 1028                 goto fail;
 1029         }
 1030 
 1031         /*
 1032          * Allocate the parent bus DMA tag appropriate for PCI.
 1033          */
 1034 #define RL_NSEG_NEW 32
 1035         error = bus_dma_tag_create(NULL,        /* parent */
 1036                         1, 0,                   /* alignment, boundary */
 1037                         BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
 1038                         BUS_SPACE_MAXADDR,      /* highaddr */
 1039                         NULL, NULL,             /* filter, filterarg */
 1040                         MAXBSIZE, RL_NSEG_NEW,  /* maxsize, nsegments */
 1041                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
 1042                         BUS_DMA_ALLOCNOW,       /* flags */
 1043                         NULL, NULL,             /* lockfunc, lockarg */
 1044                         &sc->rl_parent_tag);
 1045         if (error)
 1046                 goto fail;
 1047 
 1048         /*
 1049          * Now allocate a tag for the DMA descriptor lists.
 1050          * All of our lists are allocated as a contiguous block
 1051          * of memory.
 1052          */
 1053         error = bus_dma_tag_create(sc->rl_parent_tag,   /* parent */
 1054                         1, 0,                   /* alignment, boundary */
 1055                         BUS_SPACE_MAXADDR,      /* lowaddr */
 1056                         BUS_SPACE_MAXADDR,      /* highaddr */
 1057                         NULL, NULL,             /* filter, filterarg */
 1058                         RL_RXBUFLEN + 1518, 1,  /* maxsize,nsegments */
 1059                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
 1060                         BUS_DMA_ALLOCNOW,               /* flags */
 1061                         NULL, NULL,             /* lockfunc, lockarg */
 1062                         &sc->rl_tag);
 1063         if (error)
 1064                 goto fail;
 1065 
 1066         /*
 1067          * Now allocate a chunk of DMA-able memory based on the
 1068          * tag we just created.
 1069          */
 1070         error = bus_dmamem_alloc(sc->rl_tag,
 1071             (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
 1072             &sc->rl_cdata.rl_rx_dmamap);
 1073 
 1074         if (error) {
 1075                 printf("rl%d: no memory for list buffers!\n", unit);
 1076                 bus_dma_tag_destroy(sc->rl_tag);
 1077                 sc->rl_tag = NULL;
 1078                 goto fail;
 1079         }
 1080 
 1081         /* Leave a few bytes before the start of the RX ring buffer. */
 1082         sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
 1083         sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
 1084 
 1085         /* Do MII setup */
 1086         if (mii_phy_probe(dev, &sc->rl_miibus,
 1087             rl_ifmedia_upd, rl_ifmedia_sts)) {
 1088                 printf("rl%d: MII without any phy!\n", sc->rl_unit);
 1089                 error = ENXIO;
 1090                 goto fail;
 1091         }
 1092 
 1093         ifp = &sc->arpcom.ac_if;
 1094         ifp->if_softc = sc;
 1095         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 1096         ifp->if_mtu = ETHERMTU;
 1097         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 1098         ifp->if_ioctl = rl_ioctl;
 1099         ifp->if_output = ether_output;
 1100         ifp->if_start = rl_start;
 1101         ifp->if_watchdog = rl_watchdog;
 1102         ifp->if_init = rl_init;
 1103         ifp->if_baudrate = 10000000;
 1104         ifp->if_capabilities = IFCAP_VLAN_MTU;
 1105         ifp->if_capenable = ifp->if_capabilities;
 1106         ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
 1107         
 1108         callout_handle_init(&sc->rl_stat_ch);
 1109 
 1110         /*
 1111          * Call MI attach routine.
 1112          */
 1113         ether_ifattach(ifp, eaddr);
 1114 
 1115         /* Hook interrupt last to avoid having to lock softc */
 1116         error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
 1117             rl_intr, sc, &sc->rl_intrhand);
 1118 
 1119         if (error) {
 1120                 printf("rl%d: couldn't set up irq\n", unit);
 1121                 ether_ifdetach(ifp);
 1122                 goto fail;
 1123         }
 1124 
 1125 fail:
 1126         if (error)
 1127                 rl_detach(dev);
 1128 
 1129         return (error);
 1130 }
 1131 
 1132 /*
 1133  * Shutdown hardware and free up resources. This can be called any
 1134  * time after the mutex has been initialized. It is called in both
 1135  * the error case in attach and the normal detach case so it needs
 1136  * to be careful about only freeing resources that have actually been
 1137  * allocated.
 1138  */
 1139 static int
 1140 rl_detach(dev)
 1141         device_t                dev;
 1142 {
 1143         struct rl_softc         *sc;
 1144         struct ifnet            *ifp;
 1145 
 1146         sc = device_get_softc(dev);
 1147         KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
 1148         RL_LOCK(sc);
 1149         ifp = &sc->arpcom.ac_if;
 1150 
 1151         /* These should only be active if attach succeeded */
 1152         if (device_is_attached(dev)) {
 1153                 rl_stop(sc);
 1154                 ether_ifdetach(ifp);
 1155         }
 1156         if (sc->rl_miibus)
 1157                 device_delete_child(dev, sc->rl_miibus);
 1158         bus_generic_detach(dev);
 1159 
 1160         if (sc->rl_intrhand)
 1161                 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
 1162         if (sc->rl_irq)
 1163                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
 1164         if (sc->rl_res)
 1165                 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
 1166 
 1167         if (sc->rl_tag) {
 1168                 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
 1169                 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
 1170                     sc->rl_cdata.rl_rx_dmamap);
 1171                 bus_dma_tag_destroy(sc->rl_tag);
 1172         }
 1173         if (sc->rl_parent_tag)
 1174                 bus_dma_tag_destroy(sc->rl_parent_tag);
 1175 
 1176         RL_UNLOCK(sc);
 1177         mtx_destroy(&sc->rl_mtx);
 1178 
 1179         return(0);
 1180 }
 1181 
 1182 /*
 1183  * Initialize the transmit descriptors.
 1184  */
 1185 static int
 1186 rl_list_tx_init(sc)
 1187         struct rl_softc         *sc;
 1188 {
 1189         struct rl_chain_data    *cd;
 1190         int                     i;
 1191 
 1192         cd = &sc->rl_cdata;
 1193         for (i = 0; i < RL_TX_LIST_CNT; i++) {
 1194                 cd->rl_tx_chain[i] = NULL;
 1195                 CSR_WRITE_4(sc,
 1196                     RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
 1197         }
 1198 
 1199         sc->rl_cdata.cur_tx = 0;
 1200         sc->rl_cdata.last_tx = 0;
 1201 
 1202         return(0);
 1203 }
 1204 
 1205 /*
 1206  * A frame has been uploaded: pass the resulting mbuf chain up to
 1207  * the higher level protocols.
 1208  *
 1209  * You know there's something wrong with a PCI bus-master chip design
 1210  * when you have to use m_devget().
 1211  *
 1212  * The receive operation is badly documented in the datasheet, so I'll
 1213  * attempt to document it here. The driver provides a buffer area and
 1214  * places its base address in the RX buffer start address register.
 1215  * The chip then begins copying frames into the RX buffer. Each frame
 1216  * is preceded by a 32-bit RX status word which specifies the length
 1217  * of the frame and certain other status bits. Each frame (starting with
 1218  * the status word) is also 32-bit aligned. The frame length is in the
 1219  * first 16 bits of the status word; the lower 15 bits correspond with
 1220  * the 'rx status register' mentioned in the datasheet.
 1221  *
 1222  * Note: to make the Alpha happy, the frame payload needs to be aligned
 1223  * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
 1224  * as the offset argument to m_devget().
 1225  */
 1226 static void
 1227 rl_rxeof(sc)
 1228         struct rl_softc         *sc;
 1229 {
 1230         struct mbuf             *m;
 1231         struct ifnet            *ifp;
 1232         int                     total_len = 0;
 1233         u_int32_t               rxstat;
 1234         caddr_t                 rxbufpos;
 1235         int                     wrap = 0;
 1236         u_int16_t               cur_rx;
 1237         u_int16_t               limit;
 1238         u_int16_t               rx_bytes = 0, max_bytes;
 1239 
 1240         RL_LOCK_ASSERT(sc);
 1241 
 1242         ifp = &sc->arpcom.ac_if;
 1243 
 1244         bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
 1245             BUS_DMASYNC_POSTREAD);
 1246 
 1247         cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
 1248 
 1249         /* Do not try to read past this point. */
 1250         limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
 1251 
 1252         if (limit < cur_rx)
 1253                 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
 1254         else
 1255                 max_bytes = limit - cur_rx;
 1256 
 1257         while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
 1258 #ifdef DEVICE_POLLING
 1259                 if (ifp->if_flags & IFF_POLLING) {
 1260                         if (sc->rxcycles <= 0)
 1261                                 break;
 1262                         sc->rxcycles--;
 1263                 }
 1264 #endif /* DEVICE_POLLING */
 1265                 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
 1266                 rxstat = le32toh(*(u_int32_t *)rxbufpos);
 1267 
 1268                 /*
 1269                  * Here's a totally undocumented fact for you. When the
 1270                  * RealTek chip is in the process of copying a packet into
 1271                  * RAM for you, the length will be 0xfff0. If you spot a
 1272                  * packet header with this value, you need to stop. The
 1273                  * datasheet makes absolutely no mention of this and
 1274                  * RealTek should be shot for this.
 1275                  */
 1276                 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
 1277                         break;
 1278 
 1279                 if (!(rxstat & RL_RXSTAT_RXOK)) {
 1280                         ifp->if_ierrors++;
 1281                         rl_init(sc);
 1282                         return;
 1283                 }
 1284 
 1285                 /* No errors; receive the packet. */
 1286                 total_len = rxstat >> 16;
 1287                 rx_bytes += total_len + 4;
 1288 
 1289                 /*
 1290                  * XXX The RealTek chip includes the CRC with every
 1291                  * received frame, and there's no way to turn this
 1292                  * behavior off (at least, I can't find anything in
 1293                  * the manual that explains how to do it) so we have
 1294                  * to trim off the CRC manually.
 1295                  */
 1296                 total_len -= ETHER_CRC_LEN;
 1297 
 1298                 /*
 1299                  * Avoid trying to read more bytes than we know
 1300                  * the chip has prepared for us.
 1301                  */
 1302                 if (rx_bytes > max_bytes)
 1303                         break;
 1304 
 1305                 rxbufpos = sc->rl_cdata.rl_rx_buf +
 1306                         ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
 1307 
 1308                 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
 1309                         rxbufpos = sc->rl_cdata.rl_rx_buf;
 1310 
 1311                 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
 1312 
 1313                 if (total_len > wrap) {
 1314                         m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
 1315                             NULL);
 1316                         if (m == NULL) {
 1317                                 ifp->if_ierrors++;
 1318                         } else {
 1319                                 m_copyback(m, wrap, total_len - wrap,
 1320                                         sc->rl_cdata.rl_rx_buf);
 1321                         }
 1322                         cur_rx = (total_len - wrap + ETHER_CRC_LEN);
 1323                 } else {
 1324                         m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
 1325                             NULL);
 1326                         if (m == NULL) {
 1327                                 ifp->if_ierrors++;
 1328                         }
 1329                         cur_rx += total_len + 4 + ETHER_CRC_LEN;
 1330                 }
 1331 
 1332                 /*
 1333                  * Round up to 32-bit boundary.
 1334                  */
 1335                 cur_rx = (cur_rx + 3) & ~3;
 1336                 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
 1337 
 1338                 if (m == NULL)
 1339                         continue;
 1340 
 1341                 ifp->if_ipackets++;
 1342                 RL_UNLOCK(sc);
 1343                 (*ifp->if_input)(ifp, m);
 1344                 RL_LOCK(sc);
 1345         }
 1346 
 1347         return;
 1348 }
 1349 
 1350 /*
 1351  * A frame was downloaded to the chip. It's safe for us to clean up
 1352  * the list buffers.
 1353  */
 1354 static void
 1355 rl_txeof(sc)
 1356         struct rl_softc         *sc;
 1357 {
 1358         struct ifnet            *ifp;
 1359         u_int32_t               txstat;
 1360 
 1361         ifp = &sc->arpcom.ac_if;
 1362 
 1363         /*
 1364          * Go through our tx list and free mbufs for those
 1365          * frames that have been uploaded.
 1366          */
 1367         do {
 1368                 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
 1369                 if (!(txstat & (RL_TXSTAT_TX_OK|
 1370                     RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
 1371                         break;
 1372 
 1373                 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
 1374 
 1375                 if (RL_LAST_TXMBUF(sc) != NULL) {
 1376                         bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
 1377                         bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
 1378                         m_freem(RL_LAST_TXMBUF(sc));
 1379                         RL_LAST_TXMBUF(sc) = NULL;
 1380                 }
 1381                 if (txstat & RL_TXSTAT_TX_OK)
 1382                         ifp->if_opackets++;
 1383                 else {
 1384                         int                     oldthresh;
 1385                         ifp->if_oerrors++;
 1386                         if ((txstat & RL_TXSTAT_TXABRT) ||
 1387                             (txstat & RL_TXSTAT_OUTOFWIN))
 1388                                 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
 1389                         oldthresh = sc->rl_txthresh;
 1390                         /* error recovery */
 1391                         rl_reset(sc);
 1392                         rl_init(sc);
 1393                         /*
 1394                          * If there was a transmit underrun,
 1395                          * bump the TX threshold.
 1396                          */
 1397                         if (txstat & RL_TXSTAT_TX_UNDERRUN)
 1398                                 sc->rl_txthresh = oldthresh + 32;
 1399                         return;
 1400                 }
 1401                 RL_INC(sc->rl_cdata.last_tx);
 1402                 ifp->if_flags &= ~IFF_OACTIVE;
 1403         } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
 1404 
 1405         ifp->if_timer =
 1406             (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5;
 1407 
 1408         return;
 1409 }
 1410 
 1411 static void
 1412 rl_tick(xsc)
 1413         void                    *xsc;
 1414 {
 1415         struct rl_softc         *sc;
 1416         struct mii_data         *mii;
 1417 
 1418         sc = xsc;
 1419         RL_LOCK(sc);
 1420         mii = device_get_softc(sc->rl_miibus);
 1421 
 1422         mii_tick(mii);
 1423 
 1424         sc->rl_stat_ch = timeout(rl_tick, sc, hz);
 1425         RL_UNLOCK(sc);
 1426 
 1427         return;
 1428 }
 1429 
 1430 #ifdef DEVICE_POLLING
 1431 static void
 1432 rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
 1433 {
 1434         struct rl_softc *sc = ifp->if_softc;
 1435 
 1436         RL_LOCK(sc);
 1437         if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
 1438                 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
 1439                 goto done;
 1440         }
 1441 
 1442         sc->rxcycles = count;
 1443         rl_rxeof(sc);
 1444         rl_txeof(sc);
 1445         if (ifp->if_snd.ifq_head != NULL)
 1446                 rl_start(ifp);
 1447 
 1448         if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
 1449                 u_int16_t       status;
 1450 
 1451                 status = CSR_READ_2(sc, RL_ISR);
 1452                 if (status == 0xffff)
 1453                         goto done;
 1454                 if (status)
 1455                         CSR_WRITE_2(sc, RL_ISR, status);
 1456 
 1457                 /*
 1458                  * XXX check behaviour on receiver stalls.
 1459                  */
 1460 
 1461                 if (status & RL_ISR_SYSTEM_ERR) {
 1462                         rl_reset(sc);
 1463                         rl_init(sc);
 1464                 }
 1465         }
 1466 done:
 1467         RL_UNLOCK(sc);
 1468 }
 1469 #endif /* DEVICE_POLLING */
 1470 
 1471 static void
 1472 rl_intr(arg)
 1473         void                    *arg;
 1474 {
 1475         struct rl_softc         *sc;
 1476         struct ifnet            *ifp;
 1477         u_int16_t               status;
 1478 
 1479         sc = arg;
 1480 
 1481         if (sc->suspended) {
 1482                 return;
 1483         }
 1484 
 1485         RL_LOCK(sc);
 1486         ifp = &sc->arpcom.ac_if;
 1487 
 1488 #ifdef DEVICE_POLLING
 1489         if  (ifp->if_flags & IFF_POLLING)
 1490                 goto done;
 1491         if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */
 1492                 CSR_WRITE_2(sc, RL_IMR, 0x0000);
 1493                 rl_poll(ifp, 0, 1);
 1494                 goto done;
 1495         }
 1496 #endif /* DEVICE_POLLING */
 1497 
 1498         for (;;) {
 1499 
 1500                 status = CSR_READ_2(sc, RL_ISR);
 1501                 /* If the card has gone away the read returns 0xffff. */
 1502                 if (status == 0xffff)
 1503                         break;
 1504                 if (status)
 1505                         CSR_WRITE_2(sc, RL_ISR, status);
 1506 
 1507                 if ((status & RL_INTRS) == 0)
 1508                         break;
 1509 
 1510                 if (status & RL_ISR_RX_OK)
 1511                         rl_rxeof(sc);
 1512 
 1513                 if (status & RL_ISR_RX_ERR)
 1514                         rl_rxeof(sc);
 1515 
 1516                 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
 1517                         rl_txeof(sc);
 1518 
 1519                 if (status & RL_ISR_SYSTEM_ERR) {
 1520                         rl_reset(sc);
 1521                         rl_init(sc);
 1522                 }
 1523 
 1524         }
 1525 
 1526         if (ifp->if_snd.ifq_head != NULL)
 1527                 rl_start(ifp);
 1528 
 1529 #ifdef DEVICE_POLLING
 1530 done:
 1531 #endif
 1532         RL_UNLOCK(sc);
 1533 
 1534         return;
 1535 }
 1536 
 1537 /*
 1538  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
 1539  * pointers to the fragment pointers.
 1540  */
 1541 static int
 1542 rl_encap(sc, m_head)
 1543         struct rl_softc         *sc;
 1544         struct mbuf             *m_head;
 1545 {
 1546         struct mbuf             *m_new = NULL;
 1547 
 1548         /*
 1549          * The RealTek is brain damaged and wants longword-aligned
 1550          * TX buffers, plus we can only have one fragment buffer
 1551          * per packet. We have to copy pretty much all the time.
 1552          */
 1553         m_new = m_defrag(m_head, M_DONTWAIT);
 1554 
 1555         if (m_new == NULL) {
 1556                 m_freem(m_head);
 1557                 return(1);
 1558         }
 1559         m_head = m_new;
 1560 
 1561         /* Pad frames to at least 60 bytes. */
 1562         if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
 1563                 /*
 1564                  * Make security concious people happy: zero out the
 1565                  * bytes in the pad area, since we don't know what
 1566                  * this mbuf cluster buffer's previous user might
 1567                  * have left in it.
 1568                  */
 1569                 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
 1570                      RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
 1571                 m_head->m_pkthdr.len +=
 1572                     (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
 1573                 m_head->m_len = m_head->m_pkthdr.len;
 1574         }
 1575 
 1576         RL_CUR_TXMBUF(sc) = m_head;
 1577 
 1578         return(0);
 1579 }
 1580 
 1581 /*
 1582  * Main transmit routine.
 1583  */
 1584 
 1585 static void
 1586 rl_start(ifp)
 1587         struct ifnet            *ifp;
 1588 {
 1589         struct rl_softc         *sc;
 1590         struct mbuf             *m_head = NULL;
 1591 
 1592         sc = ifp->if_softc;
 1593         RL_LOCK(sc);
 1594 
 1595         while(RL_CUR_TXMBUF(sc) == NULL) {
 1596                 IF_DEQUEUE(&ifp->if_snd, m_head);
 1597                 if (m_head == NULL)
 1598                         break;
 1599 
 1600                 if (rl_encap(sc, m_head)) {
 1601                         break;
 1602                 }
 1603 
 1604                 /*
 1605                  * If there's a BPF listener, bounce a copy of this frame
 1606                  * to him.
 1607                  */
 1608                 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
 1609 
 1610                 /*
 1611                  * Transmit the frame.
 1612                  */
 1613                 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
 1614                 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
 1615                     mtod(RL_CUR_TXMBUF(sc), void *),
 1616                     RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
 1617                 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
 1618                     BUS_DMASYNC_PREREAD);
 1619                 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
 1620                     RL_TXTHRESH(sc->rl_txthresh) |
 1621                     RL_CUR_TXMBUF(sc)->m_pkthdr.len);
 1622 
 1623                 RL_INC(sc->rl_cdata.cur_tx);
 1624 
 1625                 /*
 1626                  * Set a timeout in case the chip goes out to lunch.
 1627                  */
 1628                 ifp->if_timer = 5;
 1629         }
 1630 
 1631         /*
 1632          * We broke out of the loop because all our TX slots are
 1633          * full. Mark the NIC as busy until it drains some of the
 1634          * packets from the queue.
 1635          */
 1636         if (RL_CUR_TXMBUF(sc) != NULL)
 1637                 ifp->if_flags |= IFF_OACTIVE;
 1638 
 1639         RL_UNLOCK(sc);
 1640 
 1641         return;
 1642 }
 1643 
 1644 static void
 1645 rl_init(xsc)
 1646         void                    *xsc;
 1647 {
 1648         struct rl_softc         *sc = xsc;
 1649         struct ifnet            *ifp = &sc->arpcom.ac_if;
 1650         struct mii_data         *mii;
 1651         u_int32_t               rxcfg = 0;
 1652 
 1653         RL_LOCK(sc);
 1654         mii = device_get_softc(sc->rl_miibus);
 1655 
 1656         /*
 1657          * Cancel pending I/O and free all RX/TX buffers.
 1658          */
 1659         rl_stop(sc);
 1660 
 1661         /*
 1662          * Init our MAC address.  Even though the chipset
 1663          * documentation doesn't mention it, we need to enter "Config
 1664          * register write enable" mode to modify the ID registers.
 1665          */
 1666         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
 1667         CSR_WRITE_STREAM_4(sc, RL_IDR0,
 1668             *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
 1669         CSR_WRITE_STREAM_4(sc, RL_IDR4,
 1670             *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
 1671         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 1672 
 1673         /* Init the RX buffer pointer register. */
 1674         bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
 1675             sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
 1676         bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
 1677             BUS_DMASYNC_PREWRITE);
 1678 
 1679         /* Init TX descriptors. */
 1680         rl_list_tx_init(sc);
 1681 
 1682         /*
 1683          * Enable transmit and receive.
 1684          */
 1685         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
 1686 
 1687         /*
 1688          * Set the initial TX and RX configuration.
 1689          */
 1690         CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
 1691         CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
 1692 
 1693         /* Set the individual bit to receive frames for this host only. */
 1694         rxcfg = CSR_READ_4(sc, RL_RXCFG);
 1695         rxcfg |= RL_RXCFG_RX_INDIV;
 1696 
 1697         /* If we want promiscuous mode, set the allframes bit. */
 1698         if (ifp->if_flags & IFF_PROMISC) {
 1699                 rxcfg |= RL_RXCFG_RX_ALLPHYS;
 1700                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
 1701         } else {
 1702                 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
 1703                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
 1704         }
 1705 
 1706         /*
 1707          * Set capture broadcast bit to capture broadcast frames.
 1708          */
 1709         if (ifp->if_flags & IFF_BROADCAST) {
 1710                 rxcfg |= RL_RXCFG_RX_BROAD;
 1711                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
 1712         } else {
 1713                 rxcfg &= ~RL_RXCFG_RX_BROAD;
 1714                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
 1715         }
 1716 
 1717         /*
 1718          * Program the multicast filter, if necessary.
 1719          */
 1720         rl_setmulti(sc);
 1721 
 1722 #ifdef DEVICE_POLLING
 1723         /*
 1724          * Disable interrupts if we are polling.
 1725          */
 1726         if (ifp->if_flags & IFF_POLLING)
 1727                 CSR_WRITE_2(sc, RL_IMR, 0);
 1728         else    /* otherwise ... */
 1729 #endif /* DEVICE_POLLING */
 1730         /*
 1731          * Enable interrupts.
 1732          */
 1733         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
 1734 
 1735         /* Set initial TX threshold */
 1736         sc->rl_txthresh = RL_TX_THRESH_INIT;
 1737 
 1738         /* Start RX/TX process. */
 1739         CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
 1740 
 1741         /* Enable receiver and transmitter. */
 1742         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
 1743 
 1744         mii_mediachg(mii);
 1745 
 1746         CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
 1747 
 1748         ifp->if_flags |= IFF_RUNNING;
 1749         ifp->if_flags &= ~IFF_OACTIVE;
 1750 
 1751         sc->rl_stat_ch = timeout(rl_tick, sc, hz);
 1752         RL_UNLOCK(sc);
 1753 
 1754         return;
 1755 }
 1756 
 1757 /*
 1758  * Set media options.
 1759  */
 1760 static int
 1761 rl_ifmedia_upd(ifp)
 1762         struct ifnet            *ifp;
 1763 {
 1764         struct rl_softc         *sc;
 1765         struct mii_data         *mii;
 1766 
 1767         sc = ifp->if_softc;
 1768         mii = device_get_softc(sc->rl_miibus);
 1769         mii_mediachg(mii);
 1770 
 1771         return(0);
 1772 }
 1773 
 1774 /*
 1775  * Report current media status.
 1776  */
 1777 static void
 1778 rl_ifmedia_sts(ifp, ifmr)
 1779         struct ifnet            *ifp;
 1780         struct ifmediareq       *ifmr;
 1781 {
 1782         struct rl_softc         *sc;
 1783         struct mii_data         *mii;
 1784 
 1785         sc = ifp->if_softc;
 1786         mii = device_get_softc(sc->rl_miibus);
 1787 
 1788         mii_pollstat(mii);
 1789         ifmr->ifm_active = mii->mii_media_active;
 1790         ifmr->ifm_status = mii->mii_media_status;
 1791 
 1792         return;
 1793 }
 1794 
 1795 static int
 1796 rl_ioctl(ifp, command, data)
 1797         struct ifnet            *ifp;
 1798         u_long                  command;
 1799         caddr_t                 data;
 1800 {
 1801         struct rl_softc         *sc = ifp->if_softc;
 1802         struct ifreq            *ifr = (struct ifreq *) data;
 1803         struct mii_data         *mii;
 1804         int                     error = 0;
 1805 
 1806         RL_LOCK(sc);
 1807 
 1808         switch(command) {
 1809         case SIOCSIFFLAGS:
 1810                 if (ifp->if_flags & IFF_UP) {
 1811                         rl_init(sc);
 1812                 } else {
 1813                         if (ifp->if_flags & IFF_RUNNING)
 1814                                 rl_stop(sc);
 1815                 }
 1816                 error = 0;
 1817                 break;
 1818         case SIOCADDMULTI:
 1819         case SIOCDELMULTI:
 1820                 rl_setmulti(sc);
 1821                 error = 0;
 1822                 break;
 1823         case SIOCGIFMEDIA:
 1824         case SIOCSIFMEDIA:
 1825                 mii = device_get_softc(sc->rl_miibus);
 1826                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 1827                 break;
 1828         default:
 1829                 error = ether_ioctl(ifp, command, data);
 1830                 break;
 1831         }
 1832 
 1833         RL_UNLOCK(sc);
 1834 
 1835         return(error);
 1836 }
 1837 
 1838 static void
 1839 rl_watchdog(ifp)
 1840         struct ifnet            *ifp;
 1841 {
 1842         struct rl_softc         *sc;
 1843 
 1844         sc = ifp->if_softc;
 1845         RL_LOCK(sc);
 1846         printf("rl%d: watchdog timeout\n", sc->rl_unit);
 1847         ifp->if_oerrors++;
 1848 
 1849         rl_txeof(sc);
 1850         rl_rxeof(sc);
 1851         rl_init(sc);
 1852         RL_UNLOCK(sc);
 1853 
 1854         return;
 1855 }
 1856 
 1857 /*
 1858  * Stop the adapter and free any mbufs allocated to the
 1859  * RX and TX lists.
 1860  */
 1861 static void
 1862 rl_stop(sc)
 1863         struct rl_softc         *sc;
 1864 {
 1865         register int            i;
 1866         struct ifnet            *ifp;
 1867 
 1868         RL_LOCK(sc);
 1869         ifp = &sc->arpcom.ac_if;
 1870         ifp->if_timer = 0;
 1871 
 1872         untimeout(rl_tick, sc, sc->rl_stat_ch);
 1873         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 1874 #ifdef DEVICE_POLLING
 1875         ether_poll_deregister(ifp);
 1876 #endif /* DEVICE_POLLING */
 1877 
 1878         CSR_WRITE_1(sc, RL_COMMAND, 0x00);
 1879         CSR_WRITE_2(sc, RL_IMR, 0x0000);
 1880         bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
 1881 
 1882         /*
 1883          * Free the TX list buffers.
 1884          */
 1885         for (i = 0; i < RL_TX_LIST_CNT; i++) {
 1886                 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
 1887                         bus_dmamap_unload(sc->rl_tag,
 1888                             sc->rl_cdata.rl_tx_dmamap[i]);
 1889                         bus_dmamap_destroy(sc->rl_tag,
 1890                             sc->rl_cdata.rl_tx_dmamap[i]);
 1891                         m_freem(sc->rl_cdata.rl_tx_chain[i]);
 1892                         sc->rl_cdata.rl_tx_chain[i] = NULL;
 1893                         CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
 1894                 }
 1895         }
 1896 
 1897         RL_UNLOCK(sc);
 1898         return;
 1899 }
 1900 
 1901 /*
 1902  * Device suspend routine.  Stop the interface and save some PCI
 1903  * settings in case the BIOS doesn't restore them properly on
 1904  * resume.
 1905  */
 1906 static int
 1907 rl_suspend(dev)
 1908         device_t                dev;
 1909 {
 1910         register int            i;
 1911         struct rl_softc         *sc;
 1912 
 1913         sc = device_get_softc(dev);
 1914 
 1915         rl_stop(sc);
 1916 
 1917         for (i = 0; i < 5; i++)
 1918                 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
 1919         sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
 1920         sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
 1921         sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
 1922         sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
 1923 
 1924         sc->suspended = 1;
 1925 
 1926         return (0);
 1927 }
 1928 
 1929 /*
 1930  * Device resume routine.  Restore some PCI settings in case the BIOS
 1931  * doesn't, re-enable busmastering, and restart the interface if
 1932  * appropriate.
 1933  */
 1934 static int
 1935 rl_resume(dev)
 1936         device_t                dev;
 1937 {
 1938         register int            i;
 1939         struct rl_softc         *sc;
 1940         struct ifnet            *ifp;
 1941 
 1942         sc = device_get_softc(dev);
 1943         ifp = &sc->arpcom.ac_if;
 1944 
 1945         /* better way to do this? */
 1946         for (i = 0; i < 5; i++)
 1947                 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
 1948         pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
 1949         pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
 1950         pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
 1951         pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
 1952 
 1953         /* reenable busmastering */
 1954         pci_enable_busmaster(dev);
 1955         pci_enable_io(dev, RL_RES);
 1956 
 1957         /* reinitialize interface if necessary */
 1958         if (ifp->if_flags & IFF_UP)
 1959                 rl_init(sc);
 1960 
 1961         sc->suspended = 0;
 1962 
 1963         return (0);
 1964 }
 1965 
 1966 /*
 1967  * Stop all chip I/O so that the kernel's probe routines don't
 1968  * get confused by errant DMAs when rebooting.
 1969  */
 1970 static void
 1971 rl_shutdown(dev)
 1972         device_t                dev;
 1973 {
 1974         struct rl_softc         *sc;
 1975 
 1976         sc = device_get_softc(dev);
 1977 
 1978         rl_stop(sc);
 1979 
 1980         return;
 1981 }

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