FreeBSD/Linux Kernel Cross Reference
sys/pci/if_rl.c
1 /*-
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/5.4/sys/pci/if_rl.c 142884 2005-03-01 08:11:52Z imp $");
35
36 /*
37 * RealTek 8129/8139 PCI NIC driver
38 *
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
41 * www.realtek.com.tw.
42 *
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
46 */
47 /*
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
53 *
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
62 *
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
68 * levels.
69 *
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
73 *
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
78 * filter.
79 *
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
84 */
85
86 #include <sys/param.h>
87 #include <sys/endian.h>
88 #include <sys/systm.h>
89 #include <sys/sockio.h>
90 #include <sys/mbuf.h>
91 #include <sys/malloc.h>
92 #include <sys/kernel.h>
93 #include <sys/module.h>
94 #include <sys/socket.h>
95
96 #include <net/if.h>
97 #include <net/if_arp.h>
98 #include <net/ethernet.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
101
102 #include <net/bpf.h>
103
104 #include <machine/bus_pio.h>
105 #include <machine/bus_memio.h>
106 #include <machine/bus.h>
107 #include <machine/resource.h>
108 #include <sys/bus.h>
109 #include <sys/rman.h>
110
111 #include <dev/mii/mii.h>
112 #include <dev/mii/miivar.h>
113
114 #include <dev/pci/pcireg.h>
115 #include <dev/pci/pcivar.h>
116
117 MODULE_DEPEND(rl, pci, 1, 1, 1);
118 MODULE_DEPEND(rl, ether, 1, 1, 1);
119 MODULE_DEPEND(rl, miibus, 1, 1, 1);
120
121 /* "controller miibus0" required. See GENERIC if you get errors here. */
122 #include "miibus_if.h"
123
124 /*
125 * Default to using PIO access for this driver. On SMP systems,
126 * there appear to be problems with memory mapped mode: it looks like
127 * doing too many memory mapped access back to back in rapid succession
128 * can hang the bus. I'm inclined to blame this on crummy design/construction
129 * on the part of RealTek. Memory mapped mode does appear to work on
130 * uniprocessor systems though.
131 */
132 #define RL_USEIOSPACE
133
134 #include <pci/if_rlreg.h>
135
136 /*
137 * Various supported device vendors/types and their names.
138 */
139 static struct rl_type rl_devs[] = {
140 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
141 "RealTek 8129 10/100BaseTX" },
142 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
143 "RealTek 8139 10/100BaseTX" },
144 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
145 "RealTek 8139 10/100BaseTX CardBus" },
146 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
147 "RealTek 8100 10/100BaseTX" },
148 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
149 "Accton MPX 5030/5038 10/100BaseTX" },
150 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
151 "Delta Electronics 8139 10/100BaseTX" },
152 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
153 "Addtron Technolgy 8139 10/100BaseTX" },
154 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
155 "D-Link DFE-530TX+ 10/100BaseTX" },
156 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
157 "D-Link DFE-690TXD 10/100BaseTX" },
158 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
159 "Nortel Networks 10/100BaseTX" },
160 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
161 "Corega FEther CB-TXD" },
162 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
163 "Corega FEtherII CB-TXD" },
164 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
165 "Peppercon AG ROL-F" },
166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
167 "Planex FNW-3800-TX" },
168 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
169 "Compaq HNE-300" },
170 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
171 "LevelOne FPC-0106TX" },
172 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
173 "Edimax EP-4103DL CardBus" },
174 { 0, 0, 0, NULL }
175 };
176
177 static int rl_attach(device_t);
178 static int rl_detach(device_t);
179 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
180 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
181 static void rl_eeprom_putbyte(struct rl_softc *, int);
182 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
183 static int rl_encap(struct rl_softc *, struct mbuf * );
184 static int rl_list_tx_init(struct rl_softc *);
185 static int rl_ifmedia_upd(struct ifnet *);
186 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
187 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
188 static void rl_intr(void *);
189 static void rl_init(void *);
190 static void rl_init_locked(struct rl_softc *sc);
191 static void rl_mii_send(struct rl_softc *, uint32_t, int);
192 static void rl_mii_sync(struct rl_softc *);
193 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
194 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
195 static int rl_miibus_readreg(device_t, int, int);
196 static void rl_miibus_statchg(device_t);
197 static int rl_miibus_writereg(device_t, int, int, int);
198 #ifdef DEVICE_POLLING
199 static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd,
200 int count);
201 static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd,
202 int count);
203 #endif
204 static int rl_probe(device_t);
205 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
206 static void rl_reset(struct rl_softc *);
207 static int rl_resume(device_t);
208 static void rl_rxeof(struct rl_softc *);
209 static void rl_setmulti(struct rl_softc *);
210 static void rl_shutdown(device_t);
211 static void rl_start(struct ifnet *);
212 static void rl_start_locked(struct ifnet *);
213 static void rl_stop(struct rl_softc *);
214 static int rl_suspend(device_t);
215 static void rl_tick(void *);
216 static void rl_txeof(struct rl_softc *);
217 static void rl_watchdog(struct ifnet *);
218
219 #ifdef RL_USEIOSPACE
220 #define RL_RES SYS_RES_IOPORT
221 #define RL_RID RL_PCI_LOIO
222 #else
223 #define RL_RES SYS_RES_MEMORY
224 #define RL_RID RL_PCI_LOMEM
225 #endif
226
227 static device_method_t rl_methods[] = {
228 /* Device interface */
229 DEVMETHOD(device_probe, rl_probe),
230 DEVMETHOD(device_attach, rl_attach),
231 DEVMETHOD(device_detach, rl_detach),
232 DEVMETHOD(device_suspend, rl_suspend),
233 DEVMETHOD(device_resume, rl_resume),
234 DEVMETHOD(device_shutdown, rl_shutdown),
235
236 /* bus interface */
237 DEVMETHOD(bus_print_child, bus_generic_print_child),
238 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
239
240 /* MII interface */
241 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
242 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
243 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
244
245 { 0, 0 }
246 };
247
248 static driver_t rl_driver = {
249 "rl",
250 rl_methods,
251 sizeof(struct rl_softc)
252 };
253
254 static devclass_t rl_devclass;
255
256 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
257 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
258 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
259
260 #define EE_SET(x) \
261 CSR_WRITE_1(sc, RL_EECMD, \
262 CSR_READ_1(sc, RL_EECMD) | x)
263
264 #define EE_CLR(x) \
265 CSR_WRITE_1(sc, RL_EECMD, \
266 CSR_READ_1(sc, RL_EECMD) & ~x)
267
268 static void
269 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
270 {
271 struct rl_softc *sc = arg;
272
273 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
274 }
275
276 static void
277 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
278 {
279 struct rl_softc *sc = arg;
280
281 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
282 }
283
284 /*
285 * Send a read command and address to the EEPROM, check for ACK.
286 */
287 static void
288 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
289 {
290 register int d, i;
291
292 d = addr | sc->rl_eecmd_read;
293
294 /*
295 * Feed in each bit and strobe the clock.
296 */
297 for (i = 0x400; i; i >>= 1) {
298 if (d & i) {
299 EE_SET(RL_EE_DATAIN);
300 } else {
301 EE_CLR(RL_EE_DATAIN);
302 }
303 DELAY(100);
304 EE_SET(RL_EE_CLK);
305 DELAY(150);
306 EE_CLR(RL_EE_CLK);
307 DELAY(100);
308 }
309 }
310
311 /*
312 * Read a word of data stored in the EEPROM at address 'addr.'
313 */
314 static void
315 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
316 {
317 register int i;
318 uint16_t word = 0;
319
320 /* Enter EEPROM access mode. */
321 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
322
323 /*
324 * Send address of word we want to read.
325 */
326 rl_eeprom_putbyte(sc, addr);
327
328 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
329
330 /*
331 * Start reading bits from EEPROM.
332 */
333 for (i = 0x8000; i; i >>= 1) {
334 EE_SET(RL_EE_CLK);
335 DELAY(100);
336 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
337 word |= i;
338 EE_CLR(RL_EE_CLK);
339 DELAY(100);
340 }
341
342 /* Turn off EEPROM access mode. */
343 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
344
345 *dest = word;
346 }
347
348 /*
349 * Read a sequence of words from the EEPROM.
350 */
351 static void
352 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
353 {
354 int i;
355 uint16_t word = 0, *ptr;
356
357 for (i = 0; i < cnt; i++) {
358 rl_eeprom_getword(sc, off + i, &word);
359 ptr = (uint16_t *)(dest + (i * 2));
360 if (swap)
361 *ptr = ntohs(word);
362 else
363 *ptr = word;
364 }
365 }
366
367 /*
368 * MII access routines are provided for the 8129, which
369 * doesn't have a built-in PHY. For the 8139, we fake things
370 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
371 * direct access PHY registers.
372 */
373 #define MII_SET(x) \
374 CSR_WRITE_1(sc, RL_MII, \
375 CSR_READ_1(sc, RL_MII) | (x))
376
377 #define MII_CLR(x) \
378 CSR_WRITE_1(sc, RL_MII, \
379 CSR_READ_1(sc, RL_MII) & ~(x))
380
381 /*
382 * Sync the PHYs by setting data bit and strobing the clock 32 times.
383 */
384 static void
385 rl_mii_sync(struct rl_softc *sc)
386 {
387 register int i;
388
389 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
390
391 for (i = 0; i < 32; i++) {
392 MII_SET(RL_MII_CLK);
393 DELAY(1);
394 MII_CLR(RL_MII_CLK);
395 DELAY(1);
396 }
397 }
398
399 /*
400 * Clock a series of bits through the MII.
401 */
402 static void
403 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
404 {
405 int i;
406
407 MII_CLR(RL_MII_CLK);
408
409 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
410 if (bits & i) {
411 MII_SET(RL_MII_DATAOUT);
412 } else {
413 MII_CLR(RL_MII_DATAOUT);
414 }
415 DELAY(1);
416 MII_CLR(RL_MII_CLK);
417 DELAY(1);
418 MII_SET(RL_MII_CLK);
419 }
420 }
421
422 /*
423 * Read an PHY register through the MII.
424 */
425 static int
426 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
427 {
428 int i, ack;
429
430 RL_LOCK(sc);
431
432 /* Set up frame for RX. */
433 frame->mii_stdelim = RL_MII_STARTDELIM;
434 frame->mii_opcode = RL_MII_READOP;
435 frame->mii_turnaround = 0;
436 frame->mii_data = 0;
437
438 CSR_WRITE_2(sc, RL_MII, 0);
439
440 /* Turn on data xmit. */
441 MII_SET(RL_MII_DIR);
442
443 rl_mii_sync(sc);
444
445 /* Send command/address info. */
446 rl_mii_send(sc, frame->mii_stdelim, 2);
447 rl_mii_send(sc, frame->mii_opcode, 2);
448 rl_mii_send(sc, frame->mii_phyaddr, 5);
449 rl_mii_send(sc, frame->mii_regaddr, 5);
450
451 /* Idle bit */
452 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
453 DELAY(1);
454 MII_SET(RL_MII_CLK);
455 DELAY(1);
456
457 /* Turn off xmit. */
458 MII_CLR(RL_MII_DIR);
459
460 /* Check for ack */
461 MII_CLR(RL_MII_CLK);
462 DELAY(1);
463 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
464 MII_SET(RL_MII_CLK);
465 DELAY(1);
466
467 /*
468 * Now try reading data bits. If the ack failed, we still
469 * need to clock through 16 cycles to keep the PHY(s) in sync.
470 */
471 if (ack) {
472 for(i = 0; i < 16; i++) {
473 MII_CLR(RL_MII_CLK);
474 DELAY(1);
475 MII_SET(RL_MII_CLK);
476 DELAY(1);
477 }
478 goto fail;
479 }
480
481 for (i = 0x8000; i; i >>= 1) {
482 MII_CLR(RL_MII_CLK);
483 DELAY(1);
484 if (!ack) {
485 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
486 frame->mii_data |= i;
487 DELAY(1);
488 }
489 MII_SET(RL_MII_CLK);
490 DELAY(1);
491 }
492
493 fail:
494 MII_CLR(RL_MII_CLK);
495 DELAY(1);
496 MII_SET(RL_MII_CLK);
497 DELAY(1);
498
499 RL_UNLOCK(sc);
500
501 return (ack ? 1 : 0);
502 }
503
504 /*
505 * Write to a PHY register through the MII.
506 */
507 static int
508 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
509 {
510
511 RL_LOCK(sc);
512
513 /* Set up frame for TX. */
514 frame->mii_stdelim = RL_MII_STARTDELIM;
515 frame->mii_opcode = RL_MII_WRITEOP;
516 frame->mii_turnaround = RL_MII_TURNAROUND;
517
518 /* Turn on data output. */
519 MII_SET(RL_MII_DIR);
520
521 rl_mii_sync(sc);
522
523 rl_mii_send(sc, frame->mii_stdelim, 2);
524 rl_mii_send(sc, frame->mii_opcode, 2);
525 rl_mii_send(sc, frame->mii_phyaddr, 5);
526 rl_mii_send(sc, frame->mii_regaddr, 5);
527 rl_mii_send(sc, frame->mii_turnaround, 2);
528 rl_mii_send(sc, frame->mii_data, 16);
529
530 /* Idle bit. */
531 MII_SET(RL_MII_CLK);
532 DELAY(1);
533 MII_CLR(RL_MII_CLK);
534 DELAY(1);
535
536 /* Turn off xmit. */
537 MII_CLR(RL_MII_DIR);
538
539 RL_UNLOCK(sc);
540
541 return (0);
542 }
543
544 static int
545 rl_miibus_readreg(device_t dev, int phy, int reg)
546 {
547 struct rl_softc *sc;
548 struct rl_mii_frame frame;
549 uint16_t rval = 0;
550 uint16_t rl8139_reg = 0;
551
552 sc = device_get_softc(dev);
553
554 if (sc->rl_type == RL_8139) {
555 /* Pretend the internal PHY is only at address 0 */
556 if (phy) {
557 return (0);
558 }
559 switch (reg) {
560 case MII_BMCR:
561 rl8139_reg = RL_BMCR;
562 break;
563 case MII_BMSR:
564 rl8139_reg = RL_BMSR;
565 break;
566 case MII_ANAR:
567 rl8139_reg = RL_ANAR;
568 break;
569 case MII_ANER:
570 rl8139_reg = RL_ANER;
571 break;
572 case MII_ANLPAR:
573 rl8139_reg = RL_LPAR;
574 break;
575 case MII_PHYIDR1:
576 case MII_PHYIDR2:
577 return (0);
578 /*
579 * Allow the rlphy driver to read the media status
580 * register. If we have a link partner which does not
581 * support NWAY, this is the register which will tell
582 * us the results of parallel detection.
583 */
584 case RL_MEDIASTAT:
585 rval = CSR_READ_1(sc, RL_MEDIASTAT);
586 return (rval);
587 default:
588 if_printf(&sc->arpcom.ac_if, "bad phy register\n");
589 return (0);
590 }
591 rval = CSR_READ_2(sc, rl8139_reg);
592 return (rval);
593 }
594
595 bzero((char *)&frame, sizeof(frame));
596 frame.mii_phyaddr = phy;
597 frame.mii_regaddr = reg;
598 rl_mii_readreg(sc, &frame);
599
600 return (frame.mii_data);
601 }
602
603 static int
604 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
605 {
606 struct rl_softc *sc;
607 struct rl_mii_frame frame;
608 uint16_t rl8139_reg = 0;
609
610 sc = device_get_softc(dev);
611
612 if (sc->rl_type == RL_8139) {
613 /* Pretend the internal PHY is only at address 0 */
614 if (phy) {
615 return (0);
616 }
617 switch (reg) {
618 case MII_BMCR:
619 rl8139_reg = RL_BMCR;
620 break;
621 case MII_BMSR:
622 rl8139_reg = RL_BMSR;
623 break;
624 case MII_ANAR:
625 rl8139_reg = RL_ANAR;
626 break;
627 case MII_ANER:
628 rl8139_reg = RL_ANER;
629 break;
630 case MII_ANLPAR:
631 rl8139_reg = RL_LPAR;
632 break;
633 case MII_PHYIDR1:
634 case MII_PHYIDR2:
635 return (0);
636 break;
637 default:
638 if_printf(&sc->arpcom.ac_if, "bad phy register\n");
639 return (0);
640 }
641 CSR_WRITE_2(sc, rl8139_reg, data);
642 return (0);
643 }
644
645 bzero((char *)&frame, sizeof(frame));
646 frame.mii_phyaddr = phy;
647 frame.mii_regaddr = reg;
648 frame.mii_data = data;
649 rl_mii_writereg(sc, &frame);
650
651 return (0);
652 }
653
654 static void
655 rl_miibus_statchg(device_t dev)
656 {
657 }
658
659 /*
660 * Program the 64-bit multicast hash filter.
661 */
662 static void
663 rl_setmulti(struct rl_softc *sc)
664 {
665 struct ifnet *ifp = &sc->arpcom.ac_if;
666 int h = 0;
667 uint32_t hashes[2] = { 0, 0 };
668 struct ifmultiaddr *ifma;
669 uint32_t rxfilt;
670 int mcnt = 0;
671
672 RL_LOCK_ASSERT(sc);
673
674 rxfilt = CSR_READ_4(sc, RL_RXCFG);
675
676 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
677 rxfilt |= RL_RXCFG_RX_MULTI;
678 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
679 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
680 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
681 return;
682 }
683
684 /* first, zot all the existing hash bits */
685 CSR_WRITE_4(sc, RL_MAR0, 0);
686 CSR_WRITE_4(sc, RL_MAR4, 0);
687
688 /* now program new ones */
689 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
690 if (ifma->ifma_addr->sa_family != AF_LINK)
691 continue;
692 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
693 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
694 if (h < 32)
695 hashes[0] |= (1 << h);
696 else
697 hashes[1] |= (1 << (h - 32));
698 mcnt++;
699 }
700
701 if (mcnt)
702 rxfilt |= RL_RXCFG_RX_MULTI;
703 else
704 rxfilt &= ~RL_RXCFG_RX_MULTI;
705
706 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
707 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
708 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
709 }
710
711 static void
712 rl_reset(struct rl_softc *sc)
713 {
714 register int i;
715
716 RL_LOCK_ASSERT(sc);
717
718 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
719
720 for (i = 0; i < RL_TIMEOUT; i++) {
721 DELAY(10);
722 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
723 break;
724 }
725 if (i == RL_TIMEOUT)
726 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
727 }
728
729 /*
730 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
731 * IDs against our list and return a device name if we find a match.
732 */
733 static int
734 rl_probe(device_t dev)
735 {
736 struct rl_softc *sc;
737 struct rl_type *t = rl_devs;
738 int rid;
739 uint32_t hwrev;
740
741 sc = device_get_softc(dev);
742
743 while (t->rl_name != NULL) {
744 if ((pci_get_vendor(dev) == t->rl_vid) &&
745 (pci_get_device(dev) == t->rl_did)) {
746 /*
747 * Temporarily map the I/O space
748 * so we can read the chip ID register.
749 */
750 rid = RL_RID;
751 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
752 RF_ACTIVE);
753 if (sc->rl_res == NULL) {
754 device_printf(dev,
755 "couldn't map ports/memory\n");
756 return (ENXIO);
757 }
758 sc->rl_btag = rman_get_bustag(sc->rl_res);
759 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
760
761 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
762 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
763
764 /* Don't attach to 8139C+ or 8169/8110 chips. */
765 if (hwrev == RL_HWREV_8139CPLUS ||
766 (hwrev == RL_HWREV_8169 &&
767 t->rl_did == RT_DEVICEID_8169) ||
768 hwrev == RL_HWREV_8169S ||
769 hwrev == RL_HWREV_8110S) {
770 t++;
771 continue;
772 }
773
774 device_set_desc(dev, t->rl_name);
775 return (BUS_PROBE_DEFAULT);
776 }
777 t++;
778 }
779
780 return (ENXIO);
781 }
782
783 /*
784 * Attach the interface. Allocate softc structures, do ifmedia
785 * setup and ethernet/BPF attach.
786 */
787 static int
788 rl_attach(device_t dev)
789 {
790 uint8_t eaddr[ETHER_ADDR_LEN];
791 uint16_t as[3];
792 struct ifnet *ifp;
793 struct rl_softc *sc;
794 struct rl_type *t;
795 int error = 0, i, rid;
796 int unit;
797 uint16_t rl_did = 0;
798
799 sc = device_get_softc(dev);
800 unit = device_get_unit(dev);
801
802 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
803 MTX_DEF);
804
805 pci_enable_busmaster(dev);
806
807 /* Map control/status registers. */
808 rid = RL_RID;
809 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
810
811 if (sc->rl_res == NULL) {
812 device_printf(dev, "couldn't map ports/memory\n");
813 error = ENXIO;
814 goto fail;
815 }
816
817 #ifdef notdef
818 /*
819 * Detect the Realtek 8139B. For some reason, this chip is very
820 * unstable when left to autoselect the media
821 * The best workaround is to set the device to the required
822 * media type or to set it to the 10 Meg speed.
823 */
824 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
825 device_printf(dev,
826 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
827 #endif
828
829 sc->rl_btag = rman_get_bustag(sc->rl_res);
830 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
831
832 /* Allocate interrupt */
833 rid = 0;
834 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
835 RF_SHAREABLE | RF_ACTIVE);
836
837 if (sc->rl_irq == NULL) {
838 device_printf(dev, "couldn't map interrupt\n");
839 error = ENXIO;
840 goto fail;
841 }
842
843 /*
844 * Reset the adapter. Only take the lock here as it's needed in
845 * order to call rl_reset().
846 */
847 RL_LOCK(sc);
848 rl_reset(sc);
849 RL_UNLOCK(sc);
850
851 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
852 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
853 if (rl_did != 0x8129)
854 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
855
856 /*
857 * Get station address from the EEPROM.
858 */
859 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
860 for (i = 0; i < 3; i++) {
861 eaddr[(i * 2) + 0] = as[i] & 0xff;
862 eaddr[(i * 2) + 1] = as[i] >> 8;
863 }
864
865 sc->rl_unit = unit;
866 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
867
868 /*
869 * Now read the exact device type from the EEPROM to find
870 * out if it's an 8129 or 8139.
871 */
872 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
873
874 t = rl_devs;
875 sc->rl_type = 0;
876 while(t->rl_name != NULL) {
877 if (rl_did == t->rl_did) {
878 sc->rl_type = t->rl_basetype;
879 break;
880 }
881 t++;
882 }
883
884 if (sc->rl_type == 0) {
885 device_printf(dev, "unknown device ID: %x\n", rl_did);
886 error = ENXIO;
887 goto fail;
888 }
889
890 /*
891 * Allocate the parent bus DMA tag appropriate for PCI.
892 */
893 #define RL_NSEG_NEW 32
894 error = bus_dma_tag_create(NULL, /* parent */
895 1, 0, /* alignment, boundary */
896 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
897 BUS_SPACE_MAXADDR, /* highaddr */
898 NULL, NULL, /* filter, filterarg */
899 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
900 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
901 BUS_DMA_ALLOCNOW, /* flags */
902 NULL, NULL, /* lockfunc, lockarg */
903 &sc->rl_parent_tag);
904 if (error)
905 goto fail;
906
907 /*
908 * Now allocate a tag for the DMA descriptor lists.
909 * All of our lists are allocated as a contiguous block
910 * of memory.
911 */
912 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
913 1, 0, /* alignment, boundary */
914 BUS_SPACE_MAXADDR, /* lowaddr */
915 BUS_SPACE_MAXADDR, /* highaddr */
916 NULL, NULL, /* filter, filterarg */
917 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
918 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
919 BUS_DMA_ALLOCNOW, /* flags */
920 NULL, NULL, /* lockfunc, lockarg */
921 &sc->rl_tag);
922 if (error)
923 goto fail;
924
925 /*
926 * Now allocate a chunk of DMA-able memory based on the
927 * tag we just created.
928 */
929 error = bus_dmamem_alloc(sc->rl_tag,
930 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
931 &sc->rl_cdata.rl_rx_dmamap);
932 if (error) {
933 device_printf(dev, "no memory for list buffers!\n");
934 bus_dma_tag_destroy(sc->rl_tag);
935 sc->rl_tag = NULL;
936 goto fail;
937 }
938
939 /* Leave a few bytes before the start of the RX ring buffer. */
940 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
941 sc->rl_cdata.rl_rx_buf += sizeof(uint64_t);
942
943 /* Do MII setup */
944 if (mii_phy_probe(dev, &sc->rl_miibus,
945 rl_ifmedia_upd, rl_ifmedia_sts)) {
946 device_printf(dev, "MII without any phy!\n");
947 error = ENXIO;
948 goto fail;
949 }
950
951 ifp = &sc->arpcom.ac_if;
952 ifp->if_softc = sc;
953 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
954 ifp->if_mtu = ETHERMTU;
955 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
956 ifp->if_ioctl = rl_ioctl;
957 ifp->if_start = rl_start;
958 ifp->if_watchdog = rl_watchdog;
959 ifp->if_init = rl_init;
960 ifp->if_baudrate = 10000000;
961 ifp->if_capabilities = IFCAP_VLAN_MTU;
962 #ifdef DEVICE_POLLING
963 ifp->if_capabilities |= IFCAP_POLLING;
964 #endif
965 ifp->if_capenable = ifp->if_capabilities;
966 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
967 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
968 IFQ_SET_READY(&ifp->if_snd);
969
970 callout_handle_init(&sc->rl_stat_ch);
971
972 /*
973 * Call MI attach routine.
974 */
975 ether_ifattach(ifp, eaddr);
976
977 /* Hook interrupt last to avoid having to lock softc */
978 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE,
979 rl_intr, sc, &sc->rl_intrhand);
980 if (error) {
981 if_printf(ifp, "couldn't set up irq\n");
982 ether_ifdetach(ifp);
983 }
984
985 fail:
986 if (error)
987 rl_detach(dev);
988
989 return (error);
990 }
991
992 /*
993 * Shutdown hardware and free up resources. This can be called any
994 * time after the mutex has been initialized. It is called in both
995 * the error case in attach and the normal detach case so it needs
996 * to be careful about only freeing resources that have actually been
997 * allocated.
998 */
999 static int
1000 rl_detach(device_t dev)
1001 {
1002 struct rl_softc *sc;
1003 struct ifnet *ifp;
1004 int attached;
1005
1006 sc = device_get_softc(dev);
1007 ifp = &sc->arpcom.ac_if;
1008
1009 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
1010 attached = device_is_attached(dev);
1011 /* These should only be active if attach succeeded */
1012 if (attached)
1013 ether_ifdetach(ifp);
1014 RL_LOCK(sc);
1015 #if 0
1016 sc->suspended = 1;
1017 #endif
1018 if (attached)
1019 rl_stop(sc);
1020 if (sc->rl_miibus)
1021 device_delete_child(dev, sc->rl_miibus);
1022 bus_generic_detach(dev);
1023
1024 if (sc->rl_intrhand)
1025 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1026 if (sc->rl_irq)
1027 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1028 if (sc->rl_res)
1029 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1030
1031 if (sc->rl_tag) {
1032 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1033 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1034 sc->rl_cdata.rl_rx_dmamap);
1035 bus_dma_tag_destroy(sc->rl_tag);
1036 }
1037 if (sc->rl_parent_tag)
1038 bus_dma_tag_destroy(sc->rl_parent_tag);
1039
1040 RL_UNLOCK(sc);
1041 mtx_destroy(&sc->rl_mtx);
1042
1043 return (0);
1044 }
1045
1046 /*
1047 * Initialize the transmit descriptors.
1048 */
1049 static int
1050 rl_list_tx_init(struct rl_softc *sc)
1051 {
1052 struct rl_chain_data *cd;
1053 int i;
1054
1055 RL_LOCK_ASSERT(sc);
1056
1057 cd = &sc->rl_cdata;
1058 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1059 cd->rl_tx_chain[i] = NULL;
1060 CSR_WRITE_4(sc,
1061 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1062 }
1063
1064 sc->rl_cdata.cur_tx = 0;
1065 sc->rl_cdata.last_tx = 0;
1066
1067 return (0);
1068 }
1069
1070 /*
1071 * A frame has been uploaded: pass the resulting mbuf chain up to
1072 * the higher level protocols.
1073 *
1074 * You know there's something wrong with a PCI bus-master chip design
1075 * when you have to use m_devget().
1076 *
1077 * The receive operation is badly documented in the datasheet, so I'll
1078 * attempt to document it here. The driver provides a buffer area and
1079 * places its base address in the RX buffer start address register.
1080 * The chip then begins copying frames into the RX buffer. Each frame
1081 * is preceded by a 32-bit RX status word which specifies the length
1082 * of the frame and certain other status bits. Each frame (starting with
1083 * the status word) is also 32-bit aligned. The frame length is in the
1084 * first 16 bits of the status word; the lower 15 bits correspond with
1085 * the 'rx status register' mentioned in the datasheet.
1086 *
1087 * Note: to make the Alpha happy, the frame payload needs to be aligned
1088 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1089 * as the offset argument to m_devget().
1090 */
1091 static void
1092 rl_rxeof(struct rl_softc *sc)
1093 {
1094 struct mbuf *m;
1095 struct ifnet *ifp = &sc->arpcom.ac_if;
1096 uint8_t *rxbufpos;
1097 int total_len = 0;
1098 int wrap = 0;
1099 uint32_t rxstat;
1100 uint16_t cur_rx;
1101 uint16_t limit;
1102 uint16_t max_bytes, rx_bytes = 0;
1103
1104 RL_LOCK_ASSERT(sc);
1105
1106 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1107 BUS_DMASYNC_POSTREAD);
1108
1109 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1110
1111 /* Do not try to read past this point. */
1112 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1113
1114 if (limit < cur_rx)
1115 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1116 else
1117 max_bytes = limit - cur_rx;
1118
1119 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1120 #ifdef DEVICE_POLLING
1121 if (ifp->if_flags & IFF_POLLING) {
1122 if (sc->rxcycles <= 0)
1123 break;
1124 sc->rxcycles--;
1125 }
1126 #endif /* DEVICE_POLLING */
1127 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1128 rxstat = le32toh(*(uint32_t *)rxbufpos);
1129
1130 /*
1131 * Here's a totally undocumented fact for you. When the
1132 * RealTek chip is in the process of copying a packet into
1133 * RAM for you, the length will be 0xfff0. If you spot a
1134 * packet header with this value, you need to stop. The
1135 * datasheet makes absolutely no mention of this and
1136 * RealTek should be shot for this.
1137 */
1138 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1139 break;
1140
1141 if (!(rxstat & RL_RXSTAT_RXOK)) {
1142 ifp->if_ierrors++;
1143 rl_init_locked(sc);
1144 return;
1145 }
1146
1147 /* No errors; receive the packet. */
1148 total_len = rxstat >> 16;
1149 rx_bytes += total_len + 4;
1150
1151 /*
1152 * XXX The RealTek chip includes the CRC with every
1153 * received frame, and there's no way to turn this
1154 * behavior off (at least, I can't find anything in
1155 * the manual that explains how to do it) so we have
1156 * to trim off the CRC manually.
1157 */
1158 total_len -= ETHER_CRC_LEN;
1159
1160 /*
1161 * Avoid trying to read more bytes than we know
1162 * the chip has prepared for us.
1163 */
1164 if (rx_bytes > max_bytes)
1165 break;
1166
1167 rxbufpos = sc->rl_cdata.rl_rx_buf +
1168 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1169 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1170 rxbufpos = sc->rl_cdata.rl_rx_buf;
1171
1172 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1173 if (total_len > wrap) {
1174 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1175 NULL);
1176 if (m == NULL) {
1177 ifp->if_ierrors++;
1178 } else {
1179 m_copyback(m, wrap, total_len - wrap,
1180 sc->rl_cdata.rl_rx_buf);
1181 }
1182 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1183 } else {
1184 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1185 NULL);
1186 if (m == NULL)
1187 ifp->if_ierrors++;
1188 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1189 }
1190
1191 /* Round up to 32-bit boundary. */
1192 cur_rx = (cur_rx + 3) & ~3;
1193 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1194
1195 if (m == NULL)
1196 continue;
1197
1198 ifp->if_ipackets++;
1199 RL_UNLOCK(sc);
1200 (*ifp->if_input)(ifp, m);
1201 RL_LOCK(sc);
1202 }
1203 }
1204
1205 /*
1206 * A frame was downloaded to the chip. It's safe for us to clean up
1207 * the list buffers.
1208 */
1209 static void
1210 rl_txeof(struct rl_softc *sc)
1211 {
1212 struct ifnet *ifp = &sc->arpcom.ac_if;
1213 uint32_t txstat;
1214
1215 RL_LOCK_ASSERT(sc);
1216
1217 /*
1218 * Go through our tx list and free mbufs for those
1219 * frames that have been uploaded.
1220 */
1221 do {
1222 if (RL_LAST_TXMBUF(sc) == NULL)
1223 break;
1224 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1225 if (!(txstat & (RL_TXSTAT_TX_OK|
1226 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1227 break;
1228
1229 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1230
1231 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1232 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1233 m_freem(RL_LAST_TXMBUF(sc));
1234 RL_LAST_TXMBUF(sc) = NULL;
1235 /*
1236 * If there was a transmit underrun, bump the TX threshold.
1237 * Make sure not to overflow the 63 * 32byte we can address
1238 * with the 6 available bit.
1239 */
1240 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1241 (sc->rl_txthresh < 2016))
1242 sc->rl_txthresh += 32;
1243 if (txstat & RL_TXSTAT_TX_OK)
1244 ifp->if_opackets++;
1245 else {
1246 int oldthresh;
1247 ifp->if_oerrors++;
1248 if ((txstat & RL_TXSTAT_TXABRT) ||
1249 (txstat & RL_TXSTAT_OUTOFWIN))
1250 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1251 oldthresh = sc->rl_txthresh;
1252 /* error recovery */
1253 rl_reset(sc);
1254 rl_init_locked(sc);
1255 /* restore original threshold */
1256 sc->rl_txthresh = oldthresh;
1257 return;
1258 }
1259 RL_INC(sc->rl_cdata.last_tx);
1260 ifp->if_flags &= ~IFF_OACTIVE;
1261 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1262
1263 if (RL_LAST_TXMBUF(sc) == NULL)
1264 ifp->if_timer = 0;
1265 else if (ifp->if_timer == 0)
1266 ifp->if_timer = 5;
1267 }
1268
1269 static void
1270 rl_tick(void *xsc)
1271 {
1272 struct rl_softc *sc = xsc;
1273 struct mii_data *mii;
1274
1275 RL_LOCK(sc);
1276 mii = device_get_softc(sc->rl_miibus);
1277 mii_tick(mii);
1278
1279 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1280 RL_UNLOCK(sc);
1281 }
1282
1283 #ifdef DEVICE_POLLING
1284 static void
1285 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1286 {
1287 struct rl_softc *sc = ifp->if_softc;
1288
1289 RL_LOCK(sc);
1290 rl_poll_locked(ifp, cmd, count);
1291 RL_UNLOCK(sc);
1292 }
1293
1294 static void
1295 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1296 {
1297 struct rl_softc *sc = ifp->if_softc;
1298
1299 RL_LOCK_ASSERT(sc);
1300
1301 if (!(ifp->if_capenable & IFCAP_POLLING)) {
1302 ether_poll_deregister(ifp);
1303 cmd = POLL_DEREGISTER;
1304 }
1305
1306 if (cmd == POLL_DEREGISTER) {
1307 /* Final call; enable interrupts. */
1308 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1309 return;
1310 }
1311
1312 sc->rxcycles = count;
1313 rl_rxeof(sc);
1314 rl_txeof(sc);
1315
1316 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1317 rl_start_locked(ifp);
1318
1319 if (cmd == POLL_AND_CHECK_STATUS) {
1320 uint16_t status;
1321
1322 /* We should also check the status register. */
1323 status = CSR_READ_2(sc, RL_ISR);
1324 if (status == 0xffff)
1325 return;
1326 if (status != 0)
1327 CSR_WRITE_2(sc, RL_ISR, status);
1328
1329 /* XXX We should check behaviour on receiver stalls. */
1330
1331 if (status & RL_ISR_SYSTEM_ERR) {
1332 rl_reset(sc);
1333 rl_init_locked(sc);
1334 }
1335 }
1336 }
1337 #endif /* DEVICE_POLLING */
1338
1339 static void
1340 rl_intr(void *arg)
1341 {
1342 struct rl_softc *sc = arg;
1343 struct ifnet *ifp = &sc->arpcom.ac_if;
1344 uint16_t status;
1345
1346 RL_LOCK(sc);
1347
1348 if (sc->suspended)
1349 goto done_locked;
1350
1351 #ifdef DEVICE_POLLING
1352 if (ifp->if_flags & IFF_POLLING)
1353 goto done_locked;
1354
1355 if ((ifp->if_capenable & IFCAP_POLLING) &&
1356 ether_poll_register(rl_poll, ifp)) {
1357 /* Disable interrupts. */
1358 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1359 rl_poll_locked(ifp, 0, 1);
1360 goto done_locked;
1361 }
1362 #endif /* DEVICE_POLLING */
1363
1364 for (;;) {
1365 status = CSR_READ_2(sc, RL_ISR);
1366 /* If the card has gone away, the read returns 0xffff. */
1367 if (status == 0xffff)
1368 break;
1369 if (status != 0)
1370 CSR_WRITE_2(sc, RL_ISR, status);
1371 if ((status & RL_INTRS) == 0)
1372 break;
1373 if (status & RL_ISR_RX_OK)
1374 rl_rxeof(sc);
1375 if (status & RL_ISR_RX_ERR)
1376 rl_rxeof(sc);
1377 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1378 rl_txeof(sc);
1379 if (status & RL_ISR_SYSTEM_ERR) {
1380 rl_reset(sc);
1381 rl_init_locked(sc);
1382 }
1383 }
1384
1385 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1386 rl_start_locked(ifp);
1387
1388 done_locked:
1389 RL_UNLOCK(sc);
1390 }
1391
1392 /*
1393 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1394 * pointers to the fragment pointers.
1395 */
1396 static int
1397 rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1398 {
1399 struct mbuf *m_new = NULL;
1400
1401 RL_LOCK_ASSERT(sc);
1402
1403 /*
1404 * The RealTek is brain damaged and wants longword-aligned
1405 * TX buffers, plus we can only have one fragment buffer
1406 * per packet. We have to copy pretty much all the time.
1407 */
1408 m_new = m_defrag(m_head, M_DONTWAIT);
1409
1410 if (m_new == NULL) {
1411 m_freem(m_head);
1412 return (1);
1413 }
1414 m_head = m_new;
1415
1416 /* Pad frames to at least 60 bytes. */
1417 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1418 /*
1419 * Make security concious people happy: zero out the
1420 * bytes in the pad area, since we don't know what
1421 * this mbuf cluster buffer's previous user might
1422 * have left in it.
1423 */
1424 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1425 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1426 m_head->m_pkthdr.len +=
1427 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1428 m_head->m_len = m_head->m_pkthdr.len;
1429 }
1430
1431 RL_CUR_TXMBUF(sc) = m_head;
1432
1433 return (0);
1434 }
1435
1436 /*
1437 * Main transmit routine.
1438 */
1439 static void
1440 rl_start(struct ifnet *ifp)
1441 {
1442 struct rl_softc *sc = ifp->if_softc;
1443
1444 RL_LOCK(sc);
1445 rl_start_locked(ifp);
1446 RL_UNLOCK(sc);
1447 }
1448
1449 static void
1450 rl_start_locked(struct ifnet *ifp)
1451 {
1452 struct rl_softc *sc = ifp->if_softc;
1453 struct mbuf *m_head = NULL;
1454
1455 RL_LOCK_ASSERT(sc);
1456
1457 while (RL_CUR_TXMBUF(sc) == NULL) {
1458
1459 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1460
1461 if (m_head == NULL)
1462 break;
1463
1464 if (rl_encap(sc, m_head))
1465 break;
1466
1467 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1468 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1469
1470 /* Transmit the frame. */
1471 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1472 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1473 mtod(RL_CUR_TXMBUF(sc), void *),
1474 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
1475 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1476 BUS_DMASYNC_PREREAD);
1477 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1478 RL_TXTHRESH(sc->rl_txthresh) |
1479 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1480
1481 RL_INC(sc->rl_cdata.cur_tx);
1482
1483 /* Set a timeout in case the chip goes out to lunch. */
1484 ifp->if_timer = 5;
1485 }
1486
1487 /*
1488 * We broke out of the loop because all our TX slots are
1489 * full. Mark the NIC as busy until it drains some of the
1490 * packets from the queue.
1491 */
1492 if (RL_CUR_TXMBUF(sc) != NULL)
1493 ifp->if_flags |= IFF_OACTIVE;
1494 }
1495
1496 static void
1497 rl_init(void *xsc)
1498 {
1499 struct rl_softc *sc = xsc;
1500
1501 RL_LOCK(sc);
1502 rl_init_locked(sc);
1503 RL_UNLOCK(sc);
1504 }
1505
1506 static void
1507 rl_init_locked(struct rl_softc *sc)
1508 {
1509 struct ifnet *ifp = &sc->arpcom.ac_if;
1510 struct mii_data *mii;
1511 uint32_t rxcfg = 0;
1512
1513 RL_LOCK_ASSERT(sc);
1514
1515 mii = device_get_softc(sc->rl_miibus);
1516
1517 /*
1518 * Cancel pending I/O and free all RX/TX buffers.
1519 */
1520 rl_stop(sc);
1521
1522 /*
1523 * Init our MAC address. Even though the chipset
1524 * documentation doesn't mention it, we need to enter "Config
1525 * register write enable" mode to modify the ID registers.
1526 */
1527 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1528 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1529 *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1530 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1531 *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
1532 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1533
1534 /* Init the RX buffer pointer register. */
1535 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1536 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1537 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1538 BUS_DMASYNC_PREWRITE);
1539
1540 /* Init TX descriptors. */
1541 rl_list_tx_init(sc);
1542
1543 /*
1544 * Enable transmit and receive.
1545 */
1546 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1547
1548 /*
1549 * Set the initial TX and RX configuration.
1550 */
1551 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1552 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1553
1554 /* Set the individual bit to receive frames for this host only. */
1555 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1556 rxcfg |= RL_RXCFG_RX_INDIV;
1557
1558 /* If we want promiscuous mode, set the allframes bit. */
1559 if (ifp->if_flags & IFF_PROMISC) {
1560 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1561 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1562 } else {
1563 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1564 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1565 }
1566
1567 /* Set capture broadcast bit to capture broadcast frames. */
1568 if (ifp->if_flags & IFF_BROADCAST) {
1569 rxcfg |= RL_RXCFG_RX_BROAD;
1570 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1571 } else {
1572 rxcfg &= ~RL_RXCFG_RX_BROAD;
1573 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1574 }
1575
1576 /* Program the multicast filter, if necessary. */
1577 rl_setmulti(sc);
1578
1579 #ifdef DEVICE_POLLING
1580 /* Disable interrupts if we are polling. */
1581 if (ifp->if_flags & IFF_POLLING)
1582 CSR_WRITE_2(sc, RL_IMR, 0);
1583 else
1584 #endif /* DEVICE_POLLING */
1585 /* Enable interrupts. */
1586 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1587
1588 /* Set initial TX threshold */
1589 sc->rl_txthresh = RL_TX_THRESH_INIT;
1590
1591 /* Start RX/TX process. */
1592 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1593
1594 /* Enable receiver and transmitter. */
1595 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1596
1597 mii_mediachg(mii);
1598
1599 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1600
1601 ifp->if_flags |= IFF_RUNNING;
1602 ifp->if_flags &= ~IFF_OACTIVE;
1603
1604 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1605 }
1606
1607 /*
1608 * Set media options.
1609 */
1610 static int
1611 rl_ifmedia_upd(struct ifnet *ifp)
1612 {
1613 struct rl_softc *sc = ifp->if_softc;
1614 struct mii_data *mii;
1615
1616 mii = device_get_softc(sc->rl_miibus);
1617
1618 mii_mediachg(mii);
1619
1620 return (0);
1621 }
1622
1623 /*
1624 * Report current media status.
1625 */
1626 static void
1627 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1628 {
1629 struct rl_softc *sc = ifp->if_softc;
1630 struct mii_data *mii;
1631
1632 mii = device_get_softc(sc->rl_miibus);
1633
1634 mii_pollstat(mii);
1635 ifmr->ifm_active = mii->mii_media_active;
1636 ifmr->ifm_status = mii->mii_media_status;
1637 }
1638
1639 static int
1640 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1641 {
1642 struct ifreq *ifr = (struct ifreq *)data;
1643 struct mii_data *mii;
1644 struct rl_softc *sc = ifp->if_softc;
1645 int error = 0;
1646
1647 switch (command) {
1648 case SIOCSIFFLAGS:
1649 RL_LOCK(sc);
1650 if (ifp->if_flags & IFF_UP) {
1651 rl_init_locked(sc);
1652 } else {
1653 if (ifp->if_flags & IFF_RUNNING)
1654 rl_stop(sc);
1655 }
1656 RL_UNLOCK(sc);
1657 error = 0;
1658 break;
1659 case SIOCADDMULTI:
1660 case SIOCDELMULTI:
1661 RL_LOCK(sc);
1662 rl_setmulti(sc);
1663 RL_UNLOCK(sc);
1664 error = 0;
1665 break;
1666 case SIOCGIFMEDIA:
1667 case SIOCSIFMEDIA:
1668 mii = device_get_softc(sc->rl_miibus);
1669 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1670 break;
1671 case SIOCSIFCAP:
1672 ifp->if_capenable &= ~IFCAP_POLLING;
1673 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING;
1674 break;
1675 default:
1676 error = ether_ioctl(ifp, command, data);
1677 break;
1678 }
1679
1680 return (error);
1681 }
1682
1683 static void
1684 rl_watchdog(struct ifnet *ifp)
1685 {
1686 struct rl_softc *sc = ifp->if_softc;
1687
1688 RL_LOCK(sc);
1689
1690 if_printf(ifp, "watchdog timeout\n");
1691 ifp->if_oerrors++;
1692
1693 rl_txeof(sc);
1694 rl_rxeof(sc);
1695 rl_init_locked(sc);
1696
1697 RL_UNLOCK(sc);
1698 }
1699
1700 /*
1701 * Stop the adapter and free any mbufs allocated to the
1702 * RX and TX lists.
1703 */
1704 static void
1705 rl_stop(struct rl_softc *sc)
1706 {
1707 register int i;
1708 struct ifnet *ifp = &sc->arpcom.ac_if;
1709
1710 RL_LOCK_ASSERT(sc);
1711
1712 ifp->if_timer = 0;
1713 untimeout(rl_tick, sc, sc->rl_stat_ch);
1714 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1715 #ifdef DEVICE_POLLING
1716 ether_poll_deregister(ifp);
1717 #endif /* DEVICE_POLLING */
1718
1719 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1720 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1721 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1722
1723 /*
1724 * Free the TX list buffers.
1725 */
1726 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1727 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1728 bus_dmamap_unload(sc->rl_tag,
1729 sc->rl_cdata.rl_tx_dmamap[i]);
1730 bus_dmamap_destroy(sc->rl_tag,
1731 sc->rl_cdata.rl_tx_dmamap[i]);
1732 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1733 sc->rl_cdata.rl_tx_chain[i] = NULL;
1734 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1735 0x0000000);
1736 }
1737 }
1738 }
1739
1740 /*
1741 * Device suspend routine. Stop the interface and save some PCI
1742 * settings in case the BIOS doesn't restore them properly on
1743 * resume.
1744 */
1745 static int
1746 rl_suspend(device_t dev)
1747 {
1748 struct rl_softc *sc;
1749
1750 sc = device_get_softc(dev);
1751
1752 RL_LOCK(sc);
1753 rl_stop(sc);
1754 sc->suspended = 1;
1755 RL_UNLOCK(sc);
1756
1757 return (0);
1758 }
1759
1760 /*
1761 * Device resume routine. Restore some PCI settings in case the BIOS
1762 * doesn't, re-enable busmastering, and restart the interface if
1763 * appropriate.
1764 */
1765 static int
1766 rl_resume(device_t dev)
1767 {
1768 struct rl_softc *sc;
1769 struct ifnet *ifp;
1770
1771 sc = device_get_softc(dev);
1772 ifp = &sc->arpcom.ac_if;
1773
1774 RL_LOCK(sc);
1775
1776 /* reinitialize interface if necessary */
1777 if (ifp->if_flags & IFF_UP)
1778 rl_init_locked(sc);
1779
1780 sc->suspended = 0;
1781
1782 RL_UNLOCK(sc);
1783
1784 return (0);
1785 }
1786
1787 /*
1788 * Stop all chip I/O so that the kernel's probe routines don't
1789 * get confused by errant DMAs when rebooting.
1790 */
1791 static void
1792 rl_shutdown(device_t dev)
1793 {
1794 struct rl_softc *sc;
1795
1796 sc = device_get_softc(dev);
1797
1798 RL_LOCK(sc);
1799 rl_stop(sc);
1800 RL_UNLOCK(sc);
1801 }
Cache object: 22e48ec2287dfac7951c8b2ef3d5151e
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