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sys/pci/if_rl.c
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1 /*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: src/sys/pci/if_rl.c,v 1.145.2.4 2006/01/29 15:39:08 emaste Exp $"); 35 36 /* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 /* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86 #include <sys/param.h> 87 #include <sys/endian.h> 88 #include <sys/systm.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/module.h> 94 #include <sys/socket.h> 95 96 #include <net/if.h> 97 #include <net/if_arp.h> 98 #include <net/ethernet.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 102 #include <net/bpf.h> 103 104 #include <machine/bus_pio.h> 105 #include <machine/bus_memio.h> 106 #include <machine/bus.h> 107 #include <machine/resource.h> 108 #include <sys/bus.h> 109 #include <sys/rman.h> 110 111 #include <dev/mii/mii.h> 112 #include <dev/mii/miivar.h> 113 114 #include <dev/pci/pcireg.h> 115 #include <dev/pci/pcivar.h> 116 117 MODULE_DEPEND(rl, pci, 1, 1, 1); 118 MODULE_DEPEND(rl, ether, 1, 1, 1); 119 MODULE_DEPEND(rl, miibus, 1, 1, 1); 120 121 /* "controller miibus0" required. See GENERIC if you get errors here. */ 122 #include "miibus_if.h" 123 124 /* 125 * Default to using PIO access for this driver. On SMP systems, 126 * there appear to be problems with memory mapped mode: it looks like 127 * doing too many memory mapped access back to back in rapid succession 128 * can hang the bus. I'm inclined to blame this on crummy design/construction 129 * on the part of RealTek. Memory mapped mode does appear to work on 130 * uniprocessor systems though. 131 */ 132 #define RL_USEIOSPACE 133 134 #include <pci/if_rlreg.h> 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 static struct rl_type rl_devs[] = { 140 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 141 "RealTek 8129 10/100BaseTX" }, 142 { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 143 "RealTek 8139 10/100BaseTX" }, 144 { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 145 "RealTek 8139 10/100BaseTX CardBus" }, 146 { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 147 "RealTek 8100 10/100BaseTX" }, 148 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 149 "Accton MPX 5030/5038 10/100BaseTX" }, 150 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 151 "Delta Electronics 8139 10/100BaseTX" }, 152 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 153 "Addtron Technolgy 8139 10/100BaseTX" }, 154 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 155 "D-Link DFE-530TX+ 10/100BaseTX" }, 156 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 157 "D-Link DFE-690TXD 10/100BaseTX" }, 158 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 159 "Nortel Networks 10/100BaseTX" }, 160 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 161 "Corega FEther CB-TXD" }, 162 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 163 "Corega FEtherII CB-TXD" }, 164 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 165 "Peppercon AG ROL-F" }, 166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 167 "Planex FNW-3800-TX" }, 168 { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 169 "Compaq HNE-300" }, 170 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 171 "LevelOne FPC-0106TX" }, 172 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 173 "Edimax EP-4103DL CardBus" }, 174 { 0, 0, 0, NULL } 175 }; 176 177 static int rl_attach(device_t); 178 static int rl_detach(device_t); 179 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int); 180 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int); 181 static void rl_eeprom_putbyte(struct rl_softc *, int); 182 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 183 static int rl_encap(struct rl_softc *, struct mbuf * ); 184 static int rl_list_tx_init(struct rl_softc *); 185 static int rl_ifmedia_upd(struct ifnet *); 186 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 187 static int rl_ioctl(struct ifnet *, u_long, caddr_t); 188 static void rl_intr(void *); 189 static void rl_init(void *); 190 static void rl_init_locked(struct rl_softc *sc); 191 static void rl_mii_send(struct rl_softc *, uint32_t, int); 192 static void rl_mii_sync(struct rl_softc *); 193 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 194 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 195 static int rl_miibus_readreg(device_t, int, int); 196 static void rl_miibus_statchg(device_t); 197 static int rl_miibus_writereg(device_t, int, int, int); 198 #ifdef DEVICE_POLLING 199 static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, 200 int count); 201 static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, 202 int count); 203 #endif 204 static int rl_probe(device_t); 205 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int); 206 static void rl_reset(struct rl_softc *); 207 static int rl_resume(device_t); 208 static void rl_rxeof(struct rl_softc *); 209 static void rl_setmulti(struct rl_softc *); 210 static void rl_shutdown(device_t); 211 static void rl_start(struct ifnet *); 212 static void rl_start_locked(struct ifnet *); 213 static void rl_stop(struct rl_softc *); 214 static int rl_suspend(device_t); 215 static void rl_tick(void *); 216 static void rl_txeof(struct rl_softc *); 217 static void rl_watchdog(struct ifnet *); 218 219 #ifdef RL_USEIOSPACE 220 #define RL_RES SYS_RES_IOPORT 221 #define RL_RID RL_PCI_LOIO 222 #else 223 #define RL_RES SYS_RES_MEMORY 224 #define RL_RID RL_PCI_LOMEM 225 #endif 226 227 static device_method_t rl_methods[] = { 228 /* Device interface */ 229 DEVMETHOD(device_probe, rl_probe), 230 DEVMETHOD(device_attach, rl_attach), 231 DEVMETHOD(device_detach, rl_detach), 232 DEVMETHOD(device_suspend, rl_suspend), 233 DEVMETHOD(device_resume, rl_resume), 234 DEVMETHOD(device_shutdown, rl_shutdown), 235 236 /* bus interface */ 237 DEVMETHOD(bus_print_child, bus_generic_print_child), 238 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 239 240 /* MII interface */ 241 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 242 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 243 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 244 245 { 0, 0 } 246 }; 247 248 static driver_t rl_driver = { 249 "rl", 250 rl_methods, 251 sizeof(struct rl_softc) 252 }; 253 254 static devclass_t rl_devclass; 255 256 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 257 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 258 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 259 260 #define EE_SET(x) \ 261 CSR_WRITE_1(sc, RL_EECMD, \ 262 CSR_READ_1(sc, RL_EECMD) | x) 263 264 #define EE_CLR(x) \ 265 CSR_WRITE_1(sc, RL_EECMD, \ 266 CSR_READ_1(sc, RL_EECMD) & ~x) 267 268 static void 269 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 270 { 271 struct rl_softc *sc = arg; 272 273 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 274 } 275 276 static void 277 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 278 { 279 struct rl_softc *sc = arg; 280 281 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 282 } 283 284 /* 285 * Send a read command and address to the EEPROM, check for ACK. 286 */ 287 static void 288 rl_eeprom_putbyte(struct rl_softc *sc, int addr) 289 { 290 register int d, i; 291 292 d = addr | sc->rl_eecmd_read; 293 294 /* 295 * Feed in each bit and strobe the clock. 296 */ 297 for (i = 0x400; i; i >>= 1) { 298 if (d & i) { 299 EE_SET(RL_EE_DATAIN); 300 } else { 301 EE_CLR(RL_EE_DATAIN); 302 } 303 DELAY(100); 304 EE_SET(RL_EE_CLK); 305 DELAY(150); 306 EE_CLR(RL_EE_CLK); 307 DELAY(100); 308 } 309 } 310 311 /* 312 * Read a word of data stored in the EEPROM at address 'addr.' 313 */ 314 static void 315 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 316 { 317 register int i; 318 uint16_t word = 0; 319 320 /* Enter EEPROM access mode. */ 321 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 322 323 /* 324 * Send address of word we want to read. 325 */ 326 rl_eeprom_putbyte(sc, addr); 327 328 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 329 330 /* 331 * Start reading bits from EEPROM. 332 */ 333 for (i = 0x8000; i; i >>= 1) { 334 EE_SET(RL_EE_CLK); 335 DELAY(100); 336 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 337 word |= i; 338 EE_CLR(RL_EE_CLK); 339 DELAY(100); 340 } 341 342 /* Turn off EEPROM access mode. */ 343 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 344 345 *dest = word; 346 } 347 348 /* 349 * Read a sequence of words from the EEPROM. 350 */ 351 static void 352 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap) 353 { 354 int i; 355 uint16_t word = 0, *ptr; 356 357 for (i = 0; i < cnt; i++) { 358 rl_eeprom_getword(sc, off + i, &word); 359 ptr = (uint16_t *)(dest + (i * 2)); 360 if (swap) 361 *ptr = ntohs(word); 362 else 363 *ptr = word; 364 } 365 } 366 367 /* 368 * MII access routines are provided for the 8129, which 369 * doesn't have a built-in PHY. For the 8139, we fake things 370 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 371 * direct access PHY registers. 372 */ 373 #define MII_SET(x) \ 374 CSR_WRITE_1(sc, RL_MII, \ 375 CSR_READ_1(sc, RL_MII) | (x)) 376 377 #define MII_CLR(x) \ 378 CSR_WRITE_1(sc, RL_MII, \ 379 CSR_READ_1(sc, RL_MII) & ~(x)) 380 381 /* 382 * Sync the PHYs by setting data bit and strobing the clock 32 times. 383 */ 384 static void 385 rl_mii_sync(struct rl_softc *sc) 386 { 387 register int i; 388 389 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 390 391 for (i = 0; i < 32; i++) { 392 MII_SET(RL_MII_CLK); 393 DELAY(1); 394 MII_CLR(RL_MII_CLK); 395 DELAY(1); 396 } 397 } 398 399 /* 400 * Clock a series of bits through the MII. 401 */ 402 static void 403 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt) 404 { 405 int i; 406 407 MII_CLR(RL_MII_CLK); 408 409 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 410 if (bits & i) { 411 MII_SET(RL_MII_DATAOUT); 412 } else { 413 MII_CLR(RL_MII_DATAOUT); 414 } 415 DELAY(1); 416 MII_CLR(RL_MII_CLK); 417 DELAY(1); 418 MII_SET(RL_MII_CLK); 419 } 420 } 421 422 /* 423 * Read an PHY register through the MII. 424 */ 425 static int 426 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 427 { 428 int i, ack; 429 430 RL_LOCK(sc); 431 432 /* Set up frame for RX. */ 433 frame->mii_stdelim = RL_MII_STARTDELIM; 434 frame->mii_opcode = RL_MII_READOP; 435 frame->mii_turnaround = 0; 436 frame->mii_data = 0; 437 438 CSR_WRITE_2(sc, RL_MII, 0); 439 440 /* Turn on data xmit. */ 441 MII_SET(RL_MII_DIR); 442 443 rl_mii_sync(sc); 444 445 /* Send command/address info. */ 446 rl_mii_send(sc, frame->mii_stdelim, 2); 447 rl_mii_send(sc, frame->mii_opcode, 2); 448 rl_mii_send(sc, frame->mii_phyaddr, 5); 449 rl_mii_send(sc, frame->mii_regaddr, 5); 450 451 /* Idle bit */ 452 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 453 DELAY(1); 454 MII_SET(RL_MII_CLK); 455 DELAY(1); 456 457 /* Turn off xmit. */ 458 MII_CLR(RL_MII_DIR); 459 460 /* Check for ack */ 461 MII_CLR(RL_MII_CLK); 462 DELAY(1); 463 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 464 MII_SET(RL_MII_CLK); 465 DELAY(1); 466 467 /* 468 * Now try reading data bits. If the ack failed, we still 469 * need to clock through 16 cycles to keep the PHY(s) in sync. 470 */ 471 if (ack) { 472 for(i = 0; i < 16; i++) { 473 MII_CLR(RL_MII_CLK); 474 DELAY(1); 475 MII_SET(RL_MII_CLK); 476 DELAY(1); 477 } 478 goto fail; 479 } 480 481 for (i = 0x8000; i; i >>= 1) { 482 MII_CLR(RL_MII_CLK); 483 DELAY(1); 484 if (!ack) { 485 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 486 frame->mii_data |= i; 487 DELAY(1); 488 } 489 MII_SET(RL_MII_CLK); 490 DELAY(1); 491 } 492 493 fail: 494 MII_CLR(RL_MII_CLK); 495 DELAY(1); 496 MII_SET(RL_MII_CLK); 497 DELAY(1); 498 499 RL_UNLOCK(sc); 500 501 return (ack ? 1 : 0); 502 } 503 504 /* 505 * Write to a PHY register through the MII. 506 */ 507 static int 508 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 509 { 510 511 RL_LOCK(sc); 512 513 /* Set up frame for TX. */ 514 frame->mii_stdelim = RL_MII_STARTDELIM; 515 frame->mii_opcode = RL_MII_WRITEOP; 516 frame->mii_turnaround = RL_MII_TURNAROUND; 517 518 /* Turn on data output. */ 519 MII_SET(RL_MII_DIR); 520 521 rl_mii_sync(sc); 522 523 rl_mii_send(sc, frame->mii_stdelim, 2); 524 rl_mii_send(sc, frame->mii_opcode, 2); 525 rl_mii_send(sc, frame->mii_phyaddr, 5); 526 rl_mii_send(sc, frame->mii_regaddr, 5); 527 rl_mii_send(sc, frame->mii_turnaround, 2); 528 rl_mii_send(sc, frame->mii_data, 16); 529 530 /* Idle bit. */ 531 MII_SET(RL_MII_CLK); 532 DELAY(1); 533 MII_CLR(RL_MII_CLK); 534 DELAY(1); 535 536 /* Turn off xmit. */ 537 MII_CLR(RL_MII_DIR); 538 539 RL_UNLOCK(sc); 540 541 return (0); 542 } 543 544 static int 545 rl_miibus_readreg(device_t dev, int phy, int reg) 546 { 547 struct rl_softc *sc; 548 struct rl_mii_frame frame; 549 uint16_t rval = 0; 550 uint16_t rl8139_reg = 0; 551 552 sc = device_get_softc(dev); 553 554 if (sc->rl_type == RL_8139) { 555 /* Pretend the internal PHY is only at address 0 */ 556 if (phy) { 557 return (0); 558 } 559 switch (reg) { 560 case MII_BMCR: 561 rl8139_reg = RL_BMCR; 562 break; 563 case MII_BMSR: 564 rl8139_reg = RL_BMSR; 565 break; 566 case MII_ANAR: 567 rl8139_reg = RL_ANAR; 568 break; 569 case MII_ANER: 570 rl8139_reg = RL_ANER; 571 break; 572 case MII_ANLPAR: 573 rl8139_reg = RL_LPAR; 574 break; 575 case MII_PHYIDR1: 576 case MII_PHYIDR2: 577 return (0); 578 /* 579 * Allow the rlphy driver to read the media status 580 * register. If we have a link partner which does not 581 * support NWAY, this is the register which will tell 582 * us the results of parallel detection. 583 */ 584 case RL_MEDIASTAT: 585 rval = CSR_READ_1(sc, RL_MEDIASTAT); 586 return (rval); 587 default: 588 if_printf(&sc->arpcom.ac_if, "bad phy register\n"); 589 return (0); 590 } 591 rval = CSR_READ_2(sc, rl8139_reg); 592 return (rval); 593 } 594 595 bzero((char *)&frame, sizeof(frame)); 596 frame.mii_phyaddr = phy; 597 frame.mii_regaddr = reg; 598 rl_mii_readreg(sc, &frame); 599 600 return (frame.mii_data); 601 } 602 603 static int 604 rl_miibus_writereg(device_t dev, int phy, int reg, int data) 605 { 606 struct rl_softc *sc; 607 struct rl_mii_frame frame; 608 uint16_t rl8139_reg = 0; 609 610 sc = device_get_softc(dev); 611 612 if (sc->rl_type == RL_8139) { 613 /* Pretend the internal PHY is only at address 0 */ 614 if (phy) { 615 return (0); 616 } 617 switch (reg) { 618 case MII_BMCR: 619 rl8139_reg = RL_BMCR; 620 break; 621 case MII_BMSR: 622 rl8139_reg = RL_BMSR; 623 break; 624 case MII_ANAR: 625 rl8139_reg = RL_ANAR; 626 break; 627 case MII_ANER: 628 rl8139_reg = RL_ANER; 629 break; 630 case MII_ANLPAR: 631 rl8139_reg = RL_LPAR; 632 break; 633 case MII_PHYIDR1: 634 case MII_PHYIDR2: 635 return (0); 636 break; 637 default: 638 if_printf(&sc->arpcom.ac_if, "bad phy register\n"); 639 return (0); 640 } 641 CSR_WRITE_2(sc, rl8139_reg, data); 642 return (0); 643 } 644 645 bzero((char *)&frame, sizeof(frame)); 646 frame.mii_phyaddr = phy; 647 frame.mii_regaddr = reg; 648 frame.mii_data = data; 649 rl_mii_writereg(sc, &frame); 650 651 return (0); 652 } 653 654 static void 655 rl_miibus_statchg(device_t dev) 656 { 657 } 658 659 /* 660 * Program the 64-bit multicast hash filter. 661 */ 662 static void 663 rl_setmulti(struct rl_softc *sc) 664 { 665 struct ifnet *ifp = &sc->arpcom.ac_if; 666 int h = 0; 667 uint32_t hashes[2] = { 0, 0 }; 668 struct ifmultiaddr *ifma; 669 uint32_t rxfilt; 670 int mcnt = 0; 671 672 RL_LOCK_ASSERT(sc); 673 674 rxfilt = CSR_READ_4(sc, RL_RXCFG); 675 676 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 677 rxfilt |= RL_RXCFG_RX_MULTI; 678 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 679 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 680 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 681 return; 682 } 683 684 /* first, zot all the existing hash bits */ 685 CSR_WRITE_4(sc, RL_MAR0, 0); 686 CSR_WRITE_4(sc, RL_MAR4, 0); 687 688 /* now program new ones */ 689 IF_ADDR_LOCK(ifp); 690 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 691 if (ifma->ifma_addr->sa_family != AF_LINK) 692 continue; 693 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 694 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 695 if (h < 32) 696 hashes[0] |= (1 << h); 697 else 698 hashes[1] |= (1 << (h - 32)); 699 mcnt++; 700 } 701 IF_ADDR_UNLOCK(ifp); 702 703 if (mcnt) 704 rxfilt |= RL_RXCFG_RX_MULTI; 705 else 706 rxfilt &= ~RL_RXCFG_RX_MULTI; 707 708 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 709 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 710 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 711 } 712 713 static void 714 rl_reset(struct rl_softc *sc) 715 { 716 register int i; 717 718 RL_LOCK_ASSERT(sc); 719 720 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 721 722 for (i = 0; i < RL_TIMEOUT; i++) { 723 DELAY(10); 724 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 725 break; 726 } 727 if (i == RL_TIMEOUT) 728 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 729 } 730 731 /* 732 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 733 * IDs against our list and return a device name if we find a match. 734 */ 735 static int 736 rl_probe(device_t dev) 737 { 738 struct rl_softc *sc; 739 struct rl_type *t = rl_devs; 740 int rid; 741 uint32_t hwrev; 742 743 sc = device_get_softc(dev); 744 745 while (t->rl_name != NULL) { 746 if ((pci_get_vendor(dev) == t->rl_vid) && 747 (pci_get_device(dev) == t->rl_did)) { 748 /* 749 * Temporarily map the I/O space 750 * so we can read the chip ID register. 751 */ 752 rid = RL_RID; 753 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 754 RF_ACTIVE); 755 if (sc->rl_res == NULL) { 756 device_printf(dev, 757 "couldn't map ports/memory\n"); 758 return (ENXIO); 759 } 760 sc->rl_btag = rman_get_bustag(sc->rl_res); 761 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 762 763 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 764 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 765 766 /* Don't attach to 8139C+ or 8169/8110 chips. */ 767 if (hwrev == RL_HWREV_8139CPLUS || 768 (hwrev == RL_HWREV_8169 && 769 t->rl_did == RT_DEVICEID_8169) || 770 hwrev == RL_HWREV_8169S || 771 hwrev == RL_HWREV_8110S) { 772 t++; 773 continue; 774 } 775 776 device_set_desc(dev, t->rl_name); 777 return (BUS_PROBE_DEFAULT); 778 } 779 t++; 780 } 781 782 return (ENXIO); 783 } 784 785 /* 786 * Attach the interface. Allocate softc structures, do ifmedia 787 * setup and ethernet/BPF attach. 788 */ 789 static int 790 rl_attach(device_t dev) 791 { 792 uint8_t eaddr[ETHER_ADDR_LEN]; 793 uint16_t as[3]; 794 struct ifnet *ifp; 795 struct rl_softc *sc; 796 struct rl_type *t; 797 int error = 0, i, rid; 798 int unit; 799 uint16_t rl_did = 0; 800 801 sc = device_get_softc(dev); 802 unit = device_get_unit(dev); 803 804 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 805 MTX_DEF); 806 807 pci_enable_busmaster(dev); 808 809 /* Map control/status registers. */ 810 rid = RL_RID; 811 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 812 813 if (sc->rl_res == NULL) { 814 device_printf(dev, "couldn't map ports/memory\n"); 815 error = ENXIO; 816 goto fail; 817 } 818 819 #ifdef notdef 820 /* 821 * Detect the Realtek 8139B. For some reason, this chip is very 822 * unstable when left to autoselect the media 823 * The best workaround is to set the device to the required 824 * media type or to set it to the 10 Meg speed. 825 */ 826 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF) 827 device_printf(dev, 828 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n"); 829 #endif 830 831 sc->rl_btag = rman_get_bustag(sc->rl_res); 832 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 833 834 /* Allocate interrupt */ 835 rid = 0; 836 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 837 RF_SHAREABLE | RF_ACTIVE); 838 839 if (sc->rl_irq == NULL) { 840 device_printf(dev, "couldn't map interrupt\n"); 841 error = ENXIO; 842 goto fail; 843 } 844 845 /* 846 * Reset the adapter. Only take the lock here as it's needed in 847 * order to call rl_reset(). 848 */ 849 RL_LOCK(sc); 850 rl_reset(sc); 851 RL_UNLOCK(sc); 852 853 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 854 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 855 if (rl_did != 0x8129) 856 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 857 858 /* 859 * Get station address from the EEPROM. 860 */ 861 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0); 862 for (i = 0; i < 3; i++) { 863 eaddr[(i * 2) + 0] = as[i] & 0xff; 864 eaddr[(i * 2) + 1] = as[i] >> 8; 865 } 866 867 sc->rl_unit = unit; 868 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 869 870 /* 871 * Now read the exact device type from the EEPROM to find 872 * out if it's an 8129 or 8139. 873 */ 874 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0); 875 876 t = rl_devs; 877 sc->rl_type = 0; 878 while(t->rl_name != NULL) { 879 if (rl_did == t->rl_did) { 880 sc->rl_type = t->rl_basetype; 881 break; 882 } 883 t++; 884 } 885 886 if (sc->rl_type == 0) { 887 device_printf(dev, "unknown device ID: %x\n", rl_did); 888 error = ENXIO; 889 goto fail; 890 } 891 892 /* 893 * Allocate the parent bus DMA tag appropriate for PCI. 894 */ 895 #define RL_NSEG_NEW 32 896 error = bus_dma_tag_create(NULL, /* parent */ 897 1, 0, /* alignment, boundary */ 898 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 899 BUS_SPACE_MAXADDR, /* highaddr */ 900 NULL, NULL, /* filter, filterarg */ 901 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 902 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 903 BUS_DMA_ALLOCNOW, /* flags */ 904 NULL, NULL, /* lockfunc, lockarg */ 905 &sc->rl_parent_tag); 906 if (error) 907 goto fail; 908 909 /* 910 * Now allocate a tag for the DMA descriptor lists. 911 * All of our lists are allocated as a contiguous block 912 * of memory. 913 */ 914 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 915 1, 0, /* alignment, boundary */ 916 BUS_SPACE_MAXADDR, /* lowaddr */ 917 BUS_SPACE_MAXADDR, /* highaddr */ 918 NULL, NULL, /* filter, filterarg */ 919 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 920 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 921 BUS_DMA_ALLOCNOW, /* flags */ 922 NULL, NULL, /* lockfunc, lockarg */ 923 &sc->rl_tag); 924 if (error) 925 goto fail; 926 927 /* 928 * Now allocate a chunk of DMA-able memory based on the 929 * tag we just created. 930 */ 931 error = bus_dmamem_alloc(sc->rl_tag, 932 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 933 &sc->rl_cdata.rl_rx_dmamap); 934 if (error) { 935 device_printf(dev, "no memory for list buffers!\n"); 936 bus_dma_tag_destroy(sc->rl_tag); 937 sc->rl_tag = NULL; 938 goto fail; 939 } 940 941 /* Leave a few bytes before the start of the RX ring buffer. */ 942 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 943 sc->rl_cdata.rl_rx_buf += sizeof(uint64_t); 944 945 /* Do MII setup */ 946 if (mii_phy_probe(dev, &sc->rl_miibus, 947 rl_ifmedia_upd, rl_ifmedia_sts)) { 948 device_printf(dev, "MII without any phy!\n"); 949 error = ENXIO; 950 goto fail; 951 } 952 953 ifp = &sc->arpcom.ac_if; 954 ifp->if_softc = sc; 955 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 956 ifp->if_mtu = ETHERMTU; 957 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 958 ifp->if_ioctl = rl_ioctl; 959 ifp->if_start = rl_start; 960 ifp->if_watchdog = rl_watchdog; 961 ifp->if_init = rl_init; 962 ifp->if_baudrate = 10000000; 963 ifp->if_capabilities = IFCAP_VLAN_MTU; 964 #ifdef DEVICE_POLLING 965 ifp->if_capabilities |= IFCAP_POLLING; 966 #endif 967 ifp->if_capenable = ifp->if_capabilities; 968 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 969 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 970 IFQ_SET_READY(&ifp->if_snd); 971 972 callout_handle_init(&sc->rl_stat_ch); 973 974 /* 975 * Call MI attach routine. 976 */ 977 ether_ifattach(ifp, eaddr); 978 979 /* Hook interrupt last to avoid having to lock softc */ 980 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE, 981 rl_intr, sc, &sc->rl_intrhand); 982 if (error) { 983 if_printf(ifp, "couldn't set up irq\n"); 984 ether_ifdetach(ifp); 985 } 986 987 fail: 988 if (error) 989 rl_detach(dev); 990 991 return (error); 992 } 993 994 /* 995 * Shutdown hardware and free up resources. This can be called any 996 * time after the mutex has been initialized. It is called in both 997 * the error case in attach and the normal detach case so it needs 998 * to be careful about only freeing resources that have actually been 999 * allocated. 1000 */ 1001 static int 1002 rl_detach(device_t dev) 1003 { 1004 struct rl_softc *sc; 1005 struct ifnet *ifp; 1006 int attached; 1007 1008 sc = device_get_softc(dev); 1009 ifp = &sc->arpcom.ac_if; 1010 1011 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1012 attached = device_is_attached(dev); 1013 /* These should only be active if attach succeeded */ 1014 if (attached) 1015 ether_ifdetach(ifp); 1016 RL_LOCK(sc); 1017 #if 0 1018 sc->suspended = 1; 1019 #endif 1020 if (attached) 1021 rl_stop(sc); 1022 if (sc->rl_miibus) 1023 device_delete_child(dev, sc->rl_miibus); 1024 bus_generic_detach(dev); 1025 1026 if (sc->rl_intrhand) 1027 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1028 if (sc->rl_irq) 1029 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1030 if (sc->rl_res) 1031 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1032 1033 if (sc->rl_tag) { 1034 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1035 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1036 sc->rl_cdata.rl_rx_dmamap); 1037 bus_dma_tag_destroy(sc->rl_tag); 1038 } 1039 if (sc->rl_parent_tag) 1040 bus_dma_tag_destroy(sc->rl_parent_tag); 1041 1042 RL_UNLOCK(sc); 1043 mtx_destroy(&sc->rl_mtx); 1044 1045 return (0); 1046 } 1047 1048 /* 1049 * Initialize the transmit descriptors. 1050 */ 1051 static int 1052 rl_list_tx_init(struct rl_softc *sc) 1053 { 1054 struct rl_chain_data *cd; 1055 int i; 1056 1057 RL_LOCK_ASSERT(sc); 1058 1059 cd = &sc->rl_cdata; 1060 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1061 cd->rl_tx_chain[i] = NULL; 1062 CSR_WRITE_4(sc, 1063 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); 1064 } 1065 1066 sc->rl_cdata.cur_tx = 0; 1067 sc->rl_cdata.last_tx = 0; 1068 1069 return (0); 1070 } 1071 1072 /* 1073 * A frame has been uploaded: pass the resulting mbuf chain up to 1074 * the higher level protocols. 1075 * 1076 * You know there's something wrong with a PCI bus-master chip design 1077 * when you have to use m_devget(). 1078 * 1079 * The receive operation is badly documented in the datasheet, so I'll 1080 * attempt to document it here. The driver provides a buffer area and 1081 * places its base address in the RX buffer start address register. 1082 * The chip then begins copying frames into the RX buffer. Each frame 1083 * is preceded by a 32-bit RX status word which specifies the length 1084 * of the frame and certain other status bits. Each frame (starting with 1085 * the status word) is also 32-bit aligned. The frame length is in the 1086 * first 16 bits of the status word; the lower 15 bits correspond with 1087 * the 'rx status register' mentioned in the datasheet. 1088 * 1089 * Note: to make the Alpha happy, the frame payload needs to be aligned 1090 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1091 * as the offset argument to m_devget(). 1092 */ 1093 static void 1094 rl_rxeof(struct rl_softc *sc) 1095 { 1096 struct mbuf *m; 1097 struct ifnet *ifp = &sc->arpcom.ac_if; 1098 uint8_t *rxbufpos; 1099 int total_len = 0; 1100 int wrap = 0; 1101 uint32_t rxstat; 1102 uint16_t cur_rx; 1103 uint16_t limit; 1104 uint16_t max_bytes, rx_bytes = 0; 1105 1106 RL_LOCK_ASSERT(sc); 1107 1108 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1109 BUS_DMASYNC_POSTREAD); 1110 1111 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1112 1113 /* Do not try to read past this point. */ 1114 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1115 1116 if (limit < cur_rx) 1117 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1118 else 1119 max_bytes = limit - cur_rx; 1120 1121 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1122 #ifdef DEVICE_POLLING 1123 if (ifp->if_flags & IFF_POLLING) { 1124 if (sc->rxcycles <= 0) 1125 break; 1126 sc->rxcycles--; 1127 } 1128 #endif /* DEVICE_POLLING */ 1129 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1130 rxstat = le32toh(*(uint32_t *)rxbufpos); 1131 1132 /* 1133 * Here's a totally undocumented fact for you. When the 1134 * RealTek chip is in the process of copying a packet into 1135 * RAM for you, the length will be 0xfff0. If you spot a 1136 * packet header with this value, you need to stop. The 1137 * datasheet makes absolutely no mention of this and 1138 * RealTek should be shot for this. 1139 */ 1140 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1141 break; 1142 1143 if (!(rxstat & RL_RXSTAT_RXOK)) { 1144 ifp->if_ierrors++; 1145 rl_init_locked(sc); 1146 return; 1147 } 1148 1149 /* No errors; receive the packet. */ 1150 total_len = rxstat >> 16; 1151 rx_bytes += total_len + 4; 1152 1153 /* 1154 * XXX The RealTek chip includes the CRC with every 1155 * received frame, and there's no way to turn this 1156 * behavior off (at least, I can't find anything in 1157 * the manual that explains how to do it) so we have 1158 * to trim off the CRC manually. 1159 */ 1160 total_len -= ETHER_CRC_LEN; 1161 1162 /* 1163 * Avoid trying to read more bytes than we know 1164 * the chip has prepared for us. 1165 */ 1166 if (rx_bytes > max_bytes) 1167 break; 1168 1169 rxbufpos = sc->rl_cdata.rl_rx_buf + 1170 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1171 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1172 rxbufpos = sc->rl_cdata.rl_rx_buf; 1173 1174 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1175 if (total_len > wrap) { 1176 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1177 NULL); 1178 if (m == NULL) { 1179 ifp->if_ierrors++; 1180 } else { 1181 m_copyback(m, wrap, total_len - wrap, 1182 sc->rl_cdata.rl_rx_buf); 1183 } 1184 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1185 } else { 1186 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1187 NULL); 1188 if (m == NULL) 1189 ifp->if_ierrors++; 1190 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1191 } 1192 1193 /* Round up to 32-bit boundary. */ 1194 cur_rx = (cur_rx + 3) & ~3; 1195 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1196 1197 if (m == NULL) 1198 continue; 1199 1200 ifp->if_ipackets++; 1201 RL_UNLOCK(sc); 1202 (*ifp->if_input)(ifp, m); 1203 RL_LOCK(sc); 1204 } 1205 } 1206 1207 /* 1208 * A frame was downloaded to the chip. It's safe for us to clean up 1209 * the list buffers. 1210 */ 1211 static void 1212 rl_txeof(struct rl_softc *sc) 1213 { 1214 struct ifnet *ifp = &sc->arpcom.ac_if; 1215 uint32_t txstat; 1216 1217 RL_LOCK_ASSERT(sc); 1218 1219 /* 1220 * Go through our tx list and free mbufs for those 1221 * frames that have been uploaded. 1222 */ 1223 do { 1224 if (RL_LAST_TXMBUF(sc) == NULL) 1225 break; 1226 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1227 if (!(txstat & (RL_TXSTAT_TX_OK| 1228 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1229 break; 1230 1231 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1232 1233 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1234 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1235 m_freem(RL_LAST_TXMBUF(sc)); 1236 RL_LAST_TXMBUF(sc) = NULL; 1237 /* 1238 * If there was a transmit underrun, bump the TX threshold. 1239 * Make sure not to overflow the 63 * 32byte we can address 1240 * with the 6 available bit. 1241 */ 1242 if ((txstat & RL_TXSTAT_TX_UNDERRUN) && 1243 (sc->rl_txthresh < 2016)) 1244 sc->rl_txthresh += 32; 1245 if (txstat & RL_TXSTAT_TX_OK) 1246 ifp->if_opackets++; 1247 else { 1248 int oldthresh; 1249 ifp->if_oerrors++; 1250 if ((txstat & RL_TXSTAT_TXABRT) || 1251 (txstat & RL_TXSTAT_OUTOFWIN)) 1252 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1253 oldthresh = sc->rl_txthresh; 1254 /* error recovery */ 1255 rl_reset(sc); 1256 rl_init_locked(sc); 1257 /* restore original threshold */ 1258 sc->rl_txthresh = oldthresh; 1259 return; 1260 } 1261 RL_INC(sc->rl_cdata.last_tx); 1262 ifp->if_flags &= ~IFF_OACTIVE; 1263 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1264 1265 if (RL_LAST_TXMBUF(sc) == NULL) 1266 ifp->if_timer = 0; 1267 else if (ifp->if_timer == 0) 1268 ifp->if_timer = 5; 1269 } 1270 1271 static void 1272 rl_tick(void *xsc) 1273 { 1274 struct rl_softc *sc = xsc; 1275 struct mii_data *mii; 1276 1277 RL_LOCK(sc); 1278 mii = device_get_softc(sc->rl_miibus); 1279 mii_tick(mii); 1280 1281 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1282 RL_UNLOCK(sc); 1283 } 1284 1285 #ifdef DEVICE_POLLING 1286 static void 1287 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1288 { 1289 struct rl_softc *sc = ifp->if_softc; 1290 1291 RL_LOCK(sc); 1292 rl_poll_locked(ifp, cmd, count); 1293 RL_UNLOCK(sc); 1294 } 1295 1296 static void 1297 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1298 { 1299 struct rl_softc *sc = ifp->if_softc; 1300 1301 RL_LOCK_ASSERT(sc); 1302 1303 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1304 ether_poll_deregister(ifp); 1305 cmd = POLL_DEREGISTER; 1306 } 1307 1308 if (cmd == POLL_DEREGISTER) { 1309 /* Final call; enable interrupts. */ 1310 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1311 return; 1312 } 1313 1314 sc->rxcycles = count; 1315 rl_rxeof(sc); 1316 rl_txeof(sc); 1317 1318 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1319 rl_start_locked(ifp); 1320 1321 if (cmd == POLL_AND_CHECK_STATUS) { 1322 uint16_t status; 1323 1324 /* We should also check the status register. */ 1325 status = CSR_READ_2(sc, RL_ISR); 1326 if (status == 0xffff) 1327 return; 1328 if (status != 0) 1329 CSR_WRITE_2(sc, RL_ISR, status); 1330 1331 /* XXX We should check behaviour on receiver stalls. */ 1332 1333 if (status & RL_ISR_SYSTEM_ERR) { 1334 rl_reset(sc); 1335 rl_init_locked(sc); 1336 } 1337 } 1338 } 1339 #endif /* DEVICE_POLLING */ 1340 1341 static void 1342 rl_intr(void *arg) 1343 { 1344 struct rl_softc *sc = arg; 1345 struct ifnet *ifp = &sc->arpcom.ac_if; 1346 uint16_t status; 1347 1348 RL_LOCK(sc); 1349 1350 if (sc->suspended) 1351 goto done_locked; 1352 1353 #ifdef DEVICE_POLLING 1354 if (ifp->if_flags & IFF_POLLING) 1355 goto done_locked; 1356 1357 if ((ifp->if_capenable & IFCAP_POLLING) && 1358 ether_poll_register(rl_poll, ifp)) { 1359 /* Disable interrupts. */ 1360 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1361 rl_poll_locked(ifp, 0, 1); 1362 goto done_locked; 1363 } 1364 #endif /* DEVICE_POLLING */ 1365 1366 for (;;) { 1367 status = CSR_READ_2(sc, RL_ISR); 1368 /* If the card has gone away, the read returns 0xffff. */ 1369 if (status == 0xffff) 1370 break; 1371 if (status != 0) 1372 CSR_WRITE_2(sc, RL_ISR, status); 1373 if ((status & RL_INTRS) == 0) 1374 break; 1375 if (status & RL_ISR_RX_OK) 1376 rl_rxeof(sc); 1377 if (status & RL_ISR_RX_ERR) 1378 rl_rxeof(sc); 1379 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1380 rl_txeof(sc); 1381 if (status & RL_ISR_SYSTEM_ERR) { 1382 rl_reset(sc); 1383 rl_init_locked(sc); 1384 } 1385 } 1386 1387 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1388 rl_start_locked(ifp); 1389 1390 done_locked: 1391 RL_UNLOCK(sc); 1392 } 1393 1394 /* 1395 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1396 * pointers to the fragment pointers. 1397 */ 1398 static int 1399 rl_encap(struct rl_softc *sc, struct mbuf *m_head) 1400 { 1401 struct mbuf *m_new = NULL; 1402 1403 RL_LOCK_ASSERT(sc); 1404 1405 /* 1406 * The RealTek is brain damaged and wants longword-aligned 1407 * TX buffers, plus we can only have one fragment buffer 1408 * per packet. We have to copy pretty much all the time. 1409 */ 1410 m_new = m_defrag(m_head, M_DONTWAIT); 1411 1412 if (m_new == NULL) { 1413 m_freem(m_head); 1414 return (1); 1415 } 1416 m_head = m_new; 1417 1418 /* Pad frames to at least 60 bytes. */ 1419 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1420 /* 1421 * Make security concious people happy: zero out the 1422 * bytes in the pad area, since we don't know what 1423 * this mbuf cluster buffer's previous user might 1424 * have left in it. 1425 */ 1426 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1427 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1428 m_head->m_pkthdr.len += 1429 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1430 m_head->m_len = m_head->m_pkthdr.len; 1431 } 1432 1433 RL_CUR_TXMBUF(sc) = m_head; 1434 1435 return (0); 1436 } 1437 1438 /* 1439 * Main transmit routine. 1440 */ 1441 static void 1442 rl_start(struct ifnet *ifp) 1443 { 1444 struct rl_softc *sc = ifp->if_softc; 1445 1446 RL_LOCK(sc); 1447 rl_start_locked(ifp); 1448 RL_UNLOCK(sc); 1449 } 1450 1451 static void 1452 rl_start_locked(struct ifnet *ifp) 1453 { 1454 struct rl_softc *sc = ifp->if_softc; 1455 struct mbuf *m_head = NULL; 1456 1457 RL_LOCK_ASSERT(sc); 1458 1459 while (RL_CUR_TXMBUF(sc) == NULL) { 1460 1461 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1462 1463 if (m_head == NULL) 1464 break; 1465 1466 if (rl_encap(sc, m_head)) 1467 break; 1468 1469 /* Pass a copy of this mbuf chain to the bpf subsystem. */ 1470 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1471 1472 /* Transmit the frame. */ 1473 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1474 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1475 mtod(RL_CUR_TXMBUF(sc), void *), 1476 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1477 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1478 BUS_DMASYNC_PREREAD); 1479 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1480 RL_TXTHRESH(sc->rl_txthresh) | 1481 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1482 1483 RL_INC(sc->rl_cdata.cur_tx); 1484 1485 /* Set a timeout in case the chip goes out to lunch. */ 1486 ifp->if_timer = 5; 1487 } 1488 1489 /* 1490 * We broke out of the loop because all our TX slots are 1491 * full. Mark the NIC as busy until it drains some of the 1492 * packets from the queue. 1493 */ 1494 if (RL_CUR_TXMBUF(sc) != NULL) 1495 ifp->if_flags |= IFF_OACTIVE; 1496 } 1497 1498 static void 1499 rl_init(void *xsc) 1500 { 1501 struct rl_softc *sc = xsc; 1502 1503 RL_LOCK(sc); 1504 rl_init_locked(sc); 1505 RL_UNLOCK(sc); 1506 } 1507 1508 static void 1509 rl_init_locked(struct rl_softc *sc) 1510 { 1511 struct ifnet *ifp = &sc->arpcom.ac_if; 1512 struct mii_data *mii; 1513 uint32_t rxcfg = 0; 1514 1515 RL_LOCK_ASSERT(sc); 1516 1517 mii = device_get_softc(sc->rl_miibus); 1518 1519 /* 1520 * Cancel pending I/O and free all RX/TX buffers. 1521 */ 1522 rl_stop(sc); 1523 1524 /* 1525 * Init our MAC address. Even though the chipset 1526 * documentation doesn't mention it, we need to enter "Config 1527 * register write enable" mode to modify the ID registers. 1528 */ 1529 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1530 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1531 *(uint32_t *)(&sc->arpcom.ac_enaddr[0])); 1532 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1533 *(uint32_t *)(&sc->arpcom.ac_enaddr[4])); 1534 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1535 1536 /* Init the RX buffer pointer register. */ 1537 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1538 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1539 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1540 BUS_DMASYNC_PREWRITE); 1541 1542 /* Init TX descriptors. */ 1543 rl_list_tx_init(sc); 1544 1545 /* 1546 * Enable transmit and receive. 1547 */ 1548 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1549 1550 /* 1551 * Set the initial TX and RX configuration. 1552 */ 1553 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1554 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1555 1556 /* Set the individual bit to receive frames for this host only. */ 1557 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1558 rxcfg |= RL_RXCFG_RX_INDIV; 1559 1560 /* If we want promiscuous mode, set the allframes bit. */ 1561 if (ifp->if_flags & IFF_PROMISC) { 1562 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1563 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1564 } else { 1565 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1566 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1567 } 1568 1569 /* Set capture broadcast bit to capture broadcast frames. */ 1570 if (ifp->if_flags & IFF_BROADCAST) { 1571 rxcfg |= RL_RXCFG_RX_BROAD; 1572 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1573 } else { 1574 rxcfg &= ~RL_RXCFG_RX_BROAD; 1575 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1576 } 1577 1578 /* Program the multicast filter, if necessary. */ 1579 rl_setmulti(sc); 1580 1581 #ifdef DEVICE_POLLING 1582 /* Disable interrupts if we are polling. */ 1583 if (ifp->if_flags & IFF_POLLING) 1584 CSR_WRITE_2(sc, RL_IMR, 0); 1585 else 1586 #endif /* DEVICE_POLLING */ 1587 /* Enable interrupts. */ 1588 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1589 1590 /* Set initial TX threshold */ 1591 sc->rl_txthresh = RL_TX_THRESH_INIT; 1592 1593 /* Start RX/TX process. */ 1594 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1595 1596 /* Enable receiver and transmitter. */ 1597 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1598 1599 mii_mediachg(mii); 1600 1601 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1602 1603 ifp->if_flags |= IFF_RUNNING; 1604 ifp->if_flags &= ~IFF_OACTIVE; 1605 1606 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1607 } 1608 1609 /* 1610 * Set media options. 1611 */ 1612 static int 1613 rl_ifmedia_upd(struct ifnet *ifp) 1614 { 1615 struct rl_softc *sc = ifp->if_softc; 1616 struct mii_data *mii; 1617 1618 mii = device_get_softc(sc->rl_miibus); 1619 1620 mii_mediachg(mii); 1621 1622 return (0); 1623 } 1624 1625 /* 1626 * Report current media status. 1627 */ 1628 static void 1629 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1630 { 1631 struct rl_softc *sc = ifp->if_softc; 1632 struct mii_data *mii; 1633 1634 mii = device_get_softc(sc->rl_miibus); 1635 1636 mii_pollstat(mii); 1637 ifmr->ifm_active = mii->mii_media_active; 1638 ifmr->ifm_status = mii->mii_media_status; 1639 } 1640 1641 static int 1642 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1643 { 1644 struct ifreq *ifr = (struct ifreq *)data; 1645 struct mii_data *mii; 1646 struct rl_softc *sc = ifp->if_softc; 1647 int error = 0; 1648 1649 switch (command) { 1650 case SIOCSIFFLAGS: 1651 RL_LOCK(sc); 1652 if (ifp->if_flags & IFF_UP) { 1653 rl_init_locked(sc); 1654 } else { 1655 if (ifp->if_flags & IFF_RUNNING) 1656 rl_stop(sc); 1657 } 1658 RL_UNLOCK(sc); 1659 error = 0; 1660 break; 1661 case SIOCADDMULTI: 1662 case SIOCDELMULTI: 1663 RL_LOCK(sc); 1664 rl_setmulti(sc); 1665 RL_UNLOCK(sc); 1666 error = 0; 1667 break; 1668 case SIOCGIFMEDIA: 1669 case SIOCSIFMEDIA: 1670 mii = device_get_softc(sc->rl_miibus); 1671 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1672 break; 1673 case SIOCSIFCAP: 1674 ifp->if_capenable &= ~IFCAP_POLLING; 1675 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 1676 break; 1677 default: 1678 error = ether_ioctl(ifp, command, data); 1679 break; 1680 } 1681 1682 return (error); 1683 } 1684 1685 static void 1686 rl_watchdog(struct ifnet *ifp) 1687 { 1688 struct rl_softc *sc = ifp->if_softc; 1689 1690 RL_LOCK(sc); 1691 1692 if_printf(ifp, "watchdog timeout\n"); 1693 ifp->if_oerrors++; 1694 1695 rl_txeof(sc); 1696 rl_rxeof(sc); 1697 rl_init_locked(sc); 1698 1699 RL_UNLOCK(sc); 1700 } 1701 1702 /* 1703 * Stop the adapter and free any mbufs allocated to the 1704 * RX and TX lists. 1705 */ 1706 static void 1707 rl_stop(struct rl_softc *sc) 1708 { 1709 register int i; 1710 struct ifnet *ifp = &sc->arpcom.ac_if; 1711 1712 RL_LOCK_ASSERT(sc); 1713 1714 ifp->if_timer = 0; 1715 untimeout(rl_tick, sc, sc->rl_stat_ch); 1716 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1717 #ifdef DEVICE_POLLING 1718 ether_poll_deregister(ifp); 1719 #endif /* DEVICE_POLLING */ 1720 1721 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1722 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1723 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1724 1725 /* 1726 * Free the TX list buffers. 1727 */ 1728 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1729 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1730 bus_dmamap_unload(sc->rl_tag, 1731 sc->rl_cdata.rl_tx_dmamap[i]); 1732 bus_dmamap_destroy(sc->rl_tag, 1733 sc->rl_cdata.rl_tx_dmamap[i]); 1734 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1735 sc->rl_cdata.rl_tx_chain[i] = NULL; 1736 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1737 0x0000000); 1738 } 1739 } 1740 } 1741 1742 /* 1743 * Device suspend routine. Stop the interface and save some PCI 1744 * settings in case the BIOS doesn't restore them properly on 1745 * resume. 1746 */ 1747 static int 1748 rl_suspend(device_t dev) 1749 { 1750 struct rl_softc *sc; 1751 1752 sc = device_get_softc(dev); 1753 1754 RL_LOCK(sc); 1755 rl_stop(sc); 1756 sc->suspended = 1; 1757 RL_UNLOCK(sc); 1758 1759 return (0); 1760 } 1761 1762 /* 1763 * Device resume routine. Restore some PCI settings in case the BIOS 1764 * doesn't, re-enable busmastering, and restart the interface if 1765 * appropriate. 1766 */ 1767 static int 1768 rl_resume(device_t dev) 1769 { 1770 struct rl_softc *sc; 1771 struct ifnet *ifp; 1772 1773 sc = device_get_softc(dev); 1774 ifp = &sc->arpcom.ac_if; 1775 1776 RL_LOCK(sc); 1777 1778 /* reinitialize interface if necessary */ 1779 if (ifp->if_flags & IFF_UP) 1780 rl_init_locked(sc); 1781 1782 sc->suspended = 0; 1783 1784 RL_UNLOCK(sc); 1785 1786 return (0); 1787 } 1788 1789 /* 1790 * Stop all chip I/O so that the kernel's probe routines don't 1791 * get confused by errant DMAs when rebooting. 1792 */ 1793 static void 1794 rl_shutdown(device_t dev) 1795 { 1796 struct rl_softc *sc; 1797 1798 sc = device_get_softc(dev); 1799 1800 RL_LOCK(sc); 1801 rl_stop(sc); 1802 RL_UNLOCK(sc); 1803 }
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