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sys/pci/if_rl.c
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1 /*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/6.1/sys/pci/if_rl.c 156820 2006-03-17 21:30:57Z glebius $"); 35 36 /* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 /* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86 #ifdef HAVE_KERNEL_OPTION_HEADERS 87 #include "opt_device_polling.h" 88 #endif 89 90 #include <sys/param.h> 91 #include <sys/endian.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/module.h> 98 #include <sys/socket.h> 99 100 #include <net/if.h> 101 #include <net/if_arp.h> 102 #include <net/ethernet.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 #include <net/if_types.h> 106 107 #include <net/bpf.h> 108 109 #include <machine/bus.h> 110 #include <machine/resource.h> 111 #include <sys/bus.h> 112 #include <sys/rman.h> 113 114 #include <dev/mii/mii.h> 115 #include <dev/mii/miivar.h> 116 117 #include <dev/pci/pcireg.h> 118 #include <dev/pci/pcivar.h> 119 120 MODULE_DEPEND(rl, pci, 1, 1, 1); 121 MODULE_DEPEND(rl, ether, 1, 1, 1); 122 MODULE_DEPEND(rl, miibus, 1, 1, 1); 123 124 /* "controller miibus0" required. See GENERIC if you get errors here. */ 125 #include "miibus_if.h" 126 127 /* 128 * Default to using PIO access for this driver. On SMP systems, 129 * there appear to be problems with memory mapped mode: it looks like 130 * doing too many memory mapped access back to back in rapid succession 131 * can hang the bus. I'm inclined to blame this on crummy design/construction 132 * on the part of RealTek. Memory mapped mode does appear to work on 133 * uniprocessor systems though. 134 */ 135 #define RL_USEIOSPACE 136 137 #include <pci/if_rlreg.h> 138 139 /* 140 * Various supported device vendors/types and their names. 141 */ 142 static struct rl_type rl_devs[] = { 143 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 144 "RealTek 8129 10/100BaseTX" }, 145 { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 146 "RealTek 8139 10/100BaseTX" }, 147 { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 148 "RealTek 8139 10/100BaseTX CardBus" }, 149 { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 150 "RealTek 8100 10/100BaseTX" }, 151 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 152 "Accton MPX 5030/5038 10/100BaseTX" }, 153 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 154 "Delta Electronics 8139 10/100BaseTX" }, 155 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 156 "Addtron Technolgy 8139 10/100BaseTX" }, 157 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 158 "D-Link DFE-530TX+ 10/100BaseTX" }, 159 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 160 "D-Link DFE-690TXD 10/100BaseTX" }, 161 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 162 "Nortel Networks 10/100BaseTX" }, 163 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 164 "Corega FEther CB-TXD" }, 165 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 166 "Corega FEtherII CB-TXD" }, 167 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 168 "Peppercon AG ROL-F" }, 169 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 170 "Planex FNW-3800-TX" }, 171 { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 172 "Compaq HNE-300" }, 173 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 174 "LevelOne FPC-0106TX" }, 175 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 176 "Edimax EP-4103DL CardBus" }, 177 { 0, 0, 0, NULL } 178 }; 179 180 static int rl_attach(device_t); 181 static int rl_detach(device_t); 182 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int); 183 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int); 184 static void rl_eeprom_putbyte(struct rl_softc *, int); 185 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 186 static int rl_encap(struct rl_softc *, struct mbuf * ); 187 static int rl_list_tx_init(struct rl_softc *); 188 static int rl_ifmedia_upd(struct ifnet *); 189 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 190 static int rl_ioctl(struct ifnet *, u_long, caddr_t); 191 static void rl_intr(void *); 192 static void rl_init(void *); 193 static void rl_init_locked(struct rl_softc *sc); 194 static void rl_mii_send(struct rl_softc *, uint32_t, int); 195 static void rl_mii_sync(struct rl_softc *); 196 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 197 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 198 static int rl_miibus_readreg(device_t, int, int); 199 static void rl_miibus_statchg(device_t); 200 static int rl_miibus_writereg(device_t, int, int, int); 201 #ifdef DEVICE_POLLING 202 static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 203 static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 204 #endif 205 static int rl_probe(device_t); 206 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int); 207 static void rl_reset(struct rl_softc *); 208 static int rl_resume(device_t); 209 static void rl_rxeof(struct rl_softc *); 210 static void rl_setmulti(struct rl_softc *); 211 static void rl_shutdown(device_t); 212 static void rl_start(struct ifnet *); 213 static void rl_start_locked(struct ifnet *); 214 static void rl_stop(struct rl_softc *); 215 static int rl_suspend(device_t); 216 static void rl_tick(void *); 217 static void rl_txeof(struct rl_softc *); 218 static void rl_watchdog(struct ifnet *); 219 220 #ifdef RL_USEIOSPACE 221 #define RL_RES SYS_RES_IOPORT 222 #define RL_RID RL_PCI_LOIO 223 #else 224 #define RL_RES SYS_RES_MEMORY 225 #define RL_RID RL_PCI_LOMEM 226 #endif 227 228 static device_method_t rl_methods[] = { 229 /* Device interface */ 230 DEVMETHOD(device_probe, rl_probe), 231 DEVMETHOD(device_attach, rl_attach), 232 DEVMETHOD(device_detach, rl_detach), 233 DEVMETHOD(device_suspend, rl_suspend), 234 DEVMETHOD(device_resume, rl_resume), 235 DEVMETHOD(device_shutdown, rl_shutdown), 236 237 /* bus interface */ 238 DEVMETHOD(bus_print_child, bus_generic_print_child), 239 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 240 241 /* MII interface */ 242 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 243 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 244 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 245 246 { 0, 0 } 247 }; 248 249 static driver_t rl_driver = { 250 "rl", 251 rl_methods, 252 sizeof(struct rl_softc) 253 }; 254 255 static devclass_t rl_devclass; 256 257 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 258 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 259 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 260 261 #define EE_SET(x) \ 262 CSR_WRITE_1(sc, RL_EECMD, \ 263 CSR_READ_1(sc, RL_EECMD) | x) 264 265 #define EE_CLR(x) \ 266 CSR_WRITE_1(sc, RL_EECMD, \ 267 CSR_READ_1(sc, RL_EECMD) & ~x) 268 269 static void 270 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 271 { 272 struct rl_softc *sc = arg; 273 274 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 275 } 276 277 static void 278 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 279 { 280 struct rl_softc *sc = arg; 281 282 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 283 } 284 285 /* 286 * Send a read command and address to the EEPROM, check for ACK. 287 */ 288 static void 289 rl_eeprom_putbyte(struct rl_softc *sc, int addr) 290 { 291 register int d, i; 292 293 d = addr | sc->rl_eecmd_read; 294 295 /* 296 * Feed in each bit and strobe the clock. 297 */ 298 for (i = 0x400; i; i >>= 1) { 299 if (d & i) { 300 EE_SET(RL_EE_DATAIN); 301 } else { 302 EE_CLR(RL_EE_DATAIN); 303 } 304 DELAY(100); 305 EE_SET(RL_EE_CLK); 306 DELAY(150); 307 EE_CLR(RL_EE_CLK); 308 DELAY(100); 309 } 310 } 311 312 /* 313 * Read a word of data stored in the EEPROM at address 'addr.' 314 */ 315 static void 316 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 317 { 318 register int i; 319 uint16_t word = 0; 320 321 /* Enter EEPROM access mode. */ 322 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 323 324 /* 325 * Send address of word we want to read. 326 */ 327 rl_eeprom_putbyte(sc, addr); 328 329 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 330 331 /* 332 * Start reading bits from EEPROM. 333 */ 334 for (i = 0x8000; i; i >>= 1) { 335 EE_SET(RL_EE_CLK); 336 DELAY(100); 337 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 338 word |= i; 339 EE_CLR(RL_EE_CLK); 340 DELAY(100); 341 } 342 343 /* Turn off EEPROM access mode. */ 344 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 345 346 *dest = word; 347 } 348 349 /* 350 * Read a sequence of words from the EEPROM. 351 */ 352 static void 353 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap) 354 { 355 int i; 356 uint16_t word = 0, *ptr; 357 358 for (i = 0; i < cnt; i++) { 359 rl_eeprom_getword(sc, off + i, &word); 360 ptr = (uint16_t *)(dest + (i * 2)); 361 if (swap) 362 *ptr = ntohs(word); 363 else 364 *ptr = word; 365 } 366 } 367 368 /* 369 * MII access routines are provided for the 8129, which 370 * doesn't have a built-in PHY. For the 8139, we fake things 371 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 372 * direct access PHY registers. 373 */ 374 #define MII_SET(x) \ 375 CSR_WRITE_1(sc, RL_MII, \ 376 CSR_READ_1(sc, RL_MII) | (x)) 377 378 #define MII_CLR(x) \ 379 CSR_WRITE_1(sc, RL_MII, \ 380 CSR_READ_1(sc, RL_MII) & ~(x)) 381 382 /* 383 * Sync the PHYs by setting data bit and strobing the clock 32 times. 384 */ 385 static void 386 rl_mii_sync(struct rl_softc *sc) 387 { 388 register int i; 389 390 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 391 392 for (i = 0; i < 32; i++) { 393 MII_SET(RL_MII_CLK); 394 DELAY(1); 395 MII_CLR(RL_MII_CLK); 396 DELAY(1); 397 } 398 } 399 400 /* 401 * Clock a series of bits through the MII. 402 */ 403 static void 404 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt) 405 { 406 int i; 407 408 MII_CLR(RL_MII_CLK); 409 410 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 411 if (bits & i) { 412 MII_SET(RL_MII_DATAOUT); 413 } else { 414 MII_CLR(RL_MII_DATAOUT); 415 } 416 DELAY(1); 417 MII_CLR(RL_MII_CLK); 418 DELAY(1); 419 MII_SET(RL_MII_CLK); 420 } 421 } 422 423 /* 424 * Read an PHY register through the MII. 425 */ 426 static int 427 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 428 { 429 int i, ack; 430 431 /* Set up frame for RX. */ 432 frame->mii_stdelim = RL_MII_STARTDELIM; 433 frame->mii_opcode = RL_MII_READOP; 434 frame->mii_turnaround = 0; 435 frame->mii_data = 0; 436 437 CSR_WRITE_2(sc, RL_MII, 0); 438 439 /* Turn on data xmit. */ 440 MII_SET(RL_MII_DIR); 441 442 rl_mii_sync(sc); 443 444 /* Send command/address info. */ 445 rl_mii_send(sc, frame->mii_stdelim, 2); 446 rl_mii_send(sc, frame->mii_opcode, 2); 447 rl_mii_send(sc, frame->mii_phyaddr, 5); 448 rl_mii_send(sc, frame->mii_regaddr, 5); 449 450 /* Idle bit */ 451 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 452 DELAY(1); 453 MII_SET(RL_MII_CLK); 454 DELAY(1); 455 456 /* Turn off xmit. */ 457 MII_CLR(RL_MII_DIR); 458 459 /* Check for ack */ 460 MII_CLR(RL_MII_CLK); 461 DELAY(1); 462 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 463 MII_SET(RL_MII_CLK); 464 DELAY(1); 465 466 /* 467 * Now try reading data bits. If the ack failed, we still 468 * need to clock through 16 cycles to keep the PHY(s) in sync. 469 */ 470 if (ack) { 471 for(i = 0; i < 16; i++) { 472 MII_CLR(RL_MII_CLK); 473 DELAY(1); 474 MII_SET(RL_MII_CLK); 475 DELAY(1); 476 } 477 goto fail; 478 } 479 480 for (i = 0x8000; i; i >>= 1) { 481 MII_CLR(RL_MII_CLK); 482 DELAY(1); 483 if (!ack) { 484 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 485 frame->mii_data |= i; 486 DELAY(1); 487 } 488 MII_SET(RL_MII_CLK); 489 DELAY(1); 490 } 491 492 fail: 493 MII_CLR(RL_MII_CLK); 494 DELAY(1); 495 MII_SET(RL_MII_CLK); 496 DELAY(1); 497 498 return (ack ? 1 : 0); 499 } 500 501 /* 502 * Write to a PHY register through the MII. 503 */ 504 static int 505 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 506 { 507 508 /* Set up frame for TX. */ 509 frame->mii_stdelim = RL_MII_STARTDELIM; 510 frame->mii_opcode = RL_MII_WRITEOP; 511 frame->mii_turnaround = RL_MII_TURNAROUND; 512 513 /* Turn on data output. */ 514 MII_SET(RL_MII_DIR); 515 516 rl_mii_sync(sc); 517 518 rl_mii_send(sc, frame->mii_stdelim, 2); 519 rl_mii_send(sc, frame->mii_opcode, 2); 520 rl_mii_send(sc, frame->mii_phyaddr, 5); 521 rl_mii_send(sc, frame->mii_regaddr, 5); 522 rl_mii_send(sc, frame->mii_turnaround, 2); 523 rl_mii_send(sc, frame->mii_data, 16); 524 525 /* Idle bit. */ 526 MII_SET(RL_MII_CLK); 527 DELAY(1); 528 MII_CLR(RL_MII_CLK); 529 DELAY(1); 530 531 /* Turn off xmit. */ 532 MII_CLR(RL_MII_DIR); 533 534 return (0); 535 } 536 537 static int 538 rl_miibus_readreg(device_t dev, int phy, int reg) 539 { 540 struct rl_softc *sc; 541 struct rl_mii_frame frame; 542 uint16_t rval = 0; 543 uint16_t rl8139_reg = 0; 544 545 sc = device_get_softc(dev); 546 547 if (sc->rl_type == RL_8139) { 548 /* Pretend the internal PHY is only at address 0 */ 549 if (phy) { 550 return (0); 551 } 552 switch (reg) { 553 case MII_BMCR: 554 rl8139_reg = RL_BMCR; 555 break; 556 case MII_BMSR: 557 rl8139_reg = RL_BMSR; 558 break; 559 case MII_ANAR: 560 rl8139_reg = RL_ANAR; 561 break; 562 case MII_ANER: 563 rl8139_reg = RL_ANER; 564 break; 565 case MII_ANLPAR: 566 rl8139_reg = RL_LPAR; 567 break; 568 case MII_PHYIDR1: 569 case MII_PHYIDR2: 570 return (0); 571 /* 572 * Allow the rlphy driver to read the media status 573 * register. If we have a link partner which does not 574 * support NWAY, this is the register which will tell 575 * us the results of parallel detection. 576 */ 577 case RL_MEDIASTAT: 578 rval = CSR_READ_1(sc, RL_MEDIASTAT); 579 return (rval); 580 default: 581 if_printf(sc->rl_ifp, "bad phy register\n"); 582 return (0); 583 } 584 rval = CSR_READ_2(sc, rl8139_reg); 585 return (rval); 586 } 587 588 bzero((char *)&frame, sizeof(frame)); 589 frame.mii_phyaddr = phy; 590 frame.mii_regaddr = reg; 591 rl_mii_readreg(sc, &frame); 592 593 return (frame.mii_data); 594 } 595 596 static int 597 rl_miibus_writereg(device_t dev, int phy, int reg, int data) 598 { 599 struct rl_softc *sc; 600 struct rl_mii_frame frame; 601 uint16_t rl8139_reg = 0; 602 603 sc = device_get_softc(dev); 604 605 if (sc->rl_type == RL_8139) { 606 /* Pretend the internal PHY is only at address 0 */ 607 if (phy) { 608 return (0); 609 } 610 switch (reg) { 611 case MII_BMCR: 612 rl8139_reg = RL_BMCR; 613 break; 614 case MII_BMSR: 615 rl8139_reg = RL_BMSR; 616 break; 617 case MII_ANAR: 618 rl8139_reg = RL_ANAR; 619 break; 620 case MII_ANER: 621 rl8139_reg = RL_ANER; 622 break; 623 case MII_ANLPAR: 624 rl8139_reg = RL_LPAR; 625 break; 626 case MII_PHYIDR1: 627 case MII_PHYIDR2: 628 return (0); 629 break; 630 default: 631 if_printf(sc->rl_ifp, "bad phy register\n"); 632 return (0); 633 } 634 CSR_WRITE_2(sc, rl8139_reg, data); 635 return (0); 636 } 637 638 bzero((char *)&frame, sizeof(frame)); 639 frame.mii_phyaddr = phy; 640 frame.mii_regaddr = reg; 641 frame.mii_data = data; 642 rl_mii_writereg(sc, &frame); 643 644 return (0); 645 } 646 647 static void 648 rl_miibus_statchg(device_t dev) 649 { 650 } 651 652 /* 653 * Program the 64-bit multicast hash filter. 654 */ 655 static void 656 rl_setmulti(struct rl_softc *sc) 657 { 658 struct ifnet *ifp = sc->rl_ifp; 659 int h = 0; 660 uint32_t hashes[2] = { 0, 0 }; 661 struct ifmultiaddr *ifma; 662 uint32_t rxfilt; 663 int mcnt = 0; 664 665 RL_LOCK_ASSERT(sc); 666 667 rxfilt = CSR_READ_4(sc, RL_RXCFG); 668 669 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 670 rxfilt |= RL_RXCFG_RX_MULTI; 671 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 672 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 673 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 674 return; 675 } 676 677 /* first, zot all the existing hash bits */ 678 CSR_WRITE_4(sc, RL_MAR0, 0); 679 CSR_WRITE_4(sc, RL_MAR4, 0); 680 681 /* now program new ones */ 682 IF_ADDR_LOCK(ifp); 683 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 684 if (ifma->ifma_addr->sa_family != AF_LINK) 685 continue; 686 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 687 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 688 if (h < 32) 689 hashes[0] |= (1 << h); 690 else 691 hashes[1] |= (1 << (h - 32)); 692 mcnt++; 693 } 694 IF_ADDR_UNLOCK(ifp); 695 696 if (mcnt) 697 rxfilt |= RL_RXCFG_RX_MULTI; 698 else 699 rxfilt &= ~RL_RXCFG_RX_MULTI; 700 701 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 702 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 703 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 704 } 705 706 static void 707 rl_reset(struct rl_softc *sc) 708 { 709 register int i; 710 711 RL_LOCK_ASSERT(sc); 712 713 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 714 715 for (i = 0; i < RL_TIMEOUT; i++) { 716 DELAY(10); 717 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 718 break; 719 } 720 if (i == RL_TIMEOUT) 721 if_printf(sc->rl_ifp, "reset never completed!\n"); 722 } 723 724 /* 725 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 726 * IDs against our list and return a device name if we find a match. 727 */ 728 static int 729 rl_probe(device_t dev) 730 { 731 struct rl_softc *sc; 732 struct rl_type *t = rl_devs; 733 int rid; 734 uint32_t hwrev; 735 736 sc = device_get_softc(dev); 737 738 while (t->rl_name != NULL) { 739 if ((pci_get_vendor(dev) == t->rl_vid) && 740 (pci_get_device(dev) == t->rl_did)) { 741 /* 742 * Temporarily map the I/O space 743 * so we can read the chip ID register. 744 */ 745 rid = RL_RID; 746 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 747 RF_ACTIVE); 748 if (sc->rl_res == NULL) { 749 device_printf(dev, 750 "couldn't map ports/memory\n"); 751 return (ENXIO); 752 } 753 sc->rl_btag = rman_get_bustag(sc->rl_res); 754 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 755 756 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 757 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 758 759 /* Don't attach to 8139C+ or 8169/8110 chips. */ 760 if (hwrev == RL_HWREV_8139CPLUS || 761 (hwrev == RL_HWREV_8169 && 762 t->rl_did == RT_DEVICEID_8169) || 763 hwrev == RL_HWREV_8169S || 764 hwrev == RL_HWREV_8110S) { 765 t++; 766 continue; 767 } 768 769 device_set_desc(dev, t->rl_name); 770 return (BUS_PROBE_DEFAULT); 771 } 772 t++; 773 } 774 775 return (ENXIO); 776 } 777 778 /* 779 * Attach the interface. Allocate softc structures, do ifmedia 780 * setup and ethernet/BPF attach. 781 */ 782 static int 783 rl_attach(device_t dev) 784 { 785 uint8_t eaddr[ETHER_ADDR_LEN]; 786 uint16_t as[3]; 787 struct ifnet *ifp; 788 struct rl_softc *sc; 789 struct rl_type *t; 790 int error = 0, i, rid; 791 int unit; 792 uint16_t rl_did = 0; 793 794 sc = device_get_softc(dev); 795 unit = device_get_unit(dev); 796 797 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 798 MTX_DEF); 799 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 800 801 pci_enable_busmaster(dev); 802 803 /* Map control/status registers. */ 804 rid = RL_RID; 805 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 806 807 if (sc->rl_res == NULL) { 808 device_printf(dev, "couldn't map ports/memory\n"); 809 error = ENXIO; 810 goto fail; 811 } 812 813 #ifdef notdef 814 /* 815 * Detect the Realtek 8139B. For some reason, this chip is very 816 * unstable when left to autoselect the media 817 * The best workaround is to set the device to the required 818 * media type or to set it to the 10 Meg speed. 819 */ 820 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF) 821 device_printf(dev, 822 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n"); 823 #endif 824 825 sc->rl_btag = rman_get_bustag(sc->rl_res); 826 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 827 828 /* Allocate interrupt */ 829 rid = 0; 830 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 831 RF_SHAREABLE | RF_ACTIVE); 832 833 if (sc->rl_irq == NULL) { 834 device_printf(dev, "couldn't map interrupt\n"); 835 error = ENXIO; 836 goto fail; 837 } 838 839 /* 840 * Reset the adapter. Only take the lock here as it's needed in 841 * order to call rl_reset(). 842 */ 843 RL_LOCK(sc); 844 rl_reset(sc); 845 RL_UNLOCK(sc); 846 847 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 848 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 849 if (rl_did != 0x8129) 850 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 851 852 /* 853 * Get station address from the EEPROM. 854 */ 855 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0); 856 for (i = 0; i < 3; i++) { 857 eaddr[(i * 2) + 0] = as[i] & 0xff; 858 eaddr[(i * 2) + 1] = as[i] >> 8; 859 } 860 861 /* 862 * Now read the exact device type from the EEPROM to find 863 * out if it's an 8129 or 8139. 864 */ 865 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0); 866 867 t = rl_devs; 868 sc->rl_type = 0; 869 while(t->rl_name != NULL) { 870 if (rl_did == t->rl_did) { 871 sc->rl_type = t->rl_basetype; 872 break; 873 } 874 t++; 875 } 876 877 if (sc->rl_type == 0) { 878 device_printf(dev, "unknown device ID: %x\n", rl_did); 879 error = ENXIO; 880 goto fail; 881 } 882 883 /* 884 * Allocate the parent bus DMA tag appropriate for PCI. 885 */ 886 #define RL_NSEG_NEW 32 887 error = bus_dma_tag_create(NULL, /* parent */ 888 1, 0, /* alignment, boundary */ 889 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 890 BUS_SPACE_MAXADDR, /* highaddr */ 891 NULL, NULL, /* filter, filterarg */ 892 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 893 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 894 BUS_DMA_ALLOCNOW, /* flags */ 895 NULL, NULL, /* lockfunc, lockarg */ 896 &sc->rl_parent_tag); 897 if (error) 898 goto fail; 899 900 /* 901 * Now allocate a tag for the DMA descriptor lists. 902 * All of our lists are allocated as a contiguous block 903 * of memory. 904 */ 905 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 906 1, 0, /* alignment, boundary */ 907 BUS_SPACE_MAXADDR, /* lowaddr */ 908 BUS_SPACE_MAXADDR, /* highaddr */ 909 NULL, NULL, /* filter, filterarg */ 910 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 911 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 912 BUS_DMA_ALLOCNOW, /* flags */ 913 NULL, NULL, /* lockfunc, lockarg */ 914 &sc->rl_tag); 915 if (error) 916 goto fail; 917 918 /* 919 * Now allocate a chunk of DMA-able memory based on the 920 * tag we just created. 921 */ 922 error = bus_dmamem_alloc(sc->rl_tag, 923 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 924 &sc->rl_cdata.rl_rx_dmamap); 925 if (error) { 926 device_printf(dev, "no memory for list buffers!\n"); 927 bus_dma_tag_destroy(sc->rl_tag); 928 sc->rl_tag = NULL; 929 goto fail; 930 } 931 932 /* Leave a few bytes before the start of the RX ring buffer. */ 933 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 934 sc->rl_cdata.rl_rx_buf += sizeof(uint64_t); 935 936 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 937 if (ifp == NULL) { 938 device_printf(dev, "can not if_alloc()\n"); 939 error = ENOSPC; 940 goto fail; 941 } 942 943 /* Do MII setup */ 944 if (mii_phy_probe(dev, &sc->rl_miibus, 945 rl_ifmedia_upd, rl_ifmedia_sts)) { 946 device_printf(dev, "MII without any phy!\n"); 947 error = ENXIO; 948 goto fail; 949 } 950 951 ifp->if_softc = sc; 952 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 953 ifp->if_mtu = ETHERMTU; 954 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 955 ifp->if_ioctl = rl_ioctl; 956 ifp->if_start = rl_start; 957 ifp->if_watchdog = rl_watchdog; 958 ifp->if_init = rl_init; 959 ifp->if_capabilities = IFCAP_VLAN_MTU; 960 ifp->if_capenable = ifp->if_capabilities; 961 #ifdef DEVICE_POLLING 962 ifp->if_capabilities |= IFCAP_POLLING; 963 #endif 964 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 965 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 966 IFQ_SET_READY(&ifp->if_snd); 967 968 /* 969 * Call MI attach routine. 970 */ 971 ether_ifattach(ifp, eaddr); 972 973 /* Hook interrupt last to avoid having to lock softc */ 974 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE, 975 rl_intr, sc, &sc->rl_intrhand); 976 if (error) { 977 if_printf(ifp, "couldn't set up irq\n"); 978 ether_ifdetach(ifp); 979 } 980 981 fail: 982 if (error) 983 rl_detach(dev); 984 985 return (error); 986 } 987 988 /* 989 * Shutdown hardware and free up resources. This can be called any 990 * time after the mutex has been initialized. It is called in both 991 * the error case in attach and the normal detach case so it needs 992 * to be careful about only freeing resources that have actually been 993 * allocated. 994 */ 995 static int 996 rl_detach(device_t dev) 997 { 998 struct rl_softc *sc; 999 struct ifnet *ifp; 1000 1001 sc = device_get_softc(dev); 1002 ifp = sc->rl_ifp; 1003 1004 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1005 #ifdef DEVICE_POLLING 1006 if (ifp->if_capenable & IFCAP_POLLING) 1007 ether_poll_deregister(ifp); 1008 #endif 1009 /* These should only be active if attach succeeded */ 1010 if (device_is_attached(dev)) { 1011 RL_LOCK(sc); 1012 rl_stop(sc); 1013 RL_UNLOCK(sc); 1014 callout_drain(&sc->rl_stat_callout); 1015 ether_ifdetach(ifp); 1016 } 1017 #if 0 1018 sc->suspended = 1; 1019 #endif 1020 if (ifp) 1021 if_free(ifp); 1022 if (sc->rl_miibus) 1023 device_delete_child(dev, sc->rl_miibus); 1024 bus_generic_detach(dev); 1025 1026 if (sc->rl_intrhand) 1027 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1028 if (sc->rl_irq) 1029 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1030 if (sc->rl_res) 1031 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1032 1033 if (sc->rl_tag) { 1034 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1035 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1036 sc->rl_cdata.rl_rx_dmamap); 1037 bus_dma_tag_destroy(sc->rl_tag); 1038 } 1039 if (sc->rl_parent_tag) 1040 bus_dma_tag_destroy(sc->rl_parent_tag); 1041 1042 mtx_destroy(&sc->rl_mtx); 1043 1044 return (0); 1045 } 1046 1047 /* 1048 * Initialize the transmit descriptors. 1049 */ 1050 static int 1051 rl_list_tx_init(struct rl_softc *sc) 1052 { 1053 struct rl_chain_data *cd; 1054 int i; 1055 1056 RL_LOCK_ASSERT(sc); 1057 1058 cd = &sc->rl_cdata; 1059 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1060 cd->rl_tx_chain[i] = NULL; 1061 CSR_WRITE_4(sc, 1062 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); 1063 } 1064 1065 sc->rl_cdata.cur_tx = 0; 1066 sc->rl_cdata.last_tx = 0; 1067 1068 return (0); 1069 } 1070 1071 /* 1072 * A frame has been uploaded: pass the resulting mbuf chain up to 1073 * the higher level protocols. 1074 * 1075 * You know there's something wrong with a PCI bus-master chip design 1076 * when you have to use m_devget(). 1077 * 1078 * The receive operation is badly documented in the datasheet, so I'll 1079 * attempt to document it here. The driver provides a buffer area and 1080 * places its base address in the RX buffer start address register. 1081 * The chip then begins copying frames into the RX buffer. Each frame 1082 * is preceded by a 32-bit RX status word which specifies the length 1083 * of the frame and certain other status bits. Each frame (starting with 1084 * the status word) is also 32-bit aligned. The frame length is in the 1085 * first 16 bits of the status word; the lower 15 bits correspond with 1086 * the 'rx status register' mentioned in the datasheet. 1087 * 1088 * Note: to make the Alpha happy, the frame payload needs to be aligned 1089 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1090 * as the offset argument to m_devget(). 1091 */ 1092 static void 1093 rl_rxeof(struct rl_softc *sc) 1094 { 1095 struct mbuf *m; 1096 struct ifnet *ifp = sc->rl_ifp; 1097 uint8_t *rxbufpos; 1098 int total_len = 0; 1099 int wrap = 0; 1100 uint32_t rxstat; 1101 uint16_t cur_rx; 1102 uint16_t limit; 1103 uint16_t max_bytes, rx_bytes = 0; 1104 1105 RL_LOCK_ASSERT(sc); 1106 1107 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1108 BUS_DMASYNC_POSTREAD); 1109 1110 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1111 1112 /* Do not try to read past this point. */ 1113 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1114 1115 if (limit < cur_rx) 1116 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1117 else 1118 max_bytes = limit - cur_rx; 1119 1120 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1121 #ifdef DEVICE_POLLING 1122 if (ifp->if_capenable & IFCAP_POLLING) { 1123 if (sc->rxcycles <= 0) 1124 break; 1125 sc->rxcycles--; 1126 } 1127 #endif 1128 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1129 rxstat = le32toh(*(uint32_t *)rxbufpos); 1130 1131 /* 1132 * Here's a totally undocumented fact for you. When the 1133 * RealTek chip is in the process of copying a packet into 1134 * RAM for you, the length will be 0xfff0. If you spot a 1135 * packet header with this value, you need to stop. The 1136 * datasheet makes absolutely no mention of this and 1137 * RealTek should be shot for this. 1138 */ 1139 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1140 break; 1141 1142 if (!(rxstat & RL_RXSTAT_RXOK)) { 1143 ifp->if_ierrors++; 1144 rl_init_locked(sc); 1145 return; 1146 } 1147 1148 /* No errors; receive the packet. */ 1149 total_len = rxstat >> 16; 1150 rx_bytes += total_len + 4; 1151 1152 /* 1153 * XXX The RealTek chip includes the CRC with every 1154 * received frame, and there's no way to turn this 1155 * behavior off (at least, I can't find anything in 1156 * the manual that explains how to do it) so we have 1157 * to trim off the CRC manually. 1158 */ 1159 total_len -= ETHER_CRC_LEN; 1160 1161 /* 1162 * Avoid trying to read more bytes than we know 1163 * the chip has prepared for us. 1164 */ 1165 if (rx_bytes > max_bytes) 1166 break; 1167 1168 rxbufpos = sc->rl_cdata.rl_rx_buf + 1169 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1170 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1171 rxbufpos = sc->rl_cdata.rl_rx_buf; 1172 1173 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1174 if (total_len > wrap) { 1175 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1176 NULL); 1177 if (m == NULL) { 1178 ifp->if_ierrors++; 1179 } else { 1180 m_copyback(m, wrap, total_len - wrap, 1181 sc->rl_cdata.rl_rx_buf); 1182 } 1183 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1184 } else { 1185 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1186 NULL); 1187 if (m == NULL) 1188 ifp->if_ierrors++; 1189 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1190 } 1191 1192 /* Round up to 32-bit boundary. */ 1193 cur_rx = (cur_rx + 3) & ~3; 1194 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1195 1196 if (m == NULL) 1197 continue; 1198 1199 ifp->if_ipackets++; 1200 RL_UNLOCK(sc); 1201 (*ifp->if_input)(ifp, m); 1202 RL_LOCK(sc); 1203 } 1204 } 1205 1206 /* 1207 * A frame was downloaded to the chip. It's safe for us to clean up 1208 * the list buffers. 1209 */ 1210 static void 1211 rl_txeof(struct rl_softc *sc) 1212 { 1213 struct ifnet *ifp = sc->rl_ifp; 1214 uint32_t txstat; 1215 1216 RL_LOCK_ASSERT(sc); 1217 1218 /* 1219 * Go through our tx list and free mbufs for those 1220 * frames that have been uploaded. 1221 */ 1222 do { 1223 if (RL_LAST_TXMBUF(sc) == NULL) 1224 break; 1225 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1226 if (!(txstat & (RL_TXSTAT_TX_OK| 1227 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1228 break; 1229 1230 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1231 1232 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1233 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1234 m_freem(RL_LAST_TXMBUF(sc)); 1235 RL_LAST_TXMBUF(sc) = NULL; 1236 /* 1237 * If there was a transmit underrun, bump the TX threshold. 1238 * Make sure not to overflow the 63 * 32byte we can address 1239 * with the 6 available bit. 1240 */ 1241 if ((txstat & RL_TXSTAT_TX_UNDERRUN) && 1242 (sc->rl_txthresh < 2016)) 1243 sc->rl_txthresh += 32; 1244 if (txstat & RL_TXSTAT_TX_OK) 1245 ifp->if_opackets++; 1246 else { 1247 int oldthresh; 1248 ifp->if_oerrors++; 1249 if ((txstat & RL_TXSTAT_TXABRT) || 1250 (txstat & RL_TXSTAT_OUTOFWIN)) 1251 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1252 oldthresh = sc->rl_txthresh; 1253 /* error recovery */ 1254 rl_reset(sc); 1255 rl_init_locked(sc); 1256 /* restore original threshold */ 1257 sc->rl_txthresh = oldthresh; 1258 return; 1259 } 1260 RL_INC(sc->rl_cdata.last_tx); 1261 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1262 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1263 1264 if (RL_LAST_TXMBUF(sc) == NULL) 1265 ifp->if_timer = 0; 1266 else if (ifp->if_timer == 0) 1267 ifp->if_timer = 5; 1268 } 1269 1270 static void 1271 rl_tick(void *xsc) 1272 { 1273 struct rl_softc *sc = xsc; 1274 struct mii_data *mii; 1275 1276 RL_LOCK_ASSERT(sc); 1277 mii = device_get_softc(sc->rl_miibus); 1278 mii_tick(mii); 1279 1280 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc); 1281 } 1282 1283 #ifdef DEVICE_POLLING 1284 static void 1285 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1286 { 1287 struct rl_softc *sc = ifp->if_softc; 1288 1289 RL_LOCK(sc); 1290 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1291 rl_poll_locked(ifp, cmd, count); 1292 RL_UNLOCK(sc); 1293 } 1294 1295 static void 1296 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1297 { 1298 struct rl_softc *sc = ifp->if_softc; 1299 1300 RL_LOCK_ASSERT(sc); 1301 1302 sc->rxcycles = count; 1303 rl_rxeof(sc); 1304 rl_txeof(sc); 1305 1306 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1307 rl_start_locked(ifp); 1308 1309 if (cmd == POLL_AND_CHECK_STATUS) { 1310 uint16_t status; 1311 1312 /* We should also check the status register. */ 1313 status = CSR_READ_2(sc, RL_ISR); 1314 if (status == 0xffff) 1315 return; 1316 if (status != 0) 1317 CSR_WRITE_2(sc, RL_ISR, status); 1318 1319 /* XXX We should check behaviour on receiver stalls. */ 1320 1321 if (status & RL_ISR_SYSTEM_ERR) { 1322 rl_reset(sc); 1323 rl_init_locked(sc); 1324 } 1325 } 1326 } 1327 #endif /* DEVICE_POLLING */ 1328 1329 static void 1330 rl_intr(void *arg) 1331 { 1332 struct rl_softc *sc = arg; 1333 struct ifnet *ifp = sc->rl_ifp; 1334 uint16_t status; 1335 1336 RL_LOCK(sc); 1337 1338 if (sc->suspended) 1339 goto done_locked; 1340 1341 #ifdef DEVICE_POLLING 1342 if (ifp->if_capenable & IFCAP_POLLING) 1343 goto done_locked; 1344 #endif 1345 1346 for (;;) { 1347 status = CSR_READ_2(sc, RL_ISR); 1348 /* If the card has gone away, the read returns 0xffff. */ 1349 if (status == 0xffff) 1350 break; 1351 if (status != 0) 1352 CSR_WRITE_2(sc, RL_ISR, status); 1353 if ((status & RL_INTRS) == 0) 1354 break; 1355 if (status & RL_ISR_RX_OK) 1356 rl_rxeof(sc); 1357 if (status & RL_ISR_RX_ERR) 1358 rl_rxeof(sc); 1359 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1360 rl_txeof(sc); 1361 if (status & RL_ISR_SYSTEM_ERR) { 1362 rl_reset(sc); 1363 rl_init_locked(sc); 1364 } 1365 } 1366 1367 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1368 rl_start_locked(ifp); 1369 1370 done_locked: 1371 RL_UNLOCK(sc); 1372 } 1373 1374 /* 1375 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1376 * pointers to the fragment pointers. 1377 */ 1378 static int 1379 rl_encap(struct rl_softc *sc, struct mbuf *m_head) 1380 { 1381 struct mbuf *m_new = NULL; 1382 1383 RL_LOCK_ASSERT(sc); 1384 1385 /* 1386 * The RealTek is brain damaged and wants longword-aligned 1387 * TX buffers, plus we can only have one fragment buffer 1388 * per packet. We have to copy pretty much all the time. 1389 */ 1390 m_new = m_defrag(m_head, M_DONTWAIT); 1391 1392 if (m_new == NULL) { 1393 m_freem(m_head); 1394 return (1); 1395 } 1396 m_head = m_new; 1397 1398 /* Pad frames to at least 60 bytes. */ 1399 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1400 /* 1401 * Make security concious people happy: zero out the 1402 * bytes in the pad area, since we don't know what 1403 * this mbuf cluster buffer's previous user might 1404 * have left in it. 1405 */ 1406 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1407 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1408 m_head->m_pkthdr.len += 1409 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1410 m_head->m_len = m_head->m_pkthdr.len; 1411 } 1412 1413 RL_CUR_TXMBUF(sc) = m_head; 1414 1415 return (0); 1416 } 1417 1418 /* 1419 * Main transmit routine. 1420 */ 1421 static void 1422 rl_start(struct ifnet *ifp) 1423 { 1424 struct rl_softc *sc = ifp->if_softc; 1425 1426 RL_LOCK(sc); 1427 rl_start_locked(ifp); 1428 RL_UNLOCK(sc); 1429 } 1430 1431 static void 1432 rl_start_locked(struct ifnet *ifp) 1433 { 1434 struct rl_softc *sc = ifp->if_softc; 1435 struct mbuf *m_head = NULL; 1436 1437 RL_LOCK_ASSERT(sc); 1438 1439 while (RL_CUR_TXMBUF(sc) == NULL) { 1440 1441 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1442 1443 if (m_head == NULL) 1444 break; 1445 1446 if (rl_encap(sc, m_head)) 1447 break; 1448 1449 /* Pass a copy of this mbuf chain to the bpf subsystem. */ 1450 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1451 1452 /* Transmit the frame. */ 1453 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1454 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1455 mtod(RL_CUR_TXMBUF(sc), void *), 1456 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1457 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1458 BUS_DMASYNC_PREREAD); 1459 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1460 RL_TXTHRESH(sc->rl_txthresh) | 1461 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1462 1463 RL_INC(sc->rl_cdata.cur_tx); 1464 1465 /* Set a timeout in case the chip goes out to lunch. */ 1466 ifp->if_timer = 5; 1467 } 1468 1469 /* 1470 * We broke out of the loop because all our TX slots are 1471 * full. Mark the NIC as busy until it drains some of the 1472 * packets from the queue. 1473 */ 1474 if (RL_CUR_TXMBUF(sc) != NULL) 1475 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1476 } 1477 1478 static void 1479 rl_init(void *xsc) 1480 { 1481 struct rl_softc *sc = xsc; 1482 1483 RL_LOCK(sc); 1484 rl_init_locked(sc); 1485 RL_UNLOCK(sc); 1486 } 1487 1488 static void 1489 rl_init_locked(struct rl_softc *sc) 1490 { 1491 struct ifnet *ifp = sc->rl_ifp; 1492 struct mii_data *mii; 1493 uint32_t rxcfg = 0; 1494 1495 RL_LOCK_ASSERT(sc); 1496 1497 mii = device_get_softc(sc->rl_miibus); 1498 1499 /* 1500 * Cancel pending I/O and free all RX/TX buffers. 1501 */ 1502 rl_stop(sc); 1503 1504 /* 1505 * Init our MAC address. Even though the chipset 1506 * documentation doesn't mention it, we need to enter "Config 1507 * register write enable" mode to modify the ID registers. 1508 */ 1509 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1510 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1511 *(uint32_t *)(&IFP2ENADDR(sc->rl_ifp)[0])); 1512 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1513 *(uint32_t *)(&IFP2ENADDR(sc->rl_ifp)[4])); 1514 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1515 1516 /* Init the RX buffer pointer register. */ 1517 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1518 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1519 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1520 BUS_DMASYNC_PREWRITE); 1521 1522 /* Init TX descriptors. */ 1523 rl_list_tx_init(sc); 1524 1525 /* 1526 * Enable transmit and receive. 1527 */ 1528 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1529 1530 /* 1531 * Set the initial TX and RX configuration. 1532 */ 1533 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1534 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1535 1536 /* Set the individual bit to receive frames for this host only. */ 1537 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1538 rxcfg |= RL_RXCFG_RX_INDIV; 1539 1540 /* If we want promiscuous mode, set the allframes bit. */ 1541 if (ifp->if_flags & IFF_PROMISC) { 1542 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1543 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1544 } else { 1545 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1546 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1547 } 1548 1549 /* Set capture broadcast bit to capture broadcast frames. */ 1550 if (ifp->if_flags & IFF_BROADCAST) { 1551 rxcfg |= RL_RXCFG_RX_BROAD; 1552 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1553 } else { 1554 rxcfg &= ~RL_RXCFG_RX_BROAD; 1555 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1556 } 1557 1558 /* Program the multicast filter, if necessary. */ 1559 rl_setmulti(sc); 1560 1561 #ifdef DEVICE_POLLING 1562 /* Disable interrupts if we are polling. */ 1563 if (ifp->if_capenable & IFCAP_POLLING) 1564 CSR_WRITE_2(sc, RL_IMR, 0); 1565 else 1566 #endif 1567 /* Enable interrupts. */ 1568 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1569 1570 /* Set initial TX threshold */ 1571 sc->rl_txthresh = RL_TX_THRESH_INIT; 1572 1573 /* Start RX/TX process. */ 1574 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1575 1576 /* Enable receiver and transmitter. */ 1577 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1578 1579 mii_mediachg(mii); 1580 1581 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1582 1583 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1584 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1585 1586 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc); 1587 } 1588 1589 /* 1590 * Set media options. 1591 */ 1592 static int 1593 rl_ifmedia_upd(struct ifnet *ifp) 1594 { 1595 struct rl_softc *sc = ifp->if_softc; 1596 struct mii_data *mii; 1597 1598 mii = device_get_softc(sc->rl_miibus); 1599 1600 RL_LOCK(sc); 1601 mii_mediachg(mii); 1602 RL_UNLOCK(sc); 1603 1604 return (0); 1605 } 1606 1607 /* 1608 * Report current media status. 1609 */ 1610 static void 1611 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1612 { 1613 struct rl_softc *sc = ifp->if_softc; 1614 struct mii_data *mii; 1615 1616 mii = device_get_softc(sc->rl_miibus); 1617 1618 RL_LOCK(sc); 1619 mii_pollstat(mii); 1620 RL_UNLOCK(sc); 1621 ifmr->ifm_active = mii->mii_media_active; 1622 ifmr->ifm_status = mii->mii_media_status; 1623 } 1624 1625 static int 1626 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1627 { 1628 struct ifreq *ifr = (struct ifreq *)data; 1629 struct mii_data *mii; 1630 struct rl_softc *sc = ifp->if_softc; 1631 int error = 0; 1632 1633 switch (command) { 1634 case SIOCSIFFLAGS: 1635 RL_LOCK(sc); 1636 if (ifp->if_flags & IFF_UP) { 1637 rl_init_locked(sc); 1638 } else { 1639 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1640 rl_stop(sc); 1641 } 1642 RL_UNLOCK(sc); 1643 error = 0; 1644 break; 1645 case SIOCADDMULTI: 1646 case SIOCDELMULTI: 1647 RL_LOCK(sc); 1648 rl_setmulti(sc); 1649 RL_UNLOCK(sc); 1650 error = 0; 1651 break; 1652 case SIOCGIFMEDIA: 1653 case SIOCSIFMEDIA: 1654 mii = device_get_softc(sc->rl_miibus); 1655 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1656 break; 1657 case SIOCSIFCAP: 1658 #ifdef DEVICE_POLLING 1659 if (ifr->ifr_reqcap & IFCAP_POLLING && 1660 !(ifp->if_capenable & IFCAP_POLLING)) { 1661 error = ether_poll_register(rl_poll, ifp); 1662 if (error) 1663 return(error); 1664 RL_LOCK(sc); 1665 /* Disable interrupts */ 1666 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1667 ifp->if_capenable |= IFCAP_POLLING; 1668 RL_UNLOCK(sc); 1669 return (error); 1670 1671 } 1672 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1673 ifp->if_capenable & IFCAP_POLLING) { 1674 error = ether_poll_deregister(ifp); 1675 /* Enable interrupts. */ 1676 RL_LOCK(sc); 1677 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1678 ifp->if_capenable &= ~IFCAP_POLLING; 1679 RL_UNLOCK(sc); 1680 return (error); 1681 } 1682 #endif /* DEVICE_POLLING */ 1683 break; 1684 default: 1685 error = ether_ioctl(ifp, command, data); 1686 break; 1687 } 1688 1689 return (error); 1690 } 1691 1692 static void 1693 rl_watchdog(struct ifnet *ifp) 1694 { 1695 struct rl_softc *sc = ifp->if_softc; 1696 1697 RL_LOCK(sc); 1698 1699 if_printf(ifp, "watchdog timeout\n"); 1700 ifp->if_oerrors++; 1701 1702 rl_txeof(sc); 1703 rl_rxeof(sc); 1704 rl_init_locked(sc); 1705 1706 RL_UNLOCK(sc); 1707 } 1708 1709 /* 1710 * Stop the adapter and free any mbufs allocated to the 1711 * RX and TX lists. 1712 */ 1713 static void 1714 rl_stop(struct rl_softc *sc) 1715 { 1716 register int i; 1717 struct ifnet *ifp = sc->rl_ifp; 1718 1719 RL_LOCK_ASSERT(sc); 1720 1721 ifp->if_timer = 0; 1722 callout_stop(&sc->rl_stat_callout); 1723 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1724 1725 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1726 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1727 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1728 1729 /* 1730 * Free the TX list buffers. 1731 */ 1732 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1733 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1734 bus_dmamap_unload(sc->rl_tag, 1735 sc->rl_cdata.rl_tx_dmamap[i]); 1736 bus_dmamap_destroy(sc->rl_tag, 1737 sc->rl_cdata.rl_tx_dmamap[i]); 1738 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1739 sc->rl_cdata.rl_tx_chain[i] = NULL; 1740 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1741 0x0000000); 1742 } 1743 } 1744 } 1745 1746 /* 1747 * Device suspend routine. Stop the interface and save some PCI 1748 * settings in case the BIOS doesn't restore them properly on 1749 * resume. 1750 */ 1751 static int 1752 rl_suspend(device_t dev) 1753 { 1754 struct rl_softc *sc; 1755 1756 sc = device_get_softc(dev); 1757 1758 RL_LOCK(sc); 1759 rl_stop(sc); 1760 sc->suspended = 1; 1761 RL_UNLOCK(sc); 1762 1763 return (0); 1764 } 1765 1766 /* 1767 * Device resume routine. Restore some PCI settings in case the BIOS 1768 * doesn't, re-enable busmastering, and restart the interface if 1769 * appropriate. 1770 */ 1771 static int 1772 rl_resume(device_t dev) 1773 { 1774 struct rl_softc *sc; 1775 struct ifnet *ifp; 1776 1777 sc = device_get_softc(dev); 1778 ifp = sc->rl_ifp; 1779 1780 RL_LOCK(sc); 1781 1782 /* reinitialize interface if necessary */ 1783 if (ifp->if_flags & IFF_UP) 1784 rl_init_locked(sc); 1785 1786 sc->suspended = 0; 1787 1788 RL_UNLOCK(sc); 1789 1790 return (0); 1791 } 1792 1793 /* 1794 * Stop all chip I/O so that the kernel's probe routines don't 1795 * get confused by errant DMAs when rebooting. 1796 */ 1797 static void 1798 rl_shutdown(device_t dev) 1799 { 1800 struct rl_softc *sc; 1801 1802 sc = device_get_softc(dev); 1803 1804 RL_LOCK(sc); 1805 rl_stop(sc); 1806 RL_UNLOCK(sc); 1807 }
Cache object: 5db493a0a03863af88cb60bca22d3908
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