The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pci/if_rl.c

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    1 /*-
    2  * Copyright (c) 1997, 1998
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD: releng/6.2/sys/pci/if_rl.c 163292 2006-10-13 07:39:25Z glebius $");
   35 
   36 /*
   37  * RealTek 8129/8139 PCI NIC driver
   38  *
   39  * Supports several extremely cheap PCI 10/100 adapters based on
   40  * the RealTek chipset. Datasheets can be obtained from
   41  * www.realtek.com.tw.
   42  *
   43  * Written by Bill Paul <wpaul@ctr.columbia.edu>
   44  * Electrical Engineering Department
   45  * Columbia University, New York City
   46  */
   47 /*
   48  * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
   49  * probably the worst PCI ethernet controller ever made, with the possible
   50  * exception of the FEAST chip made by SMC. The 8139 supports bus-master
   51  * DMA, but it has a terrible interface that nullifies any performance
   52  * gains that bus-master DMA usually offers.
   53  *
   54  * For transmission, the chip offers a series of four TX descriptor
   55  * registers. Each transmit frame must be in a contiguous buffer, aligned
   56  * on a longword (32-bit) boundary. This means we almost always have to
   57  * do mbuf copies in order to transmit a frame, except in the unlikely
   58  * case where a) the packet fits into a single mbuf, and b) the packet
   59  * is 32-bit aligned within the mbuf's data area. The presence of only
   60  * four descriptor registers means that we can never have more than four
   61  * packets queued for transmission at any one time.
   62  *
   63  * Reception is not much better. The driver has to allocate a single large
   64  * buffer area (up to 64K in size) into which the chip will DMA received
   65  * frames. Because we don't know where within this region received packets
   66  * will begin or end, we have no choice but to copy data from the buffer
   67  * area into mbufs in order to pass the packets up to the higher protocol
   68  * levels.
   69  *
   70  * It's impossible given this rotten design to really achieve decent
   71  * performance at 100Mbps, unless you happen to have a 400Mhz PII or
   72  * some equally overmuscled CPU to drive it.
   73  *
   74  * On the bright side, the 8139 does have a built-in PHY, although
   75  * rather than using an MDIO serial interface like most other NICs, the
   76  * PHY registers are directly accessible through the 8139's register
   77  * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
   78  * filter.
   79  *
   80  * The 8129 chip is an older version of the 8139 that uses an external PHY
   81  * chip. The 8129 has a serial MDIO interface for accessing the MII where
   82  * the 8139 lets you directly access the on-board PHY registers. We need
   83  * to select which interface to use depending on the chip type.
   84  */
   85 
   86 #ifdef HAVE_KERNEL_OPTION_HEADERS
   87 #include "opt_device_polling.h"
   88 #endif
   89 
   90 #include <sys/param.h>
   91 #include <sys/endian.h>
   92 #include <sys/systm.h>
   93 #include <sys/sockio.h>
   94 #include <sys/mbuf.h>
   95 #include <sys/malloc.h>
   96 #include <sys/kernel.h>
   97 #include <sys/module.h>
   98 #include <sys/socket.h>
   99 
  100 #include <net/if.h>
  101 #include <net/if_arp.h>
  102 #include <net/ethernet.h>
  103 #include <net/if_dl.h>
  104 #include <net/if_media.h>
  105 #include <net/if_types.h>
  106 
  107 #include <net/bpf.h>
  108 
  109 #include <machine/bus.h>
  110 #include <machine/resource.h>
  111 #include <sys/bus.h>
  112 #include <sys/rman.h>
  113 
  114 #include <dev/mii/mii.h>
  115 #include <dev/mii/miivar.h>
  116 
  117 #include <dev/pci/pcireg.h>
  118 #include <dev/pci/pcivar.h>
  119 
  120 MODULE_DEPEND(rl, pci, 1, 1, 1);
  121 MODULE_DEPEND(rl, ether, 1, 1, 1);
  122 MODULE_DEPEND(rl, miibus, 1, 1, 1);
  123 
  124 /* "controller miibus0" required.  See GENERIC if you get errors here. */
  125 #include "miibus_if.h"
  126 
  127 /*
  128  * Default to using PIO access for this driver. On SMP systems,
  129  * there appear to be problems with memory mapped mode: it looks like
  130  * doing too many memory mapped access back to back in rapid succession
  131  * can hang the bus. I'm inclined to blame this on crummy design/construction
  132  * on the part of RealTek. Memory mapped mode does appear to work on
  133  * uniprocessor systems though.
  134  */
  135 #define RL_USEIOSPACE
  136 
  137 #include <pci/if_rlreg.h>
  138 
  139 /*
  140  * Various supported device vendors/types and their names.
  141  */
  142 static struct rl_type rl_devs[] = {
  143         { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
  144                 "RealTek 8129 10/100BaseTX" },
  145         { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
  146                 "RealTek 8139 10/100BaseTX" },
  147         { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
  148                 "RealTek 8139 10/100BaseTX CardBus" },
  149         { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
  150                 "RealTek 8100 10/100BaseTX" },
  151         { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
  152                 "Accton MPX 5030/5038 10/100BaseTX" },
  153         { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
  154                 "Delta Electronics 8139 10/100BaseTX" },
  155         { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
  156                 "Addtron Technolgy 8139 10/100BaseTX" },
  157         { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
  158                 "D-Link DFE-530TX+ 10/100BaseTX" },
  159         { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
  160                 "D-Link DFE-690TXD 10/100BaseTX" },
  161         { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
  162                 "Nortel Networks 10/100BaseTX" },
  163         { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
  164                 "Corega FEther CB-TXD" },
  165         { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
  166                 "Corega FEtherII CB-TXD" },
  167         { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
  168                 "Peppercon AG ROL-F" },
  169         { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
  170                 "Planex FNW-3800-TX" },
  171         { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
  172                 "Compaq HNE-300" },
  173         { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
  174                 "LevelOne FPC-0106TX" },
  175         { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
  176                 "Edimax EP-4103DL CardBus" },
  177         { 0, 0, 0, NULL }
  178 };
  179 
  180 static int rl_attach(device_t);
  181 static int rl_detach(device_t);
  182 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
  183 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
  184 static void rl_eeprom_putbyte(struct rl_softc *, int);
  185 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
  186 static int rl_encap(struct rl_softc *, struct mbuf * );
  187 static int rl_list_tx_init(struct rl_softc *);
  188 static int rl_ifmedia_upd(struct ifnet *);
  189 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  190 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
  191 static void rl_intr(void *);
  192 static void rl_init(void *);
  193 static void rl_init_locked(struct rl_softc *sc);
  194 static void rl_mii_send(struct rl_softc *, uint32_t, int);
  195 static void rl_mii_sync(struct rl_softc *);
  196 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
  197 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
  198 static int rl_miibus_readreg(device_t, int, int);
  199 static void rl_miibus_statchg(device_t);
  200 static int rl_miibus_writereg(device_t, int, int, int);
  201 #ifdef DEVICE_POLLING
  202 static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
  203 static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
  204 #endif
  205 static int rl_probe(device_t);
  206 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
  207 static void rl_reset(struct rl_softc *);
  208 static int rl_resume(device_t);
  209 static void rl_rxeof(struct rl_softc *);
  210 static void rl_setmulti(struct rl_softc *);
  211 static void rl_shutdown(device_t);
  212 static void rl_start(struct ifnet *);
  213 static void rl_start_locked(struct ifnet *);
  214 static void rl_stop(struct rl_softc *);
  215 static int rl_suspend(device_t);
  216 static void rl_tick(void *);
  217 static void rl_txeof(struct rl_softc *);
  218 static void rl_watchdog(struct ifnet *);
  219 
  220 #ifdef RL_USEIOSPACE
  221 #define RL_RES                  SYS_RES_IOPORT
  222 #define RL_RID                  RL_PCI_LOIO
  223 #else
  224 #define RL_RES                  SYS_RES_MEMORY
  225 #define RL_RID                  RL_PCI_LOMEM
  226 #endif
  227 
  228 static device_method_t rl_methods[] = {
  229         /* Device interface */
  230         DEVMETHOD(device_probe,         rl_probe),
  231         DEVMETHOD(device_attach,        rl_attach),
  232         DEVMETHOD(device_detach,        rl_detach),
  233         DEVMETHOD(device_suspend,       rl_suspend),
  234         DEVMETHOD(device_resume,        rl_resume),
  235         DEVMETHOD(device_shutdown,      rl_shutdown),
  236 
  237         /* bus interface */
  238         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  239         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
  240 
  241         /* MII interface */
  242         DEVMETHOD(miibus_readreg,       rl_miibus_readreg),
  243         DEVMETHOD(miibus_writereg,      rl_miibus_writereg),
  244         DEVMETHOD(miibus_statchg,       rl_miibus_statchg),
  245 
  246         { 0, 0 }
  247 };
  248 
  249 static driver_t rl_driver = {
  250         "rl",
  251         rl_methods,
  252         sizeof(struct rl_softc)
  253 };
  254 
  255 static devclass_t rl_devclass;
  256 
  257 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
  258 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
  259 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
  260 
  261 #define EE_SET(x)                                       \
  262         CSR_WRITE_1(sc, RL_EECMD,                       \
  263                 CSR_READ_1(sc, RL_EECMD) | x)
  264 
  265 #define EE_CLR(x)                                       \
  266         CSR_WRITE_1(sc, RL_EECMD,                       \
  267                 CSR_READ_1(sc, RL_EECMD) & ~x)
  268 
  269 static void
  270 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
  271 {
  272         struct rl_softc *sc = arg;
  273 
  274         CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
  275 }
  276 
  277 static void
  278 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
  279 {
  280         struct rl_softc *sc = arg;
  281 
  282         CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
  283 }
  284 
  285 /*
  286  * Send a read command and address to the EEPROM, check for ACK.
  287  */
  288 static void
  289 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
  290 {
  291         register int            d, i;
  292 
  293         d = addr | sc->rl_eecmd_read;
  294 
  295         /*
  296          * Feed in each bit and strobe the clock.
  297          */
  298         for (i = 0x400; i; i >>= 1) {
  299                 if (d & i) {
  300                         EE_SET(RL_EE_DATAIN);
  301                 } else {
  302                         EE_CLR(RL_EE_DATAIN);
  303                 }
  304                 DELAY(100);
  305                 EE_SET(RL_EE_CLK);
  306                 DELAY(150);
  307                 EE_CLR(RL_EE_CLK);
  308                 DELAY(100);
  309         }
  310 }
  311 
  312 /*
  313  * Read a word of data stored in the EEPROM at address 'addr.'
  314  */
  315 static void
  316 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
  317 {
  318         register int            i;
  319         uint16_t                word = 0;
  320 
  321         /* Enter EEPROM access mode. */
  322         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
  323 
  324         /*
  325          * Send address of word we want to read.
  326          */
  327         rl_eeprom_putbyte(sc, addr);
  328 
  329         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
  330 
  331         /*
  332          * Start reading bits from EEPROM.
  333          */
  334         for (i = 0x8000; i; i >>= 1) {
  335                 EE_SET(RL_EE_CLK);
  336                 DELAY(100);
  337                 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
  338                         word |= i;
  339                 EE_CLR(RL_EE_CLK);
  340                 DELAY(100);
  341         }
  342 
  343         /* Turn off EEPROM access mode. */
  344         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
  345 
  346         *dest = word;
  347 }
  348 
  349 /*
  350  * Read a sequence of words from the EEPROM.
  351  */
  352 static void
  353 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
  354 {
  355         int                     i;
  356         uint16_t                word = 0, *ptr;
  357 
  358         for (i = 0; i < cnt; i++) {
  359                 rl_eeprom_getword(sc, off + i, &word);
  360                 ptr = (uint16_t *)(dest + (i * 2));
  361                 if (swap)
  362                         *ptr = ntohs(word);
  363                 else
  364                         *ptr = word;
  365         }
  366 }
  367 
  368 /*
  369  * MII access routines are provided for the 8129, which
  370  * doesn't have a built-in PHY. For the 8139, we fake things
  371  * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
  372  * direct access PHY registers.
  373  */
  374 #define MII_SET(x)                                      \
  375         CSR_WRITE_1(sc, RL_MII,                         \
  376                 CSR_READ_1(sc, RL_MII) | (x))
  377 
  378 #define MII_CLR(x)                                      \
  379         CSR_WRITE_1(sc, RL_MII,                         \
  380                 CSR_READ_1(sc, RL_MII) & ~(x))
  381 
  382 /*
  383  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  384  */
  385 static void
  386 rl_mii_sync(struct rl_softc *sc)
  387 {
  388         register int            i;
  389 
  390         MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
  391 
  392         for (i = 0; i < 32; i++) {
  393                 MII_SET(RL_MII_CLK);
  394                 DELAY(1);
  395                 MII_CLR(RL_MII_CLK);
  396                 DELAY(1);
  397         }
  398 }
  399 
  400 /*
  401  * Clock a series of bits through the MII.
  402  */
  403 static void
  404 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
  405 {
  406         int                     i;
  407 
  408         MII_CLR(RL_MII_CLK);
  409 
  410         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  411                 if (bits & i) {
  412                         MII_SET(RL_MII_DATAOUT);
  413                 } else {
  414                         MII_CLR(RL_MII_DATAOUT);
  415                 }
  416                 DELAY(1);
  417                 MII_CLR(RL_MII_CLK);
  418                 DELAY(1);
  419                 MII_SET(RL_MII_CLK);
  420         }
  421 }
  422 
  423 /*
  424  * Read an PHY register through the MII.
  425  */
  426 static int
  427 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
  428 {
  429         int                     i, ack;
  430 
  431         /* Set up frame for RX. */
  432         frame->mii_stdelim = RL_MII_STARTDELIM;
  433         frame->mii_opcode = RL_MII_READOP;
  434         frame->mii_turnaround = 0;
  435         frame->mii_data = 0;
  436 
  437         CSR_WRITE_2(sc, RL_MII, 0);
  438 
  439         /* Turn on data xmit. */
  440         MII_SET(RL_MII_DIR);
  441 
  442         rl_mii_sync(sc);
  443 
  444         /* Send command/address info. */
  445         rl_mii_send(sc, frame->mii_stdelim, 2);
  446         rl_mii_send(sc, frame->mii_opcode, 2);
  447         rl_mii_send(sc, frame->mii_phyaddr, 5);
  448         rl_mii_send(sc, frame->mii_regaddr, 5);
  449 
  450         /* Idle bit */
  451         MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
  452         DELAY(1);
  453         MII_SET(RL_MII_CLK);
  454         DELAY(1);
  455 
  456         /* Turn off xmit. */
  457         MII_CLR(RL_MII_DIR);
  458 
  459         /* Check for ack */
  460         MII_CLR(RL_MII_CLK);
  461         DELAY(1);
  462         ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
  463         MII_SET(RL_MII_CLK);
  464         DELAY(1);
  465 
  466         /*
  467          * Now try reading data bits. If the ack failed, we still
  468          * need to clock through 16 cycles to keep the PHY(s) in sync.
  469          */
  470         if (ack) {
  471                 for(i = 0; i < 16; i++) {
  472                         MII_CLR(RL_MII_CLK);
  473                         DELAY(1);
  474                         MII_SET(RL_MII_CLK);
  475                         DELAY(1);
  476                 }
  477                 goto fail;
  478         }
  479 
  480         for (i = 0x8000; i; i >>= 1) {
  481                 MII_CLR(RL_MII_CLK);
  482                 DELAY(1);
  483                 if (!ack) {
  484                         if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
  485                                 frame->mii_data |= i;
  486                         DELAY(1);
  487                 }
  488                 MII_SET(RL_MII_CLK);
  489                 DELAY(1);
  490         }
  491 
  492 fail:
  493         MII_CLR(RL_MII_CLK);
  494         DELAY(1);
  495         MII_SET(RL_MII_CLK);
  496         DELAY(1);
  497 
  498         return (ack ? 1 : 0);
  499 }
  500 
  501 /*
  502  * Write to a PHY register through the MII.
  503  */
  504 static int
  505 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
  506 {
  507 
  508         /* Set up frame for TX. */
  509         frame->mii_stdelim = RL_MII_STARTDELIM;
  510         frame->mii_opcode = RL_MII_WRITEOP;
  511         frame->mii_turnaround = RL_MII_TURNAROUND;
  512 
  513         /* Turn on data output. */
  514         MII_SET(RL_MII_DIR);
  515 
  516         rl_mii_sync(sc);
  517 
  518         rl_mii_send(sc, frame->mii_stdelim, 2);
  519         rl_mii_send(sc, frame->mii_opcode, 2);
  520         rl_mii_send(sc, frame->mii_phyaddr, 5);
  521         rl_mii_send(sc, frame->mii_regaddr, 5);
  522         rl_mii_send(sc, frame->mii_turnaround, 2);
  523         rl_mii_send(sc, frame->mii_data, 16);
  524 
  525         /* Idle bit. */
  526         MII_SET(RL_MII_CLK);
  527         DELAY(1);
  528         MII_CLR(RL_MII_CLK);
  529         DELAY(1);
  530 
  531         /* Turn off xmit. */
  532         MII_CLR(RL_MII_DIR);
  533 
  534         return (0);
  535 }
  536 
  537 static int
  538 rl_miibus_readreg(device_t dev, int phy, int reg)
  539 {
  540         struct rl_softc         *sc;
  541         struct rl_mii_frame     frame;
  542         uint16_t                rval = 0;
  543         uint16_t                rl8139_reg = 0;
  544 
  545         sc = device_get_softc(dev);
  546 
  547         if (sc->rl_type == RL_8139) {
  548                 /* Pretend the internal PHY is only at address 0 */
  549                 if (phy) {
  550                         return (0);
  551                 }
  552                 switch (reg) {
  553                 case MII_BMCR:
  554                         rl8139_reg = RL_BMCR;
  555                         break;
  556                 case MII_BMSR:
  557                         rl8139_reg = RL_BMSR;
  558                         break;
  559                 case MII_ANAR:
  560                         rl8139_reg = RL_ANAR;
  561                         break;
  562                 case MII_ANER:
  563                         rl8139_reg = RL_ANER;
  564                         break;
  565                 case MII_ANLPAR:
  566                         rl8139_reg = RL_LPAR;
  567                         break;
  568                 case MII_PHYIDR1:
  569                 case MII_PHYIDR2:
  570                         return (0);
  571                 /*
  572                  * Allow the rlphy driver to read the media status
  573                  * register. If we have a link partner which does not
  574                  * support NWAY, this is the register which will tell
  575                  * us the results of parallel detection.
  576                  */
  577                 case RL_MEDIASTAT:
  578                         rval = CSR_READ_1(sc, RL_MEDIASTAT);
  579                         return (rval);
  580                 default:
  581                         device_printf(sc->rl_dev, "bad phy register\n");
  582                         return (0);
  583                 }
  584                 rval = CSR_READ_2(sc, rl8139_reg);
  585                 return (rval);
  586         }
  587 
  588         bzero((char *)&frame, sizeof(frame));
  589         frame.mii_phyaddr = phy;
  590         frame.mii_regaddr = reg;
  591         rl_mii_readreg(sc, &frame);
  592 
  593         return (frame.mii_data);
  594 }
  595 
  596 static int
  597 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
  598 {
  599         struct rl_softc         *sc;
  600         struct rl_mii_frame     frame;
  601         uint16_t                rl8139_reg = 0;
  602 
  603         sc = device_get_softc(dev);
  604 
  605         if (sc->rl_type == RL_8139) {
  606                 /* Pretend the internal PHY is only at address 0 */
  607                 if (phy) {
  608                         return (0);
  609                 }
  610                 switch (reg) {
  611                 case MII_BMCR:
  612                         rl8139_reg = RL_BMCR;
  613                         break;
  614                 case MII_BMSR:
  615                         rl8139_reg = RL_BMSR;
  616                         break;
  617                 case MII_ANAR:
  618                         rl8139_reg = RL_ANAR;
  619                         break;
  620                 case MII_ANER:
  621                         rl8139_reg = RL_ANER;
  622                         break;
  623                 case MII_ANLPAR:
  624                         rl8139_reg = RL_LPAR;
  625                         break;
  626                 case MII_PHYIDR1:
  627                 case MII_PHYIDR2:
  628                         return (0);
  629                         break;
  630                 default:
  631                         device_printf(sc->rl_dev, "bad phy register\n");
  632                         return (0);
  633                 }
  634                 CSR_WRITE_2(sc, rl8139_reg, data);
  635                 return (0);
  636         }
  637 
  638         bzero((char *)&frame, sizeof(frame));
  639         frame.mii_phyaddr = phy;
  640         frame.mii_regaddr = reg;
  641         frame.mii_data = data;
  642         rl_mii_writereg(sc, &frame);
  643 
  644         return (0);
  645 }
  646 
  647 static void
  648 rl_miibus_statchg(device_t dev)
  649 {
  650 }
  651 
  652 /*
  653  * Program the 64-bit multicast hash filter.
  654  */
  655 static void
  656 rl_setmulti(struct rl_softc *sc)
  657 {
  658         struct ifnet            *ifp = sc->rl_ifp;
  659         int                     h = 0;
  660         uint32_t                hashes[2] = { 0, 0 };
  661         struct ifmultiaddr      *ifma;
  662         uint32_t                rxfilt;
  663         int                     mcnt = 0;
  664 
  665         RL_LOCK_ASSERT(sc);
  666 
  667         rxfilt = CSR_READ_4(sc, RL_RXCFG);
  668 
  669         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
  670                 rxfilt |= RL_RXCFG_RX_MULTI;
  671                 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
  672                 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
  673                 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
  674                 return;
  675         }
  676 
  677         /* first, zot all the existing hash bits */
  678         CSR_WRITE_4(sc, RL_MAR0, 0);
  679         CSR_WRITE_4(sc, RL_MAR4, 0);
  680 
  681         /* now program new ones */
  682         IF_ADDR_LOCK(ifp);
  683         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
  684                 if (ifma->ifma_addr->sa_family != AF_LINK)
  685                         continue;
  686                 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
  687                     ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
  688                 if (h < 32)
  689                         hashes[0] |= (1 << h);
  690                 else
  691                         hashes[1] |= (1 << (h - 32));
  692                 mcnt++;
  693         }
  694         IF_ADDR_UNLOCK(ifp);
  695 
  696         if (mcnt)
  697                 rxfilt |= RL_RXCFG_RX_MULTI;
  698         else
  699                 rxfilt &= ~RL_RXCFG_RX_MULTI;
  700 
  701         CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
  702         CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
  703         CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
  704 }
  705 
  706 static void
  707 rl_reset(struct rl_softc *sc)
  708 {
  709         register int            i;
  710 
  711         RL_LOCK_ASSERT(sc);
  712 
  713         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
  714 
  715         for (i = 0; i < RL_TIMEOUT; i++) {
  716                 DELAY(10);
  717                 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
  718                         break;
  719         }
  720         if (i == RL_TIMEOUT)
  721                 device_printf(sc->rl_dev, "reset never completed!\n");
  722 }
  723 
  724 /*
  725  * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
  726  * IDs against our list and return a device name if we find a match.
  727  */
  728 static int
  729 rl_probe(device_t dev)
  730 {
  731         struct rl_softc         *sc;
  732         struct rl_type          *t = rl_devs;
  733         int                     rid;
  734         uint32_t                hwrev;
  735 
  736         sc = device_get_softc(dev);
  737 
  738         while (t->rl_name != NULL) {
  739                 if ((pci_get_vendor(dev) == t->rl_vid) &&
  740                     (pci_get_device(dev) == t->rl_did)) {
  741                         /*
  742                          * Temporarily map the I/O space
  743                          * so we can read the chip ID register.
  744                          */
  745                         rid = RL_RID;
  746                         sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
  747                             RF_ACTIVE);
  748                         if (sc->rl_res == NULL) {
  749                                 device_printf(dev,
  750                                     "couldn't map ports/memory\n");
  751                                 return (ENXIO);
  752                         }
  753                         sc->rl_btag = rman_get_bustag(sc->rl_res);
  754                         sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
  755 
  756                         hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
  757                         bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
  758 
  759                         /* Don't attach to 8139C+ or 8169/8110 chips. */
  760                         if (hwrev == RL_HWREV_8139CPLUS ||
  761                             (hwrev == RL_HWREV_8169 &&
  762                             t->rl_did == RT_DEVICEID_8169) ||
  763                             hwrev == RL_HWREV_8169S ||
  764                             hwrev == RL_HWREV_8110S) {
  765                                 t++;
  766                                 continue;
  767                         }
  768 
  769                         device_set_desc(dev, t->rl_name);
  770                         return (BUS_PROBE_DEFAULT);
  771                 }
  772                 t++;
  773         }
  774 
  775         return (ENXIO);
  776 }
  777 
  778 /*
  779  * Attach the interface. Allocate softc structures, do ifmedia
  780  * setup and ethernet/BPF attach.
  781  */
  782 static int
  783 rl_attach(device_t dev)
  784 {
  785         uint8_t                 eaddr[ETHER_ADDR_LEN];
  786         uint16_t                as[3];
  787         struct ifnet            *ifp;
  788         struct rl_softc         *sc;
  789         struct rl_type          *t;
  790         int                     error = 0, i, rid;
  791         int                     unit;
  792         uint16_t                rl_did = 0;
  793 
  794         sc = device_get_softc(dev);
  795         unit = device_get_unit(dev);
  796         sc->rl_dev = dev;
  797 
  798         mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
  799             MTX_DEF);
  800         callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
  801 
  802         pci_enable_busmaster(dev);
  803 
  804         /* Map control/status registers. */
  805         rid = RL_RID;
  806         sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
  807 
  808         if (sc->rl_res == NULL) {
  809                 device_printf(dev, "couldn't map ports/memory\n");
  810                 error = ENXIO;
  811                 goto fail;
  812         }
  813 
  814 #ifdef notdef
  815         /*
  816          * Detect the Realtek 8139B. For some reason, this chip is very
  817          * unstable when left to autoselect the media
  818          * The best workaround is to set the device to the required
  819          * media type or to set it to the 10 Meg speed.
  820          */
  821         if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
  822                 device_printf(dev,
  823 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
  824 #endif
  825 
  826         sc->rl_btag = rman_get_bustag(sc->rl_res);
  827         sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
  828 
  829         /* Allocate interrupt */
  830         rid = 0;
  831         sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
  832             RF_SHAREABLE | RF_ACTIVE);
  833 
  834         if (sc->rl_irq == NULL) {
  835                 device_printf(dev, "couldn't map interrupt\n");
  836                 error = ENXIO;
  837                 goto fail;
  838         }
  839 
  840         /*
  841          * Reset the adapter. Only take the lock here as it's needed in
  842          * order to call rl_reset().
  843          */
  844         RL_LOCK(sc);
  845         rl_reset(sc);
  846         RL_UNLOCK(sc);
  847 
  848         sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
  849         rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
  850         if (rl_did != 0x8129)
  851                 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
  852 
  853         /*
  854          * Get station address from the EEPROM.
  855          */
  856         rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
  857         for (i = 0; i < 3; i++) {
  858                 eaddr[(i * 2) + 0] = as[i] & 0xff;
  859                 eaddr[(i * 2) + 1] = as[i] >> 8;
  860         }
  861 
  862         /*
  863          * Now read the exact device type from the EEPROM to find
  864          * out if it's an 8129 or 8139.
  865          */
  866         rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
  867 
  868         t = rl_devs;
  869         sc->rl_type = 0;
  870         while(t->rl_name != NULL) {
  871                 if (rl_did == t->rl_did) {
  872                         sc->rl_type = t->rl_basetype;
  873                         break;
  874                 }
  875                 t++;
  876         }
  877 
  878         if (sc->rl_type == 0) {
  879                 device_printf(dev, "unknown device ID: %x\n", rl_did);
  880                 error = ENXIO;
  881                 goto fail;
  882         }
  883 
  884         /*
  885          * Allocate the parent bus DMA tag appropriate for PCI.
  886          */
  887 #define RL_NSEG_NEW 32
  888         error = bus_dma_tag_create(NULL,        /* parent */
  889                         1, 0,                   /* alignment, boundary */
  890                         BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
  891                         BUS_SPACE_MAXADDR,      /* highaddr */
  892                         NULL, NULL,             /* filter, filterarg */
  893                         MAXBSIZE, RL_NSEG_NEW,  /* maxsize, nsegments */
  894                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
  895                         BUS_DMA_ALLOCNOW,       /* flags */
  896                         NULL, NULL,             /* lockfunc, lockarg */
  897                         &sc->rl_parent_tag);
  898         if (error)
  899                 goto fail;
  900 
  901         /*
  902          * Now allocate a tag for the DMA descriptor lists.
  903          * All of our lists are allocated as a contiguous block
  904          * of memory.
  905          */
  906         error = bus_dma_tag_create(sc->rl_parent_tag,   /* parent */
  907                         1, 0,                   /* alignment, boundary */
  908                         BUS_SPACE_MAXADDR,      /* lowaddr */
  909                         BUS_SPACE_MAXADDR,      /* highaddr */
  910                         NULL, NULL,             /* filter, filterarg */
  911                         RL_RXBUFLEN + 1518, 1,  /* maxsize,nsegments */
  912                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
  913                         BUS_DMA_ALLOCNOW,               /* flags */
  914                         NULL, NULL,             /* lockfunc, lockarg */
  915                         &sc->rl_tag);
  916         if (error)
  917                 goto fail;
  918 
  919         /*
  920          * Now allocate a chunk of DMA-able memory based on the
  921          * tag we just created.
  922          */
  923         error = bus_dmamem_alloc(sc->rl_tag,
  924             (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
  925             &sc->rl_cdata.rl_rx_dmamap);
  926         if (error) {
  927                 device_printf(dev, "no memory for list buffers!\n");
  928                 bus_dma_tag_destroy(sc->rl_tag);
  929                 sc->rl_tag = NULL;
  930                 goto fail;
  931         }
  932 
  933         /* Leave a few bytes before the start of the RX ring buffer. */
  934         sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
  935         sc->rl_cdata.rl_rx_buf += sizeof(uint64_t);
  936 
  937         ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
  938         if (ifp == NULL) {
  939                 device_printf(dev, "can not if_alloc()\n");
  940                 error = ENOSPC;
  941                 goto fail;
  942         }
  943 
  944         /* Do MII setup */
  945         if (mii_phy_probe(dev, &sc->rl_miibus,
  946             rl_ifmedia_upd, rl_ifmedia_sts)) {
  947                 device_printf(dev, "MII without any phy!\n");
  948                 error = ENXIO;
  949                 goto fail;
  950         }
  951 
  952         ifp->if_softc = sc;
  953         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
  954         ifp->if_mtu = ETHERMTU;
  955         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
  956         ifp->if_ioctl = rl_ioctl;
  957         ifp->if_start = rl_start;
  958         ifp->if_watchdog = rl_watchdog;
  959         ifp->if_init = rl_init;
  960         ifp->if_capabilities = IFCAP_VLAN_MTU;
  961         ifp->if_capenable = ifp->if_capabilities;
  962 #ifdef DEVICE_POLLING
  963         ifp->if_capabilities |= IFCAP_POLLING;
  964 #endif
  965         IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
  966         ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
  967         IFQ_SET_READY(&ifp->if_snd);
  968 
  969         /*
  970          * Call MI attach routine.
  971          */
  972         ether_ifattach(ifp, eaddr);
  973 
  974         /* Hook interrupt last to avoid having to lock softc */
  975         error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE,
  976             rl_intr, sc, &sc->rl_intrhand);
  977         if (error) {
  978                 device_printf(sc->rl_dev, "couldn't set up irq\n");
  979                 ether_ifdetach(ifp);
  980         }
  981 
  982 fail:
  983         if (error)
  984                 rl_detach(dev);
  985 
  986         return (error);
  987 }
  988 
  989 /*
  990  * Shutdown hardware and free up resources. This can be called any
  991  * time after the mutex has been initialized. It is called in both
  992  * the error case in attach and the normal detach case so it needs
  993  * to be careful about only freeing resources that have actually been
  994  * allocated.
  995  */
  996 static int
  997 rl_detach(device_t dev)
  998 {
  999         struct rl_softc         *sc;
 1000         struct ifnet            *ifp;
 1001 
 1002         sc = device_get_softc(dev);
 1003         ifp = sc->rl_ifp;
 1004 
 1005         KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
 1006 #ifdef DEVICE_POLLING
 1007         if (ifp->if_capenable & IFCAP_POLLING)
 1008                 ether_poll_deregister(ifp);
 1009 #endif
 1010         /* These should only be active if attach succeeded */
 1011         if (device_is_attached(dev)) {
 1012                 RL_LOCK(sc);
 1013                 rl_stop(sc);
 1014                 RL_UNLOCK(sc);
 1015                 callout_drain(&sc->rl_stat_callout);
 1016                 ether_ifdetach(ifp);
 1017         }
 1018 #if 0
 1019         sc->suspended = 1;
 1020 #endif
 1021         if (ifp)
 1022                 if_free(ifp);
 1023         if (sc->rl_miibus)
 1024                 device_delete_child(dev, sc->rl_miibus);
 1025         bus_generic_detach(dev);
 1026 
 1027         if (sc->rl_intrhand)
 1028                 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
 1029         if (sc->rl_irq)
 1030                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
 1031         if (sc->rl_res)
 1032                 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
 1033 
 1034         if (sc->rl_tag) {
 1035                 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
 1036                 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
 1037                     sc->rl_cdata.rl_rx_dmamap);
 1038                 bus_dma_tag_destroy(sc->rl_tag);
 1039         }
 1040         if (sc->rl_parent_tag)
 1041                 bus_dma_tag_destroy(sc->rl_parent_tag);
 1042 
 1043         mtx_destroy(&sc->rl_mtx);
 1044 
 1045         return (0);
 1046 }
 1047 
 1048 /*
 1049  * Initialize the transmit descriptors.
 1050  */
 1051 static int
 1052 rl_list_tx_init(struct rl_softc *sc)
 1053 {
 1054         struct rl_chain_data    *cd;
 1055         int                     i;
 1056 
 1057         RL_LOCK_ASSERT(sc);
 1058 
 1059         cd = &sc->rl_cdata;
 1060         for (i = 0; i < RL_TX_LIST_CNT; i++) {
 1061                 cd->rl_tx_chain[i] = NULL;
 1062                 CSR_WRITE_4(sc,
 1063                     RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
 1064         }
 1065 
 1066         sc->rl_cdata.cur_tx = 0;
 1067         sc->rl_cdata.last_tx = 0;
 1068 
 1069         return (0);
 1070 }
 1071 
 1072 /*
 1073  * A frame has been uploaded: pass the resulting mbuf chain up to
 1074  * the higher level protocols.
 1075  *
 1076  * You know there's something wrong with a PCI bus-master chip design
 1077  * when you have to use m_devget().
 1078  *
 1079  * The receive operation is badly documented in the datasheet, so I'll
 1080  * attempt to document it here. The driver provides a buffer area and
 1081  * places its base address in the RX buffer start address register.
 1082  * The chip then begins copying frames into the RX buffer. Each frame
 1083  * is preceded by a 32-bit RX status word which specifies the length
 1084  * of the frame and certain other status bits. Each frame (starting with
 1085  * the status word) is also 32-bit aligned. The frame length is in the
 1086  * first 16 bits of the status word; the lower 15 bits correspond with
 1087  * the 'rx status register' mentioned in the datasheet.
 1088  *
 1089  * Note: to make the Alpha happy, the frame payload needs to be aligned
 1090  * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
 1091  * as the offset argument to m_devget().
 1092  */
 1093 static void
 1094 rl_rxeof(struct rl_softc *sc)
 1095 {
 1096         struct mbuf             *m;
 1097         struct ifnet            *ifp = sc->rl_ifp;
 1098         uint8_t                 *rxbufpos;
 1099         int                     total_len = 0;
 1100         int                     wrap = 0;
 1101         uint32_t                rxstat;
 1102         uint16_t                cur_rx;
 1103         uint16_t                limit;
 1104         uint16_t                max_bytes, rx_bytes = 0;
 1105 
 1106         RL_LOCK_ASSERT(sc);
 1107 
 1108         bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
 1109             BUS_DMASYNC_POSTREAD);
 1110 
 1111         cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
 1112 
 1113         /* Do not try to read past this point. */
 1114         limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
 1115 
 1116         if (limit < cur_rx)
 1117                 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
 1118         else
 1119                 max_bytes = limit - cur_rx;
 1120 
 1121         while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
 1122 #ifdef DEVICE_POLLING
 1123                 if (ifp->if_capenable & IFCAP_POLLING) {
 1124                         if (sc->rxcycles <= 0)
 1125                                 break;
 1126                         sc->rxcycles--;
 1127                 }
 1128 #endif
 1129                 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
 1130                 rxstat = le32toh(*(uint32_t *)rxbufpos);
 1131 
 1132                 /*
 1133                  * Here's a totally undocumented fact for you. When the
 1134                  * RealTek chip is in the process of copying a packet into
 1135                  * RAM for you, the length will be 0xfff0. If you spot a
 1136                  * packet header with this value, you need to stop. The
 1137                  * datasheet makes absolutely no mention of this and
 1138                  * RealTek should be shot for this.
 1139                  */
 1140                 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
 1141                         break;
 1142 
 1143                 if (!(rxstat & RL_RXSTAT_RXOK)) {
 1144                         ifp->if_ierrors++;
 1145                         rl_init_locked(sc);
 1146                         return;
 1147                 }
 1148 
 1149                 /* No errors; receive the packet. */
 1150                 total_len = rxstat >> 16;
 1151                 rx_bytes += total_len + 4;
 1152 
 1153                 /*
 1154                  * XXX The RealTek chip includes the CRC with every
 1155                  * received frame, and there's no way to turn this
 1156                  * behavior off (at least, I can't find anything in
 1157                  * the manual that explains how to do it) so we have
 1158                  * to trim off the CRC manually.
 1159                  */
 1160                 total_len -= ETHER_CRC_LEN;
 1161 
 1162                 /*
 1163                  * Avoid trying to read more bytes than we know
 1164                  * the chip has prepared for us.
 1165                  */
 1166                 if (rx_bytes > max_bytes)
 1167                         break;
 1168 
 1169                 rxbufpos = sc->rl_cdata.rl_rx_buf +
 1170                         ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
 1171                 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
 1172                         rxbufpos = sc->rl_cdata.rl_rx_buf;
 1173 
 1174                 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
 1175                 if (total_len > wrap) {
 1176                         m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
 1177                             NULL);
 1178                         if (m == NULL) {
 1179                                 ifp->if_ierrors++;
 1180                         } else {
 1181                                 m_copyback(m, wrap, total_len - wrap,
 1182                                         sc->rl_cdata.rl_rx_buf);
 1183                         }
 1184                         cur_rx = (total_len - wrap + ETHER_CRC_LEN);
 1185                 } else {
 1186                         m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
 1187                             NULL);
 1188                         if (m == NULL)
 1189                                 ifp->if_ierrors++;
 1190                         cur_rx += total_len + 4 + ETHER_CRC_LEN;
 1191                 }
 1192 
 1193                 /* Round up to 32-bit boundary. */
 1194                 cur_rx = (cur_rx + 3) & ~3;
 1195                 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
 1196 
 1197                 if (m == NULL)
 1198                         continue;
 1199 
 1200                 ifp->if_ipackets++;
 1201                 RL_UNLOCK(sc);
 1202                 (*ifp->if_input)(ifp, m);
 1203                 RL_LOCK(sc);
 1204         }
 1205 }
 1206 
 1207 /*
 1208  * A frame was downloaded to the chip. It's safe for us to clean up
 1209  * the list buffers.
 1210  */
 1211 static void
 1212 rl_txeof(struct rl_softc *sc)
 1213 {
 1214         struct ifnet            *ifp = sc->rl_ifp;
 1215         uint32_t                txstat;
 1216 
 1217         RL_LOCK_ASSERT(sc);
 1218 
 1219         /*
 1220          * Go through our tx list and free mbufs for those
 1221          * frames that have been uploaded.
 1222          */
 1223         do {
 1224                 if (RL_LAST_TXMBUF(sc) == NULL)
 1225                         break;
 1226                 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
 1227                 if (!(txstat & (RL_TXSTAT_TX_OK|
 1228                     RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
 1229                         break;
 1230 
 1231                 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
 1232 
 1233                 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
 1234                 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
 1235                 m_freem(RL_LAST_TXMBUF(sc));
 1236                 RL_LAST_TXMBUF(sc) = NULL;
 1237                 /*
 1238                  * If there was a transmit underrun, bump the TX threshold.
 1239                  * Make sure not to overflow the 63 * 32byte we can address
 1240                  * with the 6 available bit.
 1241                  */
 1242                 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
 1243                     (sc->rl_txthresh < 2016))
 1244                         sc->rl_txthresh += 32;
 1245                 if (txstat & RL_TXSTAT_TX_OK)
 1246                         ifp->if_opackets++;
 1247                 else {
 1248                         int                     oldthresh;
 1249                         ifp->if_oerrors++;
 1250                         if ((txstat & RL_TXSTAT_TXABRT) ||
 1251                             (txstat & RL_TXSTAT_OUTOFWIN))
 1252                                 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
 1253                         oldthresh = sc->rl_txthresh;
 1254                         /* error recovery */
 1255                         rl_reset(sc);
 1256                         rl_init_locked(sc);
 1257                         /* restore original threshold */
 1258                         sc->rl_txthresh = oldthresh;
 1259                         return;
 1260                 }
 1261                 RL_INC(sc->rl_cdata.last_tx);
 1262                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 1263         } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
 1264 
 1265         if (RL_LAST_TXMBUF(sc) == NULL)
 1266                 ifp->if_timer = 0;
 1267         else if (ifp->if_timer == 0)
 1268                 ifp->if_timer = 5;
 1269 }
 1270 
 1271 static void
 1272 rl_tick(void *xsc)
 1273 {
 1274         struct rl_softc         *sc = xsc;
 1275         struct mii_data         *mii;
 1276 
 1277         RL_LOCK_ASSERT(sc);
 1278         mii = device_get_softc(sc->rl_miibus);
 1279         mii_tick(mii);
 1280 
 1281         callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
 1282 }
 1283 
 1284 #ifdef DEVICE_POLLING
 1285 static void
 1286 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
 1287 {
 1288         struct rl_softc *sc = ifp->if_softc;
 1289 
 1290         RL_LOCK(sc);
 1291         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 1292                 rl_poll_locked(ifp, cmd, count);
 1293         RL_UNLOCK(sc);
 1294 }
 1295 
 1296 static void
 1297 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
 1298 {
 1299         struct rl_softc *sc = ifp->if_softc;
 1300 
 1301         RL_LOCK_ASSERT(sc);
 1302 
 1303         sc->rxcycles = count;
 1304         rl_rxeof(sc);
 1305         rl_txeof(sc);
 1306 
 1307         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 1308                 rl_start_locked(ifp);
 1309 
 1310         if (cmd == POLL_AND_CHECK_STATUS) {
 1311                 uint16_t        status;
 1312 
 1313                 /* We should also check the status register. */
 1314                 status = CSR_READ_2(sc, RL_ISR);
 1315                 if (status == 0xffff)
 1316                         return;
 1317                 if (status != 0)
 1318                         CSR_WRITE_2(sc, RL_ISR, status);
 1319 
 1320                 /* XXX We should check behaviour on receiver stalls. */
 1321 
 1322                 if (status & RL_ISR_SYSTEM_ERR) {
 1323                         rl_reset(sc);
 1324                         rl_init_locked(sc);
 1325                 }
 1326         }
 1327 }
 1328 #endif /* DEVICE_POLLING */
 1329 
 1330 static void
 1331 rl_intr(void *arg)
 1332 {
 1333         struct rl_softc         *sc = arg;
 1334         struct ifnet            *ifp = sc->rl_ifp;
 1335         uint16_t                status;
 1336 
 1337         RL_LOCK(sc);
 1338 
 1339         if (sc->suspended)
 1340                 goto done_locked;
 1341 
 1342 #ifdef DEVICE_POLLING
 1343         if  (ifp->if_capenable & IFCAP_POLLING)
 1344                 goto done_locked;
 1345 #endif
 1346 
 1347         for (;;) {
 1348                 status = CSR_READ_2(sc, RL_ISR);
 1349                 /* If the card has gone away, the read returns 0xffff. */
 1350                 if (status == 0xffff)
 1351                         break;
 1352                 if (status != 0)
 1353                         CSR_WRITE_2(sc, RL_ISR, status);
 1354                 if ((status & RL_INTRS) == 0)
 1355                         break;
 1356                 if (status & RL_ISR_RX_OK)
 1357                         rl_rxeof(sc);
 1358                 if (status & RL_ISR_RX_ERR)
 1359                         rl_rxeof(sc);
 1360                 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
 1361                         rl_txeof(sc);
 1362                 if (status & RL_ISR_SYSTEM_ERR) {
 1363                         rl_reset(sc);
 1364                         rl_init_locked(sc);
 1365                 }
 1366         }
 1367 
 1368         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 1369                 rl_start_locked(ifp);
 1370 
 1371 done_locked:
 1372         RL_UNLOCK(sc);
 1373 }
 1374 
 1375 /*
 1376  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
 1377  * pointers to the fragment pointers.
 1378  */
 1379 static int
 1380 rl_encap(struct rl_softc *sc, struct mbuf *m_head)
 1381 {
 1382         struct mbuf             *m_new = NULL;
 1383 
 1384         RL_LOCK_ASSERT(sc);
 1385 
 1386         /*
 1387          * The RealTek is brain damaged and wants longword-aligned
 1388          * TX buffers, plus we can only have one fragment buffer
 1389          * per packet. We have to copy pretty much all the time.
 1390          */
 1391         m_new = m_defrag(m_head, M_DONTWAIT);
 1392 
 1393         if (m_new == NULL) {
 1394                 m_freem(m_head);
 1395                 return (1);
 1396         }
 1397         m_head = m_new;
 1398 
 1399         /* Pad frames to at least 60 bytes. */
 1400         if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
 1401                 /*
 1402                  * Make security concious people happy: zero out the
 1403                  * bytes in the pad area, since we don't know what
 1404                  * this mbuf cluster buffer's previous user might
 1405                  * have left in it.
 1406                  */
 1407                 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
 1408                      RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
 1409                 m_head->m_pkthdr.len +=
 1410                     (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
 1411                 m_head->m_len = m_head->m_pkthdr.len;
 1412         }
 1413 
 1414         RL_CUR_TXMBUF(sc) = m_head;
 1415 
 1416         return (0);
 1417 }
 1418 
 1419 /*
 1420  * Main transmit routine.
 1421  */
 1422 static void
 1423 rl_start(struct ifnet *ifp)
 1424 {
 1425         struct rl_softc         *sc = ifp->if_softc;
 1426 
 1427         RL_LOCK(sc);
 1428         rl_start_locked(ifp);
 1429         RL_UNLOCK(sc);
 1430 }
 1431 
 1432 static void
 1433 rl_start_locked(struct ifnet *ifp)
 1434 {
 1435         struct rl_softc         *sc = ifp->if_softc;
 1436         struct mbuf             *m_head = NULL;
 1437 
 1438         RL_LOCK_ASSERT(sc);
 1439 
 1440         while (RL_CUR_TXMBUF(sc) == NULL) {
 1441 
 1442                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
 1443 
 1444                 if (m_head == NULL)
 1445                         break;
 1446 
 1447                 if (rl_encap(sc, m_head))
 1448                         break;
 1449 
 1450                 /* Pass a copy of this mbuf chain to the bpf subsystem. */
 1451                 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
 1452 
 1453                 /* Transmit the frame. */
 1454                 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
 1455                 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
 1456                     mtod(RL_CUR_TXMBUF(sc), void *),
 1457                     RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
 1458                 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
 1459                     BUS_DMASYNC_PREREAD);
 1460                 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
 1461                     RL_TXTHRESH(sc->rl_txthresh) |
 1462                     RL_CUR_TXMBUF(sc)->m_pkthdr.len);
 1463 
 1464                 RL_INC(sc->rl_cdata.cur_tx);
 1465 
 1466                 /* Set a timeout in case the chip goes out to lunch. */
 1467                 ifp->if_timer = 5;
 1468         }
 1469 
 1470         /*
 1471          * We broke out of the loop because all our TX slots are
 1472          * full. Mark the NIC as busy until it drains some of the
 1473          * packets from the queue.
 1474          */
 1475         if (RL_CUR_TXMBUF(sc) != NULL)
 1476                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 1477 }
 1478 
 1479 static void
 1480 rl_init(void *xsc)
 1481 {
 1482         struct rl_softc         *sc = xsc;
 1483 
 1484         RL_LOCK(sc);
 1485         rl_init_locked(sc);
 1486         RL_UNLOCK(sc);
 1487 }
 1488 
 1489 static void
 1490 rl_init_locked(struct rl_softc *sc)
 1491 {
 1492         struct ifnet            *ifp = sc->rl_ifp;
 1493         struct mii_data         *mii;
 1494         uint32_t                rxcfg = 0;
 1495 
 1496         RL_LOCK_ASSERT(sc);
 1497 
 1498         mii = device_get_softc(sc->rl_miibus);
 1499 
 1500         /*
 1501          * Cancel pending I/O and free all RX/TX buffers.
 1502          */
 1503         rl_stop(sc);
 1504 
 1505         /*
 1506          * Init our MAC address.  Even though the chipset
 1507          * documentation doesn't mention it, we need to enter "Config
 1508          * register write enable" mode to modify the ID registers.
 1509          */
 1510         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
 1511         CSR_WRITE_STREAM_4(sc, RL_IDR0,
 1512             *(uint32_t *)(&IFP2ENADDR(sc->rl_ifp)[0]));
 1513         CSR_WRITE_STREAM_4(sc, RL_IDR4,
 1514             *(uint32_t *)(&IFP2ENADDR(sc->rl_ifp)[4]));
 1515         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 1516 
 1517         /* Init the RX buffer pointer register. */
 1518         bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
 1519             sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
 1520         bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
 1521             BUS_DMASYNC_PREWRITE);
 1522 
 1523         /* Init TX descriptors. */
 1524         rl_list_tx_init(sc);
 1525 
 1526         /*
 1527          * Enable transmit and receive.
 1528          */
 1529         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
 1530 
 1531         /*
 1532          * Set the initial TX and RX configuration.
 1533          */
 1534         CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
 1535         CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
 1536 
 1537         /* Set the individual bit to receive frames for this host only. */
 1538         rxcfg = CSR_READ_4(sc, RL_RXCFG);
 1539         rxcfg |= RL_RXCFG_RX_INDIV;
 1540 
 1541         /* If we want promiscuous mode, set the allframes bit. */
 1542         if (ifp->if_flags & IFF_PROMISC) {
 1543                 rxcfg |= RL_RXCFG_RX_ALLPHYS;
 1544                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
 1545         } else {
 1546                 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
 1547                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
 1548         }
 1549 
 1550         /* Set capture broadcast bit to capture broadcast frames. */
 1551         if (ifp->if_flags & IFF_BROADCAST) {
 1552                 rxcfg |= RL_RXCFG_RX_BROAD;
 1553                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
 1554         } else {
 1555                 rxcfg &= ~RL_RXCFG_RX_BROAD;
 1556                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
 1557         }
 1558 
 1559         /* Program the multicast filter, if necessary. */
 1560         rl_setmulti(sc);
 1561 
 1562 #ifdef DEVICE_POLLING
 1563         /* Disable interrupts if we are polling. */
 1564         if (ifp->if_capenable & IFCAP_POLLING)
 1565                 CSR_WRITE_2(sc, RL_IMR, 0);
 1566         else
 1567 #endif
 1568         /* Enable interrupts. */
 1569         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
 1570 
 1571         /* Set initial TX threshold */
 1572         sc->rl_txthresh = RL_TX_THRESH_INIT;
 1573 
 1574         /* Start RX/TX process. */
 1575         CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
 1576 
 1577         /* Enable receiver and transmitter. */
 1578         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
 1579 
 1580         mii_mediachg(mii);
 1581 
 1582         CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
 1583 
 1584         ifp->if_drv_flags |= IFF_DRV_RUNNING;
 1585         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 1586 
 1587         callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
 1588 }
 1589 
 1590 /*
 1591  * Set media options.
 1592  */
 1593 static int
 1594 rl_ifmedia_upd(struct ifnet *ifp)
 1595 {
 1596         struct rl_softc         *sc = ifp->if_softc;
 1597         struct mii_data         *mii;
 1598 
 1599         mii = device_get_softc(sc->rl_miibus);
 1600 
 1601         RL_LOCK(sc);
 1602         mii_mediachg(mii);
 1603         RL_UNLOCK(sc);
 1604 
 1605         return (0);
 1606 }
 1607 
 1608 /*
 1609  * Report current media status.
 1610  */
 1611 static void
 1612 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 1613 {
 1614         struct rl_softc         *sc = ifp->if_softc;
 1615         struct mii_data         *mii;
 1616 
 1617         mii = device_get_softc(sc->rl_miibus);
 1618 
 1619         RL_LOCK(sc);
 1620         mii_pollstat(mii);
 1621         RL_UNLOCK(sc);
 1622         ifmr->ifm_active = mii->mii_media_active;
 1623         ifmr->ifm_status = mii->mii_media_status;
 1624 }
 1625 
 1626 static int
 1627 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 1628 {
 1629         struct ifreq            *ifr = (struct ifreq *)data;
 1630         struct mii_data         *mii;
 1631         struct rl_softc         *sc = ifp->if_softc;
 1632         int                     error = 0;
 1633 
 1634         switch (command) {
 1635         case SIOCSIFFLAGS:
 1636                 RL_LOCK(sc);
 1637                 if (ifp->if_flags & IFF_UP) {
 1638                         rl_init_locked(sc);
 1639                 } else {
 1640                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 1641                                 rl_stop(sc);
 1642                 }
 1643                 RL_UNLOCK(sc);
 1644                 error = 0;
 1645                 break;
 1646         case SIOCADDMULTI:
 1647         case SIOCDELMULTI:
 1648                 RL_LOCK(sc);
 1649                 rl_setmulti(sc);
 1650                 RL_UNLOCK(sc);
 1651                 error = 0;
 1652                 break;
 1653         case SIOCGIFMEDIA:
 1654         case SIOCSIFMEDIA:
 1655                 mii = device_get_softc(sc->rl_miibus);
 1656                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 1657                 break;
 1658         case SIOCSIFCAP:
 1659 #ifdef DEVICE_POLLING
 1660                 if (ifr->ifr_reqcap & IFCAP_POLLING &&
 1661                     !(ifp->if_capenable & IFCAP_POLLING)) {
 1662                         error = ether_poll_register(rl_poll, ifp);
 1663                         if (error)
 1664                                 return(error);
 1665                         RL_LOCK(sc);
 1666                         /* Disable interrupts */
 1667                         CSR_WRITE_2(sc, RL_IMR, 0x0000);
 1668                         ifp->if_capenable |= IFCAP_POLLING;
 1669                         RL_UNLOCK(sc);
 1670                         return (error);
 1671                         
 1672                 }
 1673                 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
 1674                     ifp->if_capenable & IFCAP_POLLING) {
 1675                         error = ether_poll_deregister(ifp);
 1676                         /* Enable interrupts. */
 1677                         RL_LOCK(sc);
 1678                         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
 1679                         ifp->if_capenable &= ~IFCAP_POLLING;
 1680                         RL_UNLOCK(sc);
 1681                         return (error);
 1682                 }
 1683 #endif /* DEVICE_POLLING */
 1684                 break;
 1685         default:
 1686                 error = ether_ioctl(ifp, command, data);
 1687                 break;
 1688         }
 1689 
 1690         return (error);
 1691 }
 1692 
 1693 static void
 1694 rl_watchdog(struct ifnet *ifp)
 1695 {
 1696         struct rl_softc         *sc = ifp->if_softc;
 1697 
 1698         RL_LOCK(sc);
 1699 
 1700         if_printf(ifp, "watchdog timeout\n");
 1701         ifp->if_oerrors++;
 1702 
 1703         rl_txeof(sc);
 1704         rl_rxeof(sc);
 1705         rl_init_locked(sc);
 1706 
 1707         RL_UNLOCK(sc);
 1708 }
 1709 
 1710 /*
 1711  * Stop the adapter and free any mbufs allocated to the
 1712  * RX and TX lists.
 1713  */
 1714 static void
 1715 rl_stop(struct rl_softc *sc)
 1716 {
 1717         register int            i;
 1718         struct ifnet            *ifp = sc->rl_ifp;
 1719 
 1720         RL_LOCK_ASSERT(sc);
 1721 
 1722         ifp->if_timer = 0;
 1723         callout_stop(&sc->rl_stat_callout);
 1724         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
 1725 
 1726         CSR_WRITE_1(sc, RL_COMMAND, 0x00);
 1727         CSR_WRITE_2(sc, RL_IMR, 0x0000);
 1728         bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
 1729 
 1730         /*
 1731          * Free the TX list buffers.
 1732          */
 1733         for (i = 0; i < RL_TX_LIST_CNT; i++) {
 1734                 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
 1735                         bus_dmamap_unload(sc->rl_tag,
 1736                             sc->rl_cdata.rl_tx_dmamap[i]);
 1737                         bus_dmamap_destroy(sc->rl_tag,
 1738                             sc->rl_cdata.rl_tx_dmamap[i]);
 1739                         m_freem(sc->rl_cdata.rl_tx_chain[i]);
 1740                         sc->rl_cdata.rl_tx_chain[i] = NULL;
 1741                         CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
 1742                             0x0000000);
 1743                 }
 1744         }
 1745 }
 1746 
 1747 /*
 1748  * Device suspend routine.  Stop the interface and save some PCI
 1749  * settings in case the BIOS doesn't restore them properly on
 1750  * resume.
 1751  */
 1752 static int
 1753 rl_suspend(device_t dev)
 1754 {
 1755         struct rl_softc         *sc;
 1756 
 1757         sc = device_get_softc(dev);
 1758 
 1759         RL_LOCK(sc);
 1760         rl_stop(sc);
 1761         sc->suspended = 1;
 1762         RL_UNLOCK(sc);
 1763 
 1764         return (0);
 1765 }
 1766 
 1767 /*
 1768  * Device resume routine.  Restore some PCI settings in case the BIOS
 1769  * doesn't, re-enable busmastering, and restart the interface if
 1770  * appropriate.
 1771  */
 1772 static int
 1773 rl_resume(device_t dev)
 1774 {
 1775         struct rl_softc         *sc;
 1776         struct ifnet            *ifp;
 1777 
 1778         sc = device_get_softc(dev);
 1779         ifp = sc->rl_ifp;
 1780 
 1781         RL_LOCK(sc);
 1782 
 1783         /* reinitialize interface if necessary */
 1784         if (ifp->if_flags & IFF_UP)
 1785                 rl_init_locked(sc);
 1786 
 1787         sc->suspended = 0;
 1788 
 1789         RL_UNLOCK(sc);
 1790 
 1791         return (0);
 1792 }
 1793 
 1794 /*
 1795  * Stop all chip I/O so that the kernel's probe routines don't
 1796  * get confused by errant DMAs when rebooting.
 1797  */
 1798 static void
 1799 rl_shutdown(device_t dev)
 1800 {
 1801         struct rl_softc         *sc;
 1802 
 1803         sc = device_get_softc(dev);
 1804 
 1805         RL_LOCK(sc);
 1806         rl_stop(sc);
 1807         RL_UNLOCK(sc);
 1808 }

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