FreeBSD/Linux Kernel Cross Reference
sys/pci/if_rl.c
1 /*-
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/6.4/sys/pci/if_rl.c 180490 2008-07-13 11:57:59Z remko $");
35
36 /*
37 * RealTek 8129/8139 PCI NIC driver
38 *
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
41 * www.realtek.com.tw.
42 *
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
46 */
47 /*
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
53 *
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
62 *
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
68 * levels.
69 *
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
73 *
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
78 * filter.
79 *
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
84 */
85
86 #ifdef HAVE_KERNEL_OPTION_HEADERS
87 #include "opt_device_polling.h"
88 #endif
89
90 #include <sys/param.h>
91 #include <sys/endian.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
94 #include <sys/mbuf.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/module.h>
98 #include <sys/socket.h>
99
100 #include <net/if.h>
101 #include <net/if_arp.h>
102 #include <net/ethernet.h>
103 #include <net/if_dl.h>
104 #include <net/if_media.h>
105 #include <net/if_types.h>
106
107 #include <net/bpf.h>
108
109 #include <machine/bus.h>
110 #include <machine/resource.h>
111 #include <sys/bus.h>
112 #include <sys/rman.h>
113
114 #include <dev/mii/mii.h>
115 #include <dev/mii/miivar.h>
116
117 #include <dev/pci/pcireg.h>
118 #include <dev/pci/pcivar.h>
119
120 MODULE_DEPEND(rl, pci, 1, 1, 1);
121 MODULE_DEPEND(rl, ether, 1, 1, 1);
122 MODULE_DEPEND(rl, miibus, 1, 1, 1);
123
124 /* "controller miibus0" required. See GENERIC if you get errors here. */
125 #include "miibus_if.h"
126
127 /*
128 * Default to using PIO access for this driver. On SMP systems,
129 * there appear to be problems with memory mapped mode: it looks like
130 * doing too many memory mapped access back to back in rapid succession
131 * can hang the bus. I'm inclined to blame this on crummy design/construction
132 * on the part of RealTek. Memory mapped mode does appear to work on
133 * uniprocessor systems though.
134 */
135 #define RL_USEIOSPACE
136
137 #include <pci/if_rlreg.h>
138
139 /*
140 * Various supported device vendors/types and their names.
141 */
142 static struct rl_type rl_devs[] = {
143 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
144 "RealTek 8129 10/100BaseTX" },
145 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
146 "RealTek 8139 10/100BaseTX" },
147 { RT_VENDORID, RT_DEVICEID_8139D, RL_8139,
148 "RealTek 8139 10/100BaseTX" },
149 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
150 "RealTek 8139 10/100BaseTX CardBus" },
151 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
152 "RealTek 8100 10/100BaseTX" },
153 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
154 "Accton MPX 5030/5038 10/100BaseTX" },
155 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
156 "Delta Electronics 8139 10/100BaseTX" },
157 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
158 "Addtron Technolgy 8139 10/100BaseTX" },
159 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
160 "D-Link DFE-530TX+ 10/100BaseTX" },
161 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
162 "D-Link DFE-690TXD 10/100BaseTX" },
163 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
164 "Nortel Networks 10/100BaseTX" },
165 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
166 "Corega FEther CB-TXD" },
167 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
168 "Corega FEtherII CB-TXD" },
169 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
170 "Peppercon AG ROL-F" },
171 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
172 "Planex FNW-3603-TX" },
173 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
174 "Planex FNW-3800-TX" },
175 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
176 "Compaq HNE-300" },
177 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
178 "LevelOne FPC-0106TX" },
179 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
180 "Edimax EP-4103DL CardBus" },
181 { 0, 0, 0, NULL }
182 };
183
184 static int rl_attach(device_t);
185 static int rl_detach(device_t);
186 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
187 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
188 static void rl_eeprom_putbyte(struct rl_softc *, int);
189 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
190 static int rl_encap(struct rl_softc *, struct mbuf * );
191 static int rl_list_tx_init(struct rl_softc *);
192 static int rl_ifmedia_upd(struct ifnet *);
193 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
194 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
195 static void rl_intr(void *);
196 static void rl_init(void *);
197 static void rl_init_locked(struct rl_softc *sc);
198 static void rl_mii_send(struct rl_softc *, uint32_t, int);
199 static void rl_mii_sync(struct rl_softc *);
200 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
201 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
202 static int rl_miibus_readreg(device_t, int, int);
203 static void rl_miibus_statchg(device_t);
204 static int rl_miibus_writereg(device_t, int, int, int);
205 #ifdef DEVICE_POLLING
206 static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
207 static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
208 #endif
209 static int rl_probe(device_t);
210 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
211 static void rl_reset(struct rl_softc *);
212 static int rl_resume(device_t);
213 static void rl_rxeof(struct rl_softc *);
214 static void rl_setmulti(struct rl_softc *);
215 static void rl_shutdown(device_t);
216 static void rl_start(struct ifnet *);
217 static void rl_start_locked(struct ifnet *);
218 static void rl_stop(struct rl_softc *);
219 static int rl_suspend(device_t);
220 static void rl_tick(void *);
221 static void rl_txeof(struct rl_softc *);
222 static void rl_watchdog(struct ifnet *);
223
224 #ifdef RL_USEIOSPACE
225 #define RL_RES SYS_RES_IOPORT
226 #define RL_RID RL_PCI_LOIO
227 #else
228 #define RL_RES SYS_RES_MEMORY
229 #define RL_RID RL_PCI_LOMEM
230 #endif
231
232 static device_method_t rl_methods[] = {
233 /* Device interface */
234 DEVMETHOD(device_probe, rl_probe),
235 DEVMETHOD(device_attach, rl_attach),
236 DEVMETHOD(device_detach, rl_detach),
237 DEVMETHOD(device_suspend, rl_suspend),
238 DEVMETHOD(device_resume, rl_resume),
239 DEVMETHOD(device_shutdown, rl_shutdown),
240
241 /* bus interface */
242 DEVMETHOD(bus_print_child, bus_generic_print_child),
243 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
244
245 /* MII interface */
246 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
247 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
248 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
249
250 { 0, 0 }
251 };
252
253 static driver_t rl_driver = {
254 "rl",
255 rl_methods,
256 sizeof(struct rl_softc)
257 };
258
259 static devclass_t rl_devclass;
260
261 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
262 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
263 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
264
265 #define EE_SET(x) \
266 CSR_WRITE_1(sc, RL_EECMD, \
267 CSR_READ_1(sc, RL_EECMD) | x)
268
269 #define EE_CLR(x) \
270 CSR_WRITE_1(sc, RL_EECMD, \
271 CSR_READ_1(sc, RL_EECMD) & ~x)
272
273 static void
274 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
275 {
276 struct rl_softc *sc = arg;
277
278 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
279 }
280
281 static void
282 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
283 {
284 struct rl_softc *sc = arg;
285
286 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
287 }
288
289 /*
290 * Send a read command and address to the EEPROM, check for ACK.
291 */
292 static void
293 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
294 {
295 register int d, i;
296
297 d = addr | sc->rl_eecmd_read;
298
299 /*
300 * Feed in each bit and strobe the clock.
301 */
302 for (i = 0x400; i; i >>= 1) {
303 if (d & i) {
304 EE_SET(RL_EE_DATAIN);
305 } else {
306 EE_CLR(RL_EE_DATAIN);
307 }
308 DELAY(100);
309 EE_SET(RL_EE_CLK);
310 DELAY(150);
311 EE_CLR(RL_EE_CLK);
312 DELAY(100);
313 }
314 }
315
316 /*
317 * Read a word of data stored in the EEPROM at address 'addr.'
318 */
319 static void
320 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
321 {
322 register int i;
323 uint16_t word = 0;
324
325 /* Enter EEPROM access mode. */
326 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
327
328 /*
329 * Send address of word we want to read.
330 */
331 rl_eeprom_putbyte(sc, addr);
332
333 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
334
335 /*
336 * Start reading bits from EEPROM.
337 */
338 for (i = 0x8000; i; i >>= 1) {
339 EE_SET(RL_EE_CLK);
340 DELAY(100);
341 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
342 word |= i;
343 EE_CLR(RL_EE_CLK);
344 DELAY(100);
345 }
346
347 /* Turn off EEPROM access mode. */
348 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
349
350 *dest = word;
351 }
352
353 /*
354 * Read a sequence of words from the EEPROM.
355 */
356 static void
357 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
358 {
359 int i;
360 uint16_t word = 0, *ptr;
361
362 for (i = 0; i < cnt; i++) {
363 rl_eeprom_getword(sc, off + i, &word);
364 ptr = (uint16_t *)(dest + (i * 2));
365 if (swap)
366 *ptr = ntohs(word);
367 else
368 *ptr = word;
369 }
370 }
371
372 /*
373 * MII access routines are provided for the 8129, which
374 * doesn't have a built-in PHY. For the 8139, we fake things
375 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
376 * direct access PHY registers.
377 */
378 #define MII_SET(x) \
379 CSR_WRITE_1(sc, RL_MII, \
380 CSR_READ_1(sc, RL_MII) | (x))
381
382 #define MII_CLR(x) \
383 CSR_WRITE_1(sc, RL_MII, \
384 CSR_READ_1(sc, RL_MII) & ~(x))
385
386 /*
387 * Sync the PHYs by setting data bit and strobing the clock 32 times.
388 */
389 static void
390 rl_mii_sync(struct rl_softc *sc)
391 {
392 register int i;
393
394 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
395
396 for (i = 0; i < 32; i++) {
397 MII_SET(RL_MII_CLK);
398 DELAY(1);
399 MII_CLR(RL_MII_CLK);
400 DELAY(1);
401 }
402 }
403
404 /*
405 * Clock a series of bits through the MII.
406 */
407 static void
408 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
409 {
410 int i;
411
412 MII_CLR(RL_MII_CLK);
413
414 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
415 if (bits & i) {
416 MII_SET(RL_MII_DATAOUT);
417 } else {
418 MII_CLR(RL_MII_DATAOUT);
419 }
420 DELAY(1);
421 MII_CLR(RL_MII_CLK);
422 DELAY(1);
423 MII_SET(RL_MII_CLK);
424 }
425 }
426
427 /*
428 * Read an PHY register through the MII.
429 */
430 static int
431 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
432 {
433 int i, ack;
434
435 /* Set up frame for RX. */
436 frame->mii_stdelim = RL_MII_STARTDELIM;
437 frame->mii_opcode = RL_MII_READOP;
438 frame->mii_turnaround = 0;
439 frame->mii_data = 0;
440
441 CSR_WRITE_2(sc, RL_MII, 0);
442
443 /* Turn on data xmit. */
444 MII_SET(RL_MII_DIR);
445
446 rl_mii_sync(sc);
447
448 /* Send command/address info. */
449 rl_mii_send(sc, frame->mii_stdelim, 2);
450 rl_mii_send(sc, frame->mii_opcode, 2);
451 rl_mii_send(sc, frame->mii_phyaddr, 5);
452 rl_mii_send(sc, frame->mii_regaddr, 5);
453
454 /* Idle bit */
455 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
456 DELAY(1);
457 MII_SET(RL_MII_CLK);
458 DELAY(1);
459
460 /* Turn off xmit. */
461 MII_CLR(RL_MII_DIR);
462
463 /* Check for ack */
464 MII_CLR(RL_MII_CLK);
465 DELAY(1);
466 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
467 MII_SET(RL_MII_CLK);
468 DELAY(1);
469
470 /*
471 * Now try reading data bits. If the ack failed, we still
472 * need to clock through 16 cycles to keep the PHY(s) in sync.
473 */
474 if (ack) {
475 for(i = 0; i < 16; i++) {
476 MII_CLR(RL_MII_CLK);
477 DELAY(1);
478 MII_SET(RL_MII_CLK);
479 DELAY(1);
480 }
481 goto fail;
482 }
483
484 for (i = 0x8000; i; i >>= 1) {
485 MII_CLR(RL_MII_CLK);
486 DELAY(1);
487 if (!ack) {
488 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
489 frame->mii_data |= i;
490 DELAY(1);
491 }
492 MII_SET(RL_MII_CLK);
493 DELAY(1);
494 }
495
496 fail:
497 MII_CLR(RL_MII_CLK);
498 DELAY(1);
499 MII_SET(RL_MII_CLK);
500 DELAY(1);
501
502 return (ack ? 1 : 0);
503 }
504
505 /*
506 * Write to a PHY register through the MII.
507 */
508 static int
509 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
510 {
511
512 /* Set up frame for TX. */
513 frame->mii_stdelim = RL_MII_STARTDELIM;
514 frame->mii_opcode = RL_MII_WRITEOP;
515 frame->mii_turnaround = RL_MII_TURNAROUND;
516
517 /* Turn on data output. */
518 MII_SET(RL_MII_DIR);
519
520 rl_mii_sync(sc);
521
522 rl_mii_send(sc, frame->mii_stdelim, 2);
523 rl_mii_send(sc, frame->mii_opcode, 2);
524 rl_mii_send(sc, frame->mii_phyaddr, 5);
525 rl_mii_send(sc, frame->mii_regaddr, 5);
526 rl_mii_send(sc, frame->mii_turnaround, 2);
527 rl_mii_send(sc, frame->mii_data, 16);
528
529 /* Idle bit. */
530 MII_SET(RL_MII_CLK);
531 DELAY(1);
532 MII_CLR(RL_MII_CLK);
533 DELAY(1);
534
535 /* Turn off xmit. */
536 MII_CLR(RL_MII_DIR);
537
538 return (0);
539 }
540
541 static int
542 rl_miibus_readreg(device_t dev, int phy, int reg)
543 {
544 struct rl_softc *sc;
545 struct rl_mii_frame frame;
546 uint16_t rval = 0;
547 uint16_t rl8139_reg = 0;
548
549 sc = device_get_softc(dev);
550
551 if (sc->rl_type == RL_8139) {
552 /* Pretend the internal PHY is only at address 0 */
553 if (phy) {
554 return (0);
555 }
556 switch (reg) {
557 case MII_BMCR:
558 rl8139_reg = RL_BMCR;
559 break;
560 case MII_BMSR:
561 rl8139_reg = RL_BMSR;
562 break;
563 case MII_ANAR:
564 rl8139_reg = RL_ANAR;
565 break;
566 case MII_ANER:
567 rl8139_reg = RL_ANER;
568 break;
569 case MII_ANLPAR:
570 rl8139_reg = RL_LPAR;
571 break;
572 case MII_PHYIDR1:
573 case MII_PHYIDR2:
574 return (0);
575 /*
576 * Allow the rlphy driver to read the media status
577 * register. If we have a link partner which does not
578 * support NWAY, this is the register which will tell
579 * us the results of parallel detection.
580 */
581 case RL_MEDIASTAT:
582 rval = CSR_READ_1(sc, RL_MEDIASTAT);
583 return (rval);
584 default:
585 device_printf(sc->rl_dev, "bad phy register\n");
586 return (0);
587 }
588 rval = CSR_READ_2(sc, rl8139_reg);
589 return (rval);
590 }
591
592 bzero((char *)&frame, sizeof(frame));
593 frame.mii_phyaddr = phy;
594 frame.mii_regaddr = reg;
595 rl_mii_readreg(sc, &frame);
596
597 return (frame.mii_data);
598 }
599
600 static int
601 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
602 {
603 struct rl_softc *sc;
604 struct rl_mii_frame frame;
605 uint16_t rl8139_reg = 0;
606
607 sc = device_get_softc(dev);
608
609 if (sc->rl_type == RL_8139) {
610 /* Pretend the internal PHY is only at address 0 */
611 if (phy) {
612 return (0);
613 }
614 switch (reg) {
615 case MII_BMCR:
616 rl8139_reg = RL_BMCR;
617 break;
618 case MII_BMSR:
619 rl8139_reg = RL_BMSR;
620 break;
621 case MII_ANAR:
622 rl8139_reg = RL_ANAR;
623 break;
624 case MII_ANER:
625 rl8139_reg = RL_ANER;
626 break;
627 case MII_ANLPAR:
628 rl8139_reg = RL_LPAR;
629 break;
630 case MII_PHYIDR1:
631 case MII_PHYIDR2:
632 return (0);
633 break;
634 default:
635 device_printf(sc->rl_dev, "bad phy register\n");
636 return (0);
637 }
638 CSR_WRITE_2(sc, rl8139_reg, data);
639 return (0);
640 }
641
642 bzero((char *)&frame, sizeof(frame));
643 frame.mii_phyaddr = phy;
644 frame.mii_regaddr = reg;
645 frame.mii_data = data;
646 rl_mii_writereg(sc, &frame);
647
648 return (0);
649 }
650
651 static void
652 rl_miibus_statchg(device_t dev)
653 {
654 }
655
656 /*
657 * Program the 64-bit multicast hash filter.
658 */
659 static void
660 rl_setmulti(struct rl_softc *sc)
661 {
662 struct ifnet *ifp = sc->rl_ifp;
663 int h = 0;
664 uint32_t hashes[2] = { 0, 0 };
665 struct ifmultiaddr *ifma;
666 uint32_t rxfilt;
667 int mcnt = 0;
668
669 RL_LOCK_ASSERT(sc);
670
671 rxfilt = CSR_READ_4(sc, RL_RXCFG);
672
673 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
674 rxfilt |= RL_RXCFG_RX_MULTI;
675 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
676 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
677 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
678 return;
679 }
680
681 /* first, zot all the existing hash bits */
682 CSR_WRITE_4(sc, RL_MAR0, 0);
683 CSR_WRITE_4(sc, RL_MAR4, 0);
684
685 /* now program new ones */
686 IF_ADDR_LOCK(ifp);
687 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
688 if (ifma->ifma_addr->sa_family != AF_LINK)
689 continue;
690 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
691 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
692 if (h < 32)
693 hashes[0] |= (1 << h);
694 else
695 hashes[1] |= (1 << (h - 32));
696 mcnt++;
697 }
698 IF_ADDR_UNLOCK(ifp);
699
700 if (mcnt)
701 rxfilt |= RL_RXCFG_RX_MULTI;
702 else
703 rxfilt &= ~RL_RXCFG_RX_MULTI;
704
705 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
706 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
707 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
708 }
709
710 static void
711 rl_reset(struct rl_softc *sc)
712 {
713 register int i;
714
715 RL_LOCK_ASSERT(sc);
716
717 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
718
719 for (i = 0; i < RL_TIMEOUT; i++) {
720 DELAY(10);
721 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
722 break;
723 }
724 if (i == RL_TIMEOUT)
725 device_printf(sc->rl_dev, "reset never completed!\n");
726 }
727
728 /*
729 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
730 * IDs against our list and return a device name if we find a match.
731 */
732 static int
733 rl_probe(device_t dev)
734 {
735 struct rl_softc *sc;
736 struct rl_type *t = rl_devs;
737 int rid;
738 uint32_t hwrev;
739
740 sc = device_get_softc(dev);
741
742 while (t->rl_name != NULL) {
743 if ((pci_get_vendor(dev) == t->rl_vid) &&
744 (pci_get_device(dev) == t->rl_did)) {
745 /*
746 * Temporarily map the I/O space
747 * so we can read the chip ID register.
748 */
749 rid = RL_RID;
750 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
751 RF_ACTIVE);
752 if (sc->rl_res == NULL) {
753 device_printf(dev,
754 "couldn't map ports/memory\n");
755 return (ENXIO);
756 }
757 sc->rl_btag = rman_get_bustag(sc->rl_res);
758 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
759
760 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
761 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
762
763 /* Don't attach to 8139C+ or 8169/8110 chips. */
764 if (hwrev == RL_HWREV_8139CPLUS ||
765 (hwrev == RL_HWREV_8169 &&
766 t->rl_did == RT_DEVICEID_8169) ||
767 hwrev == RL_HWREV_8169S ||
768 hwrev == RL_HWREV_8110S) {
769 t++;
770 continue;
771 }
772
773 device_set_desc(dev, t->rl_name);
774 return (BUS_PROBE_DEFAULT);
775 }
776 t++;
777 }
778
779 return (ENXIO);
780 }
781
782 /*
783 * Attach the interface. Allocate softc structures, do ifmedia
784 * setup and ethernet/BPF attach.
785 */
786 static int
787 rl_attach(device_t dev)
788 {
789 uint8_t eaddr[ETHER_ADDR_LEN];
790 uint16_t as[3];
791 struct ifnet *ifp;
792 struct rl_softc *sc;
793 struct rl_type *t;
794 int error = 0, i, rid;
795 int unit;
796 uint16_t rl_did = 0;
797
798 sc = device_get_softc(dev);
799 unit = device_get_unit(dev);
800 sc->rl_dev = dev;
801
802 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
803 MTX_DEF);
804 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
805
806 pci_enable_busmaster(dev);
807
808 /* Map control/status registers. */
809 rid = RL_RID;
810 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
811
812 if (sc->rl_res == NULL) {
813 device_printf(dev, "couldn't map ports/memory\n");
814 error = ENXIO;
815 goto fail;
816 }
817
818 #ifdef notdef
819 /*
820 * Detect the Realtek 8139B. For some reason, this chip is very
821 * unstable when left to autoselect the media
822 * The best workaround is to set the device to the required
823 * media type or to set it to the 10 Meg speed.
824 */
825 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
826 device_printf(dev,
827 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
828 #endif
829
830 sc->rl_btag = rman_get_bustag(sc->rl_res);
831 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
832
833 /* Allocate interrupt */
834 rid = 0;
835 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
836 RF_SHAREABLE | RF_ACTIVE);
837
838 if (sc->rl_irq == NULL) {
839 device_printf(dev, "couldn't map interrupt\n");
840 error = ENXIO;
841 goto fail;
842 }
843
844 /*
845 * Reset the adapter. Only take the lock here as it's needed in
846 * order to call rl_reset().
847 */
848 RL_LOCK(sc);
849 rl_reset(sc);
850 RL_UNLOCK(sc);
851
852 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
853 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
854 if (rl_did != 0x8129)
855 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
856
857 /*
858 * Get station address from the EEPROM.
859 */
860 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
861 for (i = 0; i < 3; i++) {
862 eaddr[(i * 2) + 0] = as[i] & 0xff;
863 eaddr[(i * 2) + 1] = as[i] >> 8;
864 }
865
866 /*
867 * Now read the exact device type from the EEPROM to find
868 * out if it's an 8129 or 8139.
869 */
870 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
871
872 t = rl_devs;
873 sc->rl_type = 0;
874 while(t->rl_name != NULL) {
875 if (rl_did == t->rl_did) {
876 sc->rl_type = t->rl_basetype;
877 break;
878 }
879 t++;
880 }
881
882 if (sc->rl_type == 0) {
883 device_printf(dev, "unknown device ID: %x\n", rl_did);
884 error = ENXIO;
885 goto fail;
886 }
887
888 /*
889 * Allocate the parent bus DMA tag appropriate for PCI.
890 */
891 #define RL_NSEG_NEW 32
892 error = bus_dma_tag_create(NULL, /* parent */
893 1, 0, /* alignment, boundary */
894 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
895 BUS_SPACE_MAXADDR, /* highaddr */
896 NULL, NULL, /* filter, filterarg */
897 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
898 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
899 BUS_DMA_ALLOCNOW, /* flags */
900 NULL, NULL, /* lockfunc, lockarg */
901 &sc->rl_parent_tag);
902 if (error)
903 goto fail;
904
905 /*
906 * Now allocate a tag for the DMA descriptor lists.
907 * All of our lists are allocated as a contiguous block
908 * of memory.
909 */
910 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
911 1, 0, /* alignment, boundary */
912 BUS_SPACE_MAXADDR, /* lowaddr */
913 BUS_SPACE_MAXADDR, /* highaddr */
914 NULL, NULL, /* filter, filterarg */
915 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
916 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
917 BUS_DMA_ALLOCNOW, /* flags */
918 NULL, NULL, /* lockfunc, lockarg */
919 &sc->rl_tag);
920 if (error)
921 goto fail;
922
923 /*
924 * Now allocate a chunk of DMA-able memory based on the
925 * tag we just created.
926 */
927 error = bus_dmamem_alloc(sc->rl_tag,
928 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
929 &sc->rl_cdata.rl_rx_dmamap);
930 if (error) {
931 device_printf(dev, "no memory for list buffers!\n");
932 bus_dma_tag_destroy(sc->rl_tag);
933 sc->rl_tag = NULL;
934 goto fail;
935 }
936
937 /* Leave a few bytes before the start of the RX ring buffer. */
938 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
939 sc->rl_cdata.rl_rx_buf += sizeof(uint64_t);
940
941 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
942 if (ifp == NULL) {
943 device_printf(dev, "can not if_alloc()\n");
944 error = ENOSPC;
945 goto fail;
946 }
947
948 /* Do MII setup */
949 if (mii_phy_probe(dev, &sc->rl_miibus,
950 rl_ifmedia_upd, rl_ifmedia_sts)) {
951 device_printf(dev, "MII without any phy!\n");
952 error = ENXIO;
953 goto fail;
954 }
955
956 ifp->if_softc = sc;
957 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
958 ifp->if_mtu = ETHERMTU;
959 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
960 ifp->if_ioctl = rl_ioctl;
961 ifp->if_start = rl_start;
962 ifp->if_watchdog = rl_watchdog;
963 ifp->if_init = rl_init;
964 ifp->if_capabilities = IFCAP_VLAN_MTU;
965 ifp->if_capenable = ifp->if_capabilities;
966 #ifdef DEVICE_POLLING
967 ifp->if_capabilities |= IFCAP_POLLING;
968 #endif
969 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
970 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
971 IFQ_SET_READY(&ifp->if_snd);
972
973 /*
974 * Call MI attach routine.
975 */
976 ether_ifattach(ifp, eaddr);
977
978 /* Hook interrupt last to avoid having to lock softc */
979 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE,
980 rl_intr, sc, &sc->rl_intrhand);
981 if (error) {
982 device_printf(sc->rl_dev, "couldn't set up irq\n");
983 ether_ifdetach(ifp);
984 }
985
986 fail:
987 if (error)
988 rl_detach(dev);
989
990 return (error);
991 }
992
993 /*
994 * Shutdown hardware and free up resources. This can be called any
995 * time after the mutex has been initialized. It is called in both
996 * the error case in attach and the normal detach case so it needs
997 * to be careful about only freeing resources that have actually been
998 * allocated.
999 */
1000 static int
1001 rl_detach(device_t dev)
1002 {
1003 struct rl_softc *sc;
1004 struct ifnet *ifp;
1005
1006 sc = device_get_softc(dev);
1007 ifp = sc->rl_ifp;
1008
1009 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
1010 #ifdef DEVICE_POLLING
1011 if (ifp->if_capenable & IFCAP_POLLING)
1012 ether_poll_deregister(ifp);
1013 #endif
1014 /* These should only be active if attach succeeded */
1015 if (device_is_attached(dev)) {
1016 RL_LOCK(sc);
1017 rl_stop(sc);
1018 RL_UNLOCK(sc);
1019 callout_drain(&sc->rl_stat_callout);
1020 ether_ifdetach(ifp);
1021 }
1022 #if 0
1023 sc->suspended = 1;
1024 #endif
1025 if (ifp)
1026 if_free(ifp);
1027 if (sc->rl_miibus)
1028 device_delete_child(dev, sc->rl_miibus);
1029 bus_generic_detach(dev);
1030
1031 if (sc->rl_intrhand)
1032 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1033 if (sc->rl_irq)
1034 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1035 if (sc->rl_res)
1036 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1037
1038 if (sc->rl_tag) {
1039 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1040 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1041 sc->rl_cdata.rl_rx_dmamap);
1042 bus_dma_tag_destroy(sc->rl_tag);
1043 }
1044 if (sc->rl_parent_tag)
1045 bus_dma_tag_destroy(sc->rl_parent_tag);
1046
1047 mtx_destroy(&sc->rl_mtx);
1048
1049 return (0);
1050 }
1051
1052 /*
1053 * Initialize the transmit descriptors.
1054 */
1055 static int
1056 rl_list_tx_init(struct rl_softc *sc)
1057 {
1058 struct rl_chain_data *cd;
1059 int i;
1060
1061 RL_LOCK_ASSERT(sc);
1062
1063 cd = &sc->rl_cdata;
1064 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1065 cd->rl_tx_chain[i] = NULL;
1066 CSR_WRITE_4(sc,
1067 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1068 }
1069
1070 sc->rl_cdata.cur_tx = 0;
1071 sc->rl_cdata.last_tx = 0;
1072
1073 return (0);
1074 }
1075
1076 /*
1077 * A frame has been uploaded: pass the resulting mbuf chain up to
1078 * the higher level protocols.
1079 *
1080 * You know there's something wrong with a PCI bus-master chip design
1081 * when you have to use m_devget().
1082 *
1083 * The receive operation is badly documented in the datasheet, so I'll
1084 * attempt to document it here. The driver provides a buffer area and
1085 * places its base address in the RX buffer start address register.
1086 * The chip then begins copying frames into the RX buffer. Each frame
1087 * is preceded by a 32-bit RX status word which specifies the length
1088 * of the frame and certain other status bits. Each frame (starting with
1089 * the status word) is also 32-bit aligned. The frame length is in the
1090 * first 16 bits of the status word; the lower 15 bits correspond with
1091 * the 'rx status register' mentioned in the datasheet.
1092 *
1093 * Note: to make the Alpha happy, the frame payload needs to be aligned
1094 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1095 * as the offset argument to m_devget().
1096 */
1097 static void
1098 rl_rxeof(struct rl_softc *sc)
1099 {
1100 struct mbuf *m;
1101 struct ifnet *ifp = sc->rl_ifp;
1102 uint8_t *rxbufpos;
1103 int total_len = 0;
1104 int wrap = 0;
1105 uint32_t rxstat;
1106 uint16_t cur_rx;
1107 uint16_t limit;
1108 uint16_t max_bytes, rx_bytes = 0;
1109
1110 RL_LOCK_ASSERT(sc);
1111
1112 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1113 BUS_DMASYNC_POSTREAD);
1114
1115 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1116
1117 /* Do not try to read past this point. */
1118 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1119
1120 if (limit < cur_rx)
1121 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1122 else
1123 max_bytes = limit - cur_rx;
1124
1125 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1126 #ifdef DEVICE_POLLING
1127 if (ifp->if_capenable & IFCAP_POLLING) {
1128 if (sc->rxcycles <= 0)
1129 break;
1130 sc->rxcycles--;
1131 }
1132 #endif
1133 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1134 rxstat = le32toh(*(uint32_t *)rxbufpos);
1135
1136 /*
1137 * Here's a totally undocumented fact for you. When the
1138 * RealTek chip is in the process of copying a packet into
1139 * RAM for you, the length will be 0xfff0. If you spot a
1140 * packet header with this value, you need to stop. The
1141 * datasheet makes absolutely no mention of this and
1142 * RealTek should be shot for this.
1143 */
1144 total_len = rxstat >> 16;
1145 if (total_len == RL_RXSTAT_UNFINISHED)
1146 break;
1147
1148 if (!(rxstat & RL_RXSTAT_RXOK) ||
1149 total_len < ETHER_MIN_LEN ||
1150 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
1151 ifp->if_ierrors++;
1152 rl_init_locked(sc);
1153 return;
1154 }
1155
1156 /* No errors; receive the packet. */
1157 rx_bytes += total_len + 4;
1158
1159 /*
1160 * XXX The RealTek chip includes the CRC with every
1161 * received frame, and there's no way to turn this
1162 * behavior off (at least, I can't find anything in
1163 * the manual that explains how to do it) so we have
1164 * to trim off the CRC manually.
1165 */
1166 total_len -= ETHER_CRC_LEN;
1167
1168 /*
1169 * Avoid trying to read more bytes than we know
1170 * the chip has prepared for us.
1171 */
1172 if (rx_bytes > max_bytes)
1173 break;
1174
1175 rxbufpos = sc->rl_cdata.rl_rx_buf +
1176 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1177 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1178 rxbufpos = sc->rl_cdata.rl_rx_buf;
1179
1180 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1181 if (total_len > wrap) {
1182 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1183 NULL);
1184 if (m == NULL) {
1185 ifp->if_ierrors++;
1186 } else {
1187 m_copyback(m, wrap, total_len - wrap,
1188 sc->rl_cdata.rl_rx_buf);
1189 }
1190 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1191 } else {
1192 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1193 NULL);
1194 if (m == NULL)
1195 ifp->if_ierrors++;
1196 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1197 }
1198
1199 /* Round up to 32-bit boundary. */
1200 cur_rx = (cur_rx + 3) & ~3;
1201 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1202
1203 if (m == NULL)
1204 continue;
1205
1206 ifp->if_ipackets++;
1207 RL_UNLOCK(sc);
1208 (*ifp->if_input)(ifp, m);
1209 RL_LOCK(sc);
1210 }
1211 }
1212
1213 /*
1214 * A frame was downloaded to the chip. It's safe for us to clean up
1215 * the list buffers.
1216 */
1217 static void
1218 rl_txeof(struct rl_softc *sc)
1219 {
1220 struct ifnet *ifp = sc->rl_ifp;
1221 uint32_t txstat;
1222
1223 RL_LOCK_ASSERT(sc);
1224
1225 /*
1226 * Go through our tx list and free mbufs for those
1227 * frames that have been uploaded.
1228 */
1229 do {
1230 if (RL_LAST_TXMBUF(sc) == NULL)
1231 break;
1232 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1233 if (!(txstat & (RL_TXSTAT_TX_OK|
1234 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1235 break;
1236
1237 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1238
1239 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1240 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1241 m_freem(RL_LAST_TXMBUF(sc));
1242 RL_LAST_TXMBUF(sc) = NULL;
1243 /*
1244 * If there was a transmit underrun, bump the TX threshold.
1245 * Make sure not to overflow the 63 * 32byte we can address
1246 * with the 6 available bit.
1247 */
1248 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1249 (sc->rl_txthresh < 2016))
1250 sc->rl_txthresh += 32;
1251 if (txstat & RL_TXSTAT_TX_OK)
1252 ifp->if_opackets++;
1253 else {
1254 int oldthresh;
1255 ifp->if_oerrors++;
1256 if ((txstat & RL_TXSTAT_TXABRT) ||
1257 (txstat & RL_TXSTAT_OUTOFWIN))
1258 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1259 oldthresh = sc->rl_txthresh;
1260 /* error recovery */
1261 rl_reset(sc);
1262 rl_init_locked(sc);
1263 /* restore original threshold */
1264 sc->rl_txthresh = oldthresh;
1265 return;
1266 }
1267 RL_INC(sc->rl_cdata.last_tx);
1268 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1269 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1270
1271 if (RL_LAST_TXMBUF(sc) == NULL)
1272 ifp->if_timer = 0;
1273 else if (ifp->if_timer == 0)
1274 ifp->if_timer = 5;
1275 }
1276
1277 static void
1278 rl_tick(void *xsc)
1279 {
1280 struct rl_softc *sc = xsc;
1281 struct mii_data *mii;
1282
1283 RL_LOCK_ASSERT(sc);
1284 mii = device_get_softc(sc->rl_miibus);
1285 mii_tick(mii);
1286
1287 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1288 }
1289
1290 #ifdef DEVICE_POLLING
1291 static void
1292 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1293 {
1294 struct rl_softc *sc = ifp->if_softc;
1295
1296 RL_LOCK(sc);
1297 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1298 rl_poll_locked(ifp, cmd, count);
1299 RL_UNLOCK(sc);
1300 }
1301
1302 static void
1303 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1304 {
1305 struct rl_softc *sc = ifp->if_softc;
1306
1307 RL_LOCK_ASSERT(sc);
1308
1309 sc->rxcycles = count;
1310 rl_rxeof(sc);
1311 rl_txeof(sc);
1312
1313 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1314 rl_start_locked(ifp);
1315
1316 if (cmd == POLL_AND_CHECK_STATUS) {
1317 uint16_t status;
1318
1319 /* We should also check the status register. */
1320 status = CSR_READ_2(sc, RL_ISR);
1321 if (status == 0xffff)
1322 return;
1323 if (status != 0)
1324 CSR_WRITE_2(sc, RL_ISR, status);
1325
1326 /* XXX We should check behaviour on receiver stalls. */
1327
1328 if (status & RL_ISR_SYSTEM_ERR) {
1329 rl_reset(sc);
1330 rl_init_locked(sc);
1331 }
1332 }
1333 }
1334 #endif /* DEVICE_POLLING */
1335
1336 static void
1337 rl_intr(void *arg)
1338 {
1339 struct rl_softc *sc = arg;
1340 struct ifnet *ifp = sc->rl_ifp;
1341 uint16_t status;
1342
1343 RL_LOCK(sc);
1344
1345 if (sc->suspended)
1346 goto done_locked;
1347
1348 #ifdef DEVICE_POLLING
1349 if (ifp->if_capenable & IFCAP_POLLING)
1350 goto done_locked;
1351 #endif
1352
1353 for (;;) {
1354 status = CSR_READ_2(sc, RL_ISR);
1355 /* If the card has gone away, the read returns 0xffff. */
1356 if (status == 0xffff)
1357 break;
1358 if (status != 0)
1359 CSR_WRITE_2(sc, RL_ISR, status);
1360 if ((status & RL_INTRS) == 0)
1361 break;
1362 if (status & RL_ISR_RX_OK)
1363 rl_rxeof(sc);
1364 if (status & RL_ISR_RX_ERR)
1365 rl_rxeof(sc);
1366 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1367 rl_txeof(sc);
1368 if (status & RL_ISR_SYSTEM_ERR) {
1369 rl_reset(sc);
1370 rl_init_locked(sc);
1371 }
1372 }
1373
1374 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1375 rl_start_locked(ifp);
1376
1377 done_locked:
1378 RL_UNLOCK(sc);
1379 }
1380
1381 /*
1382 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1383 * pointers to the fragment pointers.
1384 */
1385 static int
1386 rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1387 {
1388 struct mbuf *m_new = NULL;
1389
1390 RL_LOCK_ASSERT(sc);
1391
1392 /*
1393 * The RealTek is brain damaged and wants longword-aligned
1394 * TX buffers, plus we can only have one fragment buffer
1395 * per packet. We have to copy pretty much all the time.
1396 */
1397 m_new = m_defrag(m_head, M_DONTWAIT);
1398
1399 if (m_new == NULL) {
1400 m_freem(m_head);
1401 return (1);
1402 }
1403 m_head = m_new;
1404
1405 /* Pad frames to at least 60 bytes. */
1406 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1407 /*
1408 * Make security concious people happy: zero out the
1409 * bytes in the pad area, since we don't know what
1410 * this mbuf cluster buffer's previous user might
1411 * have left in it.
1412 */
1413 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1414 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1415 m_head->m_pkthdr.len +=
1416 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1417 m_head->m_len = m_head->m_pkthdr.len;
1418 }
1419
1420 RL_CUR_TXMBUF(sc) = m_head;
1421
1422 return (0);
1423 }
1424
1425 /*
1426 * Main transmit routine.
1427 */
1428 static void
1429 rl_start(struct ifnet *ifp)
1430 {
1431 struct rl_softc *sc = ifp->if_softc;
1432
1433 RL_LOCK(sc);
1434 rl_start_locked(ifp);
1435 RL_UNLOCK(sc);
1436 }
1437
1438 static void
1439 rl_start_locked(struct ifnet *ifp)
1440 {
1441 struct rl_softc *sc = ifp->if_softc;
1442 struct mbuf *m_head = NULL;
1443
1444 RL_LOCK_ASSERT(sc);
1445
1446 while (RL_CUR_TXMBUF(sc) == NULL) {
1447
1448 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1449
1450 if (m_head == NULL)
1451 break;
1452
1453 if (rl_encap(sc, m_head))
1454 break;
1455
1456 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1457 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1458
1459 /* Transmit the frame. */
1460 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1461 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1462 mtod(RL_CUR_TXMBUF(sc), void *),
1463 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
1464 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1465 BUS_DMASYNC_PREREAD);
1466 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1467 RL_TXTHRESH(sc->rl_txthresh) |
1468 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1469
1470 RL_INC(sc->rl_cdata.cur_tx);
1471
1472 /* Set a timeout in case the chip goes out to lunch. */
1473 ifp->if_timer = 5;
1474 }
1475
1476 /*
1477 * We broke out of the loop because all our TX slots are
1478 * full. Mark the NIC as busy until it drains some of the
1479 * packets from the queue.
1480 */
1481 if (RL_CUR_TXMBUF(sc) != NULL)
1482 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1483 }
1484
1485 static void
1486 rl_init(void *xsc)
1487 {
1488 struct rl_softc *sc = xsc;
1489
1490 RL_LOCK(sc);
1491 rl_init_locked(sc);
1492 RL_UNLOCK(sc);
1493 }
1494
1495 static void
1496 rl_init_locked(struct rl_softc *sc)
1497 {
1498 struct ifnet *ifp = sc->rl_ifp;
1499 struct mii_data *mii;
1500 uint32_t rxcfg = 0;
1501 uint32_t eaddr[2];
1502
1503 RL_LOCK_ASSERT(sc);
1504
1505 mii = device_get_softc(sc->rl_miibus);
1506
1507 /*
1508 * Cancel pending I/O and free all RX/TX buffers.
1509 */
1510 rl_stop(sc);
1511
1512 /*
1513 * Init our MAC address. Even though the chipset
1514 * documentation doesn't mention it, we need to enter "Config
1515 * register write enable" mode to modify the ID registers.
1516 */
1517 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1518 bzero(eaddr, sizeof(eaddr));
1519 bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1520 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1521 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1522 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1523
1524 /* Init the RX buffer pointer register. */
1525 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1526 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1527 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1528 BUS_DMASYNC_PREWRITE);
1529
1530 /* Init TX descriptors. */
1531 rl_list_tx_init(sc);
1532
1533 /*
1534 * Enable transmit and receive.
1535 */
1536 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1537
1538 /*
1539 * Set the initial TX and RX configuration.
1540 */
1541 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1542 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1543
1544 /* Set the individual bit to receive frames for this host only. */
1545 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1546 rxcfg |= RL_RXCFG_RX_INDIV;
1547
1548 /* If we want promiscuous mode, set the allframes bit. */
1549 if (ifp->if_flags & IFF_PROMISC) {
1550 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1551 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1552 } else {
1553 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1554 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1555 }
1556
1557 /* Set capture broadcast bit to capture broadcast frames. */
1558 if (ifp->if_flags & IFF_BROADCAST) {
1559 rxcfg |= RL_RXCFG_RX_BROAD;
1560 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1561 } else {
1562 rxcfg &= ~RL_RXCFG_RX_BROAD;
1563 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1564 }
1565
1566 /* Program the multicast filter, if necessary. */
1567 rl_setmulti(sc);
1568
1569 #ifdef DEVICE_POLLING
1570 /* Disable interrupts if we are polling. */
1571 if (ifp->if_capenable & IFCAP_POLLING)
1572 CSR_WRITE_2(sc, RL_IMR, 0);
1573 else
1574 #endif
1575 /* Enable interrupts. */
1576 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1577
1578 /* Set initial TX threshold */
1579 sc->rl_txthresh = RL_TX_THRESH_INIT;
1580
1581 /* Start RX/TX process. */
1582 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1583
1584 /* Enable receiver and transmitter. */
1585 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1586
1587 mii_mediachg(mii);
1588
1589 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1590
1591 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1592 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1593
1594 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1595 }
1596
1597 /*
1598 * Set media options.
1599 */
1600 static int
1601 rl_ifmedia_upd(struct ifnet *ifp)
1602 {
1603 struct rl_softc *sc = ifp->if_softc;
1604 struct mii_data *mii;
1605
1606 mii = device_get_softc(sc->rl_miibus);
1607
1608 RL_LOCK(sc);
1609 mii_mediachg(mii);
1610 RL_UNLOCK(sc);
1611
1612 return (0);
1613 }
1614
1615 /*
1616 * Report current media status.
1617 */
1618 static void
1619 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1620 {
1621 struct rl_softc *sc = ifp->if_softc;
1622 struct mii_data *mii;
1623
1624 mii = device_get_softc(sc->rl_miibus);
1625
1626 RL_LOCK(sc);
1627 mii_pollstat(mii);
1628 RL_UNLOCK(sc);
1629 ifmr->ifm_active = mii->mii_media_active;
1630 ifmr->ifm_status = mii->mii_media_status;
1631 }
1632
1633 static int
1634 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1635 {
1636 struct ifreq *ifr = (struct ifreq *)data;
1637 struct mii_data *mii;
1638 struct rl_softc *sc = ifp->if_softc;
1639 int error = 0;
1640
1641 switch (command) {
1642 case SIOCSIFFLAGS:
1643 RL_LOCK(sc);
1644 if (ifp->if_flags & IFF_UP) {
1645 rl_init_locked(sc);
1646 } else {
1647 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1648 rl_stop(sc);
1649 }
1650 RL_UNLOCK(sc);
1651 error = 0;
1652 break;
1653 case SIOCADDMULTI:
1654 case SIOCDELMULTI:
1655 RL_LOCK(sc);
1656 rl_setmulti(sc);
1657 RL_UNLOCK(sc);
1658 error = 0;
1659 break;
1660 case SIOCGIFMEDIA:
1661 case SIOCSIFMEDIA:
1662 mii = device_get_softc(sc->rl_miibus);
1663 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1664 break;
1665 case SIOCSIFCAP:
1666 #ifdef DEVICE_POLLING
1667 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1668 !(ifp->if_capenable & IFCAP_POLLING)) {
1669 error = ether_poll_register(rl_poll, ifp);
1670 if (error)
1671 return(error);
1672 RL_LOCK(sc);
1673 /* Disable interrupts */
1674 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1675 ifp->if_capenable |= IFCAP_POLLING;
1676 RL_UNLOCK(sc);
1677 return (error);
1678
1679 }
1680 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1681 ifp->if_capenable & IFCAP_POLLING) {
1682 error = ether_poll_deregister(ifp);
1683 /* Enable interrupts. */
1684 RL_LOCK(sc);
1685 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1686 ifp->if_capenable &= ~IFCAP_POLLING;
1687 RL_UNLOCK(sc);
1688 return (error);
1689 }
1690 #endif /* DEVICE_POLLING */
1691 break;
1692 default:
1693 error = ether_ioctl(ifp, command, data);
1694 break;
1695 }
1696
1697 return (error);
1698 }
1699
1700 static void
1701 rl_watchdog(struct ifnet *ifp)
1702 {
1703 struct rl_softc *sc = ifp->if_softc;
1704
1705 RL_LOCK(sc);
1706
1707 if_printf(ifp, "watchdog timeout\n");
1708 ifp->if_oerrors++;
1709
1710 rl_txeof(sc);
1711 rl_rxeof(sc);
1712 rl_init_locked(sc);
1713
1714 RL_UNLOCK(sc);
1715 }
1716
1717 /*
1718 * Stop the adapter and free any mbufs allocated to the
1719 * RX and TX lists.
1720 */
1721 static void
1722 rl_stop(struct rl_softc *sc)
1723 {
1724 register int i;
1725 struct ifnet *ifp = sc->rl_ifp;
1726
1727 RL_LOCK_ASSERT(sc);
1728
1729 ifp->if_timer = 0;
1730 callout_stop(&sc->rl_stat_callout);
1731 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1732
1733 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1734 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1735 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1736
1737 /*
1738 * Free the TX list buffers.
1739 */
1740 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1741 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1742 bus_dmamap_unload(sc->rl_tag,
1743 sc->rl_cdata.rl_tx_dmamap[i]);
1744 bus_dmamap_destroy(sc->rl_tag,
1745 sc->rl_cdata.rl_tx_dmamap[i]);
1746 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1747 sc->rl_cdata.rl_tx_chain[i] = NULL;
1748 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1749 0x0000000);
1750 }
1751 }
1752 }
1753
1754 /*
1755 * Device suspend routine. Stop the interface and save some PCI
1756 * settings in case the BIOS doesn't restore them properly on
1757 * resume.
1758 */
1759 static int
1760 rl_suspend(device_t dev)
1761 {
1762 struct rl_softc *sc;
1763
1764 sc = device_get_softc(dev);
1765
1766 RL_LOCK(sc);
1767 rl_stop(sc);
1768 sc->suspended = 1;
1769 RL_UNLOCK(sc);
1770
1771 return (0);
1772 }
1773
1774 /*
1775 * Device resume routine. Restore some PCI settings in case the BIOS
1776 * doesn't, re-enable busmastering, and restart the interface if
1777 * appropriate.
1778 */
1779 static int
1780 rl_resume(device_t dev)
1781 {
1782 struct rl_softc *sc;
1783 struct ifnet *ifp;
1784
1785 sc = device_get_softc(dev);
1786 ifp = sc->rl_ifp;
1787
1788 RL_LOCK(sc);
1789
1790 /* reinitialize interface if necessary */
1791 if (ifp->if_flags & IFF_UP)
1792 rl_init_locked(sc);
1793
1794 sc->suspended = 0;
1795
1796 RL_UNLOCK(sc);
1797
1798 return (0);
1799 }
1800
1801 /*
1802 * Stop all chip I/O so that the kernel's probe routines don't
1803 * get confused by errant DMAs when rebooting.
1804 */
1805 static void
1806 rl_shutdown(device_t dev)
1807 {
1808 struct rl_softc *sc;
1809
1810 sc = device_get_softc(dev);
1811
1812 RL_LOCK(sc);
1813 rl_stop(sc);
1814 RL_UNLOCK(sc);
1815 }
Cache object: 9857e7ddb29b60922ee78e9680a0effd
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