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sys/pci/if_rl.c
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1 /*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/9.1/sys/pci/if_rl.c 233489 2012-03-26 03:54:19Z yongari $"); 35 36 /* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 /* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86 #ifdef HAVE_KERNEL_OPTION_HEADERS 87 #include "opt_device_polling.h" 88 #endif 89 90 #include <sys/param.h> 91 #include <sys/endian.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/module.h> 98 #include <sys/socket.h> 99 #include <sys/sysctl.h> 100 101 #include <net/if.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_types.h> 107 108 #include <net/bpf.h> 109 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #include <dev/mii/mii.h> 116 #include <dev/mii/mii_bitbang.h> 117 #include <dev/mii/miivar.h> 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pcivar.h> 121 122 MODULE_DEPEND(rl, pci, 1, 1, 1); 123 MODULE_DEPEND(rl, ether, 1, 1, 1); 124 MODULE_DEPEND(rl, miibus, 1, 1, 1); 125 126 /* "device miibus" required. See GENERIC if you get errors here. */ 127 #include "miibus_if.h" 128 129 #include <pci/if_rlreg.h> 130 131 /* 132 * Various supported device vendors/types and their names. 133 */ 134 static const struct rl_type const rl_devs[] = { 135 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 136 "RealTek 8129 10/100BaseTX" }, 137 { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 138 "RealTek 8139 10/100BaseTX" }, 139 { RT_VENDORID, RT_DEVICEID_8139D, RL_8139, 140 "RealTek 8139 10/100BaseTX" }, 141 { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 142 "RealTek 8139 10/100BaseTX CardBus" }, 143 { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 144 "RealTek 8100 10/100BaseTX" }, 145 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 146 "Accton MPX 5030/5038 10/100BaseTX" }, 147 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 148 "Delta Electronics 8139 10/100BaseTX" }, 149 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 150 "Addtron Technology 8139 10/100BaseTX" }, 151 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 152 "D-Link DFE-530TX+ 10/100BaseTX" }, 153 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 154 "D-Link DFE-690TXD 10/100BaseTX" }, 155 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 156 "Nortel Networks 10/100BaseTX" }, 157 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 158 "Corega FEther CB-TXD" }, 159 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 160 "Corega FEtherII CB-TXD" }, 161 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 162 "Peppercon AG ROL-F" }, 163 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139, 164 "Planex FNW-3603-TX" }, 165 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 166 "Planex FNW-3800-TX" }, 167 { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 168 "Compaq HNE-300" }, 169 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 170 "LevelOne FPC-0106TX" }, 171 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 172 "Edimax EP-4103DL CardBus" } 173 }; 174 175 static int rl_attach(device_t); 176 static int rl_detach(device_t); 177 static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int); 178 static int rl_dma_alloc(struct rl_softc *); 179 static void rl_dma_free(struct rl_softc *); 180 static void rl_eeprom_putbyte(struct rl_softc *, int); 181 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 182 static int rl_encap(struct rl_softc *, struct mbuf **); 183 static int rl_list_tx_init(struct rl_softc *); 184 static int rl_list_rx_init(struct rl_softc *); 185 static int rl_ifmedia_upd(struct ifnet *); 186 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 187 static int rl_ioctl(struct ifnet *, u_long, caddr_t); 188 static void rl_intr(void *); 189 static void rl_init(void *); 190 static void rl_init_locked(struct rl_softc *sc); 191 static int rl_miibus_readreg(device_t, int, int); 192 static void rl_miibus_statchg(device_t); 193 static int rl_miibus_writereg(device_t, int, int, int); 194 #ifdef DEVICE_POLLING 195 static int rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 196 static int rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 197 #endif 198 static int rl_probe(device_t); 199 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int); 200 static void rl_reset(struct rl_softc *); 201 static int rl_resume(device_t); 202 static int rl_rxeof(struct rl_softc *); 203 static void rl_rxfilter(struct rl_softc *); 204 static int rl_shutdown(device_t); 205 static void rl_start(struct ifnet *); 206 static void rl_start_locked(struct ifnet *); 207 static void rl_stop(struct rl_softc *); 208 static int rl_suspend(device_t); 209 static void rl_tick(void *); 210 static void rl_txeof(struct rl_softc *); 211 static void rl_watchdog(struct rl_softc *); 212 static void rl_setwol(struct rl_softc *); 213 static void rl_clrwol(struct rl_softc *); 214 215 /* 216 * MII bit-bang glue 217 */ 218 static uint32_t rl_mii_bitbang_read(device_t); 219 static void rl_mii_bitbang_write(device_t, uint32_t); 220 221 static const struct mii_bitbang_ops rl_mii_bitbang_ops = { 222 rl_mii_bitbang_read, 223 rl_mii_bitbang_write, 224 { 225 RL_MII_DATAOUT, /* MII_BIT_MDO */ 226 RL_MII_DATAIN, /* MII_BIT_MDI */ 227 RL_MII_CLK, /* MII_BIT_MDC */ 228 RL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 229 0, /* MII_BIT_DIR_PHY_HOST */ 230 } 231 }; 232 233 static device_method_t rl_methods[] = { 234 /* Device interface */ 235 DEVMETHOD(device_probe, rl_probe), 236 DEVMETHOD(device_attach, rl_attach), 237 DEVMETHOD(device_detach, rl_detach), 238 DEVMETHOD(device_suspend, rl_suspend), 239 DEVMETHOD(device_resume, rl_resume), 240 DEVMETHOD(device_shutdown, rl_shutdown), 241 242 /* MII interface */ 243 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 244 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 245 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 246 247 DEVMETHOD_END 248 }; 249 250 static driver_t rl_driver = { 251 "rl", 252 rl_methods, 253 sizeof(struct rl_softc) 254 }; 255 256 static devclass_t rl_devclass; 257 258 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 259 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 260 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 261 262 #define EE_SET(x) \ 263 CSR_WRITE_1(sc, RL_EECMD, \ 264 CSR_READ_1(sc, RL_EECMD) | x) 265 266 #define EE_CLR(x) \ 267 CSR_WRITE_1(sc, RL_EECMD, \ 268 CSR_READ_1(sc, RL_EECMD) & ~x) 269 270 /* 271 * Send a read command and address to the EEPROM, check for ACK. 272 */ 273 static void 274 rl_eeprom_putbyte(struct rl_softc *sc, int addr) 275 { 276 register int d, i; 277 278 d = addr | sc->rl_eecmd_read; 279 280 /* 281 * Feed in each bit and strobe the clock. 282 */ 283 for (i = 0x400; i; i >>= 1) { 284 if (d & i) { 285 EE_SET(RL_EE_DATAIN); 286 } else { 287 EE_CLR(RL_EE_DATAIN); 288 } 289 DELAY(100); 290 EE_SET(RL_EE_CLK); 291 DELAY(150); 292 EE_CLR(RL_EE_CLK); 293 DELAY(100); 294 } 295 } 296 297 /* 298 * Read a word of data stored in the EEPROM at address 'addr.' 299 */ 300 static void 301 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 302 { 303 register int i; 304 uint16_t word = 0; 305 306 /* Enter EEPROM access mode. */ 307 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 308 309 /* 310 * Send address of word we want to read. 311 */ 312 rl_eeprom_putbyte(sc, addr); 313 314 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 315 316 /* 317 * Start reading bits from EEPROM. 318 */ 319 for (i = 0x8000; i; i >>= 1) { 320 EE_SET(RL_EE_CLK); 321 DELAY(100); 322 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 323 word |= i; 324 EE_CLR(RL_EE_CLK); 325 DELAY(100); 326 } 327 328 /* Turn off EEPROM access mode. */ 329 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 330 331 *dest = word; 332 } 333 334 /* 335 * Read a sequence of words from the EEPROM. 336 */ 337 static void 338 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap) 339 { 340 int i; 341 uint16_t word = 0, *ptr; 342 343 for (i = 0; i < cnt; i++) { 344 rl_eeprom_getword(sc, off + i, &word); 345 ptr = (uint16_t *)(dest + (i * 2)); 346 if (swap) 347 *ptr = ntohs(word); 348 else 349 *ptr = word; 350 } 351 } 352 353 /* 354 * Read the MII serial port for the MII bit-bang module. 355 */ 356 static uint32_t 357 rl_mii_bitbang_read(device_t dev) 358 { 359 struct rl_softc *sc; 360 uint32_t val; 361 362 sc = device_get_softc(dev); 363 364 val = CSR_READ_1(sc, RL_MII); 365 CSR_BARRIER(sc, RL_MII, 1, 366 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 367 368 return (val); 369 } 370 371 /* 372 * Write the MII serial port for the MII bit-bang module. 373 */ 374 static void 375 rl_mii_bitbang_write(device_t dev, uint32_t val) 376 { 377 struct rl_softc *sc; 378 379 sc = device_get_softc(dev); 380 381 CSR_WRITE_1(sc, RL_MII, val); 382 CSR_BARRIER(sc, RL_MII, 1, 383 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 384 } 385 386 static int 387 rl_miibus_readreg(device_t dev, int phy, int reg) 388 { 389 struct rl_softc *sc; 390 uint16_t rl8139_reg; 391 392 sc = device_get_softc(dev); 393 394 if (sc->rl_type == RL_8139) { 395 switch (reg) { 396 case MII_BMCR: 397 rl8139_reg = RL_BMCR; 398 break; 399 case MII_BMSR: 400 rl8139_reg = RL_BMSR; 401 break; 402 case MII_ANAR: 403 rl8139_reg = RL_ANAR; 404 break; 405 case MII_ANER: 406 rl8139_reg = RL_ANER; 407 break; 408 case MII_ANLPAR: 409 rl8139_reg = RL_LPAR; 410 break; 411 case MII_PHYIDR1: 412 case MII_PHYIDR2: 413 return (0); 414 /* 415 * Allow the rlphy driver to read the media status 416 * register. If we have a link partner which does not 417 * support NWAY, this is the register which will tell 418 * us the results of parallel detection. 419 */ 420 case RL_MEDIASTAT: 421 return (CSR_READ_1(sc, RL_MEDIASTAT)); 422 default: 423 device_printf(sc->rl_dev, "bad phy register\n"); 424 return (0); 425 } 426 return (CSR_READ_2(sc, rl8139_reg)); 427 } 428 429 return (mii_bitbang_readreg(dev, &rl_mii_bitbang_ops, phy, reg)); 430 } 431 432 static int 433 rl_miibus_writereg(device_t dev, int phy, int reg, int data) 434 { 435 struct rl_softc *sc; 436 uint16_t rl8139_reg; 437 438 sc = device_get_softc(dev); 439 440 if (sc->rl_type == RL_8139) { 441 switch (reg) { 442 case MII_BMCR: 443 rl8139_reg = RL_BMCR; 444 break; 445 case MII_BMSR: 446 rl8139_reg = RL_BMSR; 447 break; 448 case MII_ANAR: 449 rl8139_reg = RL_ANAR; 450 break; 451 case MII_ANER: 452 rl8139_reg = RL_ANER; 453 break; 454 case MII_ANLPAR: 455 rl8139_reg = RL_LPAR; 456 break; 457 case MII_PHYIDR1: 458 case MII_PHYIDR2: 459 return (0); 460 break; 461 default: 462 device_printf(sc->rl_dev, "bad phy register\n"); 463 return (0); 464 } 465 CSR_WRITE_2(sc, rl8139_reg, data); 466 return (0); 467 } 468 469 mii_bitbang_writereg(dev, &rl_mii_bitbang_ops, phy, reg, data); 470 471 return (0); 472 } 473 474 static void 475 rl_miibus_statchg(device_t dev) 476 { 477 struct rl_softc *sc; 478 struct ifnet *ifp; 479 struct mii_data *mii; 480 481 sc = device_get_softc(dev); 482 mii = device_get_softc(sc->rl_miibus); 483 ifp = sc->rl_ifp; 484 if (mii == NULL || ifp == NULL || 485 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 486 return; 487 488 sc->rl_flags &= ~RL_FLAG_LINK; 489 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 490 (IFM_ACTIVE | IFM_AVALID)) { 491 switch (IFM_SUBTYPE(mii->mii_media_active)) { 492 case IFM_10_T: 493 case IFM_100_TX: 494 sc->rl_flags |= RL_FLAG_LINK; 495 break; 496 default: 497 break; 498 } 499 } 500 /* 501 * RealTek controllers do not provide any interface to 502 * Tx/Rx MACs for resolved speed, duplex and flow-control 503 * parameters. 504 */ 505 } 506 507 /* 508 * Program the 64-bit multicast hash filter. 509 */ 510 static void 511 rl_rxfilter(struct rl_softc *sc) 512 { 513 struct ifnet *ifp = sc->rl_ifp; 514 int h = 0; 515 uint32_t hashes[2] = { 0, 0 }; 516 struct ifmultiaddr *ifma; 517 uint32_t rxfilt; 518 519 RL_LOCK_ASSERT(sc); 520 521 rxfilt = CSR_READ_4(sc, RL_RXCFG); 522 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD | 523 RL_RXCFG_RX_MULTI); 524 /* Always accept frames destined for this host. */ 525 rxfilt |= RL_RXCFG_RX_INDIV; 526 /* Set capture broadcast bit to capture broadcast frames. */ 527 if (ifp->if_flags & IFF_BROADCAST) 528 rxfilt |= RL_RXCFG_RX_BROAD; 529 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 530 rxfilt |= RL_RXCFG_RX_MULTI; 531 if (ifp->if_flags & IFF_PROMISC) 532 rxfilt |= RL_RXCFG_RX_ALLPHYS; 533 hashes[0] = 0xFFFFFFFF; 534 hashes[1] = 0xFFFFFFFF; 535 } else { 536 /* Now program new ones. */ 537 if_maddr_rlock(ifp); 538 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 539 if (ifma->ifma_addr->sa_family != AF_LINK) 540 continue; 541 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 542 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 543 if (h < 32) 544 hashes[0] |= (1 << h); 545 else 546 hashes[1] |= (1 << (h - 32)); 547 } 548 if_maddr_runlock(ifp); 549 if (hashes[0] != 0 || hashes[1] != 0) 550 rxfilt |= RL_RXCFG_RX_MULTI; 551 } 552 553 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 554 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 555 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 556 } 557 558 static void 559 rl_reset(struct rl_softc *sc) 560 { 561 register int i; 562 563 RL_LOCK_ASSERT(sc); 564 565 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 566 567 for (i = 0; i < RL_TIMEOUT; i++) { 568 DELAY(10); 569 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 570 break; 571 } 572 if (i == RL_TIMEOUT) 573 device_printf(sc->rl_dev, "reset never completed!\n"); 574 } 575 576 /* 577 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 578 * IDs against our list and return a device name if we find a match. 579 */ 580 static int 581 rl_probe(device_t dev) 582 { 583 const struct rl_type *t; 584 uint16_t devid, revid, vendor; 585 int i; 586 587 vendor = pci_get_vendor(dev); 588 devid = pci_get_device(dev); 589 revid = pci_get_revid(dev); 590 591 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 592 if (revid == 0x20) { 593 /* 8139C+, let re(4) take care of this device. */ 594 return (ENXIO); 595 } 596 } 597 t = rl_devs; 598 for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) { 599 if (vendor == t->rl_vid && devid == t->rl_did) { 600 device_set_desc(dev, t->rl_name); 601 return (BUS_PROBE_DEFAULT); 602 } 603 } 604 605 return (ENXIO); 606 } 607 608 struct rl_dmamap_arg { 609 bus_addr_t rl_busaddr; 610 }; 611 612 static void 613 rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 614 { 615 struct rl_dmamap_arg *ctx; 616 617 if (error != 0) 618 return; 619 620 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 621 622 ctx = (struct rl_dmamap_arg *)arg; 623 ctx->rl_busaddr = segs[0].ds_addr; 624 } 625 626 /* 627 * Attach the interface. Allocate softc structures, do ifmedia 628 * setup and ethernet/BPF attach. 629 */ 630 static int 631 rl_attach(device_t dev) 632 { 633 uint8_t eaddr[ETHER_ADDR_LEN]; 634 uint16_t as[3]; 635 struct ifnet *ifp; 636 struct rl_softc *sc; 637 const struct rl_type *t; 638 struct sysctl_ctx_list *ctx; 639 struct sysctl_oid_list *children; 640 int error = 0, hwrev, i, phy, pmc, rid; 641 int prefer_iomap, unit; 642 uint16_t rl_did = 0; 643 char tn[32]; 644 645 sc = device_get_softc(dev); 646 unit = device_get_unit(dev); 647 sc->rl_dev = dev; 648 649 sc->rl_twister_enable = 0; 650 snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit); 651 TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable); 652 ctx = device_get_sysctl_ctx(sc->rl_dev); 653 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 654 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD, 655 &sc->rl_twister_enable, 0, ""); 656 657 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 658 MTX_DEF); 659 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 660 661 pci_enable_busmaster(dev); 662 663 664 /* 665 * Map control/status registers. 666 * Default to using PIO access for this driver. On SMP systems, 667 * there appear to be problems with memory mapped mode: it looks 668 * like doing too many memory mapped access back to back in rapid 669 * succession can hang the bus. I'm inclined to blame this on 670 * crummy design/construction on the part of RealTek. Memory 671 * mapped mode does appear to work on uniprocessor systems though. 672 */ 673 prefer_iomap = 1; 674 snprintf(tn, sizeof(tn), "dev.rl.%d.prefer_iomap", unit); 675 TUNABLE_INT_FETCH(tn, &prefer_iomap); 676 if (prefer_iomap) { 677 sc->rl_res_id = PCIR_BAR(0); 678 sc->rl_res_type = SYS_RES_IOPORT; 679 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 680 &sc->rl_res_id, RF_ACTIVE); 681 } 682 if (prefer_iomap == 0 || sc->rl_res == NULL) { 683 sc->rl_res_id = PCIR_BAR(1); 684 sc->rl_res_type = SYS_RES_MEMORY; 685 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 686 &sc->rl_res_id, RF_ACTIVE); 687 } 688 if (sc->rl_res == NULL) { 689 device_printf(dev, "couldn't map ports/memory\n"); 690 error = ENXIO; 691 goto fail; 692 } 693 694 #ifdef notdef 695 /* 696 * Detect the Realtek 8139B. For some reason, this chip is very 697 * unstable when left to autoselect the media 698 * The best workaround is to set the device to the required 699 * media type or to set it to the 10 Meg speed. 700 */ 701 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF) 702 device_printf(dev, 703 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n"); 704 #endif 705 706 sc->rl_btag = rman_get_bustag(sc->rl_res); 707 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 708 709 /* Allocate interrupt */ 710 rid = 0; 711 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 712 RF_SHAREABLE | RF_ACTIVE); 713 714 if (sc->rl_irq[0] == NULL) { 715 device_printf(dev, "couldn't map interrupt\n"); 716 error = ENXIO; 717 goto fail; 718 } 719 720 sc->rl_cfg0 = RL_8139_CFG0; 721 sc->rl_cfg1 = RL_8139_CFG1; 722 sc->rl_cfg2 = 0; 723 sc->rl_cfg3 = RL_8139_CFG3; 724 sc->rl_cfg4 = RL_8139_CFG4; 725 sc->rl_cfg5 = RL_8139_CFG5; 726 727 /* 728 * Reset the adapter. Only take the lock here as it's needed in 729 * order to call rl_reset(). 730 */ 731 RL_LOCK(sc); 732 rl_reset(sc); 733 RL_UNLOCK(sc); 734 735 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 736 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 737 if (rl_did != 0x8129) 738 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 739 740 /* 741 * Get station address from the EEPROM. 742 */ 743 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0); 744 for (i = 0; i < 3; i++) { 745 eaddr[(i * 2) + 0] = as[i] & 0xff; 746 eaddr[(i * 2) + 1] = as[i] >> 8; 747 } 748 749 /* 750 * Now read the exact device type from the EEPROM to find 751 * out if it's an 8129 or 8139. 752 */ 753 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0); 754 755 t = rl_devs; 756 sc->rl_type = 0; 757 while(t->rl_name != NULL) { 758 if (rl_did == t->rl_did) { 759 sc->rl_type = t->rl_basetype; 760 break; 761 } 762 t++; 763 } 764 765 if (sc->rl_type == 0) { 766 device_printf(dev, "unknown device ID: %x assuming 8139\n", 767 rl_did); 768 sc->rl_type = RL_8139; 769 /* 770 * Read RL_IDR register to get ethernet address as accessing 771 * EEPROM may not extract correct address. 772 */ 773 for (i = 0; i < ETHER_ADDR_LEN; i++) 774 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 775 } 776 777 if ((error = rl_dma_alloc(sc)) != 0) 778 goto fail; 779 780 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 781 if (ifp == NULL) { 782 device_printf(dev, "can not if_alloc()\n"); 783 error = ENOSPC; 784 goto fail; 785 } 786 787 #define RL_PHYAD_INTERNAL 0 788 789 /* Do MII setup */ 790 phy = MII_PHY_ANY; 791 if (sc->rl_type == RL_8139) 792 phy = RL_PHYAD_INTERNAL; 793 error = mii_attach(dev, &sc->rl_miibus, ifp, rl_ifmedia_upd, 794 rl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 795 if (error != 0) { 796 device_printf(dev, "attaching PHYs failed\n"); 797 goto fail; 798 } 799 800 ifp->if_softc = sc; 801 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 802 ifp->if_mtu = ETHERMTU; 803 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 804 ifp->if_ioctl = rl_ioctl; 805 ifp->if_start = rl_start; 806 ifp->if_init = rl_init; 807 ifp->if_capabilities = IFCAP_VLAN_MTU; 808 /* Check WOL for RTL8139B or newer controllers. */ 809 if (sc->rl_type == RL_8139 && 810 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) { 811 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 812 switch (hwrev) { 813 case RL_HWREV_8139B: 814 case RL_HWREV_8130: 815 case RL_HWREV_8139C: 816 case RL_HWREV_8139D: 817 case RL_HWREV_8101: 818 case RL_HWREV_8100: 819 ifp->if_capabilities |= IFCAP_WOL; 820 /* Disable WOL. */ 821 rl_clrwol(sc); 822 break; 823 default: 824 break; 825 } 826 } 827 ifp->if_capenable = ifp->if_capabilities; 828 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 829 #ifdef DEVICE_POLLING 830 ifp->if_capabilities |= IFCAP_POLLING; 831 #endif 832 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 833 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 834 IFQ_SET_READY(&ifp->if_snd); 835 836 /* 837 * Call MI attach routine. 838 */ 839 ether_ifattach(ifp, eaddr); 840 841 /* Hook interrupt last to avoid having to lock softc */ 842 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE, 843 NULL, rl_intr, sc, &sc->rl_intrhand[0]); 844 if (error) { 845 device_printf(sc->rl_dev, "couldn't set up irq\n"); 846 ether_ifdetach(ifp); 847 } 848 849 fail: 850 if (error) 851 rl_detach(dev); 852 853 return (error); 854 } 855 856 /* 857 * Shutdown hardware and free up resources. This can be called any 858 * time after the mutex has been initialized. It is called in both 859 * the error case in attach and the normal detach case so it needs 860 * to be careful about only freeing resources that have actually been 861 * allocated. 862 */ 863 static int 864 rl_detach(device_t dev) 865 { 866 struct rl_softc *sc; 867 struct ifnet *ifp; 868 869 sc = device_get_softc(dev); 870 ifp = sc->rl_ifp; 871 872 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 873 874 #ifdef DEVICE_POLLING 875 if (ifp->if_capenable & IFCAP_POLLING) 876 ether_poll_deregister(ifp); 877 #endif 878 /* These should only be active if attach succeeded */ 879 if (device_is_attached(dev)) { 880 RL_LOCK(sc); 881 rl_stop(sc); 882 RL_UNLOCK(sc); 883 callout_drain(&sc->rl_stat_callout); 884 ether_ifdetach(ifp); 885 } 886 #if 0 887 sc->suspended = 1; 888 #endif 889 if (sc->rl_miibus) 890 device_delete_child(dev, sc->rl_miibus); 891 bus_generic_detach(dev); 892 893 if (sc->rl_intrhand[0]) 894 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 895 if (sc->rl_irq[0]) 896 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]); 897 if (sc->rl_res) 898 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 899 sc->rl_res); 900 901 if (ifp) 902 if_free(ifp); 903 904 rl_dma_free(sc); 905 906 mtx_destroy(&sc->rl_mtx); 907 908 return (0); 909 } 910 911 static int 912 rl_dma_alloc(struct rl_softc *sc) 913 { 914 struct rl_dmamap_arg ctx; 915 int error, i; 916 917 /* 918 * Allocate the parent bus DMA tag appropriate for PCI. 919 */ 920 error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */ 921 1, 0, /* alignment, boundary */ 922 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 923 BUS_SPACE_MAXADDR, /* highaddr */ 924 NULL, NULL, /* filter, filterarg */ 925 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */ 926 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 927 0, /* flags */ 928 NULL, NULL, /* lockfunc, lockarg */ 929 &sc->rl_parent_tag); 930 if (error) { 931 device_printf(sc->rl_dev, 932 "failed to create parent DMA tag.\n"); 933 goto fail; 934 } 935 /* Create DMA tag for Rx memory block. */ 936 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 937 RL_RX_8139_BUF_ALIGN, 0, /* alignment, boundary */ 938 BUS_SPACE_MAXADDR, /* lowaddr */ 939 BUS_SPACE_MAXADDR, /* highaddr */ 940 NULL, NULL, /* filter, filterarg */ 941 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1, /* maxsize,nsegments */ 942 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, /* maxsegsize */ 943 0, /* flags */ 944 NULL, NULL, /* lockfunc, lockarg */ 945 &sc->rl_cdata.rl_rx_tag); 946 if (error) { 947 device_printf(sc->rl_dev, 948 "failed to create Rx memory block DMA tag.\n"); 949 goto fail; 950 } 951 /* Create DMA tag for Tx buffer. */ 952 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 953 RL_TX_8139_BUF_ALIGN, 0, /* alignment, boundary */ 954 BUS_SPACE_MAXADDR, /* lowaddr */ 955 BUS_SPACE_MAXADDR, /* highaddr */ 956 NULL, NULL, /* filter, filterarg */ 957 MCLBYTES, 1, /* maxsize, nsegments */ 958 MCLBYTES, /* maxsegsize */ 959 0, /* flags */ 960 NULL, NULL, /* lockfunc, lockarg */ 961 &sc->rl_cdata.rl_tx_tag); 962 if (error) { 963 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n"); 964 goto fail; 965 } 966 967 /* 968 * Allocate DMA'able memory and load DMA map for Rx memory block. 969 */ 970 error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag, 971 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK | 972 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap); 973 if (error != 0) { 974 device_printf(sc->rl_dev, 975 "failed to allocate Rx DMA memory block.\n"); 976 goto fail; 977 } 978 ctx.rl_busaddr = 0; 979 error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag, 980 sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf, 981 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx, 982 BUS_DMA_NOWAIT); 983 if (error != 0 || ctx.rl_busaddr == 0) { 984 device_printf(sc->rl_dev, 985 "could not load Rx DMA memory block.\n"); 986 goto fail; 987 } 988 sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr; 989 990 /* Create DMA maps for Tx buffers. */ 991 for (i = 0; i < RL_TX_LIST_CNT; i++) { 992 sc->rl_cdata.rl_tx_chain[i] = NULL; 993 sc->rl_cdata.rl_tx_dmamap[i] = NULL; 994 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0, 995 &sc->rl_cdata.rl_tx_dmamap[i]); 996 if (error != 0) { 997 device_printf(sc->rl_dev, 998 "could not create Tx dmamap.\n"); 999 goto fail; 1000 } 1001 } 1002 1003 /* Leave a few bytes before the start of the RX ring buffer. */ 1004 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1005 sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE; 1006 1007 fail: 1008 return (error); 1009 } 1010 1011 static void 1012 rl_dma_free(struct rl_softc *sc) 1013 { 1014 int i; 1015 1016 /* Rx memory block. */ 1017 if (sc->rl_cdata.rl_rx_tag != NULL) { 1018 if (sc->rl_cdata.rl_rx_dmamap != NULL) 1019 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag, 1020 sc->rl_cdata.rl_rx_dmamap); 1021 if (sc->rl_cdata.rl_rx_dmamap != NULL && 1022 sc->rl_cdata.rl_rx_buf_ptr != NULL) 1023 bus_dmamem_free(sc->rl_cdata.rl_rx_tag, 1024 sc->rl_cdata.rl_rx_buf_ptr, 1025 sc->rl_cdata.rl_rx_dmamap); 1026 sc->rl_cdata.rl_rx_buf_ptr = NULL; 1027 sc->rl_cdata.rl_rx_buf = NULL; 1028 sc->rl_cdata.rl_rx_dmamap = NULL; 1029 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag); 1030 sc->rl_cdata.rl_tx_tag = NULL; 1031 } 1032 1033 /* Tx buffers. */ 1034 if (sc->rl_cdata.rl_tx_tag != NULL) { 1035 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1036 if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) { 1037 bus_dmamap_destroy( 1038 sc->rl_cdata.rl_tx_tag, 1039 sc->rl_cdata.rl_tx_dmamap[i]); 1040 sc->rl_cdata.rl_tx_dmamap[i] = NULL; 1041 } 1042 } 1043 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag); 1044 sc->rl_cdata.rl_tx_tag = NULL; 1045 } 1046 1047 if (sc->rl_parent_tag != NULL) { 1048 bus_dma_tag_destroy(sc->rl_parent_tag); 1049 sc->rl_parent_tag = NULL; 1050 } 1051 } 1052 1053 /* 1054 * Initialize the transmit descriptors. 1055 */ 1056 static int 1057 rl_list_tx_init(struct rl_softc *sc) 1058 { 1059 struct rl_chain_data *cd; 1060 int i; 1061 1062 RL_LOCK_ASSERT(sc); 1063 1064 cd = &sc->rl_cdata; 1065 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1066 cd->rl_tx_chain[i] = NULL; 1067 CSR_WRITE_4(sc, 1068 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); 1069 } 1070 1071 sc->rl_cdata.cur_tx = 0; 1072 sc->rl_cdata.last_tx = 0; 1073 1074 return (0); 1075 } 1076 1077 static int 1078 rl_list_rx_init(struct rl_softc *sc) 1079 { 1080 1081 RL_LOCK_ASSERT(sc); 1082 1083 bzero(sc->rl_cdata.rl_rx_buf_ptr, 1084 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ); 1085 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap, 1086 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1087 1088 return (0); 1089 } 1090 1091 /* 1092 * A frame has been uploaded: pass the resulting mbuf chain up to 1093 * the higher level protocols. 1094 * 1095 * You know there's something wrong with a PCI bus-master chip design 1096 * when you have to use m_devget(). 1097 * 1098 * The receive operation is badly documented in the datasheet, so I'll 1099 * attempt to document it here. The driver provides a buffer area and 1100 * places its base address in the RX buffer start address register. 1101 * The chip then begins copying frames into the RX buffer. Each frame 1102 * is preceded by a 32-bit RX status word which specifies the length 1103 * of the frame and certain other status bits. Each frame (starting with 1104 * the status word) is also 32-bit aligned. The frame length is in the 1105 * first 16 bits of the status word; the lower 15 bits correspond with 1106 * the 'rx status register' mentioned in the datasheet. 1107 * 1108 * Note: to make the Alpha happy, the frame payload needs to be aligned 1109 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1110 * as the offset argument to m_devget(). 1111 */ 1112 static int 1113 rl_rxeof(struct rl_softc *sc) 1114 { 1115 struct mbuf *m; 1116 struct ifnet *ifp = sc->rl_ifp; 1117 uint8_t *rxbufpos; 1118 int total_len = 0; 1119 int wrap = 0; 1120 int rx_npkts = 0; 1121 uint32_t rxstat; 1122 uint16_t cur_rx; 1123 uint16_t limit; 1124 uint16_t max_bytes, rx_bytes = 0; 1125 1126 RL_LOCK_ASSERT(sc); 1127 1128 bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap, 1129 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1130 1131 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1132 1133 /* Do not try to read past this point. */ 1134 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1135 1136 if (limit < cur_rx) 1137 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1138 else 1139 max_bytes = limit - cur_rx; 1140 1141 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1142 #ifdef DEVICE_POLLING 1143 if (ifp->if_capenable & IFCAP_POLLING) { 1144 if (sc->rxcycles <= 0) 1145 break; 1146 sc->rxcycles--; 1147 } 1148 #endif 1149 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1150 rxstat = le32toh(*(uint32_t *)rxbufpos); 1151 1152 /* 1153 * Here's a totally undocumented fact for you. When the 1154 * RealTek chip is in the process of copying a packet into 1155 * RAM for you, the length will be 0xfff0. If you spot a 1156 * packet header with this value, you need to stop. The 1157 * datasheet makes absolutely no mention of this and 1158 * RealTek should be shot for this. 1159 */ 1160 total_len = rxstat >> 16; 1161 if (total_len == RL_RXSTAT_UNFINISHED) 1162 break; 1163 1164 if (!(rxstat & RL_RXSTAT_RXOK) || 1165 total_len < ETHER_MIN_LEN || 1166 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 1167 ifp->if_ierrors++; 1168 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1169 rl_init_locked(sc); 1170 return (rx_npkts); 1171 } 1172 1173 /* No errors; receive the packet. */ 1174 rx_bytes += total_len + 4; 1175 1176 /* 1177 * XXX The RealTek chip includes the CRC with every 1178 * received frame, and there's no way to turn this 1179 * behavior off (at least, I can't find anything in 1180 * the manual that explains how to do it) so we have 1181 * to trim off the CRC manually. 1182 */ 1183 total_len -= ETHER_CRC_LEN; 1184 1185 /* 1186 * Avoid trying to read more bytes than we know 1187 * the chip has prepared for us. 1188 */ 1189 if (rx_bytes > max_bytes) 1190 break; 1191 1192 rxbufpos = sc->rl_cdata.rl_rx_buf + 1193 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1194 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1195 rxbufpos = sc->rl_cdata.rl_rx_buf; 1196 1197 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1198 if (total_len > wrap) { 1199 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1200 NULL); 1201 if (m != NULL) 1202 m_copyback(m, wrap, total_len - wrap, 1203 sc->rl_cdata.rl_rx_buf); 1204 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1205 } else { 1206 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1207 NULL); 1208 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1209 } 1210 1211 /* Round up to 32-bit boundary. */ 1212 cur_rx = (cur_rx + 3) & ~3; 1213 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1214 1215 if (m == NULL) { 1216 ifp->if_iqdrops++; 1217 continue; 1218 } 1219 1220 ifp->if_ipackets++; 1221 RL_UNLOCK(sc); 1222 (*ifp->if_input)(ifp, m); 1223 RL_LOCK(sc); 1224 rx_npkts++; 1225 } 1226 1227 /* No need to sync Rx memory block as we didn't modify it. */ 1228 return (rx_npkts); 1229 } 1230 1231 /* 1232 * A frame was downloaded to the chip. It's safe for us to clean up 1233 * the list buffers. 1234 */ 1235 static void 1236 rl_txeof(struct rl_softc *sc) 1237 { 1238 struct ifnet *ifp = sc->rl_ifp; 1239 uint32_t txstat; 1240 1241 RL_LOCK_ASSERT(sc); 1242 1243 /* 1244 * Go through our tx list and free mbufs for those 1245 * frames that have been uploaded. 1246 */ 1247 do { 1248 if (RL_LAST_TXMBUF(sc) == NULL) 1249 break; 1250 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1251 if (!(txstat & (RL_TXSTAT_TX_OK| 1252 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1253 break; 1254 1255 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1256 1257 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc), 1258 BUS_DMASYNC_POSTWRITE); 1259 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc)); 1260 m_freem(RL_LAST_TXMBUF(sc)); 1261 RL_LAST_TXMBUF(sc) = NULL; 1262 /* 1263 * If there was a transmit underrun, bump the TX threshold. 1264 * Make sure not to overflow the 63 * 32byte we can address 1265 * with the 6 available bit. 1266 */ 1267 if ((txstat & RL_TXSTAT_TX_UNDERRUN) && 1268 (sc->rl_txthresh < 2016)) 1269 sc->rl_txthresh += 32; 1270 if (txstat & RL_TXSTAT_TX_OK) 1271 ifp->if_opackets++; 1272 else { 1273 int oldthresh; 1274 ifp->if_oerrors++; 1275 if ((txstat & RL_TXSTAT_TXABRT) || 1276 (txstat & RL_TXSTAT_OUTOFWIN)) 1277 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1278 oldthresh = sc->rl_txthresh; 1279 /* error recovery */ 1280 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1281 rl_init_locked(sc); 1282 /* restore original threshold */ 1283 sc->rl_txthresh = oldthresh; 1284 return; 1285 } 1286 RL_INC(sc->rl_cdata.last_tx); 1287 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1288 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1289 1290 if (RL_LAST_TXMBUF(sc) == NULL) 1291 sc->rl_watchdog_timer = 0; 1292 } 1293 1294 static void 1295 rl_twister_update(struct rl_softc *sc) 1296 { 1297 uint16_t linktest; 1298 /* 1299 * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for 1300 * Linux driver. Values undocumented otherwise. 1301 */ 1302 static const uint32_t param[4][4] = { 1303 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43}, 1304 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1305 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1306 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83} 1307 }; 1308 1309 /* 1310 * Tune the so-called twister registers of the RTL8139. These 1311 * are used to compensate for impedance mismatches. The 1312 * method for tuning these registers is undocumented and the 1313 * following procedure is collected from public sources. 1314 */ 1315 switch (sc->rl_twister) 1316 { 1317 case CHK_LINK: 1318 /* 1319 * If we have a sufficient link, then we can proceed in 1320 * the state machine to the next stage. If not, then 1321 * disable further tuning after writing sane defaults. 1322 */ 1323 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) { 1324 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD); 1325 sc->rl_twister = FIND_ROW; 1326 } else { 1327 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD); 1328 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST); 1329 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF); 1330 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF); 1331 sc->rl_twister = DONE; 1332 } 1333 break; 1334 case FIND_ROW: 1335 /* 1336 * Read how long it took to see the echo to find the tuning 1337 * row to use. 1338 */ 1339 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; 1340 if (linktest == RL_CSCFG_ROW3) 1341 sc->rl_twist_row = 3; 1342 else if (linktest == RL_CSCFG_ROW2) 1343 sc->rl_twist_row = 2; 1344 else if (linktest == RL_CSCFG_ROW1) 1345 sc->rl_twist_row = 1; 1346 else 1347 sc->rl_twist_row = 0; 1348 sc->rl_twist_col = 0; 1349 sc->rl_twister = SET_PARAM; 1350 break; 1351 case SET_PARAM: 1352 if (sc->rl_twist_col == 0) 1353 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET); 1354 CSR_WRITE_4(sc, RL_PARA7C, 1355 param[sc->rl_twist_row][sc->rl_twist_col]); 1356 if (++sc->rl_twist_col == 4) { 1357 if (sc->rl_twist_row == 3) 1358 sc->rl_twister = RECHK_LONG; 1359 else 1360 sc->rl_twister = DONE; 1361 } 1362 break; 1363 case RECHK_LONG: 1364 /* 1365 * For long cables, we have to double check to make sure we 1366 * don't mistune. 1367 */ 1368 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; 1369 if (linktest == RL_CSCFG_ROW3) 1370 sc->rl_twister = DONE; 1371 else { 1372 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE); 1373 sc->rl_twister = RETUNE; 1374 } 1375 break; 1376 case RETUNE: 1377 /* Retune for a shorter cable (try column 2) */ 1378 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST); 1379 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF); 1380 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF); 1381 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET); 1382 sc->rl_twist_row--; 1383 sc->rl_twist_col = 0; 1384 sc->rl_twister = SET_PARAM; 1385 break; 1386 1387 case DONE: 1388 break; 1389 } 1390 1391 } 1392 1393 static void 1394 rl_tick(void *xsc) 1395 { 1396 struct rl_softc *sc = xsc; 1397 struct mii_data *mii; 1398 int ticks; 1399 1400 RL_LOCK_ASSERT(sc); 1401 /* 1402 * If we're doing the twister cable calibration, then we need to defer 1403 * watchdog timeouts. This is a no-op in normal operations, but 1404 * can falsely trigger when the cable calibration takes a while and 1405 * there was traffic ready to go when rl was started. 1406 * 1407 * We don't defer mii_tick since that updates the mii status, which 1408 * helps the twister process, at least according to similar patches 1409 * for the Linux driver I found online while doing the fixes. Worst 1410 * case is a few extra mii reads during calibration. 1411 */ 1412 mii = device_get_softc(sc->rl_miibus); 1413 mii_tick(mii); 1414 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 1415 rl_miibus_statchg(sc->rl_dev); 1416 if (sc->rl_twister_enable) { 1417 if (sc->rl_twister == DONE) 1418 rl_watchdog(sc); 1419 else 1420 rl_twister_update(sc); 1421 if (sc->rl_twister == DONE) 1422 ticks = hz; 1423 else 1424 ticks = hz / 10; 1425 } else { 1426 rl_watchdog(sc); 1427 ticks = hz; 1428 } 1429 1430 callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc); 1431 } 1432 1433 #ifdef DEVICE_POLLING 1434 static int 1435 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1436 { 1437 struct rl_softc *sc = ifp->if_softc; 1438 int rx_npkts = 0; 1439 1440 RL_LOCK(sc); 1441 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1442 rx_npkts = rl_poll_locked(ifp, cmd, count); 1443 RL_UNLOCK(sc); 1444 return (rx_npkts); 1445 } 1446 1447 static int 1448 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1449 { 1450 struct rl_softc *sc = ifp->if_softc; 1451 int rx_npkts; 1452 1453 RL_LOCK_ASSERT(sc); 1454 1455 sc->rxcycles = count; 1456 rx_npkts = rl_rxeof(sc); 1457 rl_txeof(sc); 1458 1459 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1460 rl_start_locked(ifp); 1461 1462 if (cmd == POLL_AND_CHECK_STATUS) { 1463 uint16_t status; 1464 1465 /* We should also check the status register. */ 1466 status = CSR_READ_2(sc, RL_ISR); 1467 if (status == 0xffff) 1468 return (rx_npkts); 1469 if (status != 0) 1470 CSR_WRITE_2(sc, RL_ISR, status); 1471 1472 /* XXX We should check behaviour on receiver stalls. */ 1473 1474 if (status & RL_ISR_SYSTEM_ERR) { 1475 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1476 rl_init_locked(sc); 1477 } 1478 } 1479 return (rx_npkts); 1480 } 1481 #endif /* DEVICE_POLLING */ 1482 1483 static void 1484 rl_intr(void *arg) 1485 { 1486 struct rl_softc *sc = arg; 1487 struct ifnet *ifp = sc->rl_ifp; 1488 uint16_t status; 1489 int count; 1490 1491 RL_LOCK(sc); 1492 1493 if (sc->suspended) 1494 goto done_locked; 1495 1496 #ifdef DEVICE_POLLING 1497 if (ifp->if_capenable & IFCAP_POLLING) 1498 goto done_locked; 1499 #endif 1500 1501 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1502 goto done_locked2; 1503 status = CSR_READ_2(sc, RL_ISR); 1504 if (status == 0xffff || (status & RL_INTRS) == 0) 1505 goto done_locked; 1506 /* 1507 * Ours, disable further interrupts. 1508 */ 1509 CSR_WRITE_2(sc, RL_IMR, 0); 1510 for (count = 16; count > 0; count--) { 1511 CSR_WRITE_2(sc, RL_ISR, status); 1512 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1513 if (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR)) 1514 rl_rxeof(sc); 1515 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR)) 1516 rl_txeof(sc); 1517 if (status & RL_ISR_SYSTEM_ERR) { 1518 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1519 rl_init_locked(sc); 1520 RL_UNLOCK(sc); 1521 return; 1522 } 1523 } 1524 status = CSR_READ_2(sc, RL_ISR); 1525 /* If the card has gone away, the read returns 0xffff. */ 1526 if (status == 0xffff || (status & RL_INTRS) == 0) 1527 break; 1528 } 1529 1530 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1531 rl_start_locked(ifp); 1532 1533 done_locked2: 1534 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1535 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1536 done_locked: 1537 RL_UNLOCK(sc); 1538 } 1539 1540 /* 1541 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1542 * pointers to the fragment pointers. 1543 */ 1544 static int 1545 rl_encap(struct rl_softc *sc, struct mbuf **m_head) 1546 { 1547 struct mbuf *m; 1548 bus_dma_segment_t txsegs[1]; 1549 int error, nsegs, padlen; 1550 1551 RL_LOCK_ASSERT(sc); 1552 1553 m = *m_head; 1554 padlen = 0; 1555 /* 1556 * Hardware doesn't auto-pad, so we have to make sure 1557 * pad short frames out to the minimum frame length. 1558 */ 1559 if (m->m_pkthdr.len < RL_MIN_FRAMELEN) 1560 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len; 1561 /* 1562 * The RealTek is brain damaged and wants longword-aligned 1563 * TX buffers, plus we can only have one fragment buffer 1564 * per packet. We have to copy pretty much all the time. 1565 */ 1566 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 || 1567 (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) { 1568 m = m_defrag(*m_head, M_DONTWAIT); 1569 if (m == NULL) { 1570 m_freem(*m_head); 1571 *m_head = NULL; 1572 return (ENOMEM); 1573 } 1574 } 1575 *m_head = m; 1576 1577 if (padlen > 0) { 1578 /* 1579 * Make security-conscious people happy: zero out the 1580 * bytes in the pad area, since we don't know what 1581 * this mbuf cluster buffer's previous user might 1582 * have left in it. 1583 */ 1584 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1585 m->m_pkthdr.len += padlen; 1586 m->m_len = m->m_pkthdr.len; 1587 } 1588 1589 error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag, 1590 RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0); 1591 if (error != 0) 1592 return (error); 1593 if (nsegs == 0) { 1594 m_freem(*m_head); 1595 *m_head = NULL; 1596 return (EIO); 1597 } 1598 1599 RL_CUR_TXMBUF(sc) = m; 1600 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc), 1601 BUS_DMASYNC_PREWRITE); 1602 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr)); 1603 1604 return (0); 1605 } 1606 1607 /* 1608 * Main transmit routine. 1609 */ 1610 static void 1611 rl_start(struct ifnet *ifp) 1612 { 1613 struct rl_softc *sc = ifp->if_softc; 1614 1615 RL_LOCK(sc); 1616 rl_start_locked(ifp); 1617 RL_UNLOCK(sc); 1618 } 1619 1620 static void 1621 rl_start_locked(struct ifnet *ifp) 1622 { 1623 struct rl_softc *sc = ifp->if_softc; 1624 struct mbuf *m_head = NULL; 1625 1626 RL_LOCK_ASSERT(sc); 1627 1628 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1629 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 1630 return; 1631 1632 while (RL_CUR_TXMBUF(sc) == NULL) { 1633 1634 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1635 1636 if (m_head == NULL) 1637 break; 1638 1639 if (rl_encap(sc, &m_head)) { 1640 if (m_head == NULL) 1641 break; 1642 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1643 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1644 break; 1645 } 1646 1647 /* Pass a copy of this mbuf chain to the bpf subsystem. */ 1648 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1649 1650 /* Transmit the frame. */ 1651 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1652 RL_TXTHRESH(sc->rl_txthresh) | 1653 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1654 1655 RL_INC(sc->rl_cdata.cur_tx); 1656 1657 /* Set a timeout in case the chip goes out to lunch. */ 1658 sc->rl_watchdog_timer = 5; 1659 } 1660 1661 /* 1662 * We broke out of the loop because all our TX slots are 1663 * full. Mark the NIC as busy until it drains some of the 1664 * packets from the queue. 1665 */ 1666 if (RL_CUR_TXMBUF(sc) != NULL) 1667 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1668 } 1669 1670 static void 1671 rl_init(void *xsc) 1672 { 1673 struct rl_softc *sc = xsc; 1674 1675 RL_LOCK(sc); 1676 rl_init_locked(sc); 1677 RL_UNLOCK(sc); 1678 } 1679 1680 static void 1681 rl_init_locked(struct rl_softc *sc) 1682 { 1683 struct ifnet *ifp = sc->rl_ifp; 1684 struct mii_data *mii; 1685 uint32_t eaddr[2]; 1686 1687 RL_LOCK_ASSERT(sc); 1688 1689 mii = device_get_softc(sc->rl_miibus); 1690 1691 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1692 return; 1693 1694 /* 1695 * Cancel pending I/O and free all RX/TX buffers. 1696 */ 1697 rl_stop(sc); 1698 1699 rl_reset(sc); 1700 if (sc->rl_twister_enable) { 1701 /* 1702 * Reset twister register tuning state. The twister 1703 * registers and their tuning are undocumented, but 1704 * are necessary to cope with bad links. rl_twister = 1705 * DONE here will disable this entirely. 1706 */ 1707 sc->rl_twister = CHK_LINK; 1708 } 1709 1710 /* 1711 * Init our MAC address. Even though the chipset 1712 * documentation doesn't mention it, we need to enter "Config 1713 * register write enable" mode to modify the ID registers. 1714 */ 1715 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1716 bzero(eaddr, sizeof(eaddr)); 1717 bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN); 1718 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]); 1719 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]); 1720 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1721 1722 /* Init the RX memory block pointer register. */ 1723 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr + 1724 RL_RX_8139_BUF_RESERVE); 1725 /* Init TX descriptors. */ 1726 rl_list_tx_init(sc); 1727 /* Init Rx memory block. */ 1728 rl_list_rx_init(sc); 1729 1730 /* 1731 * Enable transmit and receive. 1732 */ 1733 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1734 1735 /* 1736 * Set the initial TX and RX configuration. 1737 */ 1738 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1739 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1740 1741 /* Set RX filter. */ 1742 rl_rxfilter(sc); 1743 1744 #ifdef DEVICE_POLLING 1745 /* Disable interrupts if we are polling. */ 1746 if (ifp->if_capenable & IFCAP_POLLING) 1747 CSR_WRITE_2(sc, RL_IMR, 0); 1748 else 1749 #endif 1750 /* Enable interrupts. */ 1751 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1752 1753 /* Set initial TX threshold */ 1754 sc->rl_txthresh = RL_TX_THRESH_INIT; 1755 1756 /* Start RX/TX process. */ 1757 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1758 1759 /* Enable receiver and transmitter. */ 1760 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1761 1762 sc->rl_flags &= ~RL_FLAG_LINK; 1763 mii_mediachg(mii); 1764 1765 CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1766 1767 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1768 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1769 1770 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc); 1771 } 1772 1773 /* 1774 * Set media options. 1775 */ 1776 static int 1777 rl_ifmedia_upd(struct ifnet *ifp) 1778 { 1779 struct rl_softc *sc = ifp->if_softc; 1780 struct mii_data *mii; 1781 1782 mii = device_get_softc(sc->rl_miibus); 1783 1784 RL_LOCK(sc); 1785 mii_mediachg(mii); 1786 RL_UNLOCK(sc); 1787 1788 return (0); 1789 } 1790 1791 /* 1792 * Report current media status. 1793 */ 1794 static void 1795 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1796 { 1797 struct rl_softc *sc = ifp->if_softc; 1798 struct mii_data *mii; 1799 1800 mii = device_get_softc(sc->rl_miibus); 1801 1802 RL_LOCK(sc); 1803 mii_pollstat(mii); 1804 ifmr->ifm_active = mii->mii_media_active; 1805 ifmr->ifm_status = mii->mii_media_status; 1806 RL_UNLOCK(sc); 1807 } 1808 1809 static int 1810 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1811 { 1812 struct ifreq *ifr = (struct ifreq *)data; 1813 struct mii_data *mii; 1814 struct rl_softc *sc = ifp->if_softc; 1815 int error = 0, mask; 1816 1817 switch (command) { 1818 case SIOCSIFFLAGS: 1819 RL_LOCK(sc); 1820 if (ifp->if_flags & IFF_UP) { 1821 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1822 ((ifp->if_flags ^ sc->rl_if_flags) & 1823 (IFF_PROMISC | IFF_ALLMULTI))) 1824 rl_rxfilter(sc); 1825 else 1826 rl_init_locked(sc); 1827 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1828 rl_stop(sc); 1829 sc->rl_if_flags = ifp->if_flags; 1830 RL_UNLOCK(sc); 1831 break; 1832 case SIOCADDMULTI: 1833 case SIOCDELMULTI: 1834 RL_LOCK(sc); 1835 rl_rxfilter(sc); 1836 RL_UNLOCK(sc); 1837 break; 1838 case SIOCGIFMEDIA: 1839 case SIOCSIFMEDIA: 1840 mii = device_get_softc(sc->rl_miibus); 1841 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1842 break; 1843 case SIOCSIFCAP: 1844 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1845 #ifdef DEVICE_POLLING 1846 if (ifr->ifr_reqcap & IFCAP_POLLING && 1847 !(ifp->if_capenable & IFCAP_POLLING)) { 1848 error = ether_poll_register(rl_poll, ifp); 1849 if (error) 1850 return(error); 1851 RL_LOCK(sc); 1852 /* Disable interrupts */ 1853 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1854 ifp->if_capenable |= IFCAP_POLLING; 1855 RL_UNLOCK(sc); 1856 return (error); 1857 1858 } 1859 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1860 ifp->if_capenable & IFCAP_POLLING) { 1861 error = ether_poll_deregister(ifp); 1862 /* Enable interrupts. */ 1863 RL_LOCK(sc); 1864 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1865 ifp->if_capenable &= ~IFCAP_POLLING; 1866 RL_UNLOCK(sc); 1867 return (error); 1868 } 1869 #endif /* DEVICE_POLLING */ 1870 if ((mask & IFCAP_WOL) != 0 && 1871 (ifp->if_capabilities & IFCAP_WOL) != 0) { 1872 if ((mask & IFCAP_WOL_UCAST) != 0) 1873 ifp->if_capenable ^= IFCAP_WOL_UCAST; 1874 if ((mask & IFCAP_WOL_MCAST) != 0) 1875 ifp->if_capenable ^= IFCAP_WOL_MCAST; 1876 if ((mask & IFCAP_WOL_MAGIC) != 0) 1877 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1878 } 1879 break; 1880 default: 1881 error = ether_ioctl(ifp, command, data); 1882 break; 1883 } 1884 1885 return (error); 1886 } 1887 1888 static void 1889 rl_watchdog(struct rl_softc *sc) 1890 { 1891 1892 RL_LOCK_ASSERT(sc); 1893 1894 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0) 1895 return; 1896 1897 device_printf(sc->rl_dev, "watchdog timeout\n"); 1898 sc->rl_ifp->if_oerrors++; 1899 1900 rl_txeof(sc); 1901 rl_rxeof(sc); 1902 sc->rl_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1903 rl_init_locked(sc); 1904 } 1905 1906 /* 1907 * Stop the adapter and free any mbufs allocated to the 1908 * RX and TX lists. 1909 */ 1910 static void 1911 rl_stop(struct rl_softc *sc) 1912 { 1913 register int i; 1914 struct ifnet *ifp = sc->rl_ifp; 1915 1916 RL_LOCK_ASSERT(sc); 1917 1918 sc->rl_watchdog_timer = 0; 1919 callout_stop(&sc->rl_stat_callout); 1920 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1921 sc->rl_flags &= ~RL_FLAG_LINK; 1922 1923 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1924 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1925 for (i = 0; i < RL_TIMEOUT; i++) { 1926 DELAY(10); 1927 if ((CSR_READ_1(sc, RL_COMMAND) & 1928 (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0) 1929 break; 1930 } 1931 if (i == RL_TIMEOUT) 1932 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n"); 1933 1934 /* 1935 * Free the TX list buffers. 1936 */ 1937 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1938 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1939 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1940 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, 1941 sc->rl_cdata.rl_tx_dmamap[i], 1942 BUS_DMASYNC_POSTWRITE); 1943 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, 1944 sc->rl_cdata.rl_tx_dmamap[i]); 1945 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1946 sc->rl_cdata.rl_tx_chain[i] = NULL; 1947 } 1948 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1949 0x0000000); 1950 } 1951 } 1952 } 1953 1954 /* 1955 * Device suspend routine. Stop the interface and save some PCI 1956 * settings in case the BIOS doesn't restore them properly on 1957 * resume. 1958 */ 1959 static int 1960 rl_suspend(device_t dev) 1961 { 1962 struct rl_softc *sc; 1963 1964 sc = device_get_softc(dev); 1965 1966 RL_LOCK(sc); 1967 rl_stop(sc); 1968 rl_setwol(sc); 1969 sc->suspended = 1; 1970 RL_UNLOCK(sc); 1971 1972 return (0); 1973 } 1974 1975 /* 1976 * Device resume routine. Restore some PCI settings in case the BIOS 1977 * doesn't, re-enable busmastering, and restart the interface if 1978 * appropriate. 1979 */ 1980 static int 1981 rl_resume(device_t dev) 1982 { 1983 struct rl_softc *sc; 1984 struct ifnet *ifp; 1985 int pmc; 1986 uint16_t pmstat; 1987 1988 sc = device_get_softc(dev); 1989 ifp = sc->rl_ifp; 1990 1991 RL_LOCK(sc); 1992 1993 if ((ifp->if_capabilities & IFCAP_WOL) != 0 && 1994 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) { 1995 /* Disable PME and clear PME status. */ 1996 pmstat = pci_read_config(sc->rl_dev, 1997 pmc + PCIR_POWER_STATUS, 2); 1998 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1999 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2000 pci_write_config(sc->rl_dev, 2001 pmc + PCIR_POWER_STATUS, pmstat, 2); 2002 } 2003 /* 2004 * Clear WOL matching such that normal Rx filtering 2005 * wouldn't interfere with WOL patterns. 2006 */ 2007 rl_clrwol(sc); 2008 } 2009 2010 /* reinitialize interface if necessary */ 2011 if (ifp->if_flags & IFF_UP) 2012 rl_init_locked(sc); 2013 2014 sc->suspended = 0; 2015 2016 RL_UNLOCK(sc); 2017 2018 return (0); 2019 } 2020 2021 /* 2022 * Stop all chip I/O so that the kernel's probe routines don't 2023 * get confused by errant DMAs when rebooting. 2024 */ 2025 static int 2026 rl_shutdown(device_t dev) 2027 { 2028 struct rl_softc *sc; 2029 2030 sc = device_get_softc(dev); 2031 2032 RL_LOCK(sc); 2033 rl_stop(sc); 2034 /* 2035 * Mark interface as down since otherwise we will panic if 2036 * interrupt comes in later on, which can happen in some 2037 * cases. 2038 */ 2039 sc->rl_ifp->if_flags &= ~IFF_UP; 2040 rl_setwol(sc); 2041 RL_UNLOCK(sc); 2042 2043 return (0); 2044 } 2045 2046 static void 2047 rl_setwol(struct rl_softc *sc) 2048 { 2049 struct ifnet *ifp; 2050 int pmc; 2051 uint16_t pmstat; 2052 uint8_t v; 2053 2054 RL_LOCK_ASSERT(sc); 2055 2056 ifp = sc->rl_ifp; 2057 if ((ifp->if_capabilities & IFCAP_WOL) == 0) 2058 return; 2059 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2060 return; 2061 2062 /* Enable config register write. */ 2063 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2064 2065 /* Enable PME. */ 2066 v = CSR_READ_1(sc, sc->rl_cfg1); 2067 v &= ~RL_CFG1_PME; 2068 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2069 v |= RL_CFG1_PME; 2070 CSR_WRITE_1(sc, sc->rl_cfg1, v); 2071 2072 v = CSR_READ_1(sc, sc->rl_cfg3); 2073 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2074 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2075 v |= RL_CFG3_WOL_MAGIC; 2076 CSR_WRITE_1(sc, sc->rl_cfg3, v); 2077 2078 v = CSR_READ_1(sc, sc->rl_cfg5); 2079 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2080 v &= ~RL_CFG5_WOL_LANWAKE; 2081 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2082 v |= RL_CFG5_WOL_UCAST; 2083 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2084 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 2085 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2086 v |= RL_CFG5_WOL_LANWAKE; 2087 CSR_WRITE_1(sc, sc->rl_cfg5, v); 2088 2089 /* Config register write done. */ 2090 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2091 2092 /* Request PME if WOL is requested. */ 2093 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 2094 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2095 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2096 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2097 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2098 } 2099 2100 static void 2101 rl_clrwol(struct rl_softc *sc) 2102 { 2103 struct ifnet *ifp; 2104 uint8_t v; 2105 2106 ifp = sc->rl_ifp; 2107 if ((ifp->if_capabilities & IFCAP_WOL) == 0) 2108 return; 2109 2110 /* Enable config register write. */ 2111 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2112 2113 v = CSR_READ_1(sc, sc->rl_cfg3); 2114 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2115 CSR_WRITE_1(sc, sc->rl_cfg3, v); 2116 2117 /* Config register write done. */ 2118 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2119 2120 v = CSR_READ_1(sc, sc->rl_cfg5); 2121 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2122 v &= ~RL_CFG5_WOL_LANWAKE; 2123 CSR_WRITE_1(sc, sc->rl_cfg5, v); 2124 }
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