FreeBSD/Linux Kernel Cross Reference
sys/pci/if_rlreg.h
1 /*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.84 2008/11/02 16:50:57 imp Exp $
33 */
34
35 /*
36 * RealTek 8129/8139 register offsets
37 */
38 #define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39 #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40 #define RL_IDR2 0x0002
41 #define RL_IDR3 0x0003
42 #define RL_IDR4 0x0004
43 #define RL_IDR5 0x0005
44 /* 0006-0007 reserved */
45 #define RL_MAR0 0x0008 /* Multicast hash table */
46 #define RL_MAR1 0x0009
47 #define RL_MAR2 0x000A
48 #define RL_MAR3 0x000B
49 #define RL_MAR4 0x000C
50 #define RL_MAR5 0x000D
51 #define RL_MAR6 0x000E
52 #define RL_MAR7 0x000F
53
54 #define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */
55 #define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */
56 #define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */
57 #define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */
58
59 #define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */
60 #define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */
61 #define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */
62 #define RL_TXADDR3 0x002C /* address of TX descriptor 3 */
63
64 #define RL_RXADDR 0x0030 /* RX ring start address */
65 #define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */
66 #define RL_RX_EARLY_STAT 0x0036 /* RX early status */
67 #define RL_COMMAND 0x0037 /* command register */
68 #define RL_CURRXADDR 0x0038 /* current address of packet read */
69 #define RL_CURRXBUF 0x003A /* current RX buffer address */
70 #define RL_IMR 0x003C /* interrupt mask register */
71 #define RL_ISR 0x003E /* interrupt status register */
72 #define RL_TXCFG 0x0040 /* transmit config */
73 #define RL_RXCFG 0x0044 /* receive config */
74 #define RL_TIMERCNT 0x0048 /* timer count register */
75 #define RL_MISSEDPKT 0x004C /* missed packet counter */
76 #define RL_EECMD 0x0050 /* EEPROM command register */
77 #define RL_CFG0 0x0051 /* config register #0 */
78 #define RL_CFG1 0x0052 /* config register #1 */
79 #define RL_CFG2 0x0053 /* config register #2 */
80 #define RL_CFG3 0x0054 /* config register #3 */
81 #define RL_CFG4 0x0055 /* config register #4 */
82 #define RL_CFG5 0x0056 /* config register #5 */
83 /* 0057 reserved */
84 #define RL_MEDIASTAT 0x0058 /* media status register (8139) */
85 /* 0059-005A reserved */
86 #define RL_MII 0x005A /* 8129 chip only */
87 #define RL_HALTCLK 0x005B
88 #define RL_MULTIINTR 0x005C /* multiple interrupt */
89 #define RL_PCIREV 0x005E /* PCI revision value */
90 /* 005F reserved */
91 #define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */
92
93 /* Direct PHY access registers only available on 8139 */
94 #define RL_BMCR 0x0062 /* PHY basic mode control */
95 #define RL_BMSR 0x0064 /* PHY basic mode status */
96 #define RL_ANAR 0x0066 /* PHY autoneg advert */
97 #define RL_LPAR 0x0068 /* PHY link partner ability */
98 #define RL_ANER 0x006A /* PHY autoneg expansion */
99
100 #define RL_DISCCNT 0x006C /* disconnect counter */
101 #define RL_FALSECAR 0x006E /* false carrier counter */
102 #define RL_NWAYTST 0x0070 /* NWAY test register */
103 #define RL_RX_ER 0x0072 /* RX_ER counter */
104 #define RL_CSCFG 0x0074 /* CS configuration register */
105
106 /*
107 * When operating in special C+ mode, some of the registers in an
108 * 8139C+ chip have different definitions. These are also used for
109 * the 8169 gigE chip.
110 */
111 #define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */
112 #define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */
113 #define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */
114 #define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */
115 #define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */
116 #define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */
117 #define RL_CFG2 0x0053
118 #define RL_TIMERINT 0x0054 /* interrupt on timer expire */
119 #define RL_TXSTART 0x00D9 /* 8 bits */
120 #define RL_CPLUS_CMD 0x00E0 /* 16 bits */
121 #define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */
122 #define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */
123 #define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */
124
125 /*
126 * Registers specific to the 8169 gigE chip
127 */
128 #define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */
129 #define RL_PHYAR 0x0060
130 #define RL_TBICSR 0x0064
131 #define RL_TBI_ANAR 0x0068
132 #define RL_TBI_LPAR 0x006A
133 #define RL_GMEDIASTAT 0x006C /* 8 bits */
134 #define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
135 #define RL_GTXSTART 0x0038 /* 8 bits */
136
137 /*
138 * TX config register bits
139 */
140 #define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
141 #define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
142 #define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
143 #define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
144 #define RL_TXCFG_IFG2 0x00080000 /* 8169 only */
145 #define RL_TXCFG_IFG 0x03000000 /* interframe gap */
146 #define RL_TXCFG_HWREV 0x7CC00000
147
148 #define RL_LOOPTEST_OFF 0x00000000
149 #define RL_LOOPTEST_ON 0x00020000
150 #define RL_LOOPTEST_ON_CPLUS 0x00060000
151
152 /* Known revision codes. */
153
154 #define RL_HWREV_8169 0x00000000
155 #define RL_HWREV_8110S 0x00800000
156 #define RL_HWREV_8169S 0x04000000
157 #define RL_HWREV_8169_8110SB 0x10000000
158 #define RL_HWREV_8169_8110SC 0x18000000
159 #define RL_HWREV_8102EL 0x24800000
160 #define RL_HWREV_8168_SPIN1 0x30000000
161 #define RL_HWREV_8100E 0x30800000
162 #define RL_HWREV_8101E 0x34000000
163 #define RL_HWREV_8102E 0x34800000
164 #define RL_HWREV_8168_SPIN2 0x38000000
165 #define RL_HWREV_8168_SPIN3 0x38400000
166 #define RL_HWREV_8168C 0x3C000000
167 #define RL_HWREV_8168C_SPIN2 0x3C400000
168 #define RL_HWREV_8168CP 0x3C800000
169 #define RL_HWREV_8139 0x60000000
170 #define RL_HWREV_8139A 0x70000000
171 #define RL_HWREV_8139AG 0x70800000
172 #define RL_HWREV_8139B 0x78000000
173 #define RL_HWREV_8130 0x7C000000
174 #define RL_HWREV_8139C 0x74000000
175 #define RL_HWREV_8139D 0x74400000
176 #define RL_HWREV_8139CPLUS 0x74800000
177 #define RL_HWREV_8101 0x74c00000
178 #define RL_HWREV_8100 0x78800000
179 #define RL_HWREV_8169_8110SBL 0x7CC00000
180
181 #define RL_TXDMA_16BYTES 0x00000000
182 #define RL_TXDMA_32BYTES 0x00000100
183 #define RL_TXDMA_64BYTES 0x00000200
184 #define RL_TXDMA_128BYTES 0x00000300
185 #define RL_TXDMA_256BYTES 0x00000400
186 #define RL_TXDMA_512BYTES 0x00000500
187 #define RL_TXDMA_1024BYTES 0x00000600
188 #define RL_TXDMA_2048BYTES 0x00000700
189
190 /*
191 * Transmit descriptor status register bits.
192 */
193 #define RL_TXSTAT_LENMASK 0x00001FFF
194 #define RL_TXSTAT_OWN 0x00002000
195 #define RL_TXSTAT_TX_UNDERRUN 0x00004000
196 #define RL_TXSTAT_TX_OK 0x00008000
197 #define RL_TXSTAT_EARLY_THRESH 0x003F0000
198 #define RL_TXSTAT_COLLCNT 0x0F000000
199 #define RL_TXSTAT_CARR_HBEAT 0x10000000
200 #define RL_TXSTAT_OUTOFWIN 0x20000000
201 #define RL_TXSTAT_TXABRT 0x40000000
202 #define RL_TXSTAT_CARRLOSS 0x80000000
203
204 /*
205 * Interrupt status register bits.
206 */
207 #define RL_ISR_RX_OK 0x0001
208 #define RL_ISR_RX_ERR 0x0002
209 #define RL_ISR_TX_OK 0x0004
210 #define RL_ISR_TX_ERR 0x0008
211 #define RL_ISR_RX_OVERRUN 0x0010
212 #define RL_ISR_PKT_UNDERRUN 0x0020
213 #define RL_ISR_LINKCHG 0x0020 /* 8169 only */
214 #define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
215 #define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */
216 #define RL_ISR_SWI 0x0100 /* C+ only */
217 #define RL_ISR_CABLE_LEN_CHGD 0x2000
218 #define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
219 #define RL_ISR_TIMEOUT_EXPIRED 0x4000
220 #define RL_ISR_SYSTEM_ERR 0x8000
221
222 #define RL_INTRS \
223 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
224 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
225 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
226
227 #ifdef RE_TX_MODERATION
228 #define RL_INTRS_CPLUS \
229 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
230 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
231 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
232 #else
233 #define RL_INTRS_CPLUS \
234 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \
235 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
236 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
237 #endif
238
239 /*
240 * Media status register. (8139 only)
241 */
242 #define RL_MEDIASTAT_RXPAUSE 0x01
243 #define RL_MEDIASTAT_TXPAUSE 0x02
244 #define RL_MEDIASTAT_LINK 0x04
245 #define RL_MEDIASTAT_SPEED10 0x08
246 #define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
247 #define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */
248
249 /*
250 * Receive config register.
251 */
252 #define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */
253 #define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */
254 #define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */
255 #define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */
256 #define RL_RXCFG_RX_RUNT 0x00000010
257 #define RL_RXCFG_RX_ERRPKT 0x00000020
258 #define RL_RXCFG_WRAP 0x00000080
259 #define RL_RXCFG_MAXDMA 0x00000700
260 #define RL_RXCFG_BUFSZ 0x00001800
261 #define RL_RXCFG_FIFOTHRESH 0x0000E000
262 #define RL_RXCFG_EARLYTHRESH 0x07000000
263
264 #define RL_RXDMA_16BYTES 0x00000000
265 #define RL_RXDMA_32BYTES 0x00000100
266 #define RL_RXDMA_64BYTES 0x00000200
267 #define RL_RXDMA_128BYTES 0x00000300
268 #define RL_RXDMA_256BYTES 0x00000400
269 #define RL_RXDMA_512BYTES 0x00000500
270 #define RL_RXDMA_1024BYTES 0x00000600
271 #define RL_RXDMA_UNLIMITED 0x00000700
272
273 #define RL_RXBUF_8 0x00000000
274 #define RL_RXBUF_16 0x00000800
275 #define RL_RXBUF_32 0x00001000
276 #define RL_RXBUF_64 0x00001800
277
278 #define RL_RXFIFO_16BYTES 0x00000000
279 #define RL_RXFIFO_32BYTES 0x00002000
280 #define RL_RXFIFO_64BYTES 0x00004000
281 #define RL_RXFIFO_128BYTES 0x00006000
282 #define RL_RXFIFO_256BYTES 0x00008000
283 #define RL_RXFIFO_512BYTES 0x0000A000
284 #define RL_RXFIFO_1024BYTES 0x0000C000
285 #define RL_RXFIFO_NOTHRESH 0x0000E000
286
287 /*
288 * Bits in RX status header (included with RX'ed packet
289 * in ring buffer).
290 */
291 #define RL_RXSTAT_RXOK 0x00000001
292 #define RL_RXSTAT_ALIGNERR 0x00000002
293 #define RL_RXSTAT_CRCERR 0x00000004
294 #define RL_RXSTAT_GIANT 0x00000008
295 #define RL_RXSTAT_RUNT 0x00000010
296 #define RL_RXSTAT_BADSYM 0x00000020
297 #define RL_RXSTAT_BROAD 0x00002000
298 #define RL_RXSTAT_INDIV 0x00004000
299 #define RL_RXSTAT_MULTI 0x00008000
300 #define RL_RXSTAT_LENMASK 0xFFFF0000
301
302 #define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */
303 /*
304 * Command register.
305 */
306 #define RL_CMD_EMPTY_RXBUF 0x0001
307 #define RL_CMD_TX_ENB 0x0004
308 #define RL_CMD_RX_ENB 0x0008
309 #define RL_CMD_RESET 0x0010
310
311 /*
312 * Twister register values. These are completely undocumented and derived
313 * from public sources.
314 */
315 #define RL_CSCFG_LINK_OK 0x0400
316 #define RL_CSCFG_CHANGE 0x0800
317 #define RL_CSCFG_STATUS 0xf000
318 #define RL_CSCFG_ROW3 0x7000
319 #define RL_CSCFG_ROW2 0x3000
320 #define RL_CSCFG_ROW1 0x1000
321 #define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0
322 #define RL_CSCFG_LINK_DOWN_CMD 0xf3c0
323
324 #define RL_NWAYTST_RESET 0
325 #define RL_NWAYTST_CBL_TEST 0x20
326
327 #define RL_PARA78 0x78
328 #define RL_PARA78_DEF 0x78fa8388
329 #define RL_PARA7C 0x7C
330 #define RL_PARA7C_DEF 0xcb38de43
331 #define RL_PARA7C_RETUNE 0xfb38de03
332 /*
333 * EEPROM control register
334 */
335 #define RL_EE_DATAOUT 0x01 /* Data out */
336 #define RL_EE_DATAIN 0x02 /* Data in */
337 #define RL_EE_CLK 0x04 /* clock */
338 #define RL_EE_SEL 0x08 /* chip select */
339 #define RL_EE_MODE (0x40|0x80)
340
341 #define RL_EEMODE_OFF 0x00
342 #define RL_EEMODE_AUTOLOAD 0x40
343 #define RL_EEMODE_PROGRAM 0x80
344 #define RL_EEMODE_WRITECFG (0x80|0x40)
345
346 /* 9346 EEPROM commands */
347 #define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */
348 #define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */
349
350 #define RL_9346_WRITE 0x5
351 #define RL_9346_READ 0x6
352 #define RL_9346_ERASE 0x7
353 #define RL_9346_EWEN 0x4
354 #define RL_9346_EWEN_ADDR 0x30
355 #define RL_9456_EWDS 0x4
356 #define RL_9346_EWDS_ADDR 0x00
357
358 #define RL_EECMD_WRITE 0x140
359 #define RL_EECMD_READ_6BIT 0x180
360 #define RL_EECMD_READ_8BIT 0x600
361 #define RL_EECMD_ERASE 0x1c0
362
363 #define RL_EE_ID 0x00
364 #define RL_EE_PCI_VID 0x01
365 #define RL_EE_PCI_DID 0x02
366 /* Location of station address inside EEPROM */
367 #define RL_EE_EADDR 0x07
368
369 /*
370 * MII register (8129 only)
371 */
372 #define RL_MII_CLK 0x01
373 #define RL_MII_DATAIN 0x02
374 #define RL_MII_DATAOUT 0x04
375 #define RL_MII_DIR 0x80 /* 0 == input, 1 == output */
376
377 /*
378 * Config 0 register
379 */
380 #define RL_CFG0_ROM0 0x01
381 #define RL_CFG0_ROM1 0x02
382 #define RL_CFG0_ROM2 0x04
383 #define RL_CFG0_PL0 0x08
384 #define RL_CFG0_PL1 0x10
385 #define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */
386 #define RL_CFG0_PCS 0x40
387 #define RL_CFG0_SCR 0x80
388
389 /*
390 * Config 1 register
391 */
392 #define RL_CFG1_PWRDWN 0x01
393 #define RL_CFG1_PME 0x01
394 #define RL_CFG1_SLEEP 0x02
395 #define RL_CFG1_VPDEN 0x02
396 #define RL_CFG1_IOMAP 0x04
397 #define RL_CFG1_MEMMAP 0x08
398 #define RL_CFG1_RSVD 0x10
399 #define RL_CFG1_LWACT 0x10
400 #define RL_CFG1_DRVLOAD 0x20
401 #define RL_CFG1_LED0 0x40
402 #define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
403 #define RL_CFG1_LED1 0x80
404
405 /*
406 * Config 2 register
407 */
408 #define RL_CFG2_PCI33MHZ 0x00
409 #define RL_CFG2_PCI66MHZ 0x01
410 #define RL_CFG2_PCI64BIT 0x08
411 #define RL_CFG2_AUXPWR 0x10
412 #define RL_CFG2_MSI 0x20
413
414 /*
415 * Config 3 register
416 */
417 #define RL_CFG3_GRANTSEL 0x80
418 #define RL_CFG3_WOL_MAGIC 0x20
419 #define RL_CFG3_WOL_LINK 0x10
420 #define RL_CFG3_FAST_B2B 0x01
421
422 /*
423 * Config 4 register
424 */
425 #define RL_CFG4_LWPTN 0x04
426 #define RL_CFG4_LWPME 0x10
427
428 /*
429 * Config 5 register
430 */
431 #define RL_CFG5_WOL_BCAST 0x40
432 #define RL_CFG5_WOL_MCAST 0x20
433 #define RL_CFG5_WOL_UCAST 0x10
434 #define RL_CFG5_WOL_LANWAKE 0x02
435 #define RL_CFG5_PME_STS 0x01
436
437 /*
438 * 8139C+ register definitions
439 */
440
441 /* RL_DUMPSTATS_LO register */
442
443 #define RL_DUMPSTATS_START 0x00000008
444
445 /* Transmit start register */
446
447 #define RL_TXSTART_SWI 0x01 /* generate TX interrupt */
448 #define RL_TXSTART_START 0x40 /* start normal queue transmit */
449 #define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
450
451 /*
452 * Config 2 register, 8139C+/8169/8169S/8110S only
453 */
454 #define RL_CFG2_BUSFREQ 0x07
455 #define RL_CFG2_BUSWIDTH 0x08
456 #define RL_CFG2_AUXPWRSTS 0x10
457
458 #define RL_BUSFREQ_33MHZ 0x00
459 #define RL_BUSFREQ_66MHZ 0x01
460
461 #define RL_BUSWIDTH_32BITS 0x00
462 #define RL_BUSWIDTH_64BITS 0x08
463
464 /* C+ mode command register */
465
466 #define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
467 #define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
468 #define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
469 #define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
470 #define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
471 #define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
472 #define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */
473 #define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */
474 #define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */
475 #define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */
476 #define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */
477 #define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */
478 #define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */
479 #define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */
480 #define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */
481
482 /* C+ early transmit threshold */
483
484 #define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
485
486 /*
487 * Gigabit PHY access register (8169 only)
488 */
489
490 #define RL_PHYAR_PHYDATA 0x0000FFFF
491 #define RL_PHYAR_PHYREG 0x001F0000
492 #define RL_PHYAR_BUSY 0x80000000
493
494 /*
495 * Gigabit media status (8169 only)
496 */
497 #define RL_GMEDIASTAT_FDX 0x01 /* full duplex */
498 #define RL_GMEDIASTAT_LINK 0x02 /* link up */
499 #define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */
500 #define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */
501 #define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */
502 #define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */
503 #define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */
504 #define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */
505
506 /*
507 * The RealTek doesn't use a fragment-based descriptor mechanism.
508 * Instead, there are only four register sets, each or which represents
509 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
510 * packet buffer (32-bit aligned!) and we place the buffer addresses in
511 * the registers so the chip knows where they are.
512 *
513 * We can sort of kludge together the same kind of buffer management
514 * used in previous drivers, but we have to do buffer copies almost all
515 * the time, so it doesn't really buy us much.
516 *
517 * For reception, there's just one large buffer where the chip stores
518 * all received packets.
519 */
520
521 #define RL_RX_BUF_SZ RL_RXBUF_64
522 #define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13))
523 #define RL_TX_LIST_CNT 4
524 #define RL_MIN_FRAMELEN 60
525 #define RL_TX_8139_BUF_ALIGN 4
526 #define RL_RX_8139_BUF_ALIGN 8
527 #define RL_RX_8139_BUF_RESERVE sizeof(int64_t)
528 #define RL_RX_8139_BUF_GUARD_SZ \
529 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE)
530 #define RL_TXTHRESH(x) ((x) << 11)
531 #define RL_TX_THRESH_INIT 96
532 #define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH
533 #define RL_RX_MAXDMA RL_RXDMA_UNLIMITED
534 #define RL_TX_MAXDMA RL_TXDMA_2048BYTES
535
536 #define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
537 #define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA)
538
539 #define RL_ETHER_ALIGN 2
540
541 /*
542 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets.
543 */
544 #define RL_IP4CSUMTX_MINLEN 28
545 #define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN)
546
547 struct rl_chain_data {
548 uint16_t cur_rx;
549 uint8_t *rl_rx_buf;
550 uint8_t *rl_rx_buf_ptr;
551
552 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT];
553 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT];
554 bus_dma_tag_t rl_tx_tag;
555 bus_dma_tag_t rl_rx_tag;
556 bus_dmamap_t rl_rx_dmamap;
557 bus_addr_t rl_rx_buf_paddr;
558 uint8_t last_tx;
559 uint8_t cur_tx;
560 };
561
562 #define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT)
563 #define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
564 #define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
565 #define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
566 #define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
567 #define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
568 #define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
569 #define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
570 #define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
571
572 struct rl_type {
573 uint16_t rl_vid;
574 uint16_t rl_did;
575 int rl_basetype;
576 char *rl_name;
577 };
578
579 struct rl_hwrev {
580 uint32_t rl_rev;
581 int rl_type;
582 char *rl_desc;
583 };
584
585 struct rl_mii_frame {
586 uint8_t mii_stdelim;
587 uint8_t mii_opcode;
588 uint8_t mii_phyaddr;
589 uint8_t mii_regaddr;
590 uint8_t mii_turnaround;
591 uint16_t mii_data;
592 };
593
594 /*
595 * MII constants
596 */
597 #define RL_MII_STARTDELIM 0x01
598 #define RL_MII_READOP 0x02
599 #define RL_MII_WRITEOP 0x01
600 #define RL_MII_TURNAROUND 0x02
601
602 #define RL_8129 1
603 #define RL_8139 2
604 #define RL_8139CPLUS 3
605 #define RL_8169 4
606
607 #define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \
608 (x)->rl_type == RL_8169)
609
610 /*
611 * The 8139C+ and 8160 gigE chips support descriptor-based TX
612 * and RX. In fact, they even support TCP large send. Descriptors
613 * must be allocated in contiguous blocks that are aligned on a
614 * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
615 */
616
617 /*
618 * RX/TX descriptor definition. When large send mode is enabled, the
619 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
620 * the checksum offload bits are disabled. The structure layout is
621 * the same for RX and TX descriptors
622 */
623
624 struct rl_desc {
625 uint32_t rl_cmdstat;
626 uint32_t rl_vlanctl;
627 uint32_t rl_bufaddr_lo;
628 uint32_t rl_bufaddr_hi;
629 };
630
631 #define RL_TDESC_CMD_FRAGLEN 0x0000FFFF
632 #define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
633 #define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
634 #define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
635 #define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
636 #define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */
637 #define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */
638 #define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */
639 #define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
640 #define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
641 #define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */
642
643 #define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
644 #define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
645 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
646 #define RL_TDESC_CMD_UDPCSUMV2 0x80000000
647 #define RL_TDESC_CMD_TCPCSUMV2 0x40000000
648 #define RL_TDESC_CMD_IPCSUMV2 0x20000000
649
650 /*
651 * Error bits are valid only on the last descriptor of a frame
652 * (i.e. RL_TDESC_CMD_EOF == 1)
653 */
654
655 #define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
656 #define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
657 #define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
658 #define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */
659 #define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */
660 #define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */
661 #define RL_TDESC_STAT_OWN 0x80000000
662
663 /*
664 * RX descriptor cmd/vlan definitions
665 */
666
667 #define RL_RDESC_CMD_EOR 0x40000000
668 #define RL_RDESC_CMD_OWN 0x80000000
669 #define RL_RDESC_CMD_BUFLEN 0x00001FFF
670
671 #define RL_RDESC_STAT_OWN 0x80000000
672 #define RL_RDESC_STAT_EOR 0x40000000
673 #define RL_RDESC_STAT_SOF 0x20000000
674 #define RL_RDESC_STAT_EOF 0x10000000
675 #define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */
676 #define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */
677 #define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */
678 #define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */
679 #define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */
680 #define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */
681 #define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */
682 #define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */
683 #define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */
684 #define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */
685 #define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */
686 #define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */
687 #define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */
688 #define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */
689 #define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */
690 #define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */
691 #define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */
692 #define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */
693 #define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \
694 RL_RDESC_STAT_CRCERR)
695
696 #define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available
697 (rl_vlandata valid)*/
698 #define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
699 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
700 #define RL_RDESC_IPV6 0x80000000
701 #define RL_RDESC_IPV4 0x40000000
702
703 #define RL_PROTOID_NONIP 0x00000000
704 #define RL_PROTOID_TCPIP 0x00010000
705 #define RL_PROTOID_UDPIP 0x00020000
706 #define RL_PROTOID_IP 0x00030000
707 #define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
708 RL_PROTOID_TCPIP)
709 #define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
710 RL_PROTOID_UDPIP)
711
712 /*
713 * Statistics counter structure (8139C+ and 8169 only)
714 */
715 struct rl_stats {
716 uint32_t rl_tx_pkts_lo;
717 uint32_t rl_tx_pkts_hi;
718 uint32_t rl_tx_errs_lo;
719 uint32_t rl_tx_errs_hi;
720 uint32_t rl_tx_errs;
721 uint16_t rl_missed_pkts;
722 uint16_t rl_rx_framealign_errs;
723 uint32_t rl_tx_onecoll;
724 uint32_t rl_tx_multicolls;
725 uint32_t rl_rx_ucasts_hi;
726 uint32_t rl_rx_ucasts_lo;
727 uint32_t rl_rx_bcasts_lo;
728 uint32_t rl_rx_bcasts_hi;
729 uint32_t rl_rx_mcasts;
730 uint16_t rl_tx_aborts;
731 uint16_t rl_rx_underruns;
732 };
733
734 /*
735 * Rx/Tx descriptor parameters (8139C+ and 8169 only)
736 *
737 * 8139C+
738 * Number of descriptors supported : up to 64
739 * Descriptor alignment : 256 bytes
740 * Tx buffer : At least 4 bytes in length.
741 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
742 *
743 * 8169
744 * Number of descriptors supported : up to 1024
745 * Descriptor alignment : 256 bytes
746 * Tx buffer : At least 4 bytes in length.
747 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
748 */
749 #ifndef __NO_STRICT_ALIGNMENT
750 #define RE_FIXUP_RX 1
751 #endif
752
753 #define RL_8169_TX_DESC_CNT 256
754 #define RL_8169_RX_DESC_CNT 256
755 #define RL_8139_TX_DESC_CNT 64
756 #define RL_8139_RX_DESC_CNT 64
757 #define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT
758 #define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT
759 #define RL_NTXSEGS 32
760
761 #define RL_RING_ALIGN 256
762 #define RL_IFQ_MAXLEN 512
763 #define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
764 #define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
765 #define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1))
766 #define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
767 #define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
768 #define RL_PKTSZ(x) ((x)/* >> 3*/)
769 #ifdef RE_FIXUP_RX
770 #define RE_ETHER_ALIGN sizeof(uint64_t)
771 #define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN)
772 #else
773 #define RE_ETHER_ALIGN 0
774 #define RE_RX_DESC_BUFLEN MCLBYTES
775 #endif
776
777 #define RL_MSI_MESSAGES 2
778
779 #define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
780 #define RL_ADDR_HI(y) ((uint64_t) (y) >> 32)
781
782 /*
783 * The number of bits reserved for MSS in RealTek controllers is
784 * 11bits. This limits the maximum interface MTU size in TSO case
785 * as upper stack should not generate TCP segments with MSS greater
786 * than the limit.
787 */
788 #define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN)
789
790 /* see comment in dev/re/if_re.c */
791 #define RL_JUMBO_FRAMELEN 7440
792 #define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
793 #define RL_MAX_FRAMELEN \
794 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
795
796 struct rl_txdesc {
797 struct mbuf *tx_m;
798 bus_dmamap_t tx_dmamap;
799 };
800
801 struct rl_rxdesc {
802 struct mbuf *rx_m;
803 bus_dmamap_t rx_dmamap;
804 bus_size_t rx_size;
805 };
806
807 struct rl_list_data {
808 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT];
809 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT];
810 int rl_tx_desc_cnt;
811 int rl_rx_desc_cnt;
812 int rl_tx_prodidx;
813 int rl_rx_prodidx;
814 int rl_tx_considx;
815 int rl_tx_free;
816 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */
817 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */
818 bus_dmamap_t rl_rx_sparemap;
819 bus_dma_tag_t rl_stag; /* stats mapping tag */
820 bus_dmamap_t rl_smap; /* stats map */
821 struct rl_stats *rl_stats;
822 bus_addr_t rl_stats_addr;
823 bus_dma_tag_t rl_rx_list_tag;
824 bus_dmamap_t rl_rx_list_map;
825 struct rl_desc *rl_rx_list;
826 bus_addr_t rl_rx_list_addr;
827 bus_dma_tag_t rl_tx_list_tag;
828 bus_dmamap_t rl_tx_list_map;
829 struct rl_desc *rl_tx_list;
830 bus_addr_t rl_tx_list_addr;
831 };
832
833 enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE };
834
835 struct rl_softc {
836 struct ifnet *rl_ifp; /* interface info */
837 bus_space_handle_t rl_bhandle; /* bus space handle */
838 bus_space_tag_t rl_btag; /* bus space tag */
839 device_t rl_dev;
840 struct resource *rl_res;
841 int rl_res_id;
842 int rl_res_type;
843 struct resource *rl_irq[RL_MSI_MESSAGES];
844 void *rl_intrhand[RL_MSI_MESSAGES];
845 device_t rl_miibus;
846 bus_dma_tag_t rl_parent_tag;
847 uint8_t rl_type;
848 int rl_eecmd_read;
849 int rl_eewidth;
850 uint8_t rl_stats_no_timeout;
851 int rl_txthresh;
852 struct rl_chain_data rl_cdata;
853 struct rl_list_data rl_ldata;
854 struct callout rl_stat_callout;
855 int rl_watchdog_timer;
856 struct mtx rl_mtx;
857 struct mbuf *rl_head;
858 struct mbuf *rl_tail;
859 uint32_t rl_hwrev;
860 uint32_t rl_rxlenmask;
861 int rl_testmode;
862 int rl_if_flags;
863 int rl_twister_enable;
864 enum rl_twist rl_twister;
865 int rl_twist_row;
866 int rl_twist_col;
867 int suspended; /* 0 = normal 1 = suspended */
868 #ifdef DEVICE_POLLING
869 int rxcycles;
870 #endif
871
872 struct task rl_txtask;
873 struct task rl_inttask;
874
875 int rl_txstart;
876 uint32_t rl_flags;
877 #define RL_FLAG_MSI 0x0001
878 #define RL_FLAG_INVMAR 0x0004
879 #define RL_FLAG_PHYWAKE 0x0008
880 #define RL_FLAG_NOJUMBO 0x0010
881 #define RL_FLAG_PAR 0x0020
882 #define RL_FLAG_DESCV2 0x0040
883 #define RL_FLAG_MACSTAT 0x0080
884 #define RL_FLAG_LINK 0x8000
885 };
886
887 #define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx)
888 #define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx)
889 #define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
890
891 /*
892 * register space access macros
893 */
894 #define CSR_WRITE_STREAM_4(sc, reg, val) \
895 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
896 #define CSR_WRITE_4(sc, reg, val) \
897 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
898 #define CSR_WRITE_2(sc, reg, val) \
899 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
900 #define CSR_WRITE_1(sc, reg, val) \
901 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
902
903 #define CSR_READ_4(sc, reg) \
904 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
905 #define CSR_READ_2(sc, reg) \
906 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
907 #define CSR_READ_1(sc, reg) \
908 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
909
910 #define CSR_SETBIT_1(sc, offset, val) \
911 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
912
913 #define CSR_CLRBIT_1(sc, offset, val) \
914 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
915
916 #define CSR_SETBIT_2(sc, offset, val) \
917 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
918
919 #define CSR_CLRBIT_2(sc, offset, val) \
920 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
921
922 #define CSR_SETBIT_4(sc, offset, val) \
923 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
924
925 #define CSR_CLRBIT_4(sc, offset, val) \
926 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
927
928 #define RL_TIMEOUT 1000
929
930 /*
931 * General constants that are fun to know.
932 *
933 * RealTek PCI vendor ID
934 */
935 #define RT_VENDORID 0x10EC
936
937 /*
938 * RealTek chip device IDs.
939 */
940 #define RT_DEVICEID_8139D 0x8039
941 #define RT_DEVICEID_8129 0x8129
942 #define RT_DEVICEID_8101E 0x8136
943 #define RT_DEVICEID_8138 0x8138
944 #define RT_DEVICEID_8139 0x8139
945 #define RT_DEVICEID_8169SC 0x8167
946 #define RT_DEVICEID_8168 0x8168
947 #define RT_DEVICEID_8169 0x8169
948 #define RT_DEVICEID_8100 0x8100
949
950 #define RT_REVID_8139CPLUS 0x20
951
952 /*
953 * Accton PCI vendor ID
954 */
955 #define ACCTON_VENDORID 0x1113
956
957 /*
958 * Accton MPX 5030/5038 device ID.
959 */
960 #define ACCTON_DEVICEID_5030 0x1211
961
962 /*
963 * Nortel PCI vendor ID
964 */
965 #define NORTEL_VENDORID 0x126C
966
967 /*
968 * Delta Electronics Vendor ID.
969 */
970 #define DELTA_VENDORID 0x1500
971
972 /*
973 * Delta device IDs.
974 */
975 #define DELTA_DEVICEID_8139 0x1360
976
977 /*
|