FreeBSD/Linux Kernel Cross Reference
sys/pci/if_rlreg.h
1 /*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: releng/10.0/sys/pci/if_rlreg.h 257617 2013-11-04 05:58:59Z yongari $
33 */
34
35 /*
36 * RealTek 8129/8139 register offsets
37 */
38 #define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39 #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40 #define RL_IDR2 0x0002
41 #define RL_IDR3 0x0003
42 #define RL_IDR4 0x0004
43 #define RL_IDR5 0x0005
44 /* 0006-0007 reserved */
45 #define RL_MAR0 0x0008 /* Multicast hash table */
46 #define RL_MAR1 0x0009
47 #define RL_MAR2 0x000A
48 #define RL_MAR3 0x000B
49 #define RL_MAR4 0x000C
50 #define RL_MAR5 0x000D
51 #define RL_MAR6 0x000E
52 #define RL_MAR7 0x000F
53
54 #define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */
55 #define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */
56 #define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */
57 #define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */
58
59 #define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */
60 #define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */
61 #define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */
62 #define RL_TXADDR3 0x002C /* address of TX descriptor 3 */
63
64 #define RL_RXADDR 0x0030 /* RX ring start address */
65 #define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */
66 #define RL_RX_EARLY_STAT 0x0036 /* RX early status */
67 #define RL_COMMAND 0x0037 /* command register */
68 #define RL_CURRXADDR 0x0038 /* current address of packet read */
69 #define RL_CURRXBUF 0x003A /* current RX buffer address */
70 #define RL_IMR 0x003C /* interrupt mask register */
71 #define RL_ISR 0x003E /* interrupt status register */
72 #define RL_TXCFG 0x0040 /* transmit config */
73 #define RL_RXCFG 0x0044 /* receive config */
74 #define RL_TIMERCNT 0x0048 /* timer count register */
75 #define RL_MISSEDPKT 0x004C /* missed packet counter */
76 #define RL_EECMD 0x0050 /* EEPROM command register */
77
78 /* RTL8139/RTL8139C+ only */
79 #define RL_8139_CFG0 0x0051 /* config register #0 */
80 #define RL_8139_CFG1 0x0052 /* config register #1 */
81 #define RL_8139_CFG3 0x0059 /* config register #3 */
82 #define RL_8139_CFG4 0x005A /* config register #4 */
83 #define RL_8139_CFG5 0x00D8 /* config register #5 */
84
85 #define RL_CFG0 0x0051 /* config register #0 */
86 #define RL_CFG1 0x0052 /* config register #1 */
87 #define RL_CFG2 0x0053 /* config register #2 */
88 #define RL_CFG3 0x0054 /* config register #3 */
89 #define RL_CFG4 0x0055 /* config register #4 */
90 #define RL_CFG5 0x0056 /* config register #5 */
91 /* 0057 reserved */
92 #define RL_MEDIASTAT 0x0058 /* media status register (8139) */
93 /* 0059-005A reserved */
94 #define RL_MII 0x005A /* 8129 chip only */
95 #define RL_HALTCLK 0x005B
96 #define RL_MULTIINTR 0x005C /* multiple interrupt */
97 #define RL_PCIREV 0x005E /* PCI revision value */
98 /* 005F reserved */
99 #define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */
100
101 /* Direct PHY access registers only available on 8139 */
102 #define RL_BMCR 0x0062 /* PHY basic mode control */
103 #define RL_BMSR 0x0064 /* PHY basic mode status */
104 #define RL_ANAR 0x0066 /* PHY autoneg advert */
105 #define RL_LPAR 0x0068 /* PHY link partner ability */
106 #define RL_ANER 0x006A /* PHY autoneg expansion */
107
108 #define RL_DISCCNT 0x006C /* disconnect counter */
109 #define RL_FALSECAR 0x006E /* false carrier counter */
110 #define RL_NWAYTST 0x0070 /* NWAY test register */
111 #define RL_RX_ER 0x0072 /* RX_ER counter */
112 #define RL_CSCFG 0x0074 /* CS configuration register */
113
114 /*
115 * When operating in special C+ mode, some of the registers in an
116 * 8139C+ chip have different definitions. These are also used for
117 * the 8169 gigE chip.
118 */
119 #define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */
120 #define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */
121 #define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */
122 #define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */
123 #define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */
124 #define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */
125 #define RL_CFG2 0x0053
126 #define RL_TIMERINT 0x0054 /* interrupt on timer expire */
127 #define RL_TXSTART 0x00D9 /* 8 bits */
128 #define RL_CPLUS_CMD 0x00E0 /* 16 bits */
129 #define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */
130 #define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */
131 #define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */
132
133 /*
134 * Registers specific to the 8169 gigE chip
135 */
136 #define RL_GTXSTART 0x0038 /* 8 bits */
137 #define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */
138 #define RL_PHYAR 0x0060
139 #define RL_TBICSR 0x0064
140 #define RL_TBI_ANAR 0x0068
141 #define RL_TBI_LPAR 0x006A
142 #define RL_GMEDIASTAT 0x006C /* 8 bits */
143 #define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */
144 #define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */
145 #define RL_PMCH 0x006F /* 8 bits */
146 #define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
147 #define RL_INTRMOD 0x00E2 /* 16 bits */
148
149 /*
150 * TX config register bits
151 */
152 #define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
153 #define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
154 #define RL_TXCFG_QUEUE_EMPTY 0x00000800 /* 8168E-VL or higher */
155 #define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
156 #define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
157 #define RL_TXCFG_IFG2 0x00080000 /* 8169 only */
158 #define RL_TXCFG_IFG 0x03000000 /* interframe gap */
159 #define RL_TXCFG_HWREV 0x7CC00000
160
161 #define RL_LOOPTEST_OFF 0x00000000
162 #define RL_LOOPTEST_ON 0x00020000
163 #define RL_LOOPTEST_ON_CPLUS 0x00060000
164
165 /* Known revision codes. */
166
167 #define RL_HWREV_8169 0x00000000
168 #define RL_HWREV_8169S 0x00800000
169 #define RL_HWREV_8110S 0x04000000
170 #define RL_HWREV_8169_8110SB 0x10000000
171 #define RL_HWREV_8169_8110SC 0x18000000
172 #define RL_HWREV_8401E 0x24000000
173 #define RL_HWREV_8102EL 0x24800000
174 #define RL_HWREV_8102EL_SPIN1 0x24C00000
175 #define RL_HWREV_8168D 0x28000000
176 #define RL_HWREV_8168DP 0x28800000
177 #define RL_HWREV_8168E 0x2C000000
178 #define RL_HWREV_8168E_VL 0x2C800000
179 #define RL_HWREV_8168B_SPIN1 0x30000000
180 #define RL_HWREV_8100E 0x30800000
181 #define RL_HWREV_8101E 0x34000000
182 #define RL_HWREV_8102E 0x34800000
183 #define RL_HWREV_8103E 0x34C00000
184 #define RL_HWREV_8168B_SPIN2 0x38000000
185 #define RL_HWREV_8168B_SPIN3 0x38400000
186 #define RL_HWREV_8168C 0x3C000000
187 #define RL_HWREV_8168C_SPIN2 0x3C400000
188 #define RL_HWREV_8168CP 0x3C800000
189 #define RL_HWREV_8105E 0x40800000
190 #define RL_HWREV_8105E_SPIN1 0x40C00000
191 #define RL_HWREV_8402 0x44000000
192 #define RL_HWREV_8106E 0x44800000
193 #define RL_HWREV_8168F 0x48000000
194 #define RL_HWREV_8411 0x48800000
195 #define RL_HWREV_8168G 0x4C000000
196 #define RL_HWREV_8168EP 0x50000000
197 #define RL_HWREV_8168GU 0x50800000
198 #define RL_HWREV_8411B 0x5C800000
199 #define RL_HWREV_8139 0x60000000
200 #define RL_HWREV_8139A 0x70000000
201 #define RL_HWREV_8139AG 0x70800000
202 #define RL_HWREV_8139B 0x78000000
203 #define RL_HWREV_8130 0x7C000000
204 #define RL_HWREV_8139C 0x74000000
205 #define RL_HWREV_8139D 0x74400000
206 #define RL_HWREV_8139CPLUS 0x74800000
207 #define RL_HWREV_8101 0x74C00000
208 #define RL_HWREV_8100 0x78800000
209 #define RL_HWREV_8169_8110SBL 0x7CC00000
210 #define RL_HWREV_8169_8110SCE 0x98000000
211
212 #define RL_TXDMA_16BYTES 0x00000000
213 #define RL_TXDMA_32BYTES 0x00000100
214 #define RL_TXDMA_64BYTES 0x00000200
215 #define RL_TXDMA_128BYTES 0x00000300
216 #define RL_TXDMA_256BYTES 0x00000400
217 #define RL_TXDMA_512BYTES 0x00000500
218 #define RL_TXDMA_1024BYTES 0x00000600
219 #define RL_TXDMA_2048BYTES 0x00000700
220
221 /*
222 * Transmit descriptor status register bits.
223 */
224 #define RL_TXSTAT_LENMASK 0x00001FFF
225 #define RL_TXSTAT_OWN 0x00002000
226 #define RL_TXSTAT_TX_UNDERRUN 0x00004000
227 #define RL_TXSTAT_TX_OK 0x00008000
228 #define RL_TXSTAT_EARLY_THRESH 0x003F0000
229 #define RL_TXSTAT_COLLCNT 0x0F000000
230 #define RL_TXSTAT_CARR_HBEAT 0x10000000
231 #define RL_TXSTAT_OUTOFWIN 0x20000000
232 #define RL_TXSTAT_TXABRT 0x40000000
233 #define RL_TXSTAT_CARRLOSS 0x80000000
234
235 /*
236 * Interrupt status register bits.
237 */
238 #define RL_ISR_RX_OK 0x0001
239 #define RL_ISR_RX_ERR 0x0002
240 #define RL_ISR_TX_OK 0x0004
241 #define RL_ISR_TX_ERR 0x0008
242 #define RL_ISR_RX_OVERRUN 0x0010
243 #define RL_ISR_PKT_UNDERRUN 0x0020
244 #define RL_ISR_LINKCHG 0x0020 /* 8169 only */
245 #define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
246 #define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */
247 #define RL_ISR_SWI 0x0100 /* C+ only */
248 #define RL_ISR_CABLE_LEN_CHGD 0x2000
249 #define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
250 #define RL_ISR_TIMEOUT_EXPIRED 0x4000
251 #define RL_ISR_SYSTEM_ERR 0x8000
252
253 #define RL_INTRS \
254 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
255 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
256 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
257
258 #ifdef RE_TX_MODERATION
259 #define RL_INTRS_CPLUS \
260 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
261 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
262 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
263 #else
264 #define RL_INTRS_CPLUS \
265 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \
266 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
267 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
268 #endif
269
270 /*
271 * Media status register. (8139 only)
272 */
273 #define RL_MEDIASTAT_RXPAUSE 0x01
274 #define RL_MEDIASTAT_TXPAUSE 0x02
275 #define RL_MEDIASTAT_LINK 0x04
276 #define RL_MEDIASTAT_SPEED10 0x08
277 #define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
278 #define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */
279
280 /*
281 * Receive config register.
282 */
283 #define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */
284 #define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */
285 #define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */
286 #define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */
287 #define RL_RXCFG_RX_RUNT 0x00000010
288 #define RL_RXCFG_RX_ERRPKT 0x00000020
289 #define RL_RXCFG_WRAP 0x00000080
290 #define RL_RXCFG_MAXDMA 0x00000700
291 #define RL_RXCFG_BUFSZ 0x00001800
292 #define RL_RXCFG_FIFOTHRESH 0x0000E000
293 #define RL_RXCFG_EARLYTHRESH 0x07000000
294
295 #define RL_RXDMA_16BYTES 0x00000000
296 #define RL_RXDMA_32BYTES 0x00000100
297 #define RL_RXDMA_64BYTES 0x00000200
298 #define RL_RXDMA_128BYTES 0x00000300
299 #define RL_RXDMA_256BYTES 0x00000400
300 #define RL_RXDMA_512BYTES 0x00000500
301 #define RL_RXDMA_1024BYTES 0x00000600
302 #define RL_RXDMA_UNLIMITED 0x00000700
303
304 #define RL_RXBUF_8 0x00000000
305 #define RL_RXBUF_16 0x00000800
306 #define RL_RXBUF_32 0x00001000
307 #define RL_RXBUF_64 0x00001800
308
309 #define RL_RXFIFO_16BYTES 0x00000000
310 #define RL_RXFIFO_32BYTES 0x00002000
311 #define RL_RXFIFO_64BYTES 0x00004000
312 #define RL_RXFIFO_128BYTES 0x00006000
313 #define RL_RXFIFO_256BYTES 0x00008000
314 #define RL_RXFIFO_512BYTES 0x0000A000
315 #define RL_RXFIFO_1024BYTES 0x0000C000
316 #define RL_RXFIFO_NOTHRESH 0x0000E000
317
318 /*
319 * Bits in RX status header (included with RX'ed packet
320 * in ring buffer).
321 */
322 #define RL_RXSTAT_RXOK 0x00000001
323 #define RL_RXSTAT_ALIGNERR 0x00000002
324 #define RL_RXSTAT_CRCERR 0x00000004
325 #define RL_RXSTAT_GIANT 0x00000008
326 #define RL_RXSTAT_RUNT 0x00000010
327 #define RL_RXSTAT_BADSYM 0x00000020
328 #define RL_RXSTAT_BROAD 0x00002000
329 #define RL_RXSTAT_INDIV 0x00004000
330 #define RL_RXSTAT_MULTI 0x00008000
331 #define RL_RXSTAT_LENMASK 0xFFFF0000
332
333 #define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */
334 /*
335 * Command register.
336 */
337 #define RL_CMD_EMPTY_RXBUF 0x0001
338 #define RL_CMD_TX_ENB 0x0004
339 #define RL_CMD_RX_ENB 0x0008
340 #define RL_CMD_RESET 0x0010
341 #define RL_CMD_STOPREQ 0x0080
342
343 /*
344 * Twister register values. These are completely undocumented and derived
345 * from public sources.
346 */
347 #define RL_CSCFG_LINK_OK 0x0400
348 #define RL_CSCFG_CHANGE 0x0800
349 #define RL_CSCFG_STATUS 0xf000
350 #define RL_CSCFG_ROW3 0x7000
351 #define RL_CSCFG_ROW2 0x3000
352 #define RL_CSCFG_ROW1 0x1000
353 #define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0
354 #define RL_CSCFG_LINK_DOWN_CMD 0xf3c0
355
356 #define RL_NWAYTST_RESET 0
357 #define RL_NWAYTST_CBL_TEST 0x20
358
359 #define RL_PARA78 0x78
360 #define RL_PARA78_DEF 0x78fa8388
361 #define RL_PARA7C 0x7C
362 #define RL_PARA7C_DEF 0xcb38de43
363 #define RL_PARA7C_RETUNE 0xfb38de03
364 /*
365 * EEPROM control register
366 */
367 #define RL_EE_DATAOUT 0x01 /* Data out */
368 #define RL_EE_DATAIN 0x02 /* Data in */
369 #define RL_EE_CLK 0x04 /* clock */
370 #define RL_EE_SEL 0x08 /* chip select */
371 #define RL_EE_MODE (0x40|0x80)
372
373 #define RL_EEMODE_OFF 0x00
374 #define RL_EEMODE_AUTOLOAD 0x40
375 #define RL_EEMODE_PROGRAM 0x80
376 #define RL_EEMODE_WRITECFG (0x80|0x40)
377
378 /* 9346 EEPROM commands */
379 #define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */
380 #define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */
381
382 #define RL_9346_WRITE 0x5
383 #define RL_9346_READ 0x6
384 #define RL_9346_ERASE 0x7
385 #define RL_9346_EWEN 0x4
386 #define RL_9346_EWEN_ADDR 0x30
387 #define RL_9456_EWDS 0x4
388 #define RL_9346_EWDS_ADDR 0x00
389
390 #define RL_EECMD_WRITE 0x140
391 #define RL_EECMD_READ_6BIT 0x180
392 #define RL_EECMD_READ_8BIT 0x600
393 #define RL_EECMD_ERASE 0x1c0
394
395 #define RL_EE_ID 0x00
396 #define RL_EE_PCI_VID 0x01
397 #define RL_EE_PCI_DID 0x02
398 /* Location of station address inside EEPROM */
399 #define RL_EE_EADDR 0x07
400
401 /*
402 * MII register (8129 only)
403 */
404 #define RL_MII_CLK 0x01
405 #define RL_MII_DATAIN 0x02
406 #define RL_MII_DATAOUT 0x04
407 #define RL_MII_DIR 0x80 /* 0 == input, 1 == output */
408
409 /*
410 * Config 0 register
411 */
412 #define RL_CFG0_ROM0 0x01
413 #define RL_CFG0_ROM1 0x02
414 #define RL_CFG0_ROM2 0x04
415 #define RL_CFG0_PL0 0x08
416 #define RL_CFG0_PL1 0x10
417 #define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */
418 #define RL_CFG0_PCS 0x40
419 #define RL_CFG0_SCR 0x80
420
421 /*
422 * Config 1 register
423 */
424 #define RL_CFG1_PWRDWN 0x01
425 #define RL_CFG1_PME 0x01
426 #define RL_CFG1_SLEEP 0x02
427 #define RL_CFG1_VPDEN 0x02
428 #define RL_CFG1_IOMAP 0x04
429 #define RL_CFG1_MEMMAP 0x08
430 #define RL_CFG1_RSVD 0x10
431 #define RL_CFG1_LWACT 0x10
432 #define RL_CFG1_DRVLOAD 0x20
433 #define RL_CFG1_LED0 0x40
434 #define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
435 #define RL_CFG1_LED1 0x80
436
437 /*
438 * Config 2 register
439 */
440 #define RL_CFG2_PCI33MHZ 0x00
441 #define RL_CFG2_PCI66MHZ 0x01
442 #define RL_CFG2_PCI64BIT 0x08
443 #define RL_CFG2_AUXPWR 0x10
444 #define RL_CFG2_MSI 0x20
445
446 /*
447 * Config 3 register
448 */
449 #define RL_CFG3_GRANTSEL 0x80
450 #define RL_CFG3_WOL_MAGIC 0x20
451 #define RL_CFG3_WOL_LINK 0x10
452 #define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */
453 #define RL_CFG3_FAST_B2B 0x01
454
455 /*
456 * Config 4 register
457 */
458 #define RL_CFG4_LWPTN 0x04
459 #define RL_CFG4_LWPME 0x10
460 #define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */
461
462 /*
463 * Config 5 register
464 */
465 #define RL_CFG5_WOL_BCAST 0x40
466 #define RL_CFG5_WOL_MCAST 0x20
467 #define RL_CFG5_WOL_UCAST 0x10
468 #define RL_CFG5_WOL_LANWAKE 0x02
469 #define RL_CFG5_PME_STS 0x01
470
471 /*
472 * 8139C+ register definitions
473 */
474
475 /* RL_DUMPSTATS_LO register */
476
477 #define RL_DUMPSTATS_START 0x00000008
478
479 /* Transmit start register */
480
481 #define RL_TXSTART_SWI 0x01 /* generate TX interrupt */
482 #define RL_TXSTART_START 0x40 /* start normal queue transmit */
483 #define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
484
485 /*
486 * Config 2 register, 8139C+/8169/8169S/8110S only
487 */
488 #define RL_CFG2_BUSFREQ 0x07
489 #define RL_CFG2_BUSWIDTH 0x08
490 #define RL_CFG2_AUXPWRSTS 0x10
491
492 #define RL_BUSFREQ_33MHZ 0x00
493 #define RL_BUSFREQ_66MHZ 0x01
494
495 #define RL_BUSWIDTH_32BITS 0x00
496 #define RL_BUSWIDTH_64BITS 0x08
497
498 /* C+ mode command register */
499
500 #define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
501 #define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
502 #define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
503 #define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
504 #define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
505 #define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
506 #define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */
507 #define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */
508 #define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */
509 #define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */
510 #define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */
511 #define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */
512 #define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */
513 #define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */
514 #define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */
515
516 /* C+ early transmit threshold */
517
518 #define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
519
520 /* Timer interrupt register */
521 #define RL_TIMERINT_8169_VAL 0x00001FFF
522 #define RL_TIMER_MIN 0
523 #define RL_TIMER_MAX 65 /* 65.528us */
524 #define RL_TIMER_DEFAULT RL_TIMER_MAX
525 #define RL_TIMER_PCIE_CLK 125 /* 125MHZ */
526 #define RL_USECS(x) ((x) * RL_TIMER_PCIE_CLK)
527
528 /*
529 * Gigabit PHY access register (8169 only)
530 */
531
532 #define RL_PHYAR_PHYDATA 0x0000FFFF
533 #define RL_PHYAR_PHYREG 0x001F0000
534 #define RL_PHYAR_BUSY 0x80000000
535
536 /*
537 * Gigabit media status (8169 only)
538 */
539 #define RL_GMEDIASTAT_FDX 0x01 /* full duplex */
540 #define RL_GMEDIASTAT_LINK 0x02 /* link up */
541 #define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */
542 #define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */
543 #define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */
544 #define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */
545 #define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */
546 #define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */
547
548 /*
549 * The RealTek doesn't use a fragment-based descriptor mechanism.
550 * Instead, there are only four register sets, each or which represents
551 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
552 * packet buffer (32-bit aligned!) and we place the buffer addresses in
553 * the registers so the chip knows where they are.
554 *
555 * We can sort of kludge together the same kind of buffer management
556 * used in previous drivers, but we have to do buffer copies almost all
557 * the time, so it doesn't really buy us much.
558 *
559 * For reception, there's just one large buffer where the chip stores
560 * all received packets.
561 */
562
563 #define RL_RX_BUF_SZ RL_RXBUF_64
564 #define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13))
565 #define RL_TX_LIST_CNT 4
566 #define RL_MIN_FRAMELEN 60
567 #define RL_TX_8139_BUF_ALIGN 4
568 #define RL_RX_8139_BUF_ALIGN 8
569 #define RL_RX_8139_BUF_RESERVE sizeof(int64_t)
570 #define RL_RX_8139_BUF_GUARD_SZ \
571 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE)
572 #define RL_TXTHRESH(x) ((x) << 11)
573 #define RL_TX_THRESH_INIT 96
574 #define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH
575 #define RL_RX_MAXDMA RL_RXDMA_UNLIMITED
576 #define RL_TX_MAXDMA RL_TXDMA_2048BYTES
577
578 #define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
579 #define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA)
580
581 #define RL_ETHER_ALIGN 2
582
583 /*
584 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets.
585 */
586 #define RL_IP4CSUMTX_MINLEN 28
587 #define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN)
588
589 struct rl_chain_data {
590 uint16_t cur_rx;
591 uint8_t *rl_rx_buf;
592 uint8_t *rl_rx_buf_ptr;
593
594 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT];
595 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT];
596 bus_dma_tag_t rl_tx_tag;
597 bus_dma_tag_t rl_rx_tag;
598 bus_dmamap_t rl_rx_dmamap;
599 bus_addr_t rl_rx_buf_paddr;
600 uint8_t last_tx;
601 uint8_t cur_tx;
602 };
603
604 #define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT)
605 #define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
606 #define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
607 #define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
608 #define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
609 #define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
610 #define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
611 #define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
612 #define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
613
614 struct rl_type {
615 uint16_t rl_vid;
616 uint16_t rl_did;
617 int rl_basetype;
618 const char *rl_name;
619 };
620
621 struct rl_hwrev {
622 uint32_t rl_rev;
623 int rl_type;
624 const char *rl_desc;
625 int rl_max_mtu;
626 };
627
628 #define RL_8129 1
629 #define RL_8139 2
630 #define RL_8139CPLUS 3
631 #define RL_8169 4
632
633 #define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \
634 (x)->rl_type == RL_8169)
635
636 /*
637 * The 8139C+ and 8160 gigE chips support descriptor-based TX
638 * and RX. In fact, they even support TCP large send. Descriptors
639 * must be allocated in contiguous blocks that are aligned on a
640 * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
641 */
642
643 /*
644 * RX/TX descriptor definition. When large send mode is enabled, the
645 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
646 * the checksum offload bits are disabled. The structure layout is
647 * the same for RX and TX descriptors
648 */
649
650 struct rl_desc {
651 uint32_t rl_cmdstat;
652 uint32_t rl_vlanctl;
653 uint32_t rl_bufaddr_lo;
654 uint32_t rl_bufaddr_hi;
655 };
656
657 #define RL_TDESC_CMD_FRAGLEN 0x0000FFFF
658 #define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
659 #define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
660 #define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
661 #define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
662 #define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */
663 #define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */
664 #define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */
665 #define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
666 #define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
667 #define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */
668
669 #define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
670 #define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
671 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
672 #define RL_TDESC_CMD_UDPCSUMV2 0x80000000
673 #define RL_TDESC_CMD_TCPCSUMV2 0x40000000
674 #define RL_TDESC_CMD_IPCSUMV2 0x20000000
675 #define RL_TDESC_CMD_MSSVALV2 0x1FFC0000
676 #define RL_TDESC_CMD_MSSVALV2_SHIFT 18
677
678 /*
679 * Error bits are valid only on the last descriptor of a frame
680 * (i.e. RL_TDESC_CMD_EOF == 1)
681 */
682
683 #define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
684 #define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
685 #define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
686 #define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */
687 #define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */
688 #define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */
689 #define RL_TDESC_STAT_OWN 0x80000000
690
691 /*
692 * RX descriptor cmd/vlan definitions
693 */
694
695 #define RL_RDESC_CMD_EOR 0x40000000
696 #define RL_RDESC_CMD_OWN 0x80000000
697 #define RL_RDESC_CMD_BUFLEN 0x00001FFF
698
699 #define RL_RDESC_STAT_OWN 0x80000000
700 #define RL_RDESC_STAT_EOR 0x40000000
701 #define RL_RDESC_STAT_SOF 0x20000000
702 #define RL_RDESC_STAT_EOF 0x10000000
703 #define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */
704 #define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */
705 #define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */
706 #define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */
707 #define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */
708 #define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */
709 #define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */
710 #define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */
711 #define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */
712 #define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */
713 #define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */
714 #define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */
715 #define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */
716 #define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */
717 #define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */
718 #define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */
719 #define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */
720 #define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */
721 #define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \
722 RL_RDESC_STAT_CRCERR)
723
724 #define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available
725 (rl_vlandata valid)*/
726 #define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
727 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
728 #define RL_RDESC_IPV6 0x80000000
729 #define RL_RDESC_IPV4 0x40000000
730
731 #define RL_PROTOID_NONIP 0x00000000
732 #define RL_PROTOID_TCPIP 0x00010000
733 #define RL_PROTOID_UDPIP 0x00020000
734 #define RL_PROTOID_IP 0x00030000
735 #define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
736 RL_PROTOID_TCPIP)
737 #define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
738 RL_PROTOID_UDPIP)
739
740 /*
741 * Statistics counter structure (8139C+ and 8169 only)
742 */
743 struct rl_stats {
744 uint64_t rl_tx_pkts;
745 uint64_t rl_rx_pkts;
746 uint64_t rl_tx_errs;
747 uint32_t rl_rx_errs;
748 uint16_t rl_missed_pkts;
749 uint16_t rl_rx_framealign_errs;
750 uint32_t rl_tx_onecoll;
751 uint32_t rl_tx_multicolls;
752 uint64_t rl_rx_ucasts;
753 uint64_t rl_rx_bcasts;
754 uint32_t rl_rx_mcasts;
755 uint16_t rl_tx_aborts;
756 uint16_t rl_rx_underruns;
757 };
758
759 /*
760 * Rx/Tx descriptor parameters (8139C+ and 8169 only)
761 *
762 * 8139C+
763 * Number of descriptors supported : up to 64
764 * Descriptor alignment : 256 bytes
765 * Tx buffer : At least 4 bytes in length.
766 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
767 *
768 * 8169
769 * Number of descriptors supported : up to 1024
770 * Descriptor alignment : 256 bytes
771 * Tx buffer : At least 4 bytes in length.
772 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
773 */
774 #ifndef __NO_STRICT_ALIGNMENT
775 #define RE_FIXUP_RX 1
776 #endif
777
778 #define RL_8169_TX_DESC_CNT 256
779 #define RL_8169_RX_DESC_CNT 256
780 #define RL_8139_TX_DESC_CNT 64
781 #define RL_8139_RX_DESC_CNT 64
782 #define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT
783 #define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT
784 #define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT
785 #define RL_NTXSEGS 32
786
787 #define RL_RING_ALIGN 256
788 #define RL_DUMP_ALIGN 64
789 #define RL_IFQ_MAXLEN 512
790 #define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
791 #define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
792 #define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1))
793 #define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
794 #define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
795 #define RL_PKTSZ(x) ((x)/* >> 3*/)
796 #ifdef RE_FIXUP_RX
797 #define RE_ETHER_ALIGN sizeof(uint64_t)
798 #define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN)
799 #else
800 #define RE_ETHER_ALIGN 0
801 #define RE_RX_DESC_BUFLEN MCLBYTES
802 #endif
803
804 #define RL_MSI_MESSAGES 1
805
806 #define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
807 #define RL_ADDR_HI(y) ((uint64_t) (y) >> 32)
808
809 /*
810 * The number of bits reserved for MSS in RealTek controllers is
811 * 11bits. This limits the maximum interface MTU size in TSO case
812 * as upper stack should not generate TCP segments with MSS greater
813 * than the limit.
814 */
815 #define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN)
816
817 /* see comment in dev/re/if_re.c */
818 #define RL_JUMBO_FRAMELEN 7440
819 #define RL_JUMBO_MTU \
820 (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
821 #define RL_JUMBO_MTU_6K \
822 ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
823 #define RL_JUMBO_MTU_9K \
824 ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
825 #define RL_MTU \
826 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
827
828 struct rl_txdesc {
829 struct mbuf *tx_m;
830 bus_dmamap_t tx_dmamap;
831 };
832
833 struct rl_rxdesc {
834 struct mbuf *rx_m;
835 bus_dmamap_t rx_dmamap;
836 bus_size_t rx_size;
837 };
838
839 struct rl_list_data {
840 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT];
841 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT];
842 struct rl_rxdesc rl_jrx_desc[RL_RX_JUMBO_DESC_CNT];
843 int rl_tx_desc_cnt;
844 int rl_rx_desc_cnt;
845 int rl_tx_prodidx;
846 int rl_rx_prodidx;
847 int rl_tx_considx;
848 int rl_tx_free;
849 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */
850 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */
851 bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */
852 bus_dmamap_t rl_rx_sparemap;
853 bus_dmamap_t rl_jrx_sparemap;
854 bus_dma_tag_t rl_stag; /* stats mapping tag */
855 bus_dmamap_t rl_smap; /* stats map */
856 struct rl_stats *rl_stats;
857 bus_addr_t rl_stats_addr;
858 bus_dma_tag_t rl_rx_list_tag;
859 bus_dmamap_t rl_rx_list_map;
860 struct rl_desc *rl_rx_list;
861 bus_addr_t rl_rx_list_addr;
862 bus_dma_tag_t rl_tx_list_tag;
863 bus_dmamap_t rl_tx_list_map;
864 struct rl_desc *rl_tx_list;
865 bus_addr_t rl_tx_list_addr;
866 };
867
868 enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE };
869
870 struct rl_softc {
871 struct ifnet *rl_ifp; /* interface info */
872 bus_space_handle_t rl_bhandle; /* bus space handle */
873 bus_space_tag_t rl_btag; /* bus space tag */
874 device_t rl_dev;
875 struct resource *rl_res;
876 int rl_res_id;
877 int rl_res_type;
878 struct resource *rl_res_pba;
879 struct resource *rl_irq[RL_MSI_MESSAGES];
880 void *rl_intrhand[RL_MSI_MESSAGES];
881 device_t rl_miibus;
882 bus_dma_tag_t rl_parent_tag;
883 uint8_t rl_type;
884 const struct rl_hwrev *rl_hwrev;
885 uint32_t rl_macrev;
886 int rl_eecmd_read;
887 int rl_eewidth;
888 int rl_expcap;
889 int rl_txthresh;
890 bus_size_t rl_cfg0;
891 bus_size_t rl_cfg1;
892 bus_size_t rl_cfg2;
893 bus_size_t rl_cfg3;
894 bus_size_t rl_cfg4;
895 bus_size_t rl_cfg5;
896 struct rl_chain_data rl_cdata;
897 struct rl_list_data rl_ldata;
898 struct callout rl_stat_callout;
899 int rl_watchdog_timer;
900 struct mtx rl_mtx;
901 struct mbuf *rl_head;
902 struct mbuf *rl_tail;
903 uint32_t rl_rxlenmask;
904 int rl_testmode;
905 int rl_if_flags;
906 int rl_twister_enable;
907 enum rl_twist rl_twister;
908 int rl_twist_row;
909 int rl_twist_col;
910 int suspended; /* 0 = normal 1 = suspended */
911 #ifdef DEVICE_POLLING
912 int rxcycles;
913 #endif
914
915 struct task rl_inttask;
916
917 int rl_txstart;
918 int rl_int_rx_act;
919 int rl_int_rx_mod;
920 uint32_t rl_flags;
921 #define RL_FLAG_MSI 0x00000001
922 #define RL_FLAG_AUTOPAD 0x00000002
923 #define RL_FLAG_PHYWAKE_PM 0x00000004
924 #define RL_FLAG_PHYWAKE 0x00000008
925 #define RL_FLAG_JUMBOV2 0x00000010
926 #define RL_FLAG_PAR 0x00000020
927 #define RL_FLAG_DESCV2 0x00000040
928 #define RL_FLAG_MACSTAT 0x00000080
929 #define RL_FLAG_FASTETHER 0x00000100
930 #define RL_FLAG_CMDSTOP 0x00000200
931 #define RL_FLAG_MACRESET 0x00000400
932 #define RL_FLAG_MSIX 0x00000800
933 #define RL_FLAG_WOLRXENB 0x00001000
934 #define RL_FLAG_MACSLEEP 0x00002000
935 #define RL_FLAG_WAIT_TXPOLL 0x00004000
936 #define RL_FLAG_CMDSTOP_WAIT_TXQ 0x00008000
937 #define RL_FLAG_WOL_MANLINK 0x00010000
938 #define RL_FLAG_PCIE 0x40000000
939 #define RL_FLAG_LINK 0x80000000
940 };
941
942 #define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx)
943 #define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx)
944 #define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
945
946 /*
947 * register space access macros
948 */
949 #define CSR_WRITE_STREAM_4(sc, reg, val) \
950 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
951 #define CSR_WRITE_4(sc, reg, val) \
952 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
953 #define CSR_WRITE_2(sc, reg, val) \
954 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
955 #define CSR_WRITE_1(sc, reg, val) \
956 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
957
958 #define CSR_READ_4(sc, reg) \
959 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
960 #define CSR_READ_2(sc, reg) \
961 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
962 #define CSR_READ_1(sc, reg) \
963 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
964
965 #define CSR_BARRIER(sc, reg, length, flags) \
966 bus_space_barrier(sc->rl_btag, sc->rl_bhandle, reg, length, flags)
967
968 #define CSR_SETBIT_1(sc, offset, val) \
969 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
970
971 #define CSR_CLRBIT_1(sc, offset, val) \
972 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
973
974 #define CSR_SETBIT_2(sc, offset, val) \
975 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
976
977 #define CSR_CLRBIT_2(sc, offset, val) \
978 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
979
980 #define CSR_SETBIT_4(sc, offset, val) \
981 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
982
983 #define CSR_CLRBIT_4(sc, offset, val) \
984 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
985
986 #define RL_TIMEOUT 1000
987 #define RL_PHY_TIMEOUT 2000
988
989 /*
990 * General constants that are fun to know.
991 *
992 * RealTek PCI vendor ID
993 */
994 #define RT_VENDORID 0x10EC
995
996 /*
997 * RealTek chip device IDs.
998 */
999 #define RT_DEVICEID_8139D 0x8039
1000 #define RT_DEVICEID_8129 0x8129
1001 #define RT_DEVICEID_8101E 0x8136
1002 #define RT_DEVICEID_8138 0x8138
1003 #define RT_DEVICEID_8139 0x8139
1004 #define RT_DEVICEID_8169SC 0x8167
1005 #define RT_DEVICEID_8168 0x8168
1006 #define RT_DEVICEID_8169 0x8169
1007 #define RT_DEVICEID_8100 0x8100
1008
1009 #define RT_REVID_8139CPLUS 0x20
1010
1011 /*
1012 * Accton PCI vendor ID
1013 */
1014 #define ACCTON_VENDORID 0x1113
1015
1016 /*
1017 * Accton MPX 5030/5038 device ID.
1018 */
1019 #define ACCTON_DEVICEID_5030 0x1211
1020
1021 /*
1022 * Nortel PCI vendor ID
1023 */
1024 #define NORTEL_VENDORID 0x126C
1025
1026 /*
1027 * Delta Electronics Vendor ID.
1028 */
1029 #define DELTA_VENDORID 0x1500
1030
1031 /*
1032 * Delta device IDs.
1033 */
1034 #define DELTA_DEVICEID_8139 0x1360
1035
1036 /*
1037 * Addtron vendor ID.
1038 */
1039 #define ADDTRON_VENDORID 0x4033
1040
1041 /*
1042 * Addtron device IDs.
1043 */
1044 #define ADDTRON_DEVICEID_8139 0x1360
1045
1046 /*
1047 * D-Link vendor ID.
1048 */
1049 #define DLINK_VENDORID 0x1186
1050
1051 /*
1052 * D-Link DFE-530TX+ device ID
1053 */
1054 #define DLINK_DEVICEID_530TXPLUS 0x1300
1055
1056 /*
1057 * D-Link DFE-520TX rev. C1 device ID
1058 */
1059 #define DLINK_DEVICEID_520TX_REVC1 0x4200
1060
1061 /*
1062 * D-Link DFE-5280T device ID
1063 */
1064 #define DLINK_DEVICEID_528T 0x4300
1065 #define DLINK_DEVICEID_530T_REVC 0x4302
1066
1067 /*
1068 * D-Link DFE-690TXD device ID
1069 */
1070 #define DLINK_DEVICEID_690TXD 0x1340
1071
1072 /*
1073 * Corega K.K vendor ID
1074 */
1075 #define COREGA_VENDORID 0x1259
1076
1077 /*
1078 * Corega FEther CB-TXD device ID
1079 */
1080 #define COREGA_DEVICEID_FETHERCBTXD 0xa117
1081
1082 /*
1083 * Corega FEtherII CB-TXD device ID
1084 */
1085 #define COREGA_DEVICEID_FETHERIICBTXD 0xa11e
1086
1087 /*
1088 * Corega CG-LAPCIGT device ID
1089 */
1090 #define COREGA_DEVICEID_CGLAPCIGT 0xc107
1091
1092 /*
1093 * Linksys vendor ID
1094 */
1095 #define LINKSYS_VENDORID 0x1737
1096
1097 /*
1098 * Linksys EG1032 device ID
1099 */
1100 #define LINKSYS_DEVICEID_EG1032 0x1032
1101
1102 /*
1103 * Linksys EG1032 rev 3 sub-device ID
1104 */
1105 #define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024
1106
1107 /*
1108 * Peppercon vendor ID
1109 */
1110 #define PEPPERCON_VENDORID 0x1743
1111
1112 /*
1113 * Peppercon ROL-F device ID
1114 */
1115 #define PEPPERCON_DEVICEID_ROLF 0x8139
1116
1117 /*
1118 * Planex Communications, Inc. vendor ID
1119 */
1120 #define PLANEX_VENDORID 0x14ea
1121
1122 /*
1123 * Planex FNW-3603-TX device ID
1124 */
1125 #define PLANEX_DEVICEID_FNW3603TX 0xab06
1126
1127 /*
1128 * Planex FNW-3800-TX device ID
1129 */
1130 #define PLANEX_DEVICEID_FNW3800TX 0xab07
1131
1132 /*
1133 * LevelOne vendor ID
1134 */
1135 #define LEVEL1_VENDORID 0x018A
1136
1137 /*
1138 * LevelOne FPC-0106TX devide ID
1139 */
1140 #define LEVEL1_DEVICEID_FPC0106TX 0x0106
1141
1142 /*
1143 * Compaq vendor ID
1144 */
1145 #define CP_VENDORID 0x021B
1146
1147 /*
1148 * Edimax vendor ID
1149 */
1150 #define EDIMAX_VENDORID 0x13D1
1151
1152 /*
1153 * Edimax EP-4103DL cardbus device ID
1154 */
1155 #define EDIMAX_DEVICEID_EP4103DL 0xAB06
1156
1157 /* US Robotics vendor ID */
1158
1159 #define USR_VENDORID 0x16EC
1160
1161 /* US Robotics 997902 device ID */
1162
1163 #define USR_DEVICEID_997902 0x0116
Cache object: 362bb6459fffdce6e6300a9cbdc3ffad
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